1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "sdma0/sdma0_4_2_offset.h" 34 #include "sdma0/sdma0_4_2_sh_mask.h" 35 #include "sdma1/sdma1_4_2_offset.h" 36 #include "sdma1/sdma1_4_2_sh_mask.h" 37 #include "sdma2/sdma2_4_2_2_offset.h" 38 #include "sdma2/sdma2_4_2_2_sh_mask.h" 39 #include "sdma3/sdma3_4_2_2_offset.h" 40 #include "sdma3/sdma3_4_2_2_sh_mask.h" 41 #include "sdma4/sdma4_4_2_2_offset.h" 42 #include "sdma4/sdma4_4_2_2_sh_mask.h" 43 #include "sdma5/sdma5_4_2_2_offset.h" 44 #include "sdma5/sdma5_4_2_2_sh_mask.h" 45 #include "sdma6/sdma6_4_2_2_offset.h" 46 #include "sdma6/sdma6_4_2_2_sh_mask.h" 47 #include "sdma7/sdma7_4_2_2_offset.h" 48 #include "sdma7/sdma7_4_2_2_sh_mask.h" 49 #include "sdma0/sdma0_4_1_default.h" 50 51 #include "soc15_common.h" 52 #include "soc15.h" 53 #include "vega10_sdma_pkt_open.h" 54 55 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h" 56 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h" 57 58 #include "amdgpu_ras.h" 59 #include "sdma_v4_4.h" 60 61 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin"); 62 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin"); 63 MODULE_FIRMWARE("amdgpu/vega12_sdma.bin"); 64 MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin"); 65 MODULE_FIRMWARE("amdgpu/vega20_sdma.bin"); 66 MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin"); 67 MODULE_FIRMWARE("amdgpu/raven_sdma.bin"); 68 MODULE_FIRMWARE("amdgpu/picasso_sdma.bin"); 69 MODULE_FIRMWARE("amdgpu/raven2_sdma.bin"); 70 MODULE_FIRMWARE("amdgpu/arcturus_sdma.bin"); 71 MODULE_FIRMWARE("amdgpu/renoir_sdma.bin"); 72 MODULE_FIRMWARE("amdgpu/green_sardine_sdma.bin"); 73 MODULE_FIRMWARE("amdgpu/aldebaran_sdma.bin"); 74 75 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L 76 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L 77 78 #define WREG32_SDMA(instance, offset, value) \ 79 WREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)), value) 80 #define RREG32_SDMA(instance, offset) \ 81 RREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset))) 82 83 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev); 84 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev); 85 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev); 86 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev); 87 static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev); 88 89 static const struct soc15_reg_golden golden_settings_sdma_4[] = { 90 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 91 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100), 92 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100), 93 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 94 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 95 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 96 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000), 97 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 98 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 99 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 100 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 101 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 102 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000), 103 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), 104 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100), 105 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 106 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 107 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 108 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000), 109 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 110 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 111 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 112 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 113 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0), 114 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xfc000000, 0x00000000) 115 }; 116 117 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = { 118 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 119 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 120 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 121 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 122 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 123 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 124 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 125 }; 126 127 static const struct soc15_reg_golden golden_settings_sdma_vg12[] = { 128 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), 129 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001), 130 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 131 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 132 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), 133 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001), 134 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 135 }; 136 137 static const struct soc15_reg_golden golden_settings_sdma_4_1[] = { 138 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 139 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 140 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100), 141 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 142 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051), 143 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100), 144 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 145 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100), 146 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 147 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003e0), 148 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000) 149 }; 150 151 static const struct soc15_reg_golden golden_settings_sdma0_4_2_init[] = { 152 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 153 }; 154 155 static const struct soc15_reg_golden golden_settings_sdma0_4_2[] = 156 { 157 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 158 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 159 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 160 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 161 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 162 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 163 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 164 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 165 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RD_BURST_CNTL, 0x0000000f, 0x00000003), 166 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 167 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 168 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 169 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 170 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 171 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 172 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 173 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 174 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 175 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 176 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 177 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 178 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 179 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 180 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 181 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 182 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 183 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 184 }; 185 186 static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = { 187 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 188 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), 189 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 190 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 191 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 192 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 193 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 194 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 195 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RD_BURST_CNTL, 0x0000000f, 0x00000003), 196 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 197 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 198 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 199 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 200 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 201 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 202 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 203 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 204 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 205 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 206 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 207 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 208 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 209 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 210 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 211 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 212 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0), 213 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 214 }; 215 216 static const struct soc15_reg_golden golden_settings_sdma_rv1[] = 217 { 218 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002), 219 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002) 220 }; 221 222 static const struct soc15_reg_golden golden_settings_sdma_rv2[] = 223 { 224 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00003001), 225 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003001) 226 }; 227 228 static const struct soc15_reg_golden golden_settings_sdma_arct[] = 229 { 230 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 231 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 232 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 233 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 234 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 235 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 236 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 237 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 238 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 239 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 240 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 241 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 242 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 243 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 244 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 245 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 246 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 247 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 248 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 249 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 250 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 251 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 252 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 253 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 254 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 255 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 256 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 257 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 258 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 259 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 260 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 261 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_UTCL1_TIMEOUT, 0xffffffff, 0x00010001) 262 }; 263 264 static const struct soc15_reg_golden golden_settings_sdma_aldebaran[] = { 265 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 266 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 267 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 268 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 269 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 270 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 271 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 272 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 273 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA2_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 274 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 275 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 276 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 277 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 278 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 279 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 280 }; 281 282 static const struct soc15_reg_golden golden_settings_sdma_4_3[] = { 283 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 284 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 285 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002), 286 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002), 287 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 288 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003fff07, 0x40000051), 289 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 290 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 291 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003e0), 292 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x03fbe1fe) 293 }; 294 295 static const struct soc15_ras_field_entry sdma_v4_0_ras_fields[] = { 296 { "SDMA_UCODE_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 297 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UCODE_BUF_SED), 298 0, 0, 299 }, 300 { "SDMA_RB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 301 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_RB_CMD_BUF_SED), 302 0, 0, 303 }, 304 { "SDMA_IB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 305 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_IB_CMD_BUF_SED), 306 0, 0, 307 }, 308 { "SDMA_UTCL1_RD_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 309 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UTCL1_RD_FIFO_SED), 310 0, 0, 311 }, 312 { "SDMA_UTCL1_RDBST_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 313 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UTCL1_RDBST_FIFO_SED), 314 0, 0, 315 }, 316 { "SDMA_DATA_LUT_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 317 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_DATA_LUT_FIFO_SED), 318 0, 0, 319 }, 320 { "SDMA_MBANK_DATA_BUF0_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 321 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF0_SED), 322 0, 0, 323 }, 324 { "SDMA_MBANK_DATA_BUF1_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 325 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF1_SED), 326 0, 0, 327 }, 328 { "SDMA_MBANK_DATA_BUF2_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 329 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF2_SED), 330 0, 0, 331 }, 332 { "SDMA_MBANK_DATA_BUF3_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 333 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF3_SED), 334 0, 0, 335 }, 336 { "SDMA_MBANK_DATA_BUF4_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 337 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF4_SED), 338 0, 0, 339 }, 340 { "SDMA_MBANK_DATA_BUF5_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 341 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF5_SED), 342 0, 0, 343 }, 344 { "SDMA_MBANK_DATA_BUF6_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 345 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF6_SED), 346 0, 0, 347 }, 348 { "SDMA_MBANK_DATA_BUF7_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 349 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF7_SED), 350 0, 0, 351 }, 352 { "SDMA_MBANK_DATA_BUF8_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 353 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF8_SED), 354 0, 0, 355 }, 356 { "SDMA_MBANK_DATA_BUF9_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 357 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF9_SED), 358 0, 0, 359 }, 360 { "SDMA_MBANK_DATA_BUF10_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 361 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF10_SED), 362 0, 0, 363 }, 364 { "SDMA_MBANK_DATA_BUF11_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 365 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF11_SED), 366 0, 0, 367 }, 368 { "SDMA_MBANK_DATA_BUF12_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 369 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF12_SED), 370 0, 0, 371 }, 372 { "SDMA_MBANK_DATA_BUF13_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 373 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF13_SED), 374 0, 0, 375 }, 376 { "SDMA_MBANK_DATA_BUF14_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 377 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF14_SED), 378 0, 0, 379 }, 380 { "SDMA_MBANK_DATA_BUF15_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 381 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF15_SED), 382 0, 0, 383 }, 384 { "SDMA_SPLIT_DAT_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 385 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_SPLIT_DAT_BUF_SED), 386 0, 0, 387 }, 388 { "SDMA_MC_WR_ADDR_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 389 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MC_WR_ADDR_FIFO_SED), 390 0, 0, 391 }, 392 }; 393 394 static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev, 395 u32 instance, u32 offset) 396 { 397 switch (instance) { 398 case 0: 399 return (adev->reg_offset[SDMA0_HWIP][0][0] + offset); 400 case 1: 401 return (adev->reg_offset[SDMA1_HWIP][0][0] + offset); 402 case 2: 403 return (adev->reg_offset[SDMA2_HWIP][0][1] + offset); 404 case 3: 405 return (adev->reg_offset[SDMA3_HWIP][0][1] + offset); 406 case 4: 407 return (adev->reg_offset[SDMA4_HWIP][0][1] + offset); 408 case 5: 409 return (adev->reg_offset[SDMA5_HWIP][0][1] + offset); 410 case 6: 411 return (adev->reg_offset[SDMA6_HWIP][0][1] + offset); 412 case 7: 413 return (adev->reg_offset[SDMA7_HWIP][0][1] + offset); 414 default: 415 break; 416 } 417 return 0; 418 } 419 420 static unsigned sdma_v4_0_seq_to_irq_id(int seq_num) 421 { 422 switch (seq_num) { 423 case 0: 424 return SOC15_IH_CLIENTID_SDMA0; 425 case 1: 426 return SOC15_IH_CLIENTID_SDMA1; 427 case 2: 428 return SOC15_IH_CLIENTID_SDMA2; 429 case 3: 430 return SOC15_IH_CLIENTID_SDMA3; 431 case 4: 432 return SOC15_IH_CLIENTID_SDMA4; 433 case 5: 434 return SOC15_IH_CLIENTID_SDMA5; 435 case 6: 436 return SOC15_IH_CLIENTID_SDMA6; 437 case 7: 438 return SOC15_IH_CLIENTID_SDMA7; 439 default: 440 break; 441 } 442 return -EINVAL; 443 } 444 445 static int sdma_v4_0_irq_id_to_seq(unsigned client_id) 446 { 447 switch (client_id) { 448 case SOC15_IH_CLIENTID_SDMA0: 449 return 0; 450 case SOC15_IH_CLIENTID_SDMA1: 451 return 1; 452 case SOC15_IH_CLIENTID_SDMA2: 453 return 2; 454 case SOC15_IH_CLIENTID_SDMA3: 455 return 3; 456 case SOC15_IH_CLIENTID_SDMA4: 457 return 4; 458 case SOC15_IH_CLIENTID_SDMA5: 459 return 5; 460 case SOC15_IH_CLIENTID_SDMA6: 461 return 6; 462 case SOC15_IH_CLIENTID_SDMA7: 463 return 7; 464 default: 465 break; 466 } 467 return -EINVAL; 468 } 469 470 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) 471 { 472 switch (adev->ip_versions[SDMA0_HWIP][0]) { 473 case IP_VERSION(4, 0, 0): 474 soc15_program_register_sequence(adev, 475 golden_settings_sdma_4, 476 ARRAY_SIZE(golden_settings_sdma_4)); 477 soc15_program_register_sequence(adev, 478 golden_settings_sdma_vg10, 479 ARRAY_SIZE(golden_settings_sdma_vg10)); 480 break; 481 case IP_VERSION(4, 0, 1): 482 soc15_program_register_sequence(adev, 483 golden_settings_sdma_4, 484 ARRAY_SIZE(golden_settings_sdma_4)); 485 soc15_program_register_sequence(adev, 486 golden_settings_sdma_vg12, 487 ARRAY_SIZE(golden_settings_sdma_vg12)); 488 break; 489 case IP_VERSION(4, 2, 0): 490 soc15_program_register_sequence(adev, 491 golden_settings_sdma0_4_2_init, 492 ARRAY_SIZE(golden_settings_sdma0_4_2_init)); 493 soc15_program_register_sequence(adev, 494 golden_settings_sdma0_4_2, 495 ARRAY_SIZE(golden_settings_sdma0_4_2)); 496 soc15_program_register_sequence(adev, 497 golden_settings_sdma1_4_2, 498 ARRAY_SIZE(golden_settings_sdma1_4_2)); 499 break; 500 case IP_VERSION(4, 2, 2): 501 soc15_program_register_sequence(adev, 502 golden_settings_sdma_arct, 503 ARRAY_SIZE(golden_settings_sdma_arct)); 504 break; 505 case IP_VERSION(4, 4, 0): 506 soc15_program_register_sequence(adev, 507 golden_settings_sdma_aldebaran, 508 ARRAY_SIZE(golden_settings_sdma_aldebaran)); 509 break; 510 case IP_VERSION(4, 1, 0): 511 case IP_VERSION(4, 1, 1): 512 soc15_program_register_sequence(adev, 513 golden_settings_sdma_4_1, 514 ARRAY_SIZE(golden_settings_sdma_4_1)); 515 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 516 soc15_program_register_sequence(adev, 517 golden_settings_sdma_rv2, 518 ARRAY_SIZE(golden_settings_sdma_rv2)); 519 else 520 soc15_program_register_sequence(adev, 521 golden_settings_sdma_rv1, 522 ARRAY_SIZE(golden_settings_sdma_rv1)); 523 break; 524 case IP_VERSION(4, 1, 2): 525 soc15_program_register_sequence(adev, 526 golden_settings_sdma_4_3, 527 ARRAY_SIZE(golden_settings_sdma_4_3)); 528 break; 529 default: 530 break; 531 } 532 } 533 534 static void sdma_v4_0_setup_ulv(struct amdgpu_device *adev) 535 { 536 int i; 537 538 /* 539 * The only chips with SDMAv4 and ULV are VG10 and VG20. 540 * Server SKUs take a different hysteresis setting from other SKUs. 541 */ 542 switch (adev->ip_versions[SDMA0_HWIP][0]) { 543 case IP_VERSION(4, 0, 0): 544 if (adev->pdev->device == 0x6860) 545 break; 546 return; 547 case IP_VERSION(4, 2, 0): 548 if (adev->pdev->device == 0x66a1) 549 break; 550 return; 551 default: 552 return; 553 } 554 555 for (i = 0; i < adev->sdma.num_instances; i++) { 556 uint32_t temp; 557 558 temp = RREG32_SDMA(i, mmSDMA0_ULV_CNTL); 559 temp = REG_SET_FIELD(temp, SDMA0_ULV_CNTL, HYSTERESIS, 0x0); 560 WREG32_SDMA(i, mmSDMA0_ULV_CNTL, temp); 561 } 562 } 563 564 /** 565 * sdma_v4_0_init_microcode - load ucode images from disk 566 * 567 * @adev: amdgpu_device pointer 568 * 569 * Use the firmware interface to load the ucode images into 570 * the driver (not loaded into hw). 571 * Returns 0 on success, error on failure. 572 */ 573 574 // emulation only, won't work on real chip 575 // vega10 real chip need to use PSP to load firmware 576 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev) 577 { 578 const char *chip_name; 579 char fw_name[30]; 580 int ret, i; 581 582 DRM_DEBUG("\n"); 583 584 switch (adev->ip_versions[SDMA0_HWIP][0]) { 585 case IP_VERSION(4, 0, 0): 586 chip_name = "vega10"; 587 break; 588 case IP_VERSION(4, 0, 1): 589 chip_name = "vega12"; 590 break; 591 case IP_VERSION(4, 2, 0): 592 chip_name = "vega20"; 593 break; 594 case IP_VERSION(4, 1, 0): 595 case IP_VERSION(4, 1, 1): 596 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 597 chip_name = "raven2"; 598 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 599 chip_name = "picasso"; 600 else 601 chip_name = "raven"; 602 break; 603 case IP_VERSION(4, 2, 2): 604 chip_name = "arcturus"; 605 break; 606 case IP_VERSION(4, 1, 2): 607 if (adev->apu_flags & AMD_APU_IS_RENOIR) 608 chip_name = "renoir"; 609 else 610 chip_name = "green_sardine"; 611 break; 612 case IP_VERSION(4, 4, 0): 613 chip_name = "aldebaran"; 614 break; 615 default: 616 BUG(); 617 } 618 619 for (i = 0; i < adev->sdma.num_instances; i++) { 620 if (i == 0) 621 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 622 else 623 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i); 624 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) || 625 adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 0)) { 626 /* Acturus & Aldebaran will leverage the same FW memory 627 for every SDMA instance */ 628 ret = amdgpu_sdma_init_microcode(adev, fw_name, 0, true); 629 break; 630 } else { 631 ret = amdgpu_sdma_init_microcode(adev, fw_name, i, false); 632 if (ret) 633 return ret; 634 } 635 } 636 637 return ret; 638 } 639 640 /** 641 * sdma_v4_0_ring_get_rptr - get the current read pointer 642 * 643 * @ring: amdgpu ring pointer 644 * 645 * Get the current rptr from the hardware (VEGA10+). 646 */ 647 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring) 648 { 649 u64 *rptr; 650 651 /* XXX check if swapping is necessary on BE */ 652 rptr = ((u64 *)ring->rptr_cpu_addr); 653 654 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 655 return ((*rptr) >> 2); 656 } 657 658 /** 659 * sdma_v4_0_ring_get_wptr - get the current write pointer 660 * 661 * @ring: amdgpu ring pointer 662 * 663 * Get the current wptr from the hardware (VEGA10+). 664 */ 665 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring) 666 { 667 struct amdgpu_device *adev = ring->adev; 668 u64 wptr; 669 670 if (ring->use_doorbell) { 671 /* XXX check if swapping is necessary on BE */ 672 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); 673 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 674 } else { 675 wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI); 676 wptr = wptr << 32; 677 wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR); 678 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", 679 ring->me, wptr); 680 } 681 682 return wptr >> 2; 683 } 684 685 /** 686 * sdma_v4_0_ring_set_wptr - commit the write pointer 687 * 688 * @ring: amdgpu ring pointer 689 * 690 * Write the wptr back to the hardware (VEGA10+). 691 */ 692 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring) 693 { 694 struct amdgpu_device *adev = ring->adev; 695 696 DRM_DEBUG("Setting write pointer\n"); 697 if (ring->use_doorbell) { 698 u64 *wb = (u64 *)ring->wptr_cpu_addr; 699 700 DRM_DEBUG("Using doorbell -- " 701 "wptr_offs == 0x%08x " 702 "lower_32_bits(ring->wptr << 2) == 0x%08x " 703 "upper_32_bits(ring->wptr << 2) == 0x%08x\n", 704 ring->wptr_offs, 705 lower_32_bits(ring->wptr << 2), 706 upper_32_bits(ring->wptr << 2)); 707 /* XXX check if swapping is necessary on BE */ 708 WRITE_ONCE(*wb, (ring->wptr << 2)); 709 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 710 ring->doorbell_index, ring->wptr << 2); 711 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 712 } else { 713 DRM_DEBUG("Not using doorbell -- " 714 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 715 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 716 ring->me, 717 lower_32_bits(ring->wptr << 2), 718 ring->me, 719 upper_32_bits(ring->wptr << 2)); 720 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR, 721 lower_32_bits(ring->wptr << 2)); 722 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI, 723 upper_32_bits(ring->wptr << 2)); 724 } 725 } 726 727 /** 728 * sdma_v4_0_page_ring_get_wptr - get the current write pointer 729 * 730 * @ring: amdgpu ring pointer 731 * 732 * Get the current wptr from the hardware (VEGA10+). 733 */ 734 static uint64_t sdma_v4_0_page_ring_get_wptr(struct amdgpu_ring *ring) 735 { 736 struct amdgpu_device *adev = ring->adev; 737 u64 wptr; 738 739 if (ring->use_doorbell) { 740 /* XXX check if swapping is necessary on BE */ 741 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); 742 } else { 743 wptr = RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI); 744 wptr = wptr << 32; 745 wptr |= RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR); 746 } 747 748 return wptr >> 2; 749 } 750 751 /** 752 * sdma_v4_0_page_ring_set_wptr - commit the write pointer 753 * 754 * @ring: amdgpu ring pointer 755 * 756 * Write the wptr back to the hardware (VEGA10+). 757 */ 758 static void sdma_v4_0_page_ring_set_wptr(struct amdgpu_ring *ring) 759 { 760 struct amdgpu_device *adev = ring->adev; 761 762 if (ring->use_doorbell) { 763 u64 *wb = (u64 *)ring->wptr_cpu_addr; 764 765 /* XXX check if swapping is necessary on BE */ 766 WRITE_ONCE(*wb, (ring->wptr << 2)); 767 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 768 } else { 769 uint64_t wptr = ring->wptr << 2; 770 771 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR, 772 lower_32_bits(wptr)); 773 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI, 774 upper_32_bits(wptr)); 775 } 776 } 777 778 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 779 { 780 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 781 int i; 782 783 for (i = 0; i < count; i++) 784 if (sdma && sdma->burst_nop && (i == 0)) 785 amdgpu_ring_write(ring, ring->funcs->nop | 786 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 787 else 788 amdgpu_ring_write(ring, ring->funcs->nop); 789 } 790 791 /** 792 * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine 793 * 794 * @ring: amdgpu ring pointer 795 * @job: job to retrieve vmid from 796 * @ib: IB object to schedule 797 * @flags: unused 798 * 799 * Schedule an IB in the DMA ring (VEGA10). 800 */ 801 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring, 802 struct amdgpu_job *job, 803 struct amdgpu_ib *ib, 804 uint32_t flags) 805 { 806 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 807 808 /* IB packet must end on a 8 DW boundary */ 809 sdma_v4_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 810 811 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 812 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 813 /* base must be 32 byte aligned */ 814 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 815 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 816 amdgpu_ring_write(ring, ib->length_dw); 817 amdgpu_ring_write(ring, 0); 818 amdgpu_ring_write(ring, 0); 819 820 } 821 822 static void sdma_v4_0_wait_reg_mem(struct amdgpu_ring *ring, 823 int mem_space, int hdp, 824 uint32_t addr0, uint32_t addr1, 825 uint32_t ref, uint32_t mask, 826 uint32_t inv) 827 { 828 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 829 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) | 830 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) | 831 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 832 if (mem_space) { 833 /* memory */ 834 amdgpu_ring_write(ring, addr0); 835 amdgpu_ring_write(ring, addr1); 836 } else { 837 /* registers */ 838 amdgpu_ring_write(ring, addr0 << 2); 839 amdgpu_ring_write(ring, addr1 << 2); 840 } 841 amdgpu_ring_write(ring, ref); /* reference */ 842 amdgpu_ring_write(ring, mask); /* mask */ 843 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 844 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */ 845 } 846 847 /** 848 * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 849 * 850 * @ring: amdgpu ring pointer 851 * 852 * Emit an hdp flush packet on the requested DMA ring. 853 */ 854 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 855 { 856 struct amdgpu_device *adev = ring->adev; 857 u32 ref_and_mask = 0; 858 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 859 860 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; 861 862 sdma_v4_0_wait_reg_mem(ring, 0, 1, 863 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 864 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 865 ref_and_mask, ref_and_mask, 10); 866 } 867 868 /** 869 * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring 870 * 871 * @ring: amdgpu ring pointer 872 * @addr: address 873 * @seq: sequence number 874 * @flags: fence related flags 875 * 876 * Add a DMA fence packet to the ring to write 877 * the fence seq number and DMA trap packet to generate 878 * an interrupt if needed (VEGA10). 879 */ 880 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 881 unsigned flags) 882 { 883 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 884 /* write the fence */ 885 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 886 /* zero in first two bits */ 887 BUG_ON(addr & 0x3); 888 amdgpu_ring_write(ring, lower_32_bits(addr)); 889 amdgpu_ring_write(ring, upper_32_bits(addr)); 890 amdgpu_ring_write(ring, lower_32_bits(seq)); 891 892 /* optionally write high bits as well */ 893 if (write64bit) { 894 addr += 4; 895 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 896 /* zero in first two bits */ 897 BUG_ON(addr & 0x3); 898 amdgpu_ring_write(ring, lower_32_bits(addr)); 899 amdgpu_ring_write(ring, upper_32_bits(addr)); 900 amdgpu_ring_write(ring, upper_32_bits(seq)); 901 } 902 903 /* generate an interrupt */ 904 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 905 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 906 } 907 908 909 /** 910 * sdma_v4_0_gfx_stop - stop the gfx async dma engines 911 * 912 * @adev: amdgpu_device pointer 913 * 914 * Stop the gfx async dma ring buffers (VEGA10). 915 */ 916 static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev) 917 { 918 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; 919 u32 rb_cntl, ib_cntl; 920 int i, unset = 0; 921 922 for (i = 0; i < adev->sdma.num_instances; i++) { 923 sdma[i] = &adev->sdma.instance[i].ring; 924 925 if ((adev->mman.buffer_funcs_ring == sdma[i]) && unset != 1) { 926 amdgpu_ttm_set_buffer_funcs_status(adev, false); 927 unset = 1; 928 } 929 930 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL); 931 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 932 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 933 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL); 934 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 935 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl); 936 } 937 } 938 939 /** 940 * sdma_v4_0_rlc_stop - stop the compute async dma engines 941 * 942 * @adev: amdgpu_device pointer 943 * 944 * Stop the compute async dma queues (VEGA10). 945 */ 946 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev) 947 { 948 /* XXX todo */ 949 } 950 951 /** 952 * sdma_v4_0_page_stop - stop the page async dma engines 953 * 954 * @adev: amdgpu_device pointer 955 * 956 * Stop the page async dma ring buffers (VEGA10). 957 */ 958 static void sdma_v4_0_page_stop(struct amdgpu_device *adev) 959 { 960 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; 961 u32 rb_cntl, ib_cntl; 962 int i; 963 bool unset = false; 964 965 for (i = 0; i < adev->sdma.num_instances; i++) { 966 sdma[i] = &adev->sdma.instance[i].page; 967 968 if ((adev->mman.buffer_funcs_ring == sdma[i]) && 969 (!unset)) { 970 amdgpu_ttm_set_buffer_funcs_status(adev, false); 971 unset = true; 972 } 973 974 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL); 975 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, 976 RB_ENABLE, 0); 977 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 978 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL); 979 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, 980 IB_ENABLE, 0); 981 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl); 982 } 983 } 984 985 /** 986 * sdma_v4_0_ctx_switch_enable - stop the async dma engines context switch 987 * 988 * @adev: amdgpu_device pointer 989 * @enable: enable/disable the DMA MEs context switch. 990 * 991 * Halt or unhalt the async dma engines context switch (VEGA10). 992 */ 993 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 994 { 995 u32 f32_cntl, phase_quantum = 0; 996 int i; 997 998 if (amdgpu_sdma_phase_quantum) { 999 unsigned value = amdgpu_sdma_phase_quantum; 1000 unsigned unit = 0; 1001 1002 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 1003 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 1004 value = (value + 1) >> 1; 1005 unit++; 1006 } 1007 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 1008 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 1009 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 1010 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 1011 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 1012 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 1013 WARN_ONCE(1, 1014 "clamping sdma_phase_quantum to %uK clock cycles\n", 1015 value << unit); 1016 } 1017 phase_quantum = 1018 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 1019 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 1020 } 1021 1022 for (i = 0; i < adev->sdma.num_instances; i++) { 1023 f32_cntl = RREG32_SDMA(i, mmSDMA0_CNTL); 1024 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 1025 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 1026 if (enable && amdgpu_sdma_phase_quantum) { 1027 WREG32_SDMA(i, mmSDMA0_PHASE0_QUANTUM, phase_quantum); 1028 WREG32_SDMA(i, mmSDMA0_PHASE1_QUANTUM, phase_quantum); 1029 WREG32_SDMA(i, mmSDMA0_PHASE2_QUANTUM, phase_quantum); 1030 } 1031 WREG32_SDMA(i, mmSDMA0_CNTL, f32_cntl); 1032 1033 /* 1034 * Enable SDMA utilization. Its only supported on 1035 * Arcturus for the moment and firmware version 14 1036 * and above. 1037 */ 1038 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) && 1039 adev->sdma.instance[i].fw_version >= 14) 1040 WREG32_SDMA(i, mmSDMA0_PUB_DUMMY_REG2, enable); 1041 /* Extend page fault timeout to avoid interrupt storm */ 1042 WREG32_SDMA(i, mmSDMA0_UTCL1_TIMEOUT, 0x00800080); 1043 } 1044 1045 } 1046 1047 /** 1048 * sdma_v4_0_enable - stop the async dma engines 1049 * 1050 * @adev: amdgpu_device pointer 1051 * @enable: enable/disable the DMA MEs. 1052 * 1053 * Halt or unhalt the async dma engines (VEGA10). 1054 */ 1055 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable) 1056 { 1057 u32 f32_cntl; 1058 int i; 1059 1060 if (!enable) { 1061 sdma_v4_0_gfx_stop(adev); 1062 sdma_v4_0_rlc_stop(adev); 1063 if (adev->sdma.has_page_queue) 1064 sdma_v4_0_page_stop(adev); 1065 } 1066 1067 for (i = 0; i < adev->sdma.num_instances; i++) { 1068 f32_cntl = RREG32_SDMA(i, mmSDMA0_F32_CNTL); 1069 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 1070 WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl); 1071 } 1072 } 1073 1074 /* 1075 * sdma_v4_0_rb_cntl - get parameters for rb_cntl 1076 */ 1077 static uint32_t sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl) 1078 { 1079 /* Set ring buffer size in dwords */ 1080 uint32_t rb_bufsz = order_base_2(ring->ring_size / 4); 1081 1082 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 1083 #ifdef __BIG_ENDIAN 1084 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 1085 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 1086 RPTR_WRITEBACK_SWAP_ENABLE, 1); 1087 #endif 1088 return rb_cntl; 1089 } 1090 1091 /** 1092 * sdma_v4_0_gfx_resume - setup and start the async dma engines 1093 * 1094 * @adev: amdgpu_device pointer 1095 * @i: instance to resume 1096 * 1097 * Set up the gfx DMA ring buffers and enable them (VEGA10). 1098 * Returns 0 for success, error for failure. 1099 */ 1100 static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i) 1101 { 1102 struct amdgpu_ring *ring = &adev->sdma.instance[i].ring; 1103 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 1104 u32 doorbell; 1105 u32 doorbell_offset; 1106 u64 wptr_gpu_addr; 1107 1108 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL); 1109 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl); 1110 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 1111 1112 /* Initialize the ring buffer's read and write pointers */ 1113 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR, 0); 1114 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_HI, 0); 1115 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR, 0); 1116 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_HI, 0); 1117 1118 /* set the wb address whether it's enabled or not */ 1119 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI, 1120 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); 1121 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 1122 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); 1123 1124 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 1125 RPTR_WRITEBACK_ENABLE, 1); 1126 1127 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE, ring->gpu_addr >> 8); 1128 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE_HI, ring->gpu_addr >> 40); 1129 1130 ring->wptr = 0; 1131 1132 /* before programing wptr to a less value, need set minor_ptr_update first */ 1133 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 1); 1134 1135 doorbell = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL); 1136 doorbell_offset = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET); 1137 1138 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1139 ring->use_doorbell); 1140 doorbell_offset = REG_SET_FIELD(doorbell_offset, 1141 SDMA0_GFX_DOORBELL_OFFSET, 1142 OFFSET, ring->doorbell_index); 1143 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL, doorbell); 1144 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET, doorbell_offset); 1145 1146 sdma_v4_0_ring_set_wptr(ring); 1147 1148 /* set minor_ptr_update to 0 after wptr programed */ 1149 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 0); 1150 1151 /* setup the wptr shadow polling */ 1152 wptr_gpu_addr = ring->wptr_gpu_addr; 1153 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO, 1154 lower_32_bits(wptr_gpu_addr)); 1155 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI, 1156 upper_32_bits(wptr_gpu_addr)); 1157 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL); 1158 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 1159 SDMA0_GFX_RB_WPTR_POLL_CNTL, 1160 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 1161 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 1162 1163 /* enable DMA RB */ 1164 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 1165 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 1166 1167 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL); 1168 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 1169 #ifdef __BIG_ENDIAN 1170 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 1171 #endif 1172 /* enable DMA IBs */ 1173 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl); 1174 1175 ring->sched.ready = true; 1176 } 1177 1178 /** 1179 * sdma_v4_0_page_resume - setup and start the async dma engines 1180 * 1181 * @adev: amdgpu_device pointer 1182 * @i: instance to resume 1183 * 1184 * Set up the page DMA ring buffers and enable them (VEGA10). 1185 * Returns 0 for success, error for failure. 1186 */ 1187 static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i) 1188 { 1189 struct amdgpu_ring *ring = &adev->sdma.instance[i].page; 1190 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 1191 u32 doorbell; 1192 u32 doorbell_offset; 1193 u64 wptr_gpu_addr; 1194 1195 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL); 1196 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl); 1197 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 1198 1199 /* Initialize the ring buffer's read and write pointers */ 1200 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR, 0); 1201 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_HI, 0); 1202 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR, 0); 1203 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_HI, 0); 1204 1205 /* set the wb address whether it's enabled or not */ 1206 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_HI, 1207 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); 1208 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 1209 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); 1210 1211 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, 1212 RPTR_WRITEBACK_ENABLE, 1); 1213 1214 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE, ring->gpu_addr >> 8); 1215 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE_HI, ring->gpu_addr >> 40); 1216 1217 ring->wptr = 0; 1218 1219 /* before programing wptr to a less value, need set minor_ptr_update first */ 1220 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 1); 1221 1222 doorbell = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL); 1223 doorbell_offset = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET); 1224 1225 doorbell = REG_SET_FIELD(doorbell, SDMA0_PAGE_DOORBELL, ENABLE, 1226 ring->use_doorbell); 1227 doorbell_offset = REG_SET_FIELD(doorbell_offset, 1228 SDMA0_PAGE_DOORBELL_OFFSET, 1229 OFFSET, ring->doorbell_index); 1230 WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL, doorbell); 1231 WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET, doorbell_offset); 1232 1233 /* paging queue doorbell range is setup at sdma_v4_0_gfx_resume */ 1234 sdma_v4_0_page_ring_set_wptr(ring); 1235 1236 /* set minor_ptr_update to 0 after wptr programed */ 1237 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 0); 1238 1239 /* setup the wptr shadow polling */ 1240 wptr_gpu_addr = ring->wptr_gpu_addr; 1241 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO, 1242 lower_32_bits(wptr_gpu_addr)); 1243 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI, 1244 upper_32_bits(wptr_gpu_addr)); 1245 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL); 1246 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 1247 SDMA0_PAGE_RB_WPTR_POLL_CNTL, 1248 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 1249 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 1250 1251 /* enable DMA RB */ 1252 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, RB_ENABLE, 1); 1253 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 1254 1255 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL); 1256 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_ENABLE, 1); 1257 #ifdef __BIG_ENDIAN 1258 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1); 1259 #endif 1260 /* enable DMA IBs */ 1261 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl); 1262 1263 ring->sched.ready = true; 1264 } 1265 1266 static void 1267 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable) 1268 { 1269 uint32_t def, data; 1270 1271 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) { 1272 /* enable idle interrupt */ 1273 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 1274 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 1275 1276 if (data != def) 1277 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 1278 } else { 1279 /* disable idle interrupt */ 1280 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 1281 data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 1282 if (data != def) 1283 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 1284 } 1285 } 1286 1287 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev) 1288 { 1289 uint32_t def, data; 1290 1291 /* Enable HW based PG. */ 1292 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1293 data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK; 1294 if (data != def) 1295 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1296 1297 /* enable interrupt */ 1298 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 1299 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 1300 if (data != def) 1301 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 1302 1303 /* Configure hold time to filter in-valid power on/off request. Use default right now */ 1304 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1305 data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK; 1306 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK); 1307 /* Configure switch time for hysteresis purpose. Use default right now */ 1308 data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK; 1309 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK); 1310 if(data != def) 1311 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1312 } 1313 1314 static void sdma_v4_0_init_pg(struct amdgpu_device *adev) 1315 { 1316 if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA)) 1317 return; 1318 1319 switch (adev->ip_versions[SDMA0_HWIP][0]) { 1320 case IP_VERSION(4, 1, 0): 1321 case IP_VERSION(4, 1, 1): 1322 case IP_VERSION(4, 1, 2): 1323 sdma_v4_1_init_power_gating(adev); 1324 sdma_v4_1_update_power_gating(adev, true); 1325 break; 1326 default: 1327 break; 1328 } 1329 } 1330 1331 /** 1332 * sdma_v4_0_rlc_resume - setup and start the async dma engines 1333 * 1334 * @adev: amdgpu_device pointer 1335 * 1336 * Set up the compute DMA queues and enable them (VEGA10). 1337 * Returns 0 for success, error for failure. 1338 */ 1339 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev) 1340 { 1341 sdma_v4_0_init_pg(adev); 1342 1343 return 0; 1344 } 1345 1346 /** 1347 * sdma_v4_0_load_microcode - load the sDMA ME ucode 1348 * 1349 * @adev: amdgpu_device pointer 1350 * 1351 * Loads the sDMA0/1 ucode. 1352 * Returns 0 for success, -EINVAL if the ucode is not available. 1353 */ 1354 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev) 1355 { 1356 const struct sdma_firmware_header_v1_0 *hdr; 1357 const __le32 *fw_data; 1358 u32 fw_size; 1359 int i, j; 1360 1361 /* halt the MEs */ 1362 sdma_v4_0_enable(adev, false); 1363 1364 for (i = 0; i < adev->sdma.num_instances; i++) { 1365 if (!adev->sdma.instance[i].fw) 1366 return -EINVAL; 1367 1368 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 1369 amdgpu_ucode_print_sdma_hdr(&hdr->header); 1370 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1371 1372 fw_data = (const __le32 *) 1373 (adev->sdma.instance[i].fw->data + 1374 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1375 1376 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 0); 1377 1378 for (j = 0; j < fw_size; j++) 1379 WREG32_SDMA(i, mmSDMA0_UCODE_DATA, 1380 le32_to_cpup(fw_data++)); 1381 1382 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 1383 adev->sdma.instance[i].fw_version); 1384 } 1385 1386 return 0; 1387 } 1388 1389 /** 1390 * sdma_v4_0_start - setup and start the async dma engines 1391 * 1392 * @adev: amdgpu_device pointer 1393 * 1394 * Set up the DMA engines and enable them (VEGA10). 1395 * Returns 0 for success, error for failure. 1396 */ 1397 static int sdma_v4_0_start(struct amdgpu_device *adev) 1398 { 1399 struct amdgpu_ring *ring; 1400 int i, r = 0; 1401 1402 if (amdgpu_sriov_vf(adev)) { 1403 sdma_v4_0_ctx_switch_enable(adev, false); 1404 sdma_v4_0_enable(adev, false); 1405 } else { 1406 1407 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1408 r = sdma_v4_0_load_microcode(adev); 1409 if (r) 1410 return r; 1411 } 1412 1413 /* unhalt the MEs */ 1414 sdma_v4_0_enable(adev, true); 1415 /* enable sdma ring preemption */ 1416 sdma_v4_0_ctx_switch_enable(adev, true); 1417 } 1418 1419 /* start the gfx rings and rlc compute queues */ 1420 for (i = 0; i < adev->sdma.num_instances; i++) { 1421 uint32_t temp; 1422 1423 WREG32_SDMA(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL, 0); 1424 sdma_v4_0_gfx_resume(adev, i); 1425 if (adev->sdma.has_page_queue) 1426 sdma_v4_0_page_resume(adev, i); 1427 1428 /* set utc l1 enable flag always to 1 */ 1429 temp = RREG32_SDMA(i, mmSDMA0_CNTL); 1430 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 1431 WREG32_SDMA(i, mmSDMA0_CNTL, temp); 1432 1433 if (!amdgpu_sriov_vf(adev)) { 1434 ring = &adev->sdma.instance[i].ring; 1435 adev->nbio.funcs->sdma_doorbell_range(adev, i, 1436 ring->use_doorbell, ring->doorbell_index, 1437 adev->doorbell_index.sdma_doorbell_range); 1438 1439 /* unhalt engine */ 1440 temp = RREG32_SDMA(i, mmSDMA0_F32_CNTL); 1441 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 1442 WREG32_SDMA(i, mmSDMA0_F32_CNTL, temp); 1443 } 1444 } 1445 1446 if (amdgpu_sriov_vf(adev)) { 1447 sdma_v4_0_ctx_switch_enable(adev, true); 1448 sdma_v4_0_enable(adev, true); 1449 } else { 1450 r = sdma_v4_0_rlc_resume(adev); 1451 if (r) 1452 return r; 1453 } 1454 1455 for (i = 0; i < adev->sdma.num_instances; i++) { 1456 ring = &adev->sdma.instance[i].ring; 1457 1458 r = amdgpu_ring_test_helper(ring); 1459 if (r) 1460 return r; 1461 1462 if (adev->sdma.has_page_queue) { 1463 struct amdgpu_ring *page = &adev->sdma.instance[i].page; 1464 1465 r = amdgpu_ring_test_helper(page); 1466 if (r) 1467 return r; 1468 1469 if (adev->mman.buffer_funcs_ring == page) 1470 amdgpu_ttm_set_buffer_funcs_status(adev, true); 1471 } 1472 1473 if (adev->mman.buffer_funcs_ring == ring) 1474 amdgpu_ttm_set_buffer_funcs_status(adev, true); 1475 } 1476 1477 return r; 1478 } 1479 1480 /** 1481 * sdma_v4_0_ring_test_ring - simple async dma engine test 1482 * 1483 * @ring: amdgpu_ring structure holding ring information 1484 * 1485 * Test the DMA engine by writing using it to write an 1486 * value to memory. (VEGA10). 1487 * Returns 0 for success, error for failure. 1488 */ 1489 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring) 1490 { 1491 struct amdgpu_device *adev = ring->adev; 1492 unsigned i; 1493 unsigned index; 1494 int r; 1495 u32 tmp; 1496 u64 gpu_addr; 1497 1498 r = amdgpu_device_wb_get(adev, &index); 1499 if (r) 1500 return r; 1501 1502 gpu_addr = adev->wb.gpu_addr + (index * 4); 1503 tmp = 0xCAFEDEAD; 1504 adev->wb.wb[index] = cpu_to_le32(tmp); 1505 1506 r = amdgpu_ring_alloc(ring, 5); 1507 if (r) 1508 goto error_free_wb; 1509 1510 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1511 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 1512 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 1513 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 1514 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 1515 amdgpu_ring_write(ring, 0xDEADBEEF); 1516 amdgpu_ring_commit(ring); 1517 1518 for (i = 0; i < adev->usec_timeout; i++) { 1519 tmp = le32_to_cpu(adev->wb.wb[index]); 1520 if (tmp == 0xDEADBEEF) 1521 break; 1522 udelay(1); 1523 } 1524 1525 if (i >= adev->usec_timeout) 1526 r = -ETIMEDOUT; 1527 1528 error_free_wb: 1529 amdgpu_device_wb_free(adev, index); 1530 return r; 1531 } 1532 1533 /** 1534 * sdma_v4_0_ring_test_ib - test an IB on the DMA engine 1535 * 1536 * @ring: amdgpu_ring structure holding ring information 1537 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 1538 * 1539 * Test a simple IB in the DMA ring (VEGA10). 1540 * Returns 0 on success, error on failure. 1541 */ 1542 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1543 { 1544 struct amdgpu_device *adev = ring->adev; 1545 struct amdgpu_ib ib; 1546 struct dma_fence *f = NULL; 1547 unsigned index; 1548 long r; 1549 u32 tmp = 0; 1550 u64 gpu_addr; 1551 1552 r = amdgpu_device_wb_get(adev, &index); 1553 if (r) 1554 return r; 1555 1556 gpu_addr = adev->wb.gpu_addr + (index * 4); 1557 tmp = 0xCAFEDEAD; 1558 adev->wb.wb[index] = cpu_to_le32(tmp); 1559 memset(&ib, 0, sizeof(ib)); 1560 r = amdgpu_ib_get(adev, NULL, 256, 1561 AMDGPU_IB_POOL_DIRECT, &ib); 1562 if (r) 1563 goto err0; 1564 1565 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1566 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1567 ib.ptr[1] = lower_32_bits(gpu_addr); 1568 ib.ptr[2] = upper_32_bits(gpu_addr); 1569 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1570 ib.ptr[4] = 0xDEADBEEF; 1571 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1572 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1573 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1574 ib.length_dw = 8; 1575 1576 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1577 if (r) 1578 goto err1; 1579 1580 r = dma_fence_wait_timeout(f, false, timeout); 1581 if (r == 0) { 1582 r = -ETIMEDOUT; 1583 goto err1; 1584 } else if (r < 0) { 1585 goto err1; 1586 } 1587 tmp = le32_to_cpu(adev->wb.wb[index]); 1588 if (tmp == 0xDEADBEEF) 1589 r = 0; 1590 else 1591 r = -EINVAL; 1592 1593 err1: 1594 amdgpu_ib_free(adev, &ib, NULL); 1595 dma_fence_put(f); 1596 err0: 1597 amdgpu_device_wb_free(adev, index); 1598 return r; 1599 } 1600 1601 1602 /** 1603 * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART 1604 * 1605 * @ib: indirect buffer to fill with commands 1606 * @pe: addr of the page entry 1607 * @src: src addr to copy from 1608 * @count: number of page entries to update 1609 * 1610 * Update PTEs by copying them from the GART using sDMA (VEGA10). 1611 */ 1612 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib, 1613 uint64_t pe, uint64_t src, 1614 unsigned count) 1615 { 1616 unsigned bytes = count * 8; 1617 1618 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1619 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1620 ib->ptr[ib->length_dw++] = bytes - 1; 1621 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1622 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1623 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1624 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1625 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1626 1627 } 1628 1629 /** 1630 * sdma_v4_0_vm_write_pte - update PTEs by writing them manually 1631 * 1632 * @ib: indirect buffer to fill with commands 1633 * @pe: addr of the page entry 1634 * @value: dst addr to write into pe 1635 * @count: number of page entries to update 1636 * @incr: increase next addr by incr bytes 1637 * 1638 * Update PTEs by writing them manually using sDMA (VEGA10). 1639 */ 1640 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1641 uint64_t value, unsigned count, 1642 uint32_t incr) 1643 { 1644 unsigned ndw = count * 2; 1645 1646 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1647 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1648 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1649 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1650 ib->ptr[ib->length_dw++] = ndw - 1; 1651 for (; ndw > 0; ndw -= 2) { 1652 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1653 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1654 value += incr; 1655 } 1656 } 1657 1658 /** 1659 * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA 1660 * 1661 * @ib: indirect buffer to fill with commands 1662 * @pe: addr of the page entry 1663 * @addr: dst addr to write into pe 1664 * @count: number of page entries to update 1665 * @incr: increase next addr by incr bytes 1666 * @flags: access flags 1667 * 1668 * Update the page tables using sDMA (VEGA10). 1669 */ 1670 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1671 uint64_t pe, 1672 uint64_t addr, unsigned count, 1673 uint32_t incr, uint64_t flags) 1674 { 1675 /* for physically contiguous pages (vram) */ 1676 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1677 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1678 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1679 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1680 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1681 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1682 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1683 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1684 ib->ptr[ib->length_dw++] = 0; 1685 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1686 } 1687 1688 /** 1689 * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw 1690 * 1691 * @ring: amdgpu_ring structure holding ring information 1692 * @ib: indirect buffer to fill with padding 1693 */ 1694 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1695 { 1696 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1697 u32 pad_count; 1698 int i; 1699 1700 pad_count = (-ib->length_dw) & 7; 1701 for (i = 0; i < pad_count; i++) 1702 if (sdma && sdma->burst_nop && (i == 0)) 1703 ib->ptr[ib->length_dw++] = 1704 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1705 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1706 else 1707 ib->ptr[ib->length_dw++] = 1708 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1709 } 1710 1711 1712 /** 1713 * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline 1714 * 1715 * @ring: amdgpu_ring pointer 1716 * 1717 * Make sure all previous operations are completed (CIK). 1718 */ 1719 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1720 { 1721 uint32_t seq = ring->fence_drv.sync_seq; 1722 uint64_t addr = ring->fence_drv.gpu_addr; 1723 1724 /* wait for idle */ 1725 sdma_v4_0_wait_reg_mem(ring, 1, 0, 1726 addr & 0xfffffffc, 1727 upper_32_bits(addr) & 0xffffffff, 1728 seq, 0xffffffff, 4); 1729 } 1730 1731 1732 /** 1733 * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA 1734 * 1735 * @ring: amdgpu_ring pointer 1736 * @vmid: vmid number to use 1737 * @pd_addr: address 1738 * 1739 * Update the page table base and flush the VM TLB 1740 * using sDMA (VEGA10). 1741 */ 1742 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1743 unsigned vmid, uint64_t pd_addr) 1744 { 1745 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1746 } 1747 1748 static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring, 1749 uint32_t reg, uint32_t val) 1750 { 1751 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1752 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1753 amdgpu_ring_write(ring, reg); 1754 amdgpu_ring_write(ring, val); 1755 } 1756 1757 static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1758 uint32_t val, uint32_t mask) 1759 { 1760 sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10); 1761 } 1762 1763 static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev) 1764 { 1765 uint fw_version = adev->sdma.instance[0].fw_version; 1766 1767 switch (adev->ip_versions[SDMA0_HWIP][0]) { 1768 case IP_VERSION(4, 0, 0): 1769 return fw_version >= 430; 1770 case IP_VERSION(4, 0, 1): 1771 /*return fw_version >= 31;*/ 1772 return false; 1773 case IP_VERSION(4, 2, 0): 1774 return fw_version >= 123; 1775 default: 1776 return false; 1777 } 1778 } 1779 1780 static int sdma_v4_0_early_init(void *handle) 1781 { 1782 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1783 int r; 1784 1785 r = sdma_v4_0_init_microcode(adev); 1786 if (r) { 1787 DRM_ERROR("Failed to load sdma firmware!\n"); 1788 return r; 1789 } 1790 1791 /* TODO: Page queue breaks driver reload under SRIOV */ 1792 if ((adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 0, 0)) && 1793 amdgpu_sriov_vf((adev))) 1794 adev->sdma.has_page_queue = false; 1795 else if (sdma_v4_0_fw_support_paging_queue(adev)) 1796 adev->sdma.has_page_queue = true; 1797 1798 sdma_v4_0_set_ring_funcs(adev); 1799 sdma_v4_0_set_buffer_funcs(adev); 1800 sdma_v4_0_set_vm_pte_funcs(adev); 1801 sdma_v4_0_set_irq_funcs(adev); 1802 sdma_v4_0_set_ras_funcs(adev); 1803 1804 return 0; 1805 } 1806 1807 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev, 1808 void *err_data, 1809 struct amdgpu_iv_entry *entry); 1810 1811 static int sdma_v4_0_late_init(void *handle) 1812 { 1813 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1814 1815 sdma_v4_0_setup_ulv(adev); 1816 1817 if (!amdgpu_persistent_edc_harvesting_supported(adev)) { 1818 if (adev->sdma.ras && adev->sdma.ras->ras_block.hw_ops && 1819 adev->sdma.ras->ras_block.hw_ops->reset_ras_error_count) 1820 adev->sdma.ras->ras_block.hw_ops->reset_ras_error_count(adev); 1821 } 1822 1823 return 0; 1824 } 1825 1826 static int sdma_v4_0_sw_init(void *handle) 1827 { 1828 struct amdgpu_ring *ring; 1829 int r, i; 1830 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1831 1832 /* SDMA trap event */ 1833 for (i = 0; i < adev->sdma.num_instances; i++) { 1834 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1835 SDMA0_4_0__SRCID__SDMA_TRAP, 1836 &adev->sdma.trap_irq); 1837 if (r) 1838 return r; 1839 } 1840 1841 /* SDMA SRAM ECC event */ 1842 for (i = 0; i < adev->sdma.num_instances; i++) { 1843 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1844 SDMA0_4_0__SRCID__SDMA_SRAM_ECC, 1845 &adev->sdma.ecc_irq); 1846 if (r) 1847 return r; 1848 } 1849 1850 /* SDMA VM_HOLE/DOORBELL_INV/POLL_TIMEOUT/SRBM_WRITE_PROTECTION event*/ 1851 for (i = 0; i < adev->sdma.num_instances; i++) { 1852 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1853 SDMA0_4_0__SRCID__SDMA_VM_HOLE, 1854 &adev->sdma.vm_hole_irq); 1855 if (r) 1856 return r; 1857 1858 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1859 SDMA0_4_0__SRCID__SDMA_DOORBELL_INVALID, 1860 &adev->sdma.doorbell_invalid_irq); 1861 if (r) 1862 return r; 1863 1864 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1865 SDMA0_4_0__SRCID__SDMA_POLL_TIMEOUT, 1866 &adev->sdma.pool_timeout_irq); 1867 if (r) 1868 return r; 1869 1870 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1871 SDMA0_4_0__SRCID__SDMA_SRBMWRITE, 1872 &adev->sdma.srbm_write_irq); 1873 if (r) 1874 return r; 1875 } 1876 1877 for (i = 0; i < adev->sdma.num_instances; i++) { 1878 ring = &adev->sdma.instance[i].ring; 1879 ring->ring_obj = NULL; 1880 ring->use_doorbell = true; 1881 1882 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1883 ring->use_doorbell?"true":"false"); 1884 1885 /* doorbell size is 2 dwords, get DWORD offset */ 1886 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1; 1887 1888 sprintf(ring->name, "sdma%d", i); 1889 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1890 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1891 AMDGPU_RING_PRIO_DEFAULT, NULL); 1892 if (r) 1893 return r; 1894 1895 if (adev->sdma.has_page_queue) { 1896 ring = &adev->sdma.instance[i].page; 1897 ring->ring_obj = NULL; 1898 ring->use_doorbell = true; 1899 1900 /* paging queue use same doorbell index/routing as gfx queue 1901 * with 0x400 (4096 dwords) offset on second doorbell page 1902 */ 1903 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1; 1904 ring->doorbell_index += 0x400; 1905 1906 sprintf(ring->name, "page%d", i); 1907 r = amdgpu_ring_init(adev, ring, 1024, 1908 &adev->sdma.trap_irq, 1909 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1910 AMDGPU_RING_PRIO_DEFAULT, NULL); 1911 if (r) 1912 return r; 1913 } 1914 } 1915 1916 return r; 1917 } 1918 1919 static int sdma_v4_0_sw_fini(void *handle) 1920 { 1921 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1922 int i; 1923 1924 for (i = 0; i < adev->sdma.num_instances; i++) { 1925 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1926 if (adev->sdma.has_page_queue) 1927 amdgpu_ring_fini(&adev->sdma.instance[i].page); 1928 } 1929 1930 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 0) || 1931 adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 0)) 1932 amdgpu_sdma_destroy_inst_ctx(adev, true); 1933 else 1934 amdgpu_sdma_destroy_inst_ctx(adev, false); 1935 1936 return 0; 1937 } 1938 1939 static int sdma_v4_0_hw_init(void *handle) 1940 { 1941 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1942 1943 if (adev->flags & AMD_IS_APU) 1944 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false); 1945 1946 if (!amdgpu_sriov_vf(adev)) 1947 sdma_v4_0_init_golden_registers(adev); 1948 1949 return sdma_v4_0_start(adev); 1950 } 1951 1952 static int sdma_v4_0_hw_fini(void *handle) 1953 { 1954 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1955 int i; 1956 1957 if (amdgpu_sriov_vf(adev)) 1958 return 0; 1959 1960 for (i = 0; i < adev->sdma.num_instances; i++) { 1961 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, 1962 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 1963 } 1964 1965 sdma_v4_0_ctx_switch_enable(adev, false); 1966 sdma_v4_0_enable(adev, false); 1967 1968 if (adev->flags & AMD_IS_APU) 1969 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true); 1970 1971 return 0; 1972 } 1973 1974 static int sdma_v4_0_suspend(void *handle) 1975 { 1976 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1977 1978 /* SMU saves SDMA state for us */ 1979 if (adev->in_s0ix) 1980 return 0; 1981 1982 return sdma_v4_0_hw_fini(adev); 1983 } 1984 1985 static int sdma_v4_0_resume(void *handle) 1986 { 1987 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1988 1989 /* SMU restores SDMA state for us */ 1990 if (adev->in_s0ix) 1991 return 0; 1992 1993 return sdma_v4_0_hw_init(adev); 1994 } 1995 1996 static bool sdma_v4_0_is_idle(void *handle) 1997 { 1998 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1999 u32 i; 2000 2001 for (i = 0; i < adev->sdma.num_instances; i++) { 2002 u32 tmp = RREG32_SDMA(i, mmSDMA0_STATUS_REG); 2003 2004 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 2005 return false; 2006 } 2007 2008 return true; 2009 } 2010 2011 static int sdma_v4_0_wait_for_idle(void *handle) 2012 { 2013 unsigned i, j; 2014 u32 sdma[AMDGPU_MAX_SDMA_INSTANCES]; 2015 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2016 2017 for (i = 0; i < adev->usec_timeout; i++) { 2018 for (j = 0; j < adev->sdma.num_instances; j++) { 2019 sdma[j] = RREG32_SDMA(j, mmSDMA0_STATUS_REG); 2020 if (!(sdma[j] & SDMA0_STATUS_REG__IDLE_MASK)) 2021 break; 2022 } 2023 if (j == adev->sdma.num_instances) 2024 return 0; 2025 udelay(1); 2026 } 2027 return -ETIMEDOUT; 2028 } 2029 2030 static int sdma_v4_0_soft_reset(void *handle) 2031 { 2032 /* todo */ 2033 2034 return 0; 2035 } 2036 2037 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev, 2038 struct amdgpu_irq_src *source, 2039 unsigned type, 2040 enum amdgpu_interrupt_state state) 2041 { 2042 u32 sdma_cntl; 2043 2044 sdma_cntl = RREG32_SDMA(type, mmSDMA0_CNTL); 2045 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 2046 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2047 WREG32_SDMA(type, mmSDMA0_CNTL, sdma_cntl); 2048 2049 return 0; 2050 } 2051 2052 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev, 2053 struct amdgpu_irq_src *source, 2054 struct amdgpu_iv_entry *entry) 2055 { 2056 uint32_t instance; 2057 2058 DRM_DEBUG("IH: SDMA trap\n"); 2059 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 2060 switch (entry->ring_id) { 2061 case 0: 2062 amdgpu_fence_process(&adev->sdma.instance[instance].ring); 2063 break; 2064 case 1: 2065 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 0)) 2066 amdgpu_fence_process(&adev->sdma.instance[instance].page); 2067 break; 2068 case 2: 2069 /* XXX compute */ 2070 break; 2071 case 3: 2072 if (adev->ip_versions[SDMA0_HWIP][0] != IP_VERSION(4, 2, 0)) 2073 amdgpu_fence_process(&adev->sdma.instance[instance].page); 2074 break; 2075 } 2076 return 0; 2077 } 2078 2079 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev, 2080 void *err_data, 2081 struct amdgpu_iv_entry *entry) 2082 { 2083 int instance; 2084 2085 /* When “Full RAS” is enabled, the per-IP interrupt sources should 2086 * be disabled and the driver should only look for the aggregated 2087 * interrupt via sync flood 2088 */ 2089 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 2090 goto out; 2091 2092 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 2093 if (instance < 0) 2094 goto out; 2095 2096 amdgpu_sdma_process_ras_data_cb(adev, err_data, entry); 2097 2098 out: 2099 return AMDGPU_RAS_SUCCESS; 2100 } 2101 2102 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev, 2103 struct amdgpu_irq_src *source, 2104 struct amdgpu_iv_entry *entry) 2105 { 2106 int instance; 2107 2108 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 2109 2110 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 2111 if (instance < 0) 2112 return 0; 2113 2114 switch (entry->ring_id) { 2115 case 0: 2116 drm_sched_fault(&adev->sdma.instance[instance].ring.sched); 2117 break; 2118 } 2119 return 0; 2120 } 2121 2122 static int sdma_v4_0_set_ecc_irq_state(struct amdgpu_device *adev, 2123 struct amdgpu_irq_src *source, 2124 unsigned type, 2125 enum amdgpu_interrupt_state state) 2126 { 2127 u32 sdma_edc_config; 2128 2129 sdma_edc_config = RREG32_SDMA(type, mmSDMA0_EDC_CONFIG); 2130 sdma_edc_config = REG_SET_FIELD(sdma_edc_config, SDMA0_EDC_CONFIG, ECC_INT_ENABLE, 2131 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2132 WREG32_SDMA(type, mmSDMA0_EDC_CONFIG, sdma_edc_config); 2133 2134 return 0; 2135 } 2136 2137 static int sdma_v4_0_print_iv_entry(struct amdgpu_device *adev, 2138 struct amdgpu_iv_entry *entry) 2139 { 2140 int instance; 2141 struct amdgpu_task_info task_info; 2142 u64 addr; 2143 2144 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 2145 if (instance < 0 || instance >= adev->sdma.num_instances) { 2146 dev_err(adev->dev, "sdma instance invalid %d\n", instance); 2147 return -EINVAL; 2148 } 2149 2150 addr = (u64)entry->src_data[0] << 12; 2151 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 2152 2153 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 2154 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 2155 2156 dev_dbg_ratelimited(adev->dev, 2157 "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u " 2158 "pasid:%u, for process %s pid %d thread %s pid %d\n", 2159 instance, addr, entry->src_id, entry->ring_id, entry->vmid, 2160 entry->pasid, task_info.process_name, task_info.tgid, 2161 task_info.task_name, task_info.pid); 2162 return 0; 2163 } 2164 2165 static int sdma_v4_0_process_vm_hole_irq(struct amdgpu_device *adev, 2166 struct amdgpu_irq_src *source, 2167 struct amdgpu_iv_entry *entry) 2168 { 2169 dev_dbg_ratelimited(adev->dev, "MC or SEM address in VM hole\n"); 2170 sdma_v4_0_print_iv_entry(adev, entry); 2171 return 0; 2172 } 2173 2174 static int sdma_v4_0_process_doorbell_invalid_irq(struct amdgpu_device *adev, 2175 struct amdgpu_irq_src *source, 2176 struct amdgpu_iv_entry *entry) 2177 { 2178 dev_dbg_ratelimited(adev->dev, "SDMA received a doorbell from BIF with byte_enable !=0xff\n"); 2179 sdma_v4_0_print_iv_entry(adev, entry); 2180 return 0; 2181 } 2182 2183 static int sdma_v4_0_process_pool_timeout_irq(struct amdgpu_device *adev, 2184 struct amdgpu_irq_src *source, 2185 struct amdgpu_iv_entry *entry) 2186 { 2187 dev_dbg_ratelimited(adev->dev, 2188 "Polling register/memory timeout executing POLL_REG/MEM with finite timer\n"); 2189 sdma_v4_0_print_iv_entry(adev, entry); 2190 return 0; 2191 } 2192 2193 static int sdma_v4_0_process_srbm_write_irq(struct amdgpu_device *adev, 2194 struct amdgpu_irq_src *source, 2195 struct amdgpu_iv_entry *entry) 2196 { 2197 dev_dbg_ratelimited(adev->dev, 2198 "SDMA gets an Register Write SRBM_WRITE command in non-privilege command buffer\n"); 2199 sdma_v4_0_print_iv_entry(adev, entry); 2200 return 0; 2201 } 2202 2203 static void sdma_v4_0_update_medium_grain_clock_gating( 2204 struct amdgpu_device *adev, 2205 bool enable) 2206 { 2207 uint32_t data, def; 2208 int i; 2209 2210 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 2211 for (i = 0; i < adev->sdma.num_instances; i++) { 2212 def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL); 2213 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 2214 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 2215 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 2216 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 2217 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 2218 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 2219 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 2220 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 2221 if (def != data) 2222 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data); 2223 } 2224 } else { 2225 for (i = 0; i < adev->sdma.num_instances; i++) { 2226 def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL); 2227 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 2228 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 2229 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 2230 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 2231 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 2232 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 2233 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 2234 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 2235 if (def != data) 2236 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data); 2237 } 2238 } 2239 } 2240 2241 2242 static void sdma_v4_0_update_medium_grain_light_sleep( 2243 struct amdgpu_device *adev, 2244 bool enable) 2245 { 2246 uint32_t data, def; 2247 int i; 2248 2249 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 2250 for (i = 0; i < adev->sdma.num_instances; i++) { 2251 /* 1-not override: enable sdma mem light sleep */ 2252 def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL); 2253 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 2254 if (def != data) 2255 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data); 2256 } 2257 } else { 2258 for (i = 0; i < adev->sdma.num_instances; i++) { 2259 /* 0-override:disable sdma mem light sleep */ 2260 def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL); 2261 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 2262 if (def != data) 2263 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data); 2264 } 2265 } 2266 } 2267 2268 static int sdma_v4_0_set_clockgating_state(void *handle, 2269 enum amd_clockgating_state state) 2270 { 2271 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2272 2273 if (amdgpu_sriov_vf(adev)) 2274 return 0; 2275 2276 sdma_v4_0_update_medium_grain_clock_gating(adev, 2277 state == AMD_CG_STATE_GATE); 2278 sdma_v4_0_update_medium_grain_light_sleep(adev, 2279 state == AMD_CG_STATE_GATE); 2280 return 0; 2281 } 2282 2283 static int sdma_v4_0_set_powergating_state(void *handle, 2284 enum amd_powergating_state state) 2285 { 2286 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2287 2288 switch (adev->ip_versions[SDMA0_HWIP][0]) { 2289 case IP_VERSION(4, 1, 0): 2290 case IP_VERSION(4, 1, 1): 2291 case IP_VERSION(4, 1, 2): 2292 sdma_v4_1_update_power_gating(adev, 2293 state == AMD_PG_STATE_GATE); 2294 break; 2295 default: 2296 break; 2297 } 2298 2299 return 0; 2300 } 2301 2302 static void sdma_v4_0_get_clockgating_state(void *handle, u64 *flags) 2303 { 2304 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2305 int data; 2306 2307 if (amdgpu_sriov_vf(adev)) 2308 *flags = 0; 2309 2310 /* AMD_CG_SUPPORT_SDMA_MGCG */ 2311 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 2312 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK)) 2313 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 2314 2315 /* AMD_CG_SUPPORT_SDMA_LS */ 2316 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 2317 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 2318 *flags |= AMD_CG_SUPPORT_SDMA_LS; 2319 } 2320 2321 const struct amd_ip_funcs sdma_v4_0_ip_funcs = { 2322 .name = "sdma_v4_0", 2323 .early_init = sdma_v4_0_early_init, 2324 .late_init = sdma_v4_0_late_init, 2325 .sw_init = sdma_v4_0_sw_init, 2326 .sw_fini = sdma_v4_0_sw_fini, 2327 .hw_init = sdma_v4_0_hw_init, 2328 .hw_fini = sdma_v4_0_hw_fini, 2329 .suspend = sdma_v4_0_suspend, 2330 .resume = sdma_v4_0_resume, 2331 .is_idle = sdma_v4_0_is_idle, 2332 .wait_for_idle = sdma_v4_0_wait_for_idle, 2333 .soft_reset = sdma_v4_0_soft_reset, 2334 .set_clockgating_state = sdma_v4_0_set_clockgating_state, 2335 .set_powergating_state = sdma_v4_0_set_powergating_state, 2336 .get_clockgating_state = sdma_v4_0_get_clockgating_state, 2337 }; 2338 2339 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = { 2340 .type = AMDGPU_RING_TYPE_SDMA, 2341 .align_mask = 0xf, 2342 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2343 .support_64bit_ptrs = true, 2344 .secure_submission_supported = true, 2345 .vmhub = AMDGPU_MMHUB_0, 2346 .get_rptr = sdma_v4_0_ring_get_rptr, 2347 .get_wptr = sdma_v4_0_ring_get_wptr, 2348 .set_wptr = sdma_v4_0_ring_set_wptr, 2349 .emit_frame_size = 2350 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2351 3 + /* hdp invalidate */ 2352 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2353 /* sdma_v4_0_ring_emit_vm_flush */ 2354 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2355 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2356 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2357 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2358 .emit_ib = sdma_v4_0_ring_emit_ib, 2359 .emit_fence = sdma_v4_0_ring_emit_fence, 2360 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2361 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2362 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2363 .test_ring = sdma_v4_0_ring_test_ring, 2364 .test_ib = sdma_v4_0_ring_test_ib, 2365 .insert_nop = sdma_v4_0_ring_insert_nop, 2366 .pad_ib = sdma_v4_0_ring_pad_ib, 2367 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2368 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2369 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2370 }; 2371 2372 /* 2373 * On Arcturus, SDMA instance 5~7 has a different vmhub type(AMDGPU_MMHUB_1). 2374 * So create a individual constant ring_funcs for those instances. 2375 */ 2376 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs_2nd_mmhub = { 2377 .type = AMDGPU_RING_TYPE_SDMA, 2378 .align_mask = 0xf, 2379 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2380 .support_64bit_ptrs = true, 2381 .secure_submission_supported = true, 2382 .vmhub = AMDGPU_MMHUB_1, 2383 .get_rptr = sdma_v4_0_ring_get_rptr, 2384 .get_wptr = sdma_v4_0_ring_get_wptr, 2385 .set_wptr = sdma_v4_0_ring_set_wptr, 2386 .emit_frame_size = 2387 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2388 3 + /* hdp invalidate */ 2389 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2390 /* sdma_v4_0_ring_emit_vm_flush */ 2391 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2392 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2393 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2394 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2395 .emit_ib = sdma_v4_0_ring_emit_ib, 2396 .emit_fence = sdma_v4_0_ring_emit_fence, 2397 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2398 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2399 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2400 .test_ring = sdma_v4_0_ring_test_ring, 2401 .test_ib = sdma_v4_0_ring_test_ib, 2402 .insert_nop = sdma_v4_0_ring_insert_nop, 2403 .pad_ib = sdma_v4_0_ring_pad_ib, 2404 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2405 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2406 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2407 }; 2408 2409 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = { 2410 .type = AMDGPU_RING_TYPE_SDMA, 2411 .align_mask = 0xf, 2412 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2413 .support_64bit_ptrs = true, 2414 .secure_submission_supported = true, 2415 .vmhub = AMDGPU_MMHUB_0, 2416 .get_rptr = sdma_v4_0_ring_get_rptr, 2417 .get_wptr = sdma_v4_0_page_ring_get_wptr, 2418 .set_wptr = sdma_v4_0_page_ring_set_wptr, 2419 .emit_frame_size = 2420 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2421 3 + /* hdp invalidate */ 2422 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2423 /* sdma_v4_0_ring_emit_vm_flush */ 2424 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2425 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2426 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2427 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2428 .emit_ib = sdma_v4_0_ring_emit_ib, 2429 .emit_fence = sdma_v4_0_ring_emit_fence, 2430 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2431 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2432 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2433 .test_ring = sdma_v4_0_ring_test_ring, 2434 .test_ib = sdma_v4_0_ring_test_ib, 2435 .insert_nop = sdma_v4_0_ring_insert_nop, 2436 .pad_ib = sdma_v4_0_ring_pad_ib, 2437 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2438 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2439 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2440 }; 2441 2442 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs_2nd_mmhub = { 2443 .type = AMDGPU_RING_TYPE_SDMA, 2444 .align_mask = 0xf, 2445 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2446 .support_64bit_ptrs = true, 2447 .secure_submission_supported = true, 2448 .vmhub = AMDGPU_MMHUB_1, 2449 .get_rptr = sdma_v4_0_ring_get_rptr, 2450 .get_wptr = sdma_v4_0_page_ring_get_wptr, 2451 .set_wptr = sdma_v4_0_page_ring_set_wptr, 2452 .emit_frame_size = 2453 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2454 3 + /* hdp invalidate */ 2455 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2456 /* sdma_v4_0_ring_emit_vm_flush */ 2457 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2458 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2459 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2460 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2461 .emit_ib = sdma_v4_0_ring_emit_ib, 2462 .emit_fence = sdma_v4_0_ring_emit_fence, 2463 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2464 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2465 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2466 .test_ring = sdma_v4_0_ring_test_ring, 2467 .test_ib = sdma_v4_0_ring_test_ib, 2468 .insert_nop = sdma_v4_0_ring_insert_nop, 2469 .pad_ib = sdma_v4_0_ring_pad_ib, 2470 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2471 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2472 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2473 }; 2474 2475 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev) 2476 { 2477 int i; 2478 2479 for (i = 0; i < adev->sdma.num_instances; i++) { 2480 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) && i >= 5) 2481 adev->sdma.instance[i].ring.funcs = 2482 &sdma_v4_0_ring_funcs_2nd_mmhub; 2483 else 2484 adev->sdma.instance[i].ring.funcs = 2485 &sdma_v4_0_ring_funcs; 2486 adev->sdma.instance[i].ring.me = i; 2487 if (adev->sdma.has_page_queue) { 2488 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) && i >= 5) 2489 adev->sdma.instance[i].page.funcs = 2490 &sdma_v4_0_page_ring_funcs_2nd_mmhub; 2491 else 2492 adev->sdma.instance[i].page.funcs = 2493 &sdma_v4_0_page_ring_funcs; 2494 adev->sdma.instance[i].page.me = i; 2495 } 2496 } 2497 } 2498 2499 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = { 2500 .set = sdma_v4_0_set_trap_irq_state, 2501 .process = sdma_v4_0_process_trap_irq, 2502 }; 2503 2504 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = { 2505 .process = sdma_v4_0_process_illegal_inst_irq, 2506 }; 2507 2508 static const struct amdgpu_irq_src_funcs sdma_v4_0_ecc_irq_funcs = { 2509 .set = sdma_v4_0_set_ecc_irq_state, 2510 .process = amdgpu_sdma_process_ecc_irq, 2511 }; 2512 2513 static const struct amdgpu_irq_src_funcs sdma_v4_0_vm_hole_irq_funcs = { 2514 .process = sdma_v4_0_process_vm_hole_irq, 2515 }; 2516 2517 static const struct amdgpu_irq_src_funcs sdma_v4_0_doorbell_invalid_irq_funcs = { 2518 .process = sdma_v4_0_process_doorbell_invalid_irq, 2519 }; 2520 2521 static const struct amdgpu_irq_src_funcs sdma_v4_0_pool_timeout_irq_funcs = { 2522 .process = sdma_v4_0_process_pool_timeout_irq, 2523 }; 2524 2525 static const struct amdgpu_irq_src_funcs sdma_v4_0_srbm_write_irq_funcs = { 2526 .process = sdma_v4_0_process_srbm_write_irq, 2527 }; 2528 2529 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev) 2530 { 2531 adev->sdma.trap_irq.num_types = adev->sdma.num_instances; 2532 adev->sdma.ecc_irq.num_types = adev->sdma.num_instances; 2533 /*For Arcturus and Aldebaran, add another 4 irq handler*/ 2534 switch (adev->sdma.num_instances) { 2535 case 5: 2536 case 8: 2537 adev->sdma.vm_hole_irq.num_types = adev->sdma.num_instances; 2538 adev->sdma.doorbell_invalid_irq.num_types = adev->sdma.num_instances; 2539 adev->sdma.pool_timeout_irq.num_types = adev->sdma.num_instances; 2540 adev->sdma.srbm_write_irq.num_types = adev->sdma.num_instances; 2541 break; 2542 default: 2543 break; 2544 } 2545 adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs; 2546 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs; 2547 adev->sdma.ecc_irq.funcs = &sdma_v4_0_ecc_irq_funcs; 2548 adev->sdma.vm_hole_irq.funcs = &sdma_v4_0_vm_hole_irq_funcs; 2549 adev->sdma.doorbell_invalid_irq.funcs = &sdma_v4_0_doorbell_invalid_irq_funcs; 2550 adev->sdma.pool_timeout_irq.funcs = &sdma_v4_0_pool_timeout_irq_funcs; 2551 adev->sdma.srbm_write_irq.funcs = &sdma_v4_0_srbm_write_irq_funcs; 2552 } 2553 2554 /** 2555 * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine 2556 * 2557 * @ib: indirect buffer to copy to 2558 * @src_offset: src GPU address 2559 * @dst_offset: dst GPU address 2560 * @byte_count: number of bytes to xfer 2561 * @tmz: if a secure copy should be used 2562 * 2563 * Copy GPU buffers using the DMA engine (VEGA10/12). 2564 * Used by the amdgpu ttm implementation to move pages if 2565 * registered as the asic copy callback. 2566 */ 2567 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib, 2568 uint64_t src_offset, 2569 uint64_t dst_offset, 2570 uint32_t byte_count, 2571 bool tmz) 2572 { 2573 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 2574 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 2575 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0); 2576 ib->ptr[ib->length_dw++] = byte_count - 1; 2577 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 2578 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 2579 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 2580 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2581 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2582 } 2583 2584 /** 2585 * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine 2586 * 2587 * @ib: indirect buffer to copy to 2588 * @src_data: value to write to buffer 2589 * @dst_offset: dst GPU address 2590 * @byte_count: number of bytes to xfer 2591 * 2592 * Fill GPU buffers using the DMA engine (VEGA10/12). 2593 */ 2594 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib, 2595 uint32_t src_data, 2596 uint64_t dst_offset, 2597 uint32_t byte_count) 2598 { 2599 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 2600 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2601 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2602 ib->ptr[ib->length_dw++] = src_data; 2603 ib->ptr[ib->length_dw++] = byte_count - 1; 2604 } 2605 2606 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = { 2607 .copy_max_bytes = 0x400000, 2608 .copy_num_dw = 7, 2609 .emit_copy_buffer = sdma_v4_0_emit_copy_buffer, 2610 2611 .fill_max_bytes = 0x400000, 2612 .fill_num_dw = 5, 2613 .emit_fill_buffer = sdma_v4_0_emit_fill_buffer, 2614 }; 2615 2616 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev) 2617 { 2618 adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs; 2619 if (adev->sdma.has_page_queue) 2620 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page; 2621 else 2622 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 2623 } 2624 2625 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = { 2626 .copy_pte_num_dw = 7, 2627 .copy_pte = sdma_v4_0_vm_copy_pte, 2628 2629 .write_pte = sdma_v4_0_vm_write_pte, 2630 .set_pte_pde = sdma_v4_0_vm_set_pte_pde, 2631 }; 2632 2633 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev) 2634 { 2635 struct drm_gpu_scheduler *sched; 2636 unsigned i; 2637 2638 adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs; 2639 for (i = 0; i < adev->sdma.num_instances; i++) { 2640 if (adev->sdma.has_page_queue) 2641 sched = &adev->sdma.instance[i].page.sched; 2642 else 2643 sched = &adev->sdma.instance[i].ring.sched; 2644 adev->vm_manager.vm_pte_scheds[i] = sched; 2645 } 2646 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 2647 } 2648 2649 static void sdma_v4_0_get_ras_error_count(uint32_t value, 2650 uint32_t instance, 2651 uint32_t *sec_count) 2652 { 2653 uint32_t i; 2654 uint32_t sec_cnt; 2655 2656 /* double bits error (multiple bits) error detection is not supported */ 2657 for (i = 0; i < ARRAY_SIZE(sdma_v4_0_ras_fields); i++) { 2658 /* the SDMA_EDC_COUNTER register in each sdma instance 2659 * shares the same sed shift_mask 2660 * */ 2661 sec_cnt = (value & 2662 sdma_v4_0_ras_fields[i].sec_count_mask) >> 2663 sdma_v4_0_ras_fields[i].sec_count_shift; 2664 if (sec_cnt) { 2665 DRM_INFO("Detected %s in SDMA%d, SED %d\n", 2666 sdma_v4_0_ras_fields[i].name, 2667 instance, sec_cnt); 2668 *sec_count += sec_cnt; 2669 } 2670 } 2671 } 2672 2673 static int sdma_v4_0_query_ras_error_count_by_instance(struct amdgpu_device *adev, 2674 uint32_t instance, void *ras_error_status) 2675 { 2676 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 2677 uint32_t sec_count = 0; 2678 uint32_t reg_value = 0; 2679 2680 reg_value = RREG32_SDMA(instance, mmSDMA0_EDC_COUNTER); 2681 /* double bit error is not supported */ 2682 if (reg_value) 2683 sdma_v4_0_get_ras_error_count(reg_value, 2684 instance, &sec_count); 2685 /* err_data->ce_count should be initialized to 0 2686 * before calling into this function */ 2687 err_data->ce_count += sec_count; 2688 /* double bit error is not supported 2689 * set ue count to 0 */ 2690 err_data->ue_count = 0; 2691 2692 return 0; 2693 }; 2694 2695 static void sdma_v4_0_query_ras_error_count(struct amdgpu_device *adev, void *ras_error_status) 2696 { 2697 int i = 0; 2698 2699 for (i = 0; i < adev->sdma.num_instances; i++) { 2700 if (sdma_v4_0_query_ras_error_count_by_instance(adev, i, ras_error_status)) { 2701 dev_err(adev->dev, "Query ras error count failed in SDMA%d\n", i); 2702 return; 2703 } 2704 } 2705 } 2706 2707 static void sdma_v4_0_reset_ras_error_count(struct amdgpu_device *adev) 2708 { 2709 int i; 2710 2711 /* read back edc counter registers to clear the counters */ 2712 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 2713 for (i = 0; i < adev->sdma.num_instances; i++) 2714 RREG32_SDMA(i, mmSDMA0_EDC_COUNTER); 2715 } 2716 } 2717 2718 const struct amdgpu_ras_block_hw_ops sdma_v4_0_ras_hw_ops = { 2719 .query_ras_error_count = sdma_v4_0_query_ras_error_count, 2720 .reset_ras_error_count = sdma_v4_0_reset_ras_error_count, 2721 }; 2722 2723 static struct amdgpu_sdma_ras sdma_v4_0_ras = { 2724 .ras_block = { 2725 .hw_ops = &sdma_v4_0_ras_hw_ops, 2726 .ras_cb = sdma_v4_0_process_ras_data_cb, 2727 }, 2728 }; 2729 2730 static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev) 2731 { 2732 switch (adev->ip_versions[SDMA0_HWIP][0]) { 2733 case IP_VERSION(4, 2, 0): 2734 case IP_VERSION(4, 2, 2): 2735 adev->sdma.ras = &sdma_v4_0_ras; 2736 break; 2737 case IP_VERSION(4, 4, 0): 2738 adev->sdma.ras = &sdma_v4_4_ras; 2739 break; 2740 default: 2741 break; 2742 } 2743 2744 if (adev->sdma.ras) { 2745 amdgpu_ras_register_ras_block(adev, &adev->sdma.ras->ras_block); 2746 2747 strcpy(adev->sdma.ras->ras_block.ras_comm.name, "sdma"); 2748 adev->sdma.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__SDMA; 2749 adev->sdma.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; 2750 adev->sdma.ras_if = &adev->sdma.ras->ras_block.ras_comm; 2751 2752 /* If don't define special ras_late_init function, use default ras_late_init */ 2753 if (!adev->sdma.ras->ras_block.ras_late_init) 2754 adev->sdma.ras->ras_block.ras_late_init = amdgpu_sdma_ras_late_init; 2755 2756 /* If not defined special ras_cb function, use default ras_cb */ 2757 if (!adev->sdma.ras->ras_block.ras_cb) 2758 adev->sdma.ras->ras_block.ras_cb = amdgpu_sdma_process_ras_data_cb; 2759 } 2760 } 2761 2762 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = { 2763 .type = AMD_IP_BLOCK_TYPE_SDMA, 2764 .major = 4, 2765 .minor = 0, 2766 .rev = 0, 2767 .funcs = &sdma_v4_0_ip_funcs, 2768 }; 2769