1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "sdma0/sdma0_4_2_offset.h" 34 #include "sdma0/sdma0_4_2_sh_mask.h" 35 #include "sdma1/sdma1_4_2_offset.h" 36 #include "sdma1/sdma1_4_2_sh_mask.h" 37 #include "sdma2/sdma2_4_2_2_offset.h" 38 #include "sdma2/sdma2_4_2_2_sh_mask.h" 39 #include "sdma3/sdma3_4_2_2_offset.h" 40 #include "sdma3/sdma3_4_2_2_sh_mask.h" 41 #include "sdma4/sdma4_4_2_2_offset.h" 42 #include "sdma4/sdma4_4_2_2_sh_mask.h" 43 #include "sdma5/sdma5_4_2_2_offset.h" 44 #include "sdma5/sdma5_4_2_2_sh_mask.h" 45 #include "sdma6/sdma6_4_2_2_offset.h" 46 #include "sdma6/sdma6_4_2_2_sh_mask.h" 47 #include "sdma7/sdma7_4_2_2_offset.h" 48 #include "sdma7/sdma7_4_2_2_sh_mask.h" 49 #include "sdma0/sdma0_4_1_default.h" 50 51 #include "soc15_common.h" 52 #include "soc15.h" 53 #include "vega10_sdma_pkt_open.h" 54 55 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h" 56 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h" 57 58 #include "amdgpu_ras.h" 59 60 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin"); 61 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin"); 62 MODULE_FIRMWARE("amdgpu/vega12_sdma.bin"); 63 MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin"); 64 MODULE_FIRMWARE("amdgpu/vega20_sdma.bin"); 65 MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin"); 66 MODULE_FIRMWARE("amdgpu/raven_sdma.bin"); 67 MODULE_FIRMWARE("amdgpu/picasso_sdma.bin"); 68 MODULE_FIRMWARE("amdgpu/raven2_sdma.bin"); 69 MODULE_FIRMWARE("amdgpu/arcturus_sdma.bin"); 70 MODULE_FIRMWARE("amdgpu/renoir_sdma.bin"); 71 MODULE_FIRMWARE("amdgpu/green_sardine_sdma.bin"); 72 73 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L 74 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L 75 76 #define WREG32_SDMA(instance, offset, value) \ 77 WREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)), value) 78 #define RREG32_SDMA(instance, offset) \ 79 RREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset))) 80 81 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev); 82 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev); 83 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev); 84 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev); 85 static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev); 86 87 static const struct soc15_reg_golden golden_settings_sdma_4[] = { 88 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 89 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100), 90 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100), 91 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 92 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 93 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 94 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000), 95 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 96 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 97 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 98 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 99 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 100 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000), 101 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), 102 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100), 103 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 104 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 105 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 106 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000), 107 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 108 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 109 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 110 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 111 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0), 112 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xfc000000, 0x00000000) 113 }; 114 115 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = { 116 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 117 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 118 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 119 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 120 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 121 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 122 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 123 }; 124 125 static const struct soc15_reg_golden golden_settings_sdma_vg12[] = { 126 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), 127 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001), 128 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 129 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 130 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), 131 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001), 132 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 133 }; 134 135 static const struct soc15_reg_golden golden_settings_sdma_4_1[] = { 136 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 137 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 138 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100), 139 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 140 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051), 141 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100), 142 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 143 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100), 144 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 145 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 146 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000) 147 }; 148 149 static const struct soc15_reg_golden golden_settings_sdma0_4_2_init[] = { 150 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 151 }; 152 153 static const struct soc15_reg_golden golden_settings_sdma0_4_2[] = 154 { 155 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 156 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 157 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 158 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 159 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 160 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 161 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 162 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 163 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RD_BURST_CNTL, 0x0000000f, 0x00000003), 164 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 165 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 166 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 167 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 168 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 169 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 170 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 171 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 172 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 173 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 174 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 175 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 176 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 177 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 178 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 179 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 180 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 181 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 182 }; 183 184 static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = { 185 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 186 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), 187 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 188 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 189 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 190 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 191 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 192 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 193 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RD_BURST_CNTL, 0x0000000f, 0x00000003), 194 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 195 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 196 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 197 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 198 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 199 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 200 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 201 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 202 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 203 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 204 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 205 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 206 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 207 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 208 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 209 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 210 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0), 211 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 212 }; 213 214 static const struct soc15_reg_golden golden_settings_sdma_rv1[] = 215 { 216 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002), 217 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002) 218 }; 219 220 static const struct soc15_reg_golden golden_settings_sdma_rv2[] = 221 { 222 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00003001), 223 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003001) 224 }; 225 226 static const struct soc15_reg_golden golden_settings_sdma_arct[] = 227 { 228 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 229 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 230 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 231 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 232 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 233 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 234 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 235 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 236 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 237 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 238 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 239 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 240 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 241 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 242 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 243 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 244 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 245 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 246 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 247 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 248 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 249 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 250 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 251 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 252 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 253 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 254 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 255 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 256 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 257 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 258 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 259 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_UTCL1_TIMEOUT, 0xffffffff, 0x00010001) 260 }; 261 262 static const struct soc15_reg_golden golden_settings_sdma_4_3[] = { 263 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 264 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 265 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002), 266 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002), 267 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 268 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003fff07, 0x40000051), 269 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 270 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 271 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 272 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x03fbe1fe) 273 }; 274 275 static const struct soc15_ras_field_entry sdma_v4_0_ras_fields[] = { 276 { "SDMA_UCODE_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 277 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UCODE_BUF_SED), 278 0, 0, 279 }, 280 { "SDMA_RB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 281 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_RB_CMD_BUF_SED), 282 0, 0, 283 }, 284 { "SDMA_IB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 285 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_IB_CMD_BUF_SED), 286 0, 0, 287 }, 288 { "SDMA_UTCL1_RD_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 289 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UTCL1_RD_FIFO_SED), 290 0, 0, 291 }, 292 { "SDMA_UTCL1_RDBST_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 293 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UTCL1_RDBST_FIFO_SED), 294 0, 0, 295 }, 296 { "SDMA_DATA_LUT_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 297 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_DATA_LUT_FIFO_SED), 298 0, 0, 299 }, 300 { "SDMA_MBANK_DATA_BUF0_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 301 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF0_SED), 302 0, 0, 303 }, 304 { "SDMA_MBANK_DATA_BUF1_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 305 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF1_SED), 306 0, 0, 307 }, 308 { "SDMA_MBANK_DATA_BUF2_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 309 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF2_SED), 310 0, 0, 311 }, 312 { "SDMA_MBANK_DATA_BUF3_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 313 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF3_SED), 314 0, 0, 315 }, 316 { "SDMA_MBANK_DATA_BUF4_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 317 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF4_SED), 318 0, 0, 319 }, 320 { "SDMA_MBANK_DATA_BUF5_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 321 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF5_SED), 322 0, 0, 323 }, 324 { "SDMA_MBANK_DATA_BUF6_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 325 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF6_SED), 326 0, 0, 327 }, 328 { "SDMA_MBANK_DATA_BUF7_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 329 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF7_SED), 330 0, 0, 331 }, 332 { "SDMA_MBANK_DATA_BUF8_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 333 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF8_SED), 334 0, 0, 335 }, 336 { "SDMA_MBANK_DATA_BUF9_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 337 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF9_SED), 338 0, 0, 339 }, 340 { "SDMA_MBANK_DATA_BUF10_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 341 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF10_SED), 342 0, 0, 343 }, 344 { "SDMA_MBANK_DATA_BUF11_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 345 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF11_SED), 346 0, 0, 347 }, 348 { "SDMA_MBANK_DATA_BUF12_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 349 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF12_SED), 350 0, 0, 351 }, 352 { "SDMA_MBANK_DATA_BUF13_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 353 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF13_SED), 354 0, 0, 355 }, 356 { "SDMA_MBANK_DATA_BUF14_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 357 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF14_SED), 358 0, 0, 359 }, 360 { "SDMA_MBANK_DATA_BUF15_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 361 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF15_SED), 362 0, 0, 363 }, 364 { "SDMA_SPLIT_DAT_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 365 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_SPLIT_DAT_BUF_SED), 366 0, 0, 367 }, 368 { "SDMA_MC_WR_ADDR_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 369 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MC_WR_ADDR_FIFO_SED), 370 0, 0, 371 }, 372 }; 373 374 static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev, 375 u32 instance, u32 offset) 376 { 377 switch (instance) { 378 case 0: 379 return (adev->reg_offset[SDMA0_HWIP][0][0] + offset); 380 case 1: 381 return (adev->reg_offset[SDMA1_HWIP][0][0] + offset); 382 case 2: 383 return (adev->reg_offset[SDMA2_HWIP][0][1] + offset); 384 case 3: 385 return (adev->reg_offset[SDMA3_HWIP][0][1] + offset); 386 case 4: 387 return (adev->reg_offset[SDMA4_HWIP][0][1] + offset); 388 case 5: 389 return (adev->reg_offset[SDMA5_HWIP][0][1] + offset); 390 case 6: 391 return (adev->reg_offset[SDMA6_HWIP][0][1] + offset); 392 case 7: 393 return (adev->reg_offset[SDMA7_HWIP][0][1] + offset); 394 default: 395 break; 396 } 397 return 0; 398 } 399 400 static unsigned sdma_v4_0_seq_to_irq_id(int seq_num) 401 { 402 switch (seq_num) { 403 case 0: 404 return SOC15_IH_CLIENTID_SDMA0; 405 case 1: 406 return SOC15_IH_CLIENTID_SDMA1; 407 case 2: 408 return SOC15_IH_CLIENTID_SDMA2; 409 case 3: 410 return SOC15_IH_CLIENTID_SDMA3; 411 case 4: 412 return SOC15_IH_CLIENTID_SDMA4; 413 case 5: 414 return SOC15_IH_CLIENTID_SDMA5; 415 case 6: 416 return SOC15_IH_CLIENTID_SDMA6; 417 case 7: 418 return SOC15_IH_CLIENTID_SDMA7; 419 default: 420 break; 421 } 422 return -EINVAL; 423 } 424 425 static int sdma_v4_0_irq_id_to_seq(unsigned client_id) 426 { 427 switch (client_id) { 428 case SOC15_IH_CLIENTID_SDMA0: 429 return 0; 430 case SOC15_IH_CLIENTID_SDMA1: 431 return 1; 432 case SOC15_IH_CLIENTID_SDMA2: 433 return 2; 434 case SOC15_IH_CLIENTID_SDMA3: 435 return 3; 436 case SOC15_IH_CLIENTID_SDMA4: 437 return 4; 438 case SOC15_IH_CLIENTID_SDMA5: 439 return 5; 440 case SOC15_IH_CLIENTID_SDMA6: 441 return 6; 442 case SOC15_IH_CLIENTID_SDMA7: 443 return 7; 444 default: 445 break; 446 } 447 return -EINVAL; 448 } 449 450 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) 451 { 452 switch (adev->asic_type) { 453 case CHIP_VEGA10: 454 soc15_program_register_sequence(adev, 455 golden_settings_sdma_4, 456 ARRAY_SIZE(golden_settings_sdma_4)); 457 soc15_program_register_sequence(adev, 458 golden_settings_sdma_vg10, 459 ARRAY_SIZE(golden_settings_sdma_vg10)); 460 break; 461 case CHIP_VEGA12: 462 soc15_program_register_sequence(adev, 463 golden_settings_sdma_4, 464 ARRAY_SIZE(golden_settings_sdma_4)); 465 soc15_program_register_sequence(adev, 466 golden_settings_sdma_vg12, 467 ARRAY_SIZE(golden_settings_sdma_vg12)); 468 break; 469 case CHIP_VEGA20: 470 soc15_program_register_sequence(adev, 471 golden_settings_sdma0_4_2_init, 472 ARRAY_SIZE(golden_settings_sdma0_4_2_init)); 473 soc15_program_register_sequence(adev, 474 golden_settings_sdma0_4_2, 475 ARRAY_SIZE(golden_settings_sdma0_4_2)); 476 soc15_program_register_sequence(adev, 477 golden_settings_sdma1_4_2, 478 ARRAY_SIZE(golden_settings_sdma1_4_2)); 479 break; 480 case CHIP_ARCTURUS: 481 soc15_program_register_sequence(adev, 482 golden_settings_sdma_arct, 483 ARRAY_SIZE(golden_settings_sdma_arct)); 484 break; 485 case CHIP_RAVEN: 486 soc15_program_register_sequence(adev, 487 golden_settings_sdma_4_1, 488 ARRAY_SIZE(golden_settings_sdma_4_1)); 489 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 490 soc15_program_register_sequence(adev, 491 golden_settings_sdma_rv2, 492 ARRAY_SIZE(golden_settings_sdma_rv2)); 493 else 494 soc15_program_register_sequence(adev, 495 golden_settings_sdma_rv1, 496 ARRAY_SIZE(golden_settings_sdma_rv1)); 497 break; 498 case CHIP_RENOIR: 499 soc15_program_register_sequence(adev, 500 golden_settings_sdma_4_3, 501 ARRAY_SIZE(golden_settings_sdma_4_3)); 502 break; 503 default: 504 break; 505 } 506 } 507 508 static void sdma_v4_0_setup_ulv(struct amdgpu_device *adev) 509 { 510 int i; 511 512 /* 513 * The only chips with SDMAv4 and ULV are VG10 and VG20. 514 * Server SKUs take a different hysteresis setting from other SKUs. 515 */ 516 switch (adev->asic_type) { 517 case CHIP_VEGA10: 518 if (adev->pdev->device == 0x6860) 519 break; 520 return; 521 case CHIP_VEGA20: 522 if (adev->pdev->device == 0x66a1) 523 break; 524 return; 525 default: 526 return; 527 } 528 529 for (i = 0; i < adev->sdma.num_instances; i++) { 530 uint32_t temp; 531 532 temp = RREG32_SDMA(i, mmSDMA0_ULV_CNTL); 533 temp = REG_SET_FIELD(temp, SDMA0_ULV_CNTL, HYSTERESIS, 0x0); 534 WREG32_SDMA(i, mmSDMA0_ULV_CNTL, temp); 535 } 536 } 537 538 static int sdma_v4_0_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst) 539 { 540 int err = 0; 541 const struct sdma_firmware_header_v1_0 *hdr; 542 543 err = amdgpu_ucode_validate(sdma_inst->fw); 544 if (err) 545 return err; 546 547 hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data; 548 sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version); 549 sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version); 550 551 if (sdma_inst->feature_version >= 20) 552 sdma_inst->burst_nop = true; 553 554 return 0; 555 } 556 557 static void sdma_v4_0_destroy_inst_ctx(struct amdgpu_device *adev) 558 { 559 int i; 560 561 for (i = 0; i < adev->sdma.num_instances; i++) { 562 release_firmware(adev->sdma.instance[i].fw); 563 adev->sdma.instance[i].fw = NULL; 564 565 /* arcturus shares the same FW memory across 566 all SDMA isntances */ 567 if (adev->asic_type == CHIP_ARCTURUS) 568 break; 569 } 570 571 memset((void *)adev->sdma.instance, 0, 572 sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES); 573 } 574 575 /** 576 * sdma_v4_0_init_microcode - load ucode images from disk 577 * 578 * @adev: amdgpu_device pointer 579 * 580 * Use the firmware interface to load the ucode images into 581 * the driver (not loaded into hw). 582 * Returns 0 on success, error on failure. 583 */ 584 585 // emulation only, won't work on real chip 586 // vega10 real chip need to use PSP to load firmware 587 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev) 588 { 589 const char *chip_name; 590 char fw_name[30]; 591 int err = 0, i; 592 struct amdgpu_firmware_info *info = NULL; 593 const struct common_firmware_header *header = NULL; 594 595 DRM_DEBUG("\n"); 596 597 switch (adev->asic_type) { 598 case CHIP_VEGA10: 599 chip_name = "vega10"; 600 break; 601 case CHIP_VEGA12: 602 chip_name = "vega12"; 603 break; 604 case CHIP_VEGA20: 605 chip_name = "vega20"; 606 break; 607 case CHIP_RAVEN: 608 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 609 chip_name = "raven2"; 610 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 611 chip_name = "picasso"; 612 else 613 chip_name = "raven"; 614 break; 615 case CHIP_ARCTURUS: 616 chip_name = "arcturus"; 617 break; 618 case CHIP_RENOIR: 619 if (adev->apu_flags & AMD_APU_IS_RENOIR) 620 chip_name = "renoir"; 621 else 622 chip_name = "green_sardine"; 623 break; 624 default: 625 BUG(); 626 } 627 628 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 629 630 err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev); 631 if (err) 632 goto out; 633 634 err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[0]); 635 if (err) 636 goto out; 637 638 for (i = 1; i < adev->sdma.num_instances; i++) { 639 if (adev->asic_type == CHIP_ARCTURUS) { 640 /* Acturus will leverage the same FW memory 641 for every SDMA instance */ 642 memcpy((void *)&adev->sdma.instance[i], 643 (void *)&adev->sdma.instance[0], 644 sizeof(struct amdgpu_sdma_instance)); 645 } 646 else { 647 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i); 648 649 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 650 if (err) 651 goto out; 652 653 err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[i]); 654 if (err) 655 goto out; 656 } 657 } 658 659 DRM_DEBUG("psp_load == '%s'\n", 660 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); 661 662 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 663 for (i = 0; i < adev->sdma.num_instances; i++) { 664 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 665 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 666 info->fw = adev->sdma.instance[i].fw; 667 header = (const struct common_firmware_header *)info->fw->data; 668 adev->firmware.fw_size += 669 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 670 } 671 } 672 673 out: 674 if (err) { 675 DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name); 676 sdma_v4_0_destroy_inst_ctx(adev); 677 } 678 return err; 679 } 680 681 /** 682 * sdma_v4_0_ring_get_rptr - get the current read pointer 683 * 684 * @ring: amdgpu ring pointer 685 * 686 * Get the current rptr from the hardware (VEGA10+). 687 */ 688 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring) 689 { 690 u64 *rptr; 691 692 /* XXX check if swapping is necessary on BE */ 693 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]); 694 695 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 696 return ((*rptr) >> 2); 697 } 698 699 /** 700 * sdma_v4_0_ring_get_wptr - get the current write pointer 701 * 702 * @ring: amdgpu ring pointer 703 * 704 * Get the current wptr from the hardware (VEGA10+). 705 */ 706 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring) 707 { 708 struct amdgpu_device *adev = ring->adev; 709 u64 wptr; 710 711 if (ring->use_doorbell) { 712 /* XXX check if swapping is necessary on BE */ 713 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 714 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 715 } else { 716 wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI); 717 wptr = wptr << 32; 718 wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR); 719 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", 720 ring->me, wptr); 721 } 722 723 return wptr >> 2; 724 } 725 726 /** 727 * sdma_v4_0_page_ring_set_wptr - commit the write pointer 728 * 729 * @ring: amdgpu ring pointer 730 * 731 * Write the wptr back to the hardware (VEGA10+). 732 */ 733 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring) 734 { 735 struct amdgpu_device *adev = ring->adev; 736 737 DRM_DEBUG("Setting write pointer\n"); 738 if (ring->use_doorbell) { 739 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 740 741 DRM_DEBUG("Using doorbell -- " 742 "wptr_offs == 0x%08x " 743 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 744 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 745 ring->wptr_offs, 746 lower_32_bits(ring->wptr << 2), 747 upper_32_bits(ring->wptr << 2)); 748 /* XXX check if swapping is necessary on BE */ 749 WRITE_ONCE(*wb, (ring->wptr << 2)); 750 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 751 ring->doorbell_index, ring->wptr << 2); 752 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 753 } else { 754 DRM_DEBUG("Not using doorbell -- " 755 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 756 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 757 ring->me, 758 lower_32_bits(ring->wptr << 2), 759 ring->me, 760 upper_32_bits(ring->wptr << 2)); 761 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR, 762 lower_32_bits(ring->wptr << 2)); 763 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI, 764 upper_32_bits(ring->wptr << 2)); 765 } 766 } 767 768 /** 769 * sdma_v4_0_page_ring_get_wptr - get the current write pointer 770 * 771 * @ring: amdgpu ring pointer 772 * 773 * Get the current wptr from the hardware (VEGA10+). 774 */ 775 static uint64_t sdma_v4_0_page_ring_get_wptr(struct amdgpu_ring *ring) 776 { 777 struct amdgpu_device *adev = ring->adev; 778 u64 wptr; 779 780 if (ring->use_doorbell) { 781 /* XXX check if swapping is necessary on BE */ 782 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 783 } else { 784 wptr = RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI); 785 wptr = wptr << 32; 786 wptr |= RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR); 787 } 788 789 return wptr >> 2; 790 } 791 792 /** 793 * sdma_v4_0_ring_set_wptr - commit the write pointer 794 * 795 * @ring: amdgpu ring pointer 796 * 797 * Write the wptr back to the hardware (VEGA10+). 798 */ 799 static void sdma_v4_0_page_ring_set_wptr(struct amdgpu_ring *ring) 800 { 801 struct amdgpu_device *adev = ring->adev; 802 803 if (ring->use_doorbell) { 804 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 805 806 /* XXX check if swapping is necessary on BE */ 807 WRITE_ONCE(*wb, (ring->wptr << 2)); 808 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 809 } else { 810 uint64_t wptr = ring->wptr << 2; 811 812 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR, 813 lower_32_bits(wptr)); 814 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI, 815 upper_32_bits(wptr)); 816 } 817 } 818 819 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 820 { 821 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 822 int i; 823 824 for (i = 0; i < count; i++) 825 if (sdma && sdma->burst_nop && (i == 0)) 826 amdgpu_ring_write(ring, ring->funcs->nop | 827 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 828 else 829 amdgpu_ring_write(ring, ring->funcs->nop); 830 } 831 832 /** 833 * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine 834 * 835 * @ring: amdgpu ring pointer 836 * @job: job to retrieve vmid from 837 * @ib: IB object to schedule 838 * @flags: unused 839 * 840 * Schedule an IB in the DMA ring (VEGA10). 841 */ 842 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring, 843 struct amdgpu_job *job, 844 struct amdgpu_ib *ib, 845 uint32_t flags) 846 { 847 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 848 849 /* IB packet must end on a 8 DW boundary */ 850 sdma_v4_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 851 852 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 853 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 854 /* base must be 32 byte aligned */ 855 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 856 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 857 amdgpu_ring_write(ring, ib->length_dw); 858 amdgpu_ring_write(ring, 0); 859 amdgpu_ring_write(ring, 0); 860 861 } 862 863 static void sdma_v4_0_wait_reg_mem(struct amdgpu_ring *ring, 864 int mem_space, int hdp, 865 uint32_t addr0, uint32_t addr1, 866 uint32_t ref, uint32_t mask, 867 uint32_t inv) 868 { 869 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 870 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) | 871 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) | 872 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 873 if (mem_space) { 874 /* memory */ 875 amdgpu_ring_write(ring, addr0); 876 amdgpu_ring_write(ring, addr1); 877 } else { 878 /* registers */ 879 amdgpu_ring_write(ring, addr0 << 2); 880 amdgpu_ring_write(ring, addr1 << 2); 881 } 882 amdgpu_ring_write(ring, ref); /* reference */ 883 amdgpu_ring_write(ring, mask); /* mask */ 884 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 885 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */ 886 } 887 888 /** 889 * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 890 * 891 * @ring: amdgpu ring pointer 892 * 893 * Emit an hdp flush packet on the requested DMA ring. 894 */ 895 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 896 { 897 struct amdgpu_device *adev = ring->adev; 898 u32 ref_and_mask = 0; 899 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 900 901 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; 902 903 sdma_v4_0_wait_reg_mem(ring, 0, 1, 904 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 905 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 906 ref_and_mask, ref_and_mask, 10); 907 } 908 909 /** 910 * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring 911 * 912 * @ring: amdgpu ring pointer 913 * @addr: address 914 * @seq: sequence number 915 * @flags: fence related flags 916 * 917 * Add a DMA fence packet to the ring to write 918 * the fence seq number and DMA trap packet to generate 919 * an interrupt if needed (VEGA10). 920 */ 921 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 922 unsigned flags) 923 { 924 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 925 /* write the fence */ 926 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 927 /* zero in first two bits */ 928 BUG_ON(addr & 0x3); 929 amdgpu_ring_write(ring, lower_32_bits(addr)); 930 amdgpu_ring_write(ring, upper_32_bits(addr)); 931 amdgpu_ring_write(ring, lower_32_bits(seq)); 932 933 /* optionally write high bits as well */ 934 if (write64bit) { 935 addr += 4; 936 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 937 /* zero in first two bits */ 938 BUG_ON(addr & 0x3); 939 amdgpu_ring_write(ring, lower_32_bits(addr)); 940 amdgpu_ring_write(ring, upper_32_bits(addr)); 941 amdgpu_ring_write(ring, upper_32_bits(seq)); 942 } 943 944 /* generate an interrupt */ 945 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 946 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 947 } 948 949 950 /** 951 * sdma_v4_0_gfx_stop - stop the gfx async dma engines 952 * 953 * @adev: amdgpu_device pointer 954 * 955 * Stop the gfx async dma ring buffers (VEGA10). 956 */ 957 static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev) 958 { 959 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; 960 u32 rb_cntl, ib_cntl; 961 int i, unset = 0; 962 963 for (i = 0; i < adev->sdma.num_instances; i++) { 964 sdma[i] = &adev->sdma.instance[i].ring; 965 966 if ((adev->mman.buffer_funcs_ring == sdma[i]) && unset != 1) { 967 amdgpu_ttm_set_buffer_funcs_status(adev, false); 968 unset = 1; 969 } 970 971 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL); 972 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 973 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 974 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL); 975 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 976 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl); 977 } 978 } 979 980 /** 981 * sdma_v4_0_rlc_stop - stop the compute async dma engines 982 * 983 * @adev: amdgpu_device pointer 984 * 985 * Stop the compute async dma queues (VEGA10). 986 */ 987 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev) 988 { 989 /* XXX todo */ 990 } 991 992 /** 993 * sdma_v4_0_page_stop - stop the page async dma engines 994 * 995 * @adev: amdgpu_device pointer 996 * 997 * Stop the page async dma ring buffers (VEGA10). 998 */ 999 static void sdma_v4_0_page_stop(struct amdgpu_device *adev) 1000 { 1001 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; 1002 u32 rb_cntl, ib_cntl; 1003 int i; 1004 bool unset = false; 1005 1006 for (i = 0; i < adev->sdma.num_instances; i++) { 1007 sdma[i] = &adev->sdma.instance[i].page; 1008 1009 if ((adev->mman.buffer_funcs_ring == sdma[i]) && 1010 (!unset)) { 1011 amdgpu_ttm_set_buffer_funcs_status(adev, false); 1012 unset = true; 1013 } 1014 1015 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL); 1016 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, 1017 RB_ENABLE, 0); 1018 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 1019 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL); 1020 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, 1021 IB_ENABLE, 0); 1022 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl); 1023 } 1024 } 1025 1026 /** 1027 * sdma_v4_0_ctx_switch_enable - stop the async dma engines context switch 1028 * 1029 * @adev: amdgpu_device pointer 1030 * @enable: enable/disable the DMA MEs context switch. 1031 * 1032 * Halt or unhalt the async dma engines context switch (VEGA10). 1033 */ 1034 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 1035 { 1036 u32 f32_cntl, phase_quantum = 0; 1037 int i; 1038 1039 if (amdgpu_sdma_phase_quantum) { 1040 unsigned value = amdgpu_sdma_phase_quantum; 1041 unsigned unit = 0; 1042 1043 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 1044 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 1045 value = (value + 1) >> 1; 1046 unit++; 1047 } 1048 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 1049 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 1050 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 1051 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 1052 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 1053 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 1054 WARN_ONCE(1, 1055 "clamping sdma_phase_quantum to %uK clock cycles\n", 1056 value << unit); 1057 } 1058 phase_quantum = 1059 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 1060 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 1061 } 1062 1063 for (i = 0; i < adev->sdma.num_instances; i++) { 1064 f32_cntl = RREG32_SDMA(i, mmSDMA0_CNTL); 1065 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 1066 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 1067 if (enable && amdgpu_sdma_phase_quantum) { 1068 WREG32_SDMA(i, mmSDMA0_PHASE0_QUANTUM, phase_quantum); 1069 WREG32_SDMA(i, mmSDMA0_PHASE1_QUANTUM, phase_quantum); 1070 WREG32_SDMA(i, mmSDMA0_PHASE2_QUANTUM, phase_quantum); 1071 } 1072 WREG32_SDMA(i, mmSDMA0_CNTL, f32_cntl); 1073 1074 /* 1075 * Enable SDMA utilization. Its only supported on 1076 * Arcturus for the moment and firmware version 14 1077 * and above. 1078 */ 1079 if (adev->asic_type == CHIP_ARCTURUS && 1080 adev->sdma.instance[i].fw_version >= 14) 1081 WREG32_SDMA(i, mmSDMA0_PUB_DUMMY_REG2, enable); 1082 } 1083 1084 } 1085 1086 /** 1087 * sdma_v4_0_enable - stop the async dma engines 1088 * 1089 * @adev: amdgpu_device pointer 1090 * @enable: enable/disable the DMA MEs. 1091 * 1092 * Halt or unhalt the async dma engines (VEGA10). 1093 */ 1094 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable) 1095 { 1096 u32 f32_cntl; 1097 int i; 1098 1099 if (!enable) { 1100 sdma_v4_0_gfx_stop(adev); 1101 sdma_v4_0_rlc_stop(adev); 1102 if (adev->sdma.has_page_queue) 1103 sdma_v4_0_page_stop(adev); 1104 } 1105 1106 for (i = 0; i < adev->sdma.num_instances; i++) { 1107 f32_cntl = RREG32_SDMA(i, mmSDMA0_F32_CNTL); 1108 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 1109 WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl); 1110 } 1111 } 1112 1113 /* 1114 * sdma_v4_0_rb_cntl - get parameters for rb_cntl 1115 */ 1116 static uint32_t sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl) 1117 { 1118 /* Set ring buffer size in dwords */ 1119 uint32_t rb_bufsz = order_base_2(ring->ring_size / 4); 1120 1121 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 1122 #ifdef __BIG_ENDIAN 1123 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 1124 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 1125 RPTR_WRITEBACK_SWAP_ENABLE, 1); 1126 #endif 1127 return rb_cntl; 1128 } 1129 1130 /** 1131 * sdma_v4_0_gfx_resume - setup and start the async dma engines 1132 * 1133 * @adev: amdgpu_device pointer 1134 * @i: instance to resume 1135 * 1136 * Set up the gfx DMA ring buffers and enable them (VEGA10). 1137 * Returns 0 for success, error for failure. 1138 */ 1139 static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i) 1140 { 1141 struct amdgpu_ring *ring = &adev->sdma.instance[i].ring; 1142 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 1143 u32 wb_offset; 1144 u32 doorbell; 1145 u32 doorbell_offset; 1146 u64 wptr_gpu_addr; 1147 1148 wb_offset = (ring->rptr_offs * 4); 1149 1150 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL); 1151 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl); 1152 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 1153 1154 /* Initialize the ring buffer's read and write pointers */ 1155 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR, 0); 1156 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_HI, 0); 1157 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR, 0); 1158 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_HI, 0); 1159 1160 /* set the wb address whether it's enabled or not */ 1161 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI, 1162 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 1163 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 1164 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 1165 1166 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 1167 RPTR_WRITEBACK_ENABLE, 1); 1168 1169 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE, ring->gpu_addr >> 8); 1170 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE_HI, ring->gpu_addr >> 40); 1171 1172 ring->wptr = 0; 1173 1174 /* before programing wptr to a less value, need set minor_ptr_update first */ 1175 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 1); 1176 1177 doorbell = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL); 1178 doorbell_offset = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET); 1179 1180 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1181 ring->use_doorbell); 1182 doorbell_offset = REG_SET_FIELD(doorbell_offset, 1183 SDMA0_GFX_DOORBELL_OFFSET, 1184 OFFSET, ring->doorbell_index); 1185 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL, doorbell); 1186 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET, doorbell_offset); 1187 1188 sdma_v4_0_ring_set_wptr(ring); 1189 1190 /* set minor_ptr_update to 0 after wptr programed */ 1191 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 0); 1192 1193 /* setup the wptr shadow polling */ 1194 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1195 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO, 1196 lower_32_bits(wptr_gpu_addr)); 1197 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI, 1198 upper_32_bits(wptr_gpu_addr)); 1199 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL); 1200 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 1201 SDMA0_GFX_RB_WPTR_POLL_CNTL, 1202 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 1203 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 1204 1205 /* enable DMA RB */ 1206 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 1207 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 1208 1209 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL); 1210 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 1211 #ifdef __BIG_ENDIAN 1212 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 1213 #endif 1214 /* enable DMA IBs */ 1215 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl); 1216 1217 ring->sched.ready = true; 1218 } 1219 1220 /** 1221 * sdma_v4_0_page_resume - setup and start the async dma engines 1222 * 1223 * @adev: amdgpu_device pointer 1224 * @i: instance to resume 1225 * 1226 * Set up the page DMA ring buffers and enable them (VEGA10). 1227 * Returns 0 for success, error for failure. 1228 */ 1229 static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i) 1230 { 1231 struct amdgpu_ring *ring = &adev->sdma.instance[i].page; 1232 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 1233 u32 wb_offset; 1234 u32 doorbell; 1235 u32 doorbell_offset; 1236 u64 wptr_gpu_addr; 1237 1238 wb_offset = (ring->rptr_offs * 4); 1239 1240 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL); 1241 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl); 1242 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 1243 1244 /* Initialize the ring buffer's read and write pointers */ 1245 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR, 0); 1246 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_HI, 0); 1247 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR, 0); 1248 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_HI, 0); 1249 1250 /* set the wb address whether it's enabled or not */ 1251 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_HI, 1252 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 1253 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 1254 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 1255 1256 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, 1257 RPTR_WRITEBACK_ENABLE, 1); 1258 1259 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE, ring->gpu_addr >> 8); 1260 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE_HI, ring->gpu_addr >> 40); 1261 1262 ring->wptr = 0; 1263 1264 /* before programing wptr to a less value, need set minor_ptr_update first */ 1265 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 1); 1266 1267 doorbell = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL); 1268 doorbell_offset = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET); 1269 1270 doorbell = REG_SET_FIELD(doorbell, SDMA0_PAGE_DOORBELL, ENABLE, 1271 ring->use_doorbell); 1272 doorbell_offset = REG_SET_FIELD(doorbell_offset, 1273 SDMA0_PAGE_DOORBELL_OFFSET, 1274 OFFSET, ring->doorbell_index); 1275 WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL, doorbell); 1276 WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET, doorbell_offset); 1277 1278 /* paging queue doorbell range is setup at sdma_v4_0_gfx_resume */ 1279 sdma_v4_0_page_ring_set_wptr(ring); 1280 1281 /* set minor_ptr_update to 0 after wptr programed */ 1282 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 0); 1283 1284 /* setup the wptr shadow polling */ 1285 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1286 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO, 1287 lower_32_bits(wptr_gpu_addr)); 1288 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI, 1289 upper_32_bits(wptr_gpu_addr)); 1290 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL); 1291 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 1292 SDMA0_PAGE_RB_WPTR_POLL_CNTL, 1293 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 1294 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 1295 1296 /* enable DMA RB */ 1297 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, RB_ENABLE, 1); 1298 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 1299 1300 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL); 1301 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_ENABLE, 1); 1302 #ifdef __BIG_ENDIAN 1303 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1); 1304 #endif 1305 /* enable DMA IBs */ 1306 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl); 1307 1308 ring->sched.ready = true; 1309 } 1310 1311 static void 1312 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable) 1313 { 1314 uint32_t def, data; 1315 1316 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) { 1317 /* enable idle interrupt */ 1318 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 1319 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 1320 1321 if (data != def) 1322 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 1323 } else { 1324 /* disable idle interrupt */ 1325 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 1326 data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 1327 if (data != def) 1328 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 1329 } 1330 } 1331 1332 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev) 1333 { 1334 uint32_t def, data; 1335 1336 /* Enable HW based PG. */ 1337 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1338 data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK; 1339 if (data != def) 1340 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1341 1342 /* enable interrupt */ 1343 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 1344 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 1345 if (data != def) 1346 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 1347 1348 /* Configure hold time to filter in-valid power on/off request. Use default right now */ 1349 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1350 data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK; 1351 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK); 1352 /* Configure switch time for hysteresis purpose. Use default right now */ 1353 data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK; 1354 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK); 1355 if(data != def) 1356 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1357 } 1358 1359 static void sdma_v4_0_init_pg(struct amdgpu_device *adev) 1360 { 1361 if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA)) 1362 return; 1363 1364 switch (adev->asic_type) { 1365 case CHIP_RAVEN: 1366 case CHIP_RENOIR: 1367 sdma_v4_1_init_power_gating(adev); 1368 sdma_v4_1_update_power_gating(adev, true); 1369 break; 1370 default: 1371 break; 1372 } 1373 } 1374 1375 /** 1376 * sdma_v4_0_rlc_resume - setup and start the async dma engines 1377 * 1378 * @adev: amdgpu_device pointer 1379 * 1380 * Set up the compute DMA queues and enable them (VEGA10). 1381 * Returns 0 for success, error for failure. 1382 */ 1383 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev) 1384 { 1385 sdma_v4_0_init_pg(adev); 1386 1387 return 0; 1388 } 1389 1390 /** 1391 * sdma_v4_0_load_microcode - load the sDMA ME ucode 1392 * 1393 * @adev: amdgpu_device pointer 1394 * 1395 * Loads the sDMA0/1 ucode. 1396 * Returns 0 for success, -EINVAL if the ucode is not available. 1397 */ 1398 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev) 1399 { 1400 const struct sdma_firmware_header_v1_0 *hdr; 1401 const __le32 *fw_data; 1402 u32 fw_size; 1403 int i, j; 1404 1405 /* halt the MEs */ 1406 sdma_v4_0_enable(adev, false); 1407 1408 for (i = 0; i < adev->sdma.num_instances; i++) { 1409 if (!adev->sdma.instance[i].fw) 1410 return -EINVAL; 1411 1412 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 1413 amdgpu_ucode_print_sdma_hdr(&hdr->header); 1414 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1415 1416 fw_data = (const __le32 *) 1417 (adev->sdma.instance[i].fw->data + 1418 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1419 1420 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 0); 1421 1422 for (j = 0; j < fw_size; j++) 1423 WREG32_SDMA(i, mmSDMA0_UCODE_DATA, 1424 le32_to_cpup(fw_data++)); 1425 1426 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 1427 adev->sdma.instance[i].fw_version); 1428 } 1429 1430 return 0; 1431 } 1432 1433 /** 1434 * sdma_v4_0_start - setup and start the async dma engines 1435 * 1436 * @adev: amdgpu_device pointer 1437 * 1438 * Set up the DMA engines and enable them (VEGA10). 1439 * Returns 0 for success, error for failure. 1440 */ 1441 static int sdma_v4_0_start(struct amdgpu_device *adev) 1442 { 1443 struct amdgpu_ring *ring; 1444 int i, r = 0; 1445 1446 if (amdgpu_sriov_vf(adev)) { 1447 sdma_v4_0_ctx_switch_enable(adev, false); 1448 sdma_v4_0_enable(adev, false); 1449 } else { 1450 1451 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1452 r = sdma_v4_0_load_microcode(adev); 1453 if (r) 1454 return r; 1455 } 1456 1457 /* unhalt the MEs */ 1458 sdma_v4_0_enable(adev, true); 1459 /* enable sdma ring preemption */ 1460 sdma_v4_0_ctx_switch_enable(adev, true); 1461 } 1462 1463 /* start the gfx rings and rlc compute queues */ 1464 for (i = 0; i < adev->sdma.num_instances; i++) { 1465 uint32_t temp; 1466 1467 WREG32_SDMA(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL, 0); 1468 sdma_v4_0_gfx_resume(adev, i); 1469 if (adev->sdma.has_page_queue) 1470 sdma_v4_0_page_resume(adev, i); 1471 1472 /* set utc l1 enable flag always to 1 */ 1473 temp = RREG32_SDMA(i, mmSDMA0_CNTL); 1474 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 1475 WREG32_SDMA(i, mmSDMA0_CNTL, temp); 1476 1477 if (!amdgpu_sriov_vf(adev)) { 1478 /* unhalt engine */ 1479 temp = RREG32_SDMA(i, mmSDMA0_F32_CNTL); 1480 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 1481 WREG32_SDMA(i, mmSDMA0_F32_CNTL, temp); 1482 } 1483 } 1484 1485 if (amdgpu_sriov_vf(adev)) { 1486 sdma_v4_0_ctx_switch_enable(adev, true); 1487 sdma_v4_0_enable(adev, true); 1488 } else { 1489 r = sdma_v4_0_rlc_resume(adev); 1490 if (r) 1491 return r; 1492 } 1493 1494 for (i = 0; i < adev->sdma.num_instances; i++) { 1495 ring = &adev->sdma.instance[i].ring; 1496 1497 r = amdgpu_ring_test_helper(ring); 1498 if (r) 1499 return r; 1500 1501 if (adev->sdma.has_page_queue) { 1502 struct amdgpu_ring *page = &adev->sdma.instance[i].page; 1503 1504 r = amdgpu_ring_test_helper(page); 1505 if (r) 1506 return r; 1507 1508 if (adev->mman.buffer_funcs_ring == page) 1509 amdgpu_ttm_set_buffer_funcs_status(adev, true); 1510 } 1511 1512 if (adev->mman.buffer_funcs_ring == ring) 1513 amdgpu_ttm_set_buffer_funcs_status(adev, true); 1514 } 1515 1516 return r; 1517 } 1518 1519 /** 1520 * sdma_v4_0_ring_test_ring - simple async dma engine test 1521 * 1522 * @ring: amdgpu_ring structure holding ring information 1523 * 1524 * Test the DMA engine by writing using it to write an 1525 * value to memory. (VEGA10). 1526 * Returns 0 for success, error for failure. 1527 */ 1528 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring) 1529 { 1530 struct amdgpu_device *adev = ring->adev; 1531 unsigned i; 1532 unsigned index; 1533 int r; 1534 u32 tmp; 1535 u64 gpu_addr; 1536 1537 r = amdgpu_device_wb_get(adev, &index); 1538 if (r) 1539 return r; 1540 1541 gpu_addr = adev->wb.gpu_addr + (index * 4); 1542 tmp = 0xCAFEDEAD; 1543 adev->wb.wb[index] = cpu_to_le32(tmp); 1544 1545 r = amdgpu_ring_alloc(ring, 5); 1546 if (r) 1547 goto error_free_wb; 1548 1549 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1550 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 1551 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 1552 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 1553 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 1554 amdgpu_ring_write(ring, 0xDEADBEEF); 1555 amdgpu_ring_commit(ring); 1556 1557 for (i = 0; i < adev->usec_timeout; i++) { 1558 tmp = le32_to_cpu(adev->wb.wb[index]); 1559 if (tmp == 0xDEADBEEF) 1560 break; 1561 udelay(1); 1562 } 1563 1564 if (i >= adev->usec_timeout) 1565 r = -ETIMEDOUT; 1566 1567 error_free_wb: 1568 amdgpu_device_wb_free(adev, index); 1569 return r; 1570 } 1571 1572 /** 1573 * sdma_v4_0_ring_test_ib - test an IB on the DMA engine 1574 * 1575 * @ring: amdgpu_ring structure holding ring information 1576 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 1577 * 1578 * Test a simple IB in the DMA ring (VEGA10). 1579 * Returns 0 on success, error on failure. 1580 */ 1581 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1582 { 1583 struct amdgpu_device *adev = ring->adev; 1584 struct amdgpu_ib ib; 1585 struct dma_fence *f = NULL; 1586 unsigned index; 1587 long r; 1588 u32 tmp = 0; 1589 u64 gpu_addr; 1590 1591 r = amdgpu_device_wb_get(adev, &index); 1592 if (r) 1593 return r; 1594 1595 gpu_addr = adev->wb.gpu_addr + (index * 4); 1596 tmp = 0xCAFEDEAD; 1597 adev->wb.wb[index] = cpu_to_le32(tmp); 1598 memset(&ib, 0, sizeof(ib)); 1599 r = amdgpu_ib_get(adev, NULL, 256, 1600 AMDGPU_IB_POOL_DIRECT, &ib); 1601 if (r) 1602 goto err0; 1603 1604 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1605 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1606 ib.ptr[1] = lower_32_bits(gpu_addr); 1607 ib.ptr[2] = upper_32_bits(gpu_addr); 1608 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1609 ib.ptr[4] = 0xDEADBEEF; 1610 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1611 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1612 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1613 ib.length_dw = 8; 1614 1615 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1616 if (r) 1617 goto err1; 1618 1619 r = dma_fence_wait_timeout(f, false, timeout); 1620 if (r == 0) { 1621 r = -ETIMEDOUT; 1622 goto err1; 1623 } else if (r < 0) { 1624 goto err1; 1625 } 1626 tmp = le32_to_cpu(adev->wb.wb[index]); 1627 if (tmp == 0xDEADBEEF) 1628 r = 0; 1629 else 1630 r = -EINVAL; 1631 1632 err1: 1633 amdgpu_ib_free(adev, &ib, NULL); 1634 dma_fence_put(f); 1635 err0: 1636 amdgpu_device_wb_free(adev, index); 1637 return r; 1638 } 1639 1640 1641 /** 1642 * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART 1643 * 1644 * @ib: indirect buffer to fill with commands 1645 * @pe: addr of the page entry 1646 * @src: src addr to copy from 1647 * @count: number of page entries to update 1648 * 1649 * Update PTEs by copying them from the GART using sDMA (VEGA10). 1650 */ 1651 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib, 1652 uint64_t pe, uint64_t src, 1653 unsigned count) 1654 { 1655 unsigned bytes = count * 8; 1656 1657 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1658 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1659 ib->ptr[ib->length_dw++] = bytes - 1; 1660 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1661 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1662 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1663 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1664 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1665 1666 } 1667 1668 /** 1669 * sdma_v4_0_vm_write_pte - update PTEs by writing them manually 1670 * 1671 * @ib: indirect buffer to fill with commands 1672 * @pe: addr of the page entry 1673 * @value: dst addr to write into pe 1674 * @count: number of page entries to update 1675 * @incr: increase next addr by incr bytes 1676 * 1677 * Update PTEs by writing them manually using sDMA (VEGA10). 1678 */ 1679 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1680 uint64_t value, unsigned count, 1681 uint32_t incr) 1682 { 1683 unsigned ndw = count * 2; 1684 1685 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1686 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1687 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1688 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1689 ib->ptr[ib->length_dw++] = ndw - 1; 1690 for (; ndw > 0; ndw -= 2) { 1691 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1692 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1693 value += incr; 1694 } 1695 } 1696 1697 /** 1698 * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA 1699 * 1700 * @ib: indirect buffer to fill with commands 1701 * @pe: addr of the page entry 1702 * @addr: dst addr to write into pe 1703 * @count: number of page entries to update 1704 * @incr: increase next addr by incr bytes 1705 * @flags: access flags 1706 * 1707 * Update the page tables using sDMA (VEGA10). 1708 */ 1709 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1710 uint64_t pe, 1711 uint64_t addr, unsigned count, 1712 uint32_t incr, uint64_t flags) 1713 { 1714 /* for physically contiguous pages (vram) */ 1715 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1716 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1717 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1718 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1719 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1720 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1721 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1722 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1723 ib->ptr[ib->length_dw++] = 0; 1724 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1725 } 1726 1727 /** 1728 * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw 1729 * 1730 * @ring: amdgpu_ring structure holding ring information 1731 * @ib: indirect buffer to fill with padding 1732 */ 1733 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1734 { 1735 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1736 u32 pad_count; 1737 int i; 1738 1739 pad_count = (-ib->length_dw) & 7; 1740 for (i = 0; i < pad_count; i++) 1741 if (sdma && sdma->burst_nop && (i == 0)) 1742 ib->ptr[ib->length_dw++] = 1743 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1744 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1745 else 1746 ib->ptr[ib->length_dw++] = 1747 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1748 } 1749 1750 1751 /** 1752 * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline 1753 * 1754 * @ring: amdgpu_ring pointer 1755 * 1756 * Make sure all previous operations are completed (CIK). 1757 */ 1758 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1759 { 1760 uint32_t seq = ring->fence_drv.sync_seq; 1761 uint64_t addr = ring->fence_drv.gpu_addr; 1762 1763 /* wait for idle */ 1764 sdma_v4_0_wait_reg_mem(ring, 1, 0, 1765 addr & 0xfffffffc, 1766 upper_32_bits(addr) & 0xffffffff, 1767 seq, 0xffffffff, 4); 1768 } 1769 1770 1771 /** 1772 * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA 1773 * 1774 * @ring: amdgpu_ring pointer 1775 * @vmid: vmid number to use 1776 * @pd_addr: address 1777 * 1778 * Update the page table base and flush the VM TLB 1779 * using sDMA (VEGA10). 1780 */ 1781 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1782 unsigned vmid, uint64_t pd_addr) 1783 { 1784 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1785 } 1786 1787 static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring, 1788 uint32_t reg, uint32_t val) 1789 { 1790 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1791 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1792 amdgpu_ring_write(ring, reg); 1793 amdgpu_ring_write(ring, val); 1794 } 1795 1796 static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1797 uint32_t val, uint32_t mask) 1798 { 1799 sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10); 1800 } 1801 1802 static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev) 1803 { 1804 uint fw_version = adev->sdma.instance[0].fw_version; 1805 1806 switch (adev->asic_type) { 1807 case CHIP_VEGA10: 1808 return fw_version >= 430; 1809 case CHIP_VEGA12: 1810 /*return fw_version >= 31;*/ 1811 return false; 1812 case CHIP_VEGA20: 1813 return fw_version >= 123; 1814 default: 1815 return false; 1816 } 1817 } 1818 1819 static int sdma_v4_0_early_init(void *handle) 1820 { 1821 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1822 int r; 1823 1824 if (adev->flags & AMD_IS_APU) 1825 adev->sdma.num_instances = 1; 1826 else if (adev->asic_type == CHIP_ARCTURUS) 1827 adev->sdma.num_instances = 8; 1828 else 1829 adev->sdma.num_instances = 2; 1830 1831 r = sdma_v4_0_init_microcode(adev); 1832 if (r) { 1833 DRM_ERROR("Failed to load sdma firmware!\n"); 1834 return r; 1835 } 1836 1837 /* TODO: Page queue breaks driver reload under SRIOV */ 1838 if ((adev->asic_type == CHIP_VEGA10) && amdgpu_sriov_vf((adev))) 1839 adev->sdma.has_page_queue = false; 1840 else if (sdma_v4_0_fw_support_paging_queue(adev)) 1841 adev->sdma.has_page_queue = true; 1842 1843 sdma_v4_0_set_ring_funcs(adev); 1844 sdma_v4_0_set_buffer_funcs(adev); 1845 sdma_v4_0_set_vm_pte_funcs(adev); 1846 sdma_v4_0_set_irq_funcs(adev); 1847 sdma_v4_0_set_ras_funcs(adev); 1848 1849 return 0; 1850 } 1851 1852 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev, 1853 void *err_data, 1854 struct amdgpu_iv_entry *entry); 1855 1856 static int sdma_v4_0_late_init(void *handle) 1857 { 1858 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1859 struct ras_ih_if ih_info = { 1860 .cb = sdma_v4_0_process_ras_data_cb, 1861 }; 1862 1863 sdma_v4_0_setup_ulv(adev); 1864 1865 if (adev->sdma.funcs && adev->sdma.funcs->reset_ras_error_count) 1866 adev->sdma.funcs->reset_ras_error_count(adev); 1867 1868 if (adev->sdma.funcs && adev->sdma.funcs->ras_late_init) 1869 return adev->sdma.funcs->ras_late_init(adev, &ih_info); 1870 else 1871 return 0; 1872 } 1873 1874 static int sdma_v4_0_sw_init(void *handle) 1875 { 1876 struct amdgpu_ring *ring; 1877 int r, i; 1878 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1879 1880 /* SDMA trap event */ 1881 for (i = 0; i < adev->sdma.num_instances; i++) { 1882 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1883 SDMA0_4_0__SRCID__SDMA_TRAP, 1884 &adev->sdma.trap_irq); 1885 if (r) 1886 return r; 1887 } 1888 1889 /* SDMA SRAM ECC event */ 1890 for (i = 0; i < adev->sdma.num_instances; i++) { 1891 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1892 SDMA0_4_0__SRCID__SDMA_SRAM_ECC, 1893 &adev->sdma.ecc_irq); 1894 if (r) 1895 return r; 1896 } 1897 1898 /* SDMA VM_HOLE/DOORBELL_INV/POLL_TIMEOUT/SRBM_WRITE_PROTECTION event*/ 1899 for (i = 0; i < adev->sdma.num_instances; i++) { 1900 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1901 SDMA0_4_0__SRCID__SDMA_VM_HOLE, 1902 &adev->sdma.vm_hole_irq); 1903 if (r) 1904 return r; 1905 1906 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1907 SDMA0_4_0__SRCID__SDMA_DOORBELL_INVALID, 1908 &adev->sdma.doorbell_invalid_irq); 1909 if (r) 1910 return r; 1911 1912 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1913 SDMA0_4_0__SRCID__SDMA_POLL_TIMEOUT, 1914 &adev->sdma.pool_timeout_irq); 1915 if (r) 1916 return r; 1917 1918 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1919 SDMA0_4_0__SRCID__SDMA_SRBMWRITE, 1920 &adev->sdma.srbm_write_irq); 1921 if (r) 1922 return r; 1923 } 1924 1925 for (i = 0; i < adev->sdma.num_instances; i++) { 1926 ring = &adev->sdma.instance[i].ring; 1927 ring->ring_obj = NULL; 1928 ring->use_doorbell = true; 1929 1930 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1931 ring->use_doorbell?"true":"false"); 1932 1933 /* doorbell size is 2 dwords, get DWORD offset */ 1934 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1; 1935 1936 sprintf(ring->name, "sdma%d", i); 1937 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1938 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1939 AMDGPU_RING_PRIO_DEFAULT); 1940 if (r) 1941 return r; 1942 1943 if (adev->sdma.has_page_queue) { 1944 ring = &adev->sdma.instance[i].page; 1945 ring->ring_obj = NULL; 1946 ring->use_doorbell = true; 1947 1948 /* paging queue use same doorbell index/routing as gfx queue 1949 * with 0x400 (4096 dwords) offset on second doorbell page 1950 */ 1951 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1; 1952 ring->doorbell_index += 0x400; 1953 1954 sprintf(ring->name, "page%d", i); 1955 r = amdgpu_ring_init(adev, ring, 1024, 1956 &adev->sdma.trap_irq, 1957 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1958 AMDGPU_RING_PRIO_DEFAULT); 1959 if (r) 1960 return r; 1961 } 1962 } 1963 1964 return r; 1965 } 1966 1967 static int sdma_v4_0_sw_fini(void *handle) 1968 { 1969 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1970 int i; 1971 1972 if (adev->sdma.funcs && adev->sdma.funcs->ras_fini) 1973 adev->sdma.funcs->ras_fini(adev); 1974 1975 for (i = 0; i < adev->sdma.num_instances; i++) { 1976 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1977 if (adev->sdma.has_page_queue) 1978 amdgpu_ring_fini(&adev->sdma.instance[i].page); 1979 } 1980 1981 sdma_v4_0_destroy_inst_ctx(adev); 1982 1983 return 0; 1984 } 1985 1986 static int sdma_v4_0_hw_init(void *handle) 1987 { 1988 int r; 1989 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1990 1991 if (adev->flags & AMD_IS_APU) 1992 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false); 1993 1994 if (!amdgpu_sriov_vf(adev)) 1995 sdma_v4_0_init_golden_registers(adev); 1996 1997 r = sdma_v4_0_start(adev); 1998 1999 return r; 2000 } 2001 2002 static int sdma_v4_0_hw_fini(void *handle) 2003 { 2004 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2005 int i; 2006 2007 if (amdgpu_sriov_vf(adev)) 2008 return 0; 2009 2010 for (i = 0; i < adev->sdma.num_instances; i++) { 2011 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, 2012 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 2013 } 2014 2015 sdma_v4_0_ctx_switch_enable(adev, false); 2016 sdma_v4_0_enable(adev, false); 2017 2018 if (adev->flags & AMD_IS_APU) 2019 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true); 2020 2021 return 0; 2022 } 2023 2024 static int sdma_v4_0_suspend(void *handle) 2025 { 2026 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2027 2028 return sdma_v4_0_hw_fini(adev); 2029 } 2030 2031 static int sdma_v4_0_resume(void *handle) 2032 { 2033 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2034 2035 return sdma_v4_0_hw_init(adev); 2036 } 2037 2038 static bool sdma_v4_0_is_idle(void *handle) 2039 { 2040 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2041 u32 i; 2042 2043 for (i = 0; i < adev->sdma.num_instances; i++) { 2044 u32 tmp = RREG32_SDMA(i, mmSDMA0_STATUS_REG); 2045 2046 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 2047 return false; 2048 } 2049 2050 return true; 2051 } 2052 2053 static int sdma_v4_0_wait_for_idle(void *handle) 2054 { 2055 unsigned i, j; 2056 u32 sdma[AMDGPU_MAX_SDMA_INSTANCES]; 2057 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2058 2059 for (i = 0; i < adev->usec_timeout; i++) { 2060 for (j = 0; j < adev->sdma.num_instances; j++) { 2061 sdma[j] = RREG32_SDMA(j, mmSDMA0_STATUS_REG); 2062 if (!(sdma[j] & SDMA0_STATUS_REG__IDLE_MASK)) 2063 break; 2064 } 2065 if (j == adev->sdma.num_instances) 2066 return 0; 2067 udelay(1); 2068 } 2069 return -ETIMEDOUT; 2070 } 2071 2072 static int sdma_v4_0_soft_reset(void *handle) 2073 { 2074 /* todo */ 2075 2076 return 0; 2077 } 2078 2079 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev, 2080 struct amdgpu_irq_src *source, 2081 unsigned type, 2082 enum amdgpu_interrupt_state state) 2083 { 2084 u32 sdma_cntl; 2085 2086 sdma_cntl = RREG32_SDMA(type, mmSDMA0_CNTL); 2087 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 2088 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2089 WREG32_SDMA(type, mmSDMA0_CNTL, sdma_cntl); 2090 2091 return 0; 2092 } 2093 2094 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev, 2095 struct amdgpu_irq_src *source, 2096 struct amdgpu_iv_entry *entry) 2097 { 2098 uint32_t instance; 2099 2100 DRM_DEBUG("IH: SDMA trap\n"); 2101 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 2102 switch (entry->ring_id) { 2103 case 0: 2104 amdgpu_fence_process(&adev->sdma.instance[instance].ring); 2105 break; 2106 case 1: 2107 if (adev->asic_type == CHIP_VEGA20) 2108 amdgpu_fence_process(&adev->sdma.instance[instance].page); 2109 break; 2110 case 2: 2111 /* XXX compute */ 2112 break; 2113 case 3: 2114 if (adev->asic_type != CHIP_VEGA20) 2115 amdgpu_fence_process(&adev->sdma.instance[instance].page); 2116 break; 2117 } 2118 return 0; 2119 } 2120 2121 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev, 2122 void *err_data, 2123 struct amdgpu_iv_entry *entry) 2124 { 2125 int instance; 2126 2127 /* When “Full RAS” is enabled, the per-IP interrupt sources should 2128 * be disabled and the driver should only look for the aggregated 2129 * interrupt via sync flood 2130 */ 2131 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 2132 goto out; 2133 2134 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 2135 if (instance < 0) 2136 goto out; 2137 2138 amdgpu_sdma_process_ras_data_cb(adev, err_data, entry); 2139 2140 out: 2141 return AMDGPU_RAS_SUCCESS; 2142 } 2143 2144 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev, 2145 struct amdgpu_irq_src *source, 2146 struct amdgpu_iv_entry *entry) 2147 { 2148 int instance; 2149 2150 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 2151 2152 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 2153 if (instance < 0) 2154 return 0; 2155 2156 switch (entry->ring_id) { 2157 case 0: 2158 drm_sched_fault(&adev->sdma.instance[instance].ring.sched); 2159 break; 2160 } 2161 return 0; 2162 } 2163 2164 static int sdma_v4_0_set_ecc_irq_state(struct amdgpu_device *adev, 2165 struct amdgpu_irq_src *source, 2166 unsigned type, 2167 enum amdgpu_interrupt_state state) 2168 { 2169 u32 sdma_edc_config; 2170 2171 sdma_edc_config = RREG32_SDMA(type, mmSDMA0_EDC_CONFIG); 2172 sdma_edc_config = REG_SET_FIELD(sdma_edc_config, SDMA0_EDC_CONFIG, ECC_INT_ENABLE, 2173 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2174 WREG32_SDMA(type, mmSDMA0_EDC_CONFIG, sdma_edc_config); 2175 2176 return 0; 2177 } 2178 2179 static int sdma_v4_0_print_iv_entry(struct amdgpu_device *adev, 2180 struct amdgpu_iv_entry *entry) 2181 { 2182 int instance; 2183 struct amdgpu_task_info task_info; 2184 u64 addr; 2185 2186 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 2187 if (instance < 0 || instance >= adev->sdma.num_instances) { 2188 dev_err(adev->dev, "sdma instance invalid %d\n", instance); 2189 return -EINVAL; 2190 } 2191 2192 addr = (u64)entry->src_data[0] << 12; 2193 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 2194 2195 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 2196 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 2197 2198 dev_info(adev->dev, 2199 "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u " 2200 "pasid:%u, for process %s pid %d thread %s pid %d\n", 2201 instance, addr, entry->src_id, entry->ring_id, entry->vmid, 2202 entry->pasid, task_info.process_name, task_info.tgid, 2203 task_info.task_name, task_info.pid); 2204 return 0; 2205 } 2206 2207 static int sdma_v4_0_process_vm_hole_irq(struct amdgpu_device *adev, 2208 struct amdgpu_irq_src *source, 2209 struct amdgpu_iv_entry *entry) 2210 { 2211 dev_err(adev->dev, "MC or SEM address in VM hole\n"); 2212 sdma_v4_0_print_iv_entry(adev, entry); 2213 return 0; 2214 } 2215 2216 static int sdma_v4_0_process_doorbell_invalid_irq(struct amdgpu_device *adev, 2217 struct amdgpu_irq_src *source, 2218 struct amdgpu_iv_entry *entry) 2219 { 2220 dev_err(adev->dev, "SDMA received a doorbell from BIF with byte_enable !=0xff\n"); 2221 sdma_v4_0_print_iv_entry(adev, entry); 2222 return 0; 2223 } 2224 2225 static int sdma_v4_0_process_pool_timeout_irq(struct amdgpu_device *adev, 2226 struct amdgpu_irq_src *source, 2227 struct amdgpu_iv_entry *entry) 2228 { 2229 dev_err(adev->dev, 2230 "Polling register/memory timeout executing POLL_REG/MEM with finite timer\n"); 2231 sdma_v4_0_print_iv_entry(adev, entry); 2232 return 0; 2233 } 2234 2235 static int sdma_v4_0_process_srbm_write_irq(struct amdgpu_device *adev, 2236 struct amdgpu_irq_src *source, 2237 struct amdgpu_iv_entry *entry) 2238 { 2239 dev_err(adev->dev, 2240 "SDMA gets an Register Write SRBM_WRITE command in non-privilege command buffer\n"); 2241 sdma_v4_0_print_iv_entry(adev, entry); 2242 return 0; 2243 } 2244 2245 static void sdma_v4_0_update_medium_grain_clock_gating( 2246 struct amdgpu_device *adev, 2247 bool enable) 2248 { 2249 uint32_t data, def; 2250 int i; 2251 2252 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 2253 for (i = 0; i < adev->sdma.num_instances; i++) { 2254 def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL); 2255 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 2256 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 2257 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 2258 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 2259 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 2260 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 2261 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 2262 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 2263 if (def != data) 2264 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data); 2265 } 2266 } else { 2267 for (i = 0; i < adev->sdma.num_instances; i++) { 2268 def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL); 2269 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 2270 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 2271 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 2272 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 2273 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 2274 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 2275 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 2276 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 2277 if (def != data) 2278 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data); 2279 } 2280 } 2281 } 2282 2283 2284 static void sdma_v4_0_update_medium_grain_light_sleep( 2285 struct amdgpu_device *adev, 2286 bool enable) 2287 { 2288 uint32_t data, def; 2289 int i; 2290 2291 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 2292 for (i = 0; i < adev->sdma.num_instances; i++) { 2293 /* 1-not override: enable sdma mem light sleep */ 2294 def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL); 2295 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 2296 if (def != data) 2297 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data); 2298 } 2299 } else { 2300 for (i = 0; i < adev->sdma.num_instances; i++) { 2301 /* 0-override:disable sdma mem light sleep */ 2302 def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL); 2303 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 2304 if (def != data) 2305 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data); 2306 } 2307 } 2308 } 2309 2310 static int sdma_v4_0_set_clockgating_state(void *handle, 2311 enum amd_clockgating_state state) 2312 { 2313 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2314 2315 if (amdgpu_sriov_vf(adev)) 2316 return 0; 2317 2318 sdma_v4_0_update_medium_grain_clock_gating(adev, 2319 state == AMD_CG_STATE_GATE); 2320 sdma_v4_0_update_medium_grain_light_sleep(adev, 2321 state == AMD_CG_STATE_GATE); 2322 return 0; 2323 } 2324 2325 static int sdma_v4_0_set_powergating_state(void *handle, 2326 enum amd_powergating_state state) 2327 { 2328 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2329 2330 switch (adev->asic_type) { 2331 case CHIP_RAVEN: 2332 case CHIP_RENOIR: 2333 sdma_v4_1_update_power_gating(adev, 2334 state == AMD_PG_STATE_GATE); 2335 break; 2336 default: 2337 break; 2338 } 2339 2340 return 0; 2341 } 2342 2343 static void sdma_v4_0_get_clockgating_state(void *handle, u32 *flags) 2344 { 2345 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2346 int data; 2347 2348 if (amdgpu_sriov_vf(adev)) 2349 *flags = 0; 2350 2351 /* AMD_CG_SUPPORT_SDMA_MGCG */ 2352 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 2353 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK)) 2354 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 2355 2356 /* AMD_CG_SUPPORT_SDMA_LS */ 2357 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 2358 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 2359 *flags |= AMD_CG_SUPPORT_SDMA_LS; 2360 } 2361 2362 const struct amd_ip_funcs sdma_v4_0_ip_funcs = { 2363 .name = "sdma_v4_0", 2364 .early_init = sdma_v4_0_early_init, 2365 .late_init = sdma_v4_0_late_init, 2366 .sw_init = sdma_v4_0_sw_init, 2367 .sw_fini = sdma_v4_0_sw_fini, 2368 .hw_init = sdma_v4_0_hw_init, 2369 .hw_fini = sdma_v4_0_hw_fini, 2370 .suspend = sdma_v4_0_suspend, 2371 .resume = sdma_v4_0_resume, 2372 .is_idle = sdma_v4_0_is_idle, 2373 .wait_for_idle = sdma_v4_0_wait_for_idle, 2374 .soft_reset = sdma_v4_0_soft_reset, 2375 .set_clockgating_state = sdma_v4_0_set_clockgating_state, 2376 .set_powergating_state = sdma_v4_0_set_powergating_state, 2377 .get_clockgating_state = sdma_v4_0_get_clockgating_state, 2378 }; 2379 2380 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = { 2381 .type = AMDGPU_RING_TYPE_SDMA, 2382 .align_mask = 0xf, 2383 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2384 .support_64bit_ptrs = true, 2385 .vmhub = AMDGPU_MMHUB_0, 2386 .get_rptr = sdma_v4_0_ring_get_rptr, 2387 .get_wptr = sdma_v4_0_ring_get_wptr, 2388 .set_wptr = sdma_v4_0_ring_set_wptr, 2389 .emit_frame_size = 2390 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2391 3 + /* hdp invalidate */ 2392 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2393 /* sdma_v4_0_ring_emit_vm_flush */ 2394 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2395 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2396 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2397 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2398 .emit_ib = sdma_v4_0_ring_emit_ib, 2399 .emit_fence = sdma_v4_0_ring_emit_fence, 2400 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2401 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2402 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2403 .test_ring = sdma_v4_0_ring_test_ring, 2404 .test_ib = sdma_v4_0_ring_test_ib, 2405 .insert_nop = sdma_v4_0_ring_insert_nop, 2406 .pad_ib = sdma_v4_0_ring_pad_ib, 2407 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2408 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2409 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2410 }; 2411 2412 /* 2413 * On Arcturus, SDMA instance 5~7 has a different vmhub type(AMDGPU_MMHUB_1). 2414 * So create a individual constant ring_funcs for those instances. 2415 */ 2416 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs_2nd_mmhub = { 2417 .type = AMDGPU_RING_TYPE_SDMA, 2418 .align_mask = 0xf, 2419 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2420 .support_64bit_ptrs = true, 2421 .vmhub = AMDGPU_MMHUB_1, 2422 .get_rptr = sdma_v4_0_ring_get_rptr, 2423 .get_wptr = sdma_v4_0_ring_get_wptr, 2424 .set_wptr = sdma_v4_0_ring_set_wptr, 2425 .emit_frame_size = 2426 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2427 3 + /* hdp invalidate */ 2428 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2429 /* sdma_v4_0_ring_emit_vm_flush */ 2430 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2431 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2432 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2433 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2434 .emit_ib = sdma_v4_0_ring_emit_ib, 2435 .emit_fence = sdma_v4_0_ring_emit_fence, 2436 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2437 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2438 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2439 .test_ring = sdma_v4_0_ring_test_ring, 2440 .test_ib = sdma_v4_0_ring_test_ib, 2441 .insert_nop = sdma_v4_0_ring_insert_nop, 2442 .pad_ib = sdma_v4_0_ring_pad_ib, 2443 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2444 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2445 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2446 }; 2447 2448 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = { 2449 .type = AMDGPU_RING_TYPE_SDMA, 2450 .align_mask = 0xf, 2451 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2452 .support_64bit_ptrs = true, 2453 .vmhub = AMDGPU_MMHUB_0, 2454 .get_rptr = sdma_v4_0_ring_get_rptr, 2455 .get_wptr = sdma_v4_0_page_ring_get_wptr, 2456 .set_wptr = sdma_v4_0_page_ring_set_wptr, 2457 .emit_frame_size = 2458 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2459 3 + /* hdp invalidate */ 2460 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2461 /* sdma_v4_0_ring_emit_vm_flush */ 2462 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2463 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2464 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2465 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2466 .emit_ib = sdma_v4_0_ring_emit_ib, 2467 .emit_fence = sdma_v4_0_ring_emit_fence, 2468 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2469 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2470 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2471 .test_ring = sdma_v4_0_ring_test_ring, 2472 .test_ib = sdma_v4_0_ring_test_ib, 2473 .insert_nop = sdma_v4_0_ring_insert_nop, 2474 .pad_ib = sdma_v4_0_ring_pad_ib, 2475 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2476 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2477 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2478 }; 2479 2480 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs_2nd_mmhub = { 2481 .type = AMDGPU_RING_TYPE_SDMA, 2482 .align_mask = 0xf, 2483 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2484 .support_64bit_ptrs = true, 2485 .vmhub = AMDGPU_MMHUB_1, 2486 .get_rptr = sdma_v4_0_ring_get_rptr, 2487 .get_wptr = sdma_v4_0_page_ring_get_wptr, 2488 .set_wptr = sdma_v4_0_page_ring_set_wptr, 2489 .emit_frame_size = 2490 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2491 3 + /* hdp invalidate */ 2492 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2493 /* sdma_v4_0_ring_emit_vm_flush */ 2494 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2495 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2496 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2497 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2498 .emit_ib = sdma_v4_0_ring_emit_ib, 2499 .emit_fence = sdma_v4_0_ring_emit_fence, 2500 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2501 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2502 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2503 .test_ring = sdma_v4_0_ring_test_ring, 2504 .test_ib = sdma_v4_0_ring_test_ib, 2505 .insert_nop = sdma_v4_0_ring_insert_nop, 2506 .pad_ib = sdma_v4_0_ring_pad_ib, 2507 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2508 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2509 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2510 }; 2511 2512 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev) 2513 { 2514 int i; 2515 2516 for (i = 0; i < adev->sdma.num_instances; i++) { 2517 if (adev->asic_type == CHIP_ARCTURUS && i >= 5) 2518 adev->sdma.instance[i].ring.funcs = 2519 &sdma_v4_0_ring_funcs_2nd_mmhub; 2520 else 2521 adev->sdma.instance[i].ring.funcs = 2522 &sdma_v4_0_ring_funcs; 2523 adev->sdma.instance[i].ring.me = i; 2524 if (adev->sdma.has_page_queue) { 2525 if (adev->asic_type == CHIP_ARCTURUS && i >= 5) 2526 adev->sdma.instance[i].page.funcs = 2527 &sdma_v4_0_page_ring_funcs_2nd_mmhub; 2528 else 2529 adev->sdma.instance[i].page.funcs = 2530 &sdma_v4_0_page_ring_funcs; 2531 adev->sdma.instance[i].page.me = i; 2532 } 2533 } 2534 } 2535 2536 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = { 2537 .set = sdma_v4_0_set_trap_irq_state, 2538 .process = sdma_v4_0_process_trap_irq, 2539 }; 2540 2541 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = { 2542 .process = sdma_v4_0_process_illegal_inst_irq, 2543 }; 2544 2545 static const struct amdgpu_irq_src_funcs sdma_v4_0_ecc_irq_funcs = { 2546 .set = sdma_v4_0_set_ecc_irq_state, 2547 .process = amdgpu_sdma_process_ecc_irq, 2548 }; 2549 2550 static const struct amdgpu_irq_src_funcs sdma_v4_0_vm_hole_irq_funcs = { 2551 .process = sdma_v4_0_process_vm_hole_irq, 2552 }; 2553 2554 static const struct amdgpu_irq_src_funcs sdma_v4_0_doorbell_invalid_irq_funcs = { 2555 .process = sdma_v4_0_process_doorbell_invalid_irq, 2556 }; 2557 2558 static const struct amdgpu_irq_src_funcs sdma_v4_0_pool_timeout_irq_funcs = { 2559 .process = sdma_v4_0_process_pool_timeout_irq, 2560 }; 2561 2562 static const struct amdgpu_irq_src_funcs sdma_v4_0_srbm_write_irq_funcs = { 2563 .process = sdma_v4_0_process_srbm_write_irq, 2564 }; 2565 2566 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev) 2567 { 2568 switch (adev->sdma.num_instances) { 2569 case 1: 2570 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1; 2571 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1; 2572 break; 2573 case 8: 2574 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 2575 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 2576 adev->sdma.vm_hole_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE5; 2577 adev->sdma.doorbell_invalid_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 2578 adev->sdma.pool_timeout_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 2579 adev->sdma.srbm_write_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 2580 break; 2581 case 2: 2582 default: 2583 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2; 2584 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2; 2585 break; 2586 } 2587 adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs; 2588 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs; 2589 adev->sdma.ecc_irq.funcs = &sdma_v4_0_ecc_irq_funcs; 2590 adev->sdma.vm_hole_irq.funcs = &sdma_v4_0_vm_hole_irq_funcs; 2591 adev->sdma.doorbell_invalid_irq.funcs = &sdma_v4_0_doorbell_invalid_irq_funcs; 2592 adev->sdma.pool_timeout_irq.funcs = &sdma_v4_0_pool_timeout_irq_funcs; 2593 adev->sdma.srbm_write_irq.funcs = &sdma_v4_0_srbm_write_irq_funcs; 2594 } 2595 2596 /** 2597 * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine 2598 * 2599 * @ib: indirect buffer to copy to 2600 * @src_offset: src GPU address 2601 * @dst_offset: dst GPU address 2602 * @byte_count: number of bytes to xfer 2603 * @tmz: if a secure copy should be used 2604 * 2605 * Copy GPU buffers using the DMA engine (VEGA10/12). 2606 * Used by the amdgpu ttm implementation to move pages if 2607 * registered as the asic copy callback. 2608 */ 2609 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib, 2610 uint64_t src_offset, 2611 uint64_t dst_offset, 2612 uint32_t byte_count, 2613 bool tmz) 2614 { 2615 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 2616 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 2617 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0); 2618 ib->ptr[ib->length_dw++] = byte_count - 1; 2619 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 2620 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 2621 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 2622 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2623 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2624 } 2625 2626 /** 2627 * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine 2628 * 2629 * @ib: indirect buffer to copy to 2630 * @src_data: value to write to buffer 2631 * @dst_offset: dst GPU address 2632 * @byte_count: number of bytes to xfer 2633 * 2634 * Fill GPU buffers using the DMA engine (VEGA10/12). 2635 */ 2636 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib, 2637 uint32_t src_data, 2638 uint64_t dst_offset, 2639 uint32_t byte_count) 2640 { 2641 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 2642 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2643 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2644 ib->ptr[ib->length_dw++] = src_data; 2645 ib->ptr[ib->length_dw++] = byte_count - 1; 2646 } 2647 2648 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = { 2649 .copy_max_bytes = 0x400000, 2650 .copy_num_dw = 7, 2651 .emit_copy_buffer = sdma_v4_0_emit_copy_buffer, 2652 2653 .fill_max_bytes = 0x400000, 2654 .fill_num_dw = 5, 2655 .emit_fill_buffer = sdma_v4_0_emit_fill_buffer, 2656 }; 2657 2658 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev) 2659 { 2660 adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs; 2661 if (adev->sdma.has_page_queue) 2662 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page; 2663 else 2664 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 2665 } 2666 2667 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = { 2668 .copy_pte_num_dw = 7, 2669 .copy_pte = sdma_v4_0_vm_copy_pte, 2670 2671 .write_pte = sdma_v4_0_vm_write_pte, 2672 .set_pte_pde = sdma_v4_0_vm_set_pte_pde, 2673 }; 2674 2675 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev) 2676 { 2677 struct drm_gpu_scheduler *sched; 2678 unsigned i; 2679 2680 adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs; 2681 for (i = 0; i < adev->sdma.num_instances; i++) { 2682 if (adev->sdma.has_page_queue) 2683 sched = &adev->sdma.instance[i].page.sched; 2684 else 2685 sched = &adev->sdma.instance[i].ring.sched; 2686 adev->vm_manager.vm_pte_scheds[i] = sched; 2687 } 2688 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 2689 } 2690 2691 static void sdma_v4_0_get_ras_error_count(uint32_t value, 2692 uint32_t instance, 2693 uint32_t *sec_count) 2694 { 2695 uint32_t i; 2696 uint32_t sec_cnt; 2697 2698 /* double bits error (multiple bits) error detection is not supported */ 2699 for (i = 0; i < ARRAY_SIZE(sdma_v4_0_ras_fields); i++) { 2700 /* the SDMA_EDC_COUNTER register in each sdma instance 2701 * shares the same sed shift_mask 2702 * */ 2703 sec_cnt = (value & 2704 sdma_v4_0_ras_fields[i].sec_count_mask) >> 2705 sdma_v4_0_ras_fields[i].sec_count_shift; 2706 if (sec_cnt) { 2707 DRM_INFO("Detected %s in SDMA%d, SED %d\n", 2708 sdma_v4_0_ras_fields[i].name, 2709 instance, sec_cnt); 2710 *sec_count += sec_cnt; 2711 } 2712 } 2713 } 2714 2715 static int sdma_v4_0_query_ras_error_count(struct amdgpu_device *adev, 2716 uint32_t instance, void *ras_error_status) 2717 { 2718 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 2719 uint32_t sec_count = 0; 2720 uint32_t reg_value = 0; 2721 2722 reg_value = RREG32_SDMA(instance, mmSDMA0_EDC_COUNTER); 2723 /* double bit error is not supported */ 2724 if (reg_value) 2725 sdma_v4_0_get_ras_error_count(reg_value, 2726 instance, &sec_count); 2727 /* err_data->ce_count should be initialized to 0 2728 * before calling into this function */ 2729 err_data->ce_count += sec_count; 2730 /* double bit error is not supported 2731 * set ue count to 0 */ 2732 err_data->ue_count = 0; 2733 2734 return 0; 2735 }; 2736 2737 static void sdma_v4_0_reset_ras_error_count(struct amdgpu_device *adev) 2738 { 2739 int i; 2740 2741 /* read back edc counter registers to clear the counters */ 2742 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 2743 for (i = 0; i < adev->sdma.num_instances; i++) 2744 RREG32_SDMA(i, mmSDMA0_EDC_COUNTER); 2745 } 2746 } 2747 2748 static const struct amdgpu_sdma_ras_funcs sdma_v4_0_ras_funcs = { 2749 .ras_late_init = amdgpu_sdma_ras_late_init, 2750 .ras_fini = amdgpu_sdma_ras_fini, 2751 .query_ras_error_count = sdma_v4_0_query_ras_error_count, 2752 .reset_ras_error_count = sdma_v4_0_reset_ras_error_count, 2753 }; 2754 2755 static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev) 2756 { 2757 switch (adev->asic_type) { 2758 case CHIP_VEGA20: 2759 case CHIP_ARCTURUS: 2760 adev->sdma.funcs = &sdma_v4_0_ras_funcs; 2761 break; 2762 default: 2763 break; 2764 } 2765 } 2766 2767 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = { 2768 .type = AMD_IP_BLOCK_TYPE_SDMA, 2769 .major = 4, 2770 .minor = 0, 2771 .rev = 0, 2772 .funcs = &sdma_v4_0_ip_funcs, 2773 }; 2774