1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "sdma0/sdma0_4_2_offset.h" 34 #include "sdma0/sdma0_4_2_sh_mask.h" 35 #include "sdma1/sdma1_4_2_offset.h" 36 #include "sdma1/sdma1_4_2_sh_mask.h" 37 #include "sdma2/sdma2_4_2_2_offset.h" 38 #include "sdma2/sdma2_4_2_2_sh_mask.h" 39 #include "sdma3/sdma3_4_2_2_offset.h" 40 #include "sdma3/sdma3_4_2_2_sh_mask.h" 41 #include "sdma4/sdma4_4_2_2_offset.h" 42 #include "sdma4/sdma4_4_2_2_sh_mask.h" 43 #include "sdma5/sdma5_4_2_2_offset.h" 44 #include "sdma5/sdma5_4_2_2_sh_mask.h" 45 #include "sdma6/sdma6_4_2_2_offset.h" 46 #include "sdma6/sdma6_4_2_2_sh_mask.h" 47 #include "sdma7/sdma7_4_2_2_offset.h" 48 #include "sdma7/sdma7_4_2_2_sh_mask.h" 49 #include "sdma0/sdma0_4_1_default.h" 50 51 #include "soc15_common.h" 52 #include "soc15.h" 53 #include "vega10_sdma_pkt_open.h" 54 55 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h" 56 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h" 57 58 #include "amdgpu_ras.h" 59 #include "sdma_v4_4.h" 60 61 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin"); 62 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin"); 63 MODULE_FIRMWARE("amdgpu/vega12_sdma.bin"); 64 MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin"); 65 MODULE_FIRMWARE("amdgpu/vega20_sdma.bin"); 66 MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin"); 67 MODULE_FIRMWARE("amdgpu/raven_sdma.bin"); 68 MODULE_FIRMWARE("amdgpu/picasso_sdma.bin"); 69 MODULE_FIRMWARE("amdgpu/raven2_sdma.bin"); 70 MODULE_FIRMWARE("amdgpu/arcturus_sdma.bin"); 71 MODULE_FIRMWARE("amdgpu/renoir_sdma.bin"); 72 MODULE_FIRMWARE("amdgpu/green_sardine_sdma.bin"); 73 MODULE_FIRMWARE("amdgpu/aldebaran_sdma.bin"); 74 75 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L 76 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L 77 78 #define WREG32_SDMA(instance, offset, value) \ 79 WREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)), value) 80 #define RREG32_SDMA(instance, offset) \ 81 RREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset))) 82 83 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev); 84 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev); 85 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev); 86 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev); 87 static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev); 88 89 static const struct soc15_reg_golden golden_settings_sdma_4[] = { 90 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 91 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100), 92 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100), 93 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 94 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 95 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 96 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000), 97 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 98 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 99 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 100 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 101 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 102 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000), 103 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), 104 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100), 105 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 106 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 107 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 108 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000), 109 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 110 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 111 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 112 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 113 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0), 114 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xfc000000, 0x00000000) 115 }; 116 117 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = { 118 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 119 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 120 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 121 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 122 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 123 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 124 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 125 }; 126 127 static const struct soc15_reg_golden golden_settings_sdma_vg12[] = { 128 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), 129 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001), 130 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 131 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 132 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), 133 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001), 134 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 135 }; 136 137 static const struct soc15_reg_golden golden_settings_sdma_4_1[] = { 138 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 139 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 140 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100), 141 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 142 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051), 143 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100), 144 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 145 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100), 146 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 147 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003e0), 148 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000) 149 }; 150 151 static const struct soc15_reg_golden golden_settings_sdma0_4_2_init[] = { 152 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 153 }; 154 155 static const struct soc15_reg_golden golden_settings_sdma0_4_2[] = 156 { 157 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 158 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 159 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 160 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 161 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 162 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 163 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 164 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 165 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RD_BURST_CNTL, 0x0000000f, 0x00000003), 166 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 167 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 168 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 169 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 170 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 171 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 172 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 173 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 174 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 175 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 176 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 177 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 178 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 179 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 180 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 181 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 182 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 183 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 184 }; 185 186 static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = { 187 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 188 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), 189 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 190 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 191 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 192 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 193 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 194 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 195 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RD_BURST_CNTL, 0x0000000f, 0x00000003), 196 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 197 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 198 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 199 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 200 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 201 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 202 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 203 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 204 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 205 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 206 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 207 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 208 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 209 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 210 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 211 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 212 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0), 213 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 214 }; 215 216 static const struct soc15_reg_golden golden_settings_sdma_rv1[] = 217 { 218 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002), 219 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002) 220 }; 221 222 static const struct soc15_reg_golden golden_settings_sdma_rv2[] = 223 { 224 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00003001), 225 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003001) 226 }; 227 228 static const struct soc15_reg_golden golden_settings_sdma_arct[] = 229 { 230 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 231 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 232 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 233 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 234 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 235 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 236 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 237 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 238 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 239 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 240 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 241 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 242 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 243 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 244 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 245 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 246 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 247 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 248 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 249 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 250 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 251 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 252 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 253 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 254 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 255 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 256 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 257 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 258 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 259 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 260 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 261 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_UTCL1_TIMEOUT, 0xffffffff, 0x00010001) 262 }; 263 264 static const struct soc15_reg_golden golden_settings_sdma_aldebaran[] = { 265 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 266 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 267 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 268 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 269 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 270 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 271 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 272 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 273 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA2_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 274 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 275 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 276 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 277 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 278 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 279 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 280 }; 281 282 static const struct soc15_reg_golden golden_settings_sdma_4_3[] = { 283 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 284 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 285 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002), 286 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002), 287 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 288 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003fff07, 0x40000051), 289 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 290 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 291 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003e0), 292 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x03fbe1fe) 293 }; 294 295 static const struct soc15_ras_field_entry sdma_v4_0_ras_fields[] = { 296 { "SDMA_UCODE_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 297 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UCODE_BUF_SED), 298 0, 0, 299 }, 300 { "SDMA_RB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 301 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_RB_CMD_BUF_SED), 302 0, 0, 303 }, 304 { "SDMA_IB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 305 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_IB_CMD_BUF_SED), 306 0, 0, 307 }, 308 { "SDMA_UTCL1_RD_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 309 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UTCL1_RD_FIFO_SED), 310 0, 0, 311 }, 312 { "SDMA_UTCL1_RDBST_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 313 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UTCL1_RDBST_FIFO_SED), 314 0, 0, 315 }, 316 { "SDMA_DATA_LUT_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 317 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_DATA_LUT_FIFO_SED), 318 0, 0, 319 }, 320 { "SDMA_MBANK_DATA_BUF0_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 321 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF0_SED), 322 0, 0, 323 }, 324 { "SDMA_MBANK_DATA_BUF1_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 325 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF1_SED), 326 0, 0, 327 }, 328 { "SDMA_MBANK_DATA_BUF2_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 329 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF2_SED), 330 0, 0, 331 }, 332 { "SDMA_MBANK_DATA_BUF3_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 333 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF3_SED), 334 0, 0, 335 }, 336 { "SDMA_MBANK_DATA_BUF4_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 337 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF4_SED), 338 0, 0, 339 }, 340 { "SDMA_MBANK_DATA_BUF5_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 341 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF5_SED), 342 0, 0, 343 }, 344 { "SDMA_MBANK_DATA_BUF6_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 345 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF6_SED), 346 0, 0, 347 }, 348 { "SDMA_MBANK_DATA_BUF7_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 349 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF7_SED), 350 0, 0, 351 }, 352 { "SDMA_MBANK_DATA_BUF8_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 353 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF8_SED), 354 0, 0, 355 }, 356 { "SDMA_MBANK_DATA_BUF9_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 357 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF9_SED), 358 0, 0, 359 }, 360 { "SDMA_MBANK_DATA_BUF10_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 361 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF10_SED), 362 0, 0, 363 }, 364 { "SDMA_MBANK_DATA_BUF11_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 365 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF11_SED), 366 0, 0, 367 }, 368 { "SDMA_MBANK_DATA_BUF12_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 369 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF12_SED), 370 0, 0, 371 }, 372 { "SDMA_MBANK_DATA_BUF13_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 373 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF13_SED), 374 0, 0, 375 }, 376 { "SDMA_MBANK_DATA_BUF14_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 377 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF14_SED), 378 0, 0, 379 }, 380 { "SDMA_MBANK_DATA_BUF15_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 381 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF15_SED), 382 0, 0, 383 }, 384 { "SDMA_SPLIT_DAT_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 385 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_SPLIT_DAT_BUF_SED), 386 0, 0, 387 }, 388 { "SDMA_MC_WR_ADDR_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 389 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MC_WR_ADDR_FIFO_SED), 390 0, 0, 391 }, 392 }; 393 394 static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev, 395 u32 instance, u32 offset) 396 { 397 switch (instance) { 398 case 0: 399 return (adev->reg_offset[SDMA0_HWIP][0][0] + offset); 400 case 1: 401 return (adev->reg_offset[SDMA1_HWIP][0][0] + offset); 402 case 2: 403 return (adev->reg_offset[SDMA2_HWIP][0][1] + offset); 404 case 3: 405 return (adev->reg_offset[SDMA3_HWIP][0][1] + offset); 406 case 4: 407 return (adev->reg_offset[SDMA4_HWIP][0][1] + offset); 408 case 5: 409 return (adev->reg_offset[SDMA5_HWIP][0][1] + offset); 410 case 6: 411 return (adev->reg_offset[SDMA6_HWIP][0][1] + offset); 412 case 7: 413 return (adev->reg_offset[SDMA7_HWIP][0][1] + offset); 414 default: 415 break; 416 } 417 return 0; 418 } 419 420 static unsigned sdma_v4_0_seq_to_irq_id(int seq_num) 421 { 422 switch (seq_num) { 423 case 0: 424 return SOC15_IH_CLIENTID_SDMA0; 425 case 1: 426 return SOC15_IH_CLIENTID_SDMA1; 427 case 2: 428 return SOC15_IH_CLIENTID_SDMA2; 429 case 3: 430 return SOC15_IH_CLIENTID_SDMA3; 431 case 4: 432 return SOC15_IH_CLIENTID_SDMA4; 433 case 5: 434 return SOC15_IH_CLIENTID_SDMA5; 435 case 6: 436 return SOC15_IH_CLIENTID_SDMA6; 437 case 7: 438 return SOC15_IH_CLIENTID_SDMA7; 439 default: 440 break; 441 } 442 return -EINVAL; 443 } 444 445 static int sdma_v4_0_irq_id_to_seq(unsigned client_id) 446 { 447 switch (client_id) { 448 case SOC15_IH_CLIENTID_SDMA0: 449 return 0; 450 case SOC15_IH_CLIENTID_SDMA1: 451 return 1; 452 case SOC15_IH_CLIENTID_SDMA2: 453 return 2; 454 case SOC15_IH_CLIENTID_SDMA3: 455 return 3; 456 case SOC15_IH_CLIENTID_SDMA4: 457 return 4; 458 case SOC15_IH_CLIENTID_SDMA5: 459 return 5; 460 case SOC15_IH_CLIENTID_SDMA6: 461 return 6; 462 case SOC15_IH_CLIENTID_SDMA7: 463 return 7; 464 default: 465 break; 466 } 467 return -EINVAL; 468 } 469 470 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) 471 { 472 switch (adev->ip_versions[SDMA0_HWIP][0]) { 473 case IP_VERSION(4, 0, 0): 474 soc15_program_register_sequence(adev, 475 golden_settings_sdma_4, 476 ARRAY_SIZE(golden_settings_sdma_4)); 477 soc15_program_register_sequence(adev, 478 golden_settings_sdma_vg10, 479 ARRAY_SIZE(golden_settings_sdma_vg10)); 480 break; 481 case IP_VERSION(4, 0, 1): 482 soc15_program_register_sequence(adev, 483 golden_settings_sdma_4, 484 ARRAY_SIZE(golden_settings_sdma_4)); 485 soc15_program_register_sequence(adev, 486 golden_settings_sdma_vg12, 487 ARRAY_SIZE(golden_settings_sdma_vg12)); 488 break; 489 case IP_VERSION(4, 2, 0): 490 soc15_program_register_sequence(adev, 491 golden_settings_sdma0_4_2_init, 492 ARRAY_SIZE(golden_settings_sdma0_4_2_init)); 493 soc15_program_register_sequence(adev, 494 golden_settings_sdma0_4_2, 495 ARRAY_SIZE(golden_settings_sdma0_4_2)); 496 soc15_program_register_sequence(adev, 497 golden_settings_sdma1_4_2, 498 ARRAY_SIZE(golden_settings_sdma1_4_2)); 499 break; 500 case IP_VERSION(4, 2, 2): 501 soc15_program_register_sequence(adev, 502 golden_settings_sdma_arct, 503 ARRAY_SIZE(golden_settings_sdma_arct)); 504 break; 505 case IP_VERSION(4, 4, 0): 506 soc15_program_register_sequence(adev, 507 golden_settings_sdma_aldebaran, 508 ARRAY_SIZE(golden_settings_sdma_aldebaran)); 509 break; 510 case IP_VERSION(4, 1, 0): 511 case IP_VERSION(4, 1, 1): 512 soc15_program_register_sequence(adev, 513 golden_settings_sdma_4_1, 514 ARRAY_SIZE(golden_settings_sdma_4_1)); 515 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 516 soc15_program_register_sequence(adev, 517 golden_settings_sdma_rv2, 518 ARRAY_SIZE(golden_settings_sdma_rv2)); 519 else 520 soc15_program_register_sequence(adev, 521 golden_settings_sdma_rv1, 522 ARRAY_SIZE(golden_settings_sdma_rv1)); 523 break; 524 case IP_VERSION(4, 1, 2): 525 soc15_program_register_sequence(adev, 526 golden_settings_sdma_4_3, 527 ARRAY_SIZE(golden_settings_sdma_4_3)); 528 break; 529 default: 530 break; 531 } 532 } 533 534 static void sdma_v4_0_setup_ulv(struct amdgpu_device *adev) 535 { 536 int i; 537 538 /* 539 * The only chips with SDMAv4 and ULV are VG10 and VG20. 540 * Server SKUs take a different hysteresis setting from other SKUs. 541 */ 542 switch (adev->ip_versions[SDMA0_HWIP][0]) { 543 case IP_VERSION(4, 0, 0): 544 if (adev->pdev->device == 0x6860) 545 break; 546 return; 547 case IP_VERSION(4, 2, 0): 548 if (adev->pdev->device == 0x66a1) 549 break; 550 return; 551 default: 552 return; 553 } 554 555 for (i = 0; i < adev->sdma.num_instances; i++) { 556 uint32_t temp; 557 558 temp = RREG32_SDMA(i, mmSDMA0_ULV_CNTL); 559 temp = REG_SET_FIELD(temp, SDMA0_ULV_CNTL, HYSTERESIS, 0x0); 560 WREG32_SDMA(i, mmSDMA0_ULV_CNTL, temp); 561 } 562 } 563 564 static int sdma_v4_0_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst) 565 { 566 int err = 0; 567 const struct sdma_firmware_header_v1_0 *hdr; 568 569 err = amdgpu_ucode_validate(sdma_inst->fw); 570 if (err) 571 return err; 572 573 hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data; 574 sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version); 575 sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version); 576 577 if (sdma_inst->feature_version >= 20) 578 sdma_inst->burst_nop = true; 579 580 return 0; 581 } 582 583 static void sdma_v4_0_destroy_inst_ctx(struct amdgpu_device *adev) 584 { 585 int i; 586 587 for (i = 0; i < adev->sdma.num_instances; i++) { 588 release_firmware(adev->sdma.instance[i].fw); 589 adev->sdma.instance[i].fw = NULL; 590 591 /* arcturus shares the same FW memory across 592 all SDMA isntances */ 593 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) || 594 adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 0)) 595 break; 596 } 597 598 memset((void *)adev->sdma.instance, 0, 599 sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES); 600 } 601 602 /** 603 * sdma_v4_0_init_microcode - load ucode images from disk 604 * 605 * @adev: amdgpu_device pointer 606 * 607 * Use the firmware interface to load the ucode images into 608 * the driver (not loaded into hw). 609 * Returns 0 on success, error on failure. 610 */ 611 612 // emulation only, won't work on real chip 613 // vega10 real chip need to use PSP to load firmware 614 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev) 615 { 616 const char *chip_name; 617 char fw_name[30]; 618 int err = 0, i; 619 struct amdgpu_firmware_info *info = NULL; 620 const struct common_firmware_header *header = NULL; 621 622 DRM_DEBUG("\n"); 623 624 switch (adev->ip_versions[SDMA0_HWIP][0]) { 625 case IP_VERSION(4, 0, 0): 626 chip_name = "vega10"; 627 break; 628 case IP_VERSION(4, 0, 1): 629 chip_name = "vega12"; 630 break; 631 case IP_VERSION(4, 2, 0): 632 chip_name = "vega20"; 633 break; 634 case IP_VERSION(4, 1, 0): 635 case IP_VERSION(4, 1, 1): 636 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 637 chip_name = "raven2"; 638 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 639 chip_name = "picasso"; 640 else 641 chip_name = "raven"; 642 break; 643 case IP_VERSION(4, 2, 2): 644 chip_name = "arcturus"; 645 break; 646 case IP_VERSION(4, 1, 2): 647 if (adev->apu_flags & AMD_APU_IS_RENOIR) 648 chip_name = "renoir"; 649 else 650 chip_name = "green_sardine"; 651 break; 652 case IP_VERSION(4, 4, 0): 653 chip_name = "aldebaran"; 654 break; 655 default: 656 BUG(); 657 } 658 659 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 660 661 err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev); 662 if (err) 663 goto out; 664 665 err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[0]); 666 if (err) 667 goto out; 668 669 for (i = 1; i < adev->sdma.num_instances; i++) { 670 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) || 671 adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 0)) { 672 /* Acturus & Aldebaran will leverage the same FW memory 673 for every SDMA instance */ 674 memcpy((void *)&adev->sdma.instance[i], 675 (void *)&adev->sdma.instance[0], 676 sizeof(struct amdgpu_sdma_instance)); 677 } 678 else { 679 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i); 680 681 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 682 if (err) 683 goto out; 684 685 err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[i]); 686 if (err) 687 goto out; 688 } 689 } 690 691 DRM_DEBUG("psp_load == '%s'\n", 692 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); 693 694 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 695 for (i = 0; i < adev->sdma.num_instances; i++) { 696 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 697 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 698 info->fw = adev->sdma.instance[i].fw; 699 header = (const struct common_firmware_header *)info->fw->data; 700 adev->firmware.fw_size += 701 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 702 } 703 } 704 705 out: 706 if (err) { 707 DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name); 708 sdma_v4_0_destroy_inst_ctx(adev); 709 } 710 return err; 711 } 712 713 /** 714 * sdma_v4_0_ring_get_rptr - get the current read pointer 715 * 716 * @ring: amdgpu ring pointer 717 * 718 * Get the current rptr from the hardware (VEGA10+). 719 */ 720 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring) 721 { 722 u64 *rptr; 723 724 /* XXX check if swapping is necessary on BE */ 725 rptr = ((u64 *)ring->rptr_cpu_addr); 726 727 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 728 return ((*rptr) >> 2); 729 } 730 731 /** 732 * sdma_v4_0_ring_get_wptr - get the current write pointer 733 * 734 * @ring: amdgpu ring pointer 735 * 736 * Get the current wptr from the hardware (VEGA10+). 737 */ 738 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring) 739 { 740 struct amdgpu_device *adev = ring->adev; 741 u64 wptr; 742 743 if (ring->use_doorbell) { 744 /* XXX check if swapping is necessary on BE */ 745 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); 746 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 747 } else { 748 wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI); 749 wptr = wptr << 32; 750 wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR); 751 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", 752 ring->me, wptr); 753 } 754 755 return wptr >> 2; 756 } 757 758 /** 759 * sdma_v4_0_ring_set_wptr - commit the write pointer 760 * 761 * @ring: amdgpu ring pointer 762 * 763 * Write the wptr back to the hardware (VEGA10+). 764 */ 765 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring) 766 { 767 struct amdgpu_device *adev = ring->adev; 768 769 DRM_DEBUG("Setting write pointer\n"); 770 if (ring->use_doorbell) { 771 u64 *wb = (u64 *)ring->wptr_cpu_addr; 772 773 DRM_DEBUG("Using doorbell -- " 774 "wptr_offs == 0x%08x " 775 "lower_32_bits(ring->wptr << 2) == 0x%08x " 776 "upper_32_bits(ring->wptr << 2) == 0x%08x\n", 777 ring->wptr_offs, 778 lower_32_bits(ring->wptr << 2), 779 upper_32_bits(ring->wptr << 2)); 780 /* XXX check if swapping is necessary on BE */ 781 WRITE_ONCE(*wb, (ring->wptr << 2)); 782 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 783 ring->doorbell_index, ring->wptr << 2); 784 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 785 } else { 786 DRM_DEBUG("Not using doorbell -- " 787 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 788 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 789 ring->me, 790 lower_32_bits(ring->wptr << 2), 791 ring->me, 792 upper_32_bits(ring->wptr << 2)); 793 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR, 794 lower_32_bits(ring->wptr << 2)); 795 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI, 796 upper_32_bits(ring->wptr << 2)); 797 } 798 } 799 800 /** 801 * sdma_v4_0_page_ring_get_wptr - get the current write pointer 802 * 803 * @ring: amdgpu ring pointer 804 * 805 * Get the current wptr from the hardware (VEGA10+). 806 */ 807 static uint64_t sdma_v4_0_page_ring_get_wptr(struct amdgpu_ring *ring) 808 { 809 struct amdgpu_device *adev = ring->adev; 810 u64 wptr; 811 812 if (ring->use_doorbell) { 813 /* XXX check if swapping is necessary on BE */ 814 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); 815 } else { 816 wptr = RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI); 817 wptr = wptr << 32; 818 wptr |= RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR); 819 } 820 821 return wptr >> 2; 822 } 823 824 /** 825 * sdma_v4_0_page_ring_set_wptr - commit the write pointer 826 * 827 * @ring: amdgpu ring pointer 828 * 829 * Write the wptr back to the hardware (VEGA10+). 830 */ 831 static void sdma_v4_0_page_ring_set_wptr(struct amdgpu_ring *ring) 832 { 833 struct amdgpu_device *adev = ring->adev; 834 835 if (ring->use_doorbell) { 836 u64 *wb = (u64 *)ring->wptr_cpu_addr; 837 838 /* XXX check if swapping is necessary on BE */ 839 WRITE_ONCE(*wb, (ring->wptr << 2)); 840 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 841 } else { 842 uint64_t wptr = ring->wptr << 2; 843 844 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR, 845 lower_32_bits(wptr)); 846 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI, 847 upper_32_bits(wptr)); 848 } 849 } 850 851 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 852 { 853 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 854 int i; 855 856 for (i = 0; i < count; i++) 857 if (sdma && sdma->burst_nop && (i == 0)) 858 amdgpu_ring_write(ring, ring->funcs->nop | 859 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 860 else 861 amdgpu_ring_write(ring, ring->funcs->nop); 862 } 863 864 /** 865 * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine 866 * 867 * @ring: amdgpu ring pointer 868 * @job: job to retrieve vmid from 869 * @ib: IB object to schedule 870 * @flags: unused 871 * 872 * Schedule an IB in the DMA ring (VEGA10). 873 */ 874 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring, 875 struct amdgpu_job *job, 876 struct amdgpu_ib *ib, 877 uint32_t flags) 878 { 879 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 880 881 /* IB packet must end on a 8 DW boundary */ 882 sdma_v4_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 883 884 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 885 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 886 /* base must be 32 byte aligned */ 887 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 888 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 889 amdgpu_ring_write(ring, ib->length_dw); 890 amdgpu_ring_write(ring, 0); 891 amdgpu_ring_write(ring, 0); 892 893 } 894 895 static void sdma_v4_0_wait_reg_mem(struct amdgpu_ring *ring, 896 int mem_space, int hdp, 897 uint32_t addr0, uint32_t addr1, 898 uint32_t ref, uint32_t mask, 899 uint32_t inv) 900 { 901 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 902 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) | 903 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) | 904 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 905 if (mem_space) { 906 /* memory */ 907 amdgpu_ring_write(ring, addr0); 908 amdgpu_ring_write(ring, addr1); 909 } else { 910 /* registers */ 911 amdgpu_ring_write(ring, addr0 << 2); 912 amdgpu_ring_write(ring, addr1 << 2); 913 } 914 amdgpu_ring_write(ring, ref); /* reference */ 915 amdgpu_ring_write(ring, mask); /* mask */ 916 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 917 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */ 918 } 919 920 /** 921 * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 922 * 923 * @ring: amdgpu ring pointer 924 * 925 * Emit an hdp flush packet on the requested DMA ring. 926 */ 927 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 928 { 929 struct amdgpu_device *adev = ring->adev; 930 u32 ref_and_mask = 0; 931 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 932 933 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; 934 935 sdma_v4_0_wait_reg_mem(ring, 0, 1, 936 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 937 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 938 ref_and_mask, ref_and_mask, 10); 939 } 940 941 /** 942 * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring 943 * 944 * @ring: amdgpu ring pointer 945 * @addr: address 946 * @seq: sequence number 947 * @flags: fence related flags 948 * 949 * Add a DMA fence packet to the ring to write 950 * the fence seq number and DMA trap packet to generate 951 * an interrupt if needed (VEGA10). 952 */ 953 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 954 unsigned flags) 955 { 956 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 957 /* write the fence */ 958 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 959 /* zero in first two bits */ 960 BUG_ON(addr & 0x3); 961 amdgpu_ring_write(ring, lower_32_bits(addr)); 962 amdgpu_ring_write(ring, upper_32_bits(addr)); 963 amdgpu_ring_write(ring, lower_32_bits(seq)); 964 965 /* optionally write high bits as well */ 966 if (write64bit) { 967 addr += 4; 968 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 969 /* zero in first two bits */ 970 BUG_ON(addr & 0x3); 971 amdgpu_ring_write(ring, lower_32_bits(addr)); 972 amdgpu_ring_write(ring, upper_32_bits(addr)); 973 amdgpu_ring_write(ring, upper_32_bits(seq)); 974 } 975 976 /* generate an interrupt */ 977 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 978 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 979 } 980 981 982 /** 983 * sdma_v4_0_gfx_stop - stop the gfx async dma engines 984 * 985 * @adev: amdgpu_device pointer 986 * 987 * Stop the gfx async dma ring buffers (VEGA10). 988 */ 989 static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev) 990 { 991 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; 992 u32 rb_cntl, ib_cntl; 993 int i, unset = 0; 994 995 for (i = 0; i < adev->sdma.num_instances; i++) { 996 sdma[i] = &adev->sdma.instance[i].ring; 997 998 if ((adev->mman.buffer_funcs_ring == sdma[i]) && unset != 1) { 999 amdgpu_ttm_set_buffer_funcs_status(adev, false); 1000 unset = 1; 1001 } 1002 1003 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL); 1004 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 1005 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 1006 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL); 1007 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 1008 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl); 1009 } 1010 } 1011 1012 /** 1013 * sdma_v4_0_rlc_stop - stop the compute async dma engines 1014 * 1015 * @adev: amdgpu_device pointer 1016 * 1017 * Stop the compute async dma queues (VEGA10). 1018 */ 1019 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev) 1020 { 1021 /* XXX todo */ 1022 } 1023 1024 /** 1025 * sdma_v4_0_page_stop - stop the page async dma engines 1026 * 1027 * @adev: amdgpu_device pointer 1028 * 1029 * Stop the page async dma ring buffers (VEGA10). 1030 */ 1031 static void sdma_v4_0_page_stop(struct amdgpu_device *adev) 1032 { 1033 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; 1034 u32 rb_cntl, ib_cntl; 1035 int i; 1036 bool unset = false; 1037 1038 for (i = 0; i < adev->sdma.num_instances; i++) { 1039 sdma[i] = &adev->sdma.instance[i].page; 1040 1041 if ((adev->mman.buffer_funcs_ring == sdma[i]) && 1042 (!unset)) { 1043 amdgpu_ttm_set_buffer_funcs_status(adev, false); 1044 unset = true; 1045 } 1046 1047 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL); 1048 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, 1049 RB_ENABLE, 0); 1050 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 1051 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL); 1052 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, 1053 IB_ENABLE, 0); 1054 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl); 1055 } 1056 } 1057 1058 /** 1059 * sdma_v4_0_ctx_switch_enable - stop the async dma engines context switch 1060 * 1061 * @adev: amdgpu_device pointer 1062 * @enable: enable/disable the DMA MEs context switch. 1063 * 1064 * Halt or unhalt the async dma engines context switch (VEGA10). 1065 */ 1066 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 1067 { 1068 u32 f32_cntl, phase_quantum = 0; 1069 int i; 1070 1071 if (amdgpu_sdma_phase_quantum) { 1072 unsigned value = amdgpu_sdma_phase_quantum; 1073 unsigned unit = 0; 1074 1075 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 1076 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 1077 value = (value + 1) >> 1; 1078 unit++; 1079 } 1080 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 1081 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 1082 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 1083 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 1084 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 1085 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 1086 WARN_ONCE(1, 1087 "clamping sdma_phase_quantum to %uK clock cycles\n", 1088 value << unit); 1089 } 1090 phase_quantum = 1091 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 1092 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 1093 } 1094 1095 for (i = 0; i < adev->sdma.num_instances; i++) { 1096 f32_cntl = RREG32_SDMA(i, mmSDMA0_CNTL); 1097 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 1098 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 1099 if (enable && amdgpu_sdma_phase_quantum) { 1100 WREG32_SDMA(i, mmSDMA0_PHASE0_QUANTUM, phase_quantum); 1101 WREG32_SDMA(i, mmSDMA0_PHASE1_QUANTUM, phase_quantum); 1102 WREG32_SDMA(i, mmSDMA0_PHASE2_QUANTUM, phase_quantum); 1103 } 1104 WREG32_SDMA(i, mmSDMA0_CNTL, f32_cntl); 1105 1106 /* 1107 * Enable SDMA utilization. Its only supported on 1108 * Arcturus for the moment and firmware version 14 1109 * and above. 1110 */ 1111 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) && 1112 adev->sdma.instance[i].fw_version >= 14) 1113 WREG32_SDMA(i, mmSDMA0_PUB_DUMMY_REG2, enable); 1114 /* Extend page fault timeout to avoid interrupt storm */ 1115 WREG32_SDMA(i, mmSDMA0_UTCL1_TIMEOUT, 0x00800080); 1116 } 1117 1118 } 1119 1120 /** 1121 * sdma_v4_0_enable - stop the async dma engines 1122 * 1123 * @adev: amdgpu_device pointer 1124 * @enable: enable/disable the DMA MEs. 1125 * 1126 * Halt or unhalt the async dma engines (VEGA10). 1127 */ 1128 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable) 1129 { 1130 u32 f32_cntl; 1131 int i; 1132 1133 if (!enable) { 1134 sdma_v4_0_gfx_stop(adev); 1135 sdma_v4_0_rlc_stop(adev); 1136 if (adev->sdma.has_page_queue) 1137 sdma_v4_0_page_stop(adev); 1138 } 1139 1140 for (i = 0; i < adev->sdma.num_instances; i++) { 1141 f32_cntl = RREG32_SDMA(i, mmSDMA0_F32_CNTL); 1142 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 1143 WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl); 1144 } 1145 } 1146 1147 /* 1148 * sdma_v4_0_rb_cntl - get parameters for rb_cntl 1149 */ 1150 static uint32_t sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl) 1151 { 1152 /* Set ring buffer size in dwords */ 1153 uint32_t rb_bufsz = order_base_2(ring->ring_size / 4); 1154 1155 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 1156 #ifdef __BIG_ENDIAN 1157 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 1158 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 1159 RPTR_WRITEBACK_SWAP_ENABLE, 1); 1160 #endif 1161 return rb_cntl; 1162 } 1163 1164 /** 1165 * sdma_v4_0_gfx_resume - setup and start the async dma engines 1166 * 1167 * @adev: amdgpu_device pointer 1168 * @i: instance to resume 1169 * 1170 * Set up the gfx DMA ring buffers and enable them (VEGA10). 1171 * Returns 0 for success, error for failure. 1172 */ 1173 static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i) 1174 { 1175 struct amdgpu_ring *ring = &adev->sdma.instance[i].ring; 1176 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 1177 u32 doorbell; 1178 u32 doorbell_offset; 1179 u64 wptr_gpu_addr; 1180 1181 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL); 1182 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl); 1183 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 1184 1185 /* Initialize the ring buffer's read and write pointers */ 1186 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR, 0); 1187 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_HI, 0); 1188 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR, 0); 1189 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_HI, 0); 1190 1191 /* set the wb address whether it's enabled or not */ 1192 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI, 1193 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); 1194 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 1195 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); 1196 1197 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 1198 RPTR_WRITEBACK_ENABLE, 1); 1199 1200 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE, ring->gpu_addr >> 8); 1201 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE_HI, ring->gpu_addr >> 40); 1202 1203 ring->wptr = 0; 1204 1205 /* before programing wptr to a less value, need set minor_ptr_update first */ 1206 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 1); 1207 1208 doorbell = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL); 1209 doorbell_offset = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET); 1210 1211 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1212 ring->use_doorbell); 1213 doorbell_offset = REG_SET_FIELD(doorbell_offset, 1214 SDMA0_GFX_DOORBELL_OFFSET, 1215 OFFSET, ring->doorbell_index); 1216 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL, doorbell); 1217 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET, doorbell_offset); 1218 1219 sdma_v4_0_ring_set_wptr(ring); 1220 1221 /* set minor_ptr_update to 0 after wptr programed */ 1222 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 0); 1223 1224 /* setup the wptr shadow polling */ 1225 wptr_gpu_addr = ring->wptr_gpu_addr; 1226 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO, 1227 lower_32_bits(wptr_gpu_addr)); 1228 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI, 1229 upper_32_bits(wptr_gpu_addr)); 1230 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL); 1231 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 1232 SDMA0_GFX_RB_WPTR_POLL_CNTL, 1233 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 1234 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 1235 1236 /* enable DMA RB */ 1237 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 1238 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 1239 1240 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL); 1241 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 1242 #ifdef __BIG_ENDIAN 1243 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 1244 #endif 1245 /* enable DMA IBs */ 1246 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl); 1247 1248 ring->sched.ready = true; 1249 } 1250 1251 /** 1252 * sdma_v4_0_page_resume - setup and start the async dma engines 1253 * 1254 * @adev: amdgpu_device pointer 1255 * @i: instance to resume 1256 * 1257 * Set up the page DMA ring buffers and enable them (VEGA10). 1258 * Returns 0 for success, error for failure. 1259 */ 1260 static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i) 1261 { 1262 struct amdgpu_ring *ring = &adev->sdma.instance[i].page; 1263 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 1264 u32 doorbell; 1265 u32 doorbell_offset; 1266 u64 wptr_gpu_addr; 1267 1268 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL); 1269 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl); 1270 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 1271 1272 /* Initialize the ring buffer's read and write pointers */ 1273 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR, 0); 1274 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_HI, 0); 1275 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR, 0); 1276 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_HI, 0); 1277 1278 /* set the wb address whether it's enabled or not */ 1279 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_HI, 1280 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); 1281 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 1282 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); 1283 1284 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, 1285 RPTR_WRITEBACK_ENABLE, 1); 1286 1287 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE, ring->gpu_addr >> 8); 1288 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE_HI, ring->gpu_addr >> 40); 1289 1290 ring->wptr = 0; 1291 1292 /* before programing wptr to a less value, need set minor_ptr_update first */ 1293 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 1); 1294 1295 doorbell = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL); 1296 doorbell_offset = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET); 1297 1298 doorbell = REG_SET_FIELD(doorbell, SDMA0_PAGE_DOORBELL, ENABLE, 1299 ring->use_doorbell); 1300 doorbell_offset = REG_SET_FIELD(doorbell_offset, 1301 SDMA0_PAGE_DOORBELL_OFFSET, 1302 OFFSET, ring->doorbell_index); 1303 WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL, doorbell); 1304 WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET, doorbell_offset); 1305 1306 /* paging queue doorbell range is setup at sdma_v4_0_gfx_resume */ 1307 sdma_v4_0_page_ring_set_wptr(ring); 1308 1309 /* set minor_ptr_update to 0 after wptr programed */ 1310 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 0); 1311 1312 /* setup the wptr shadow polling */ 1313 wptr_gpu_addr = ring->wptr_gpu_addr; 1314 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO, 1315 lower_32_bits(wptr_gpu_addr)); 1316 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI, 1317 upper_32_bits(wptr_gpu_addr)); 1318 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL); 1319 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 1320 SDMA0_PAGE_RB_WPTR_POLL_CNTL, 1321 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 1322 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 1323 1324 /* enable DMA RB */ 1325 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, RB_ENABLE, 1); 1326 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 1327 1328 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL); 1329 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_ENABLE, 1); 1330 #ifdef __BIG_ENDIAN 1331 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1); 1332 #endif 1333 /* enable DMA IBs */ 1334 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl); 1335 1336 ring->sched.ready = true; 1337 } 1338 1339 static void 1340 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable) 1341 { 1342 uint32_t def, data; 1343 1344 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) { 1345 /* enable idle interrupt */ 1346 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 1347 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 1348 1349 if (data != def) 1350 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 1351 } else { 1352 /* disable idle interrupt */ 1353 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 1354 data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 1355 if (data != def) 1356 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 1357 } 1358 } 1359 1360 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev) 1361 { 1362 uint32_t def, data; 1363 1364 /* Enable HW based PG. */ 1365 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1366 data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK; 1367 if (data != def) 1368 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1369 1370 /* enable interrupt */ 1371 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 1372 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 1373 if (data != def) 1374 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 1375 1376 /* Configure hold time to filter in-valid power on/off request. Use default right now */ 1377 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1378 data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK; 1379 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK); 1380 /* Configure switch time for hysteresis purpose. Use default right now */ 1381 data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK; 1382 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK); 1383 if(data != def) 1384 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1385 } 1386 1387 static void sdma_v4_0_init_pg(struct amdgpu_device *adev) 1388 { 1389 if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA)) 1390 return; 1391 1392 switch (adev->ip_versions[SDMA0_HWIP][0]) { 1393 case IP_VERSION(4, 1, 0): 1394 case IP_VERSION(4, 1, 1): 1395 case IP_VERSION(4, 1, 2): 1396 sdma_v4_1_init_power_gating(adev); 1397 sdma_v4_1_update_power_gating(adev, true); 1398 break; 1399 default: 1400 break; 1401 } 1402 } 1403 1404 /** 1405 * sdma_v4_0_rlc_resume - setup and start the async dma engines 1406 * 1407 * @adev: amdgpu_device pointer 1408 * 1409 * Set up the compute DMA queues and enable them (VEGA10). 1410 * Returns 0 for success, error for failure. 1411 */ 1412 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev) 1413 { 1414 sdma_v4_0_init_pg(adev); 1415 1416 return 0; 1417 } 1418 1419 /** 1420 * sdma_v4_0_load_microcode - load the sDMA ME ucode 1421 * 1422 * @adev: amdgpu_device pointer 1423 * 1424 * Loads the sDMA0/1 ucode. 1425 * Returns 0 for success, -EINVAL if the ucode is not available. 1426 */ 1427 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev) 1428 { 1429 const struct sdma_firmware_header_v1_0 *hdr; 1430 const __le32 *fw_data; 1431 u32 fw_size; 1432 int i, j; 1433 1434 /* halt the MEs */ 1435 sdma_v4_0_enable(adev, false); 1436 1437 for (i = 0; i < adev->sdma.num_instances; i++) { 1438 if (!adev->sdma.instance[i].fw) 1439 return -EINVAL; 1440 1441 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 1442 amdgpu_ucode_print_sdma_hdr(&hdr->header); 1443 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1444 1445 fw_data = (const __le32 *) 1446 (adev->sdma.instance[i].fw->data + 1447 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1448 1449 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 0); 1450 1451 for (j = 0; j < fw_size; j++) 1452 WREG32_SDMA(i, mmSDMA0_UCODE_DATA, 1453 le32_to_cpup(fw_data++)); 1454 1455 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 1456 adev->sdma.instance[i].fw_version); 1457 } 1458 1459 return 0; 1460 } 1461 1462 /** 1463 * sdma_v4_0_start - setup and start the async dma engines 1464 * 1465 * @adev: amdgpu_device pointer 1466 * 1467 * Set up the DMA engines and enable them (VEGA10). 1468 * Returns 0 for success, error for failure. 1469 */ 1470 static int sdma_v4_0_start(struct amdgpu_device *adev) 1471 { 1472 struct amdgpu_ring *ring; 1473 int i, r = 0; 1474 1475 if (amdgpu_sriov_vf(adev)) { 1476 sdma_v4_0_ctx_switch_enable(adev, false); 1477 sdma_v4_0_enable(adev, false); 1478 } else { 1479 1480 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1481 r = sdma_v4_0_load_microcode(adev); 1482 if (r) 1483 return r; 1484 } 1485 1486 /* unhalt the MEs */ 1487 sdma_v4_0_enable(adev, true); 1488 /* enable sdma ring preemption */ 1489 sdma_v4_0_ctx_switch_enable(adev, true); 1490 } 1491 1492 /* start the gfx rings and rlc compute queues */ 1493 for (i = 0; i < adev->sdma.num_instances; i++) { 1494 uint32_t temp; 1495 1496 WREG32_SDMA(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL, 0); 1497 sdma_v4_0_gfx_resume(adev, i); 1498 if (adev->sdma.has_page_queue) 1499 sdma_v4_0_page_resume(adev, i); 1500 1501 /* set utc l1 enable flag always to 1 */ 1502 temp = RREG32_SDMA(i, mmSDMA0_CNTL); 1503 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 1504 WREG32_SDMA(i, mmSDMA0_CNTL, temp); 1505 1506 if (!amdgpu_sriov_vf(adev)) { 1507 ring = &adev->sdma.instance[i].ring; 1508 adev->nbio.funcs->sdma_doorbell_range(adev, i, 1509 ring->use_doorbell, ring->doorbell_index, 1510 adev->doorbell_index.sdma_doorbell_range); 1511 1512 /* unhalt engine */ 1513 temp = RREG32_SDMA(i, mmSDMA0_F32_CNTL); 1514 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 1515 WREG32_SDMA(i, mmSDMA0_F32_CNTL, temp); 1516 } 1517 } 1518 1519 if (amdgpu_sriov_vf(adev)) { 1520 sdma_v4_0_ctx_switch_enable(adev, true); 1521 sdma_v4_0_enable(adev, true); 1522 } else { 1523 r = sdma_v4_0_rlc_resume(adev); 1524 if (r) 1525 return r; 1526 } 1527 1528 for (i = 0; i < adev->sdma.num_instances; i++) { 1529 ring = &adev->sdma.instance[i].ring; 1530 1531 r = amdgpu_ring_test_helper(ring); 1532 if (r) 1533 return r; 1534 1535 if (adev->sdma.has_page_queue) { 1536 struct amdgpu_ring *page = &adev->sdma.instance[i].page; 1537 1538 r = amdgpu_ring_test_helper(page); 1539 if (r) 1540 return r; 1541 1542 if (adev->mman.buffer_funcs_ring == page) 1543 amdgpu_ttm_set_buffer_funcs_status(adev, true); 1544 } 1545 1546 if (adev->mman.buffer_funcs_ring == ring) 1547 amdgpu_ttm_set_buffer_funcs_status(adev, true); 1548 } 1549 1550 return r; 1551 } 1552 1553 /** 1554 * sdma_v4_0_ring_test_ring - simple async dma engine test 1555 * 1556 * @ring: amdgpu_ring structure holding ring information 1557 * 1558 * Test the DMA engine by writing using it to write an 1559 * value to memory. (VEGA10). 1560 * Returns 0 for success, error for failure. 1561 */ 1562 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring) 1563 { 1564 struct amdgpu_device *adev = ring->adev; 1565 unsigned i; 1566 unsigned index; 1567 int r; 1568 u32 tmp; 1569 u64 gpu_addr; 1570 1571 r = amdgpu_device_wb_get(adev, &index); 1572 if (r) 1573 return r; 1574 1575 gpu_addr = adev->wb.gpu_addr + (index * 4); 1576 tmp = 0xCAFEDEAD; 1577 adev->wb.wb[index] = cpu_to_le32(tmp); 1578 1579 r = amdgpu_ring_alloc(ring, 5); 1580 if (r) 1581 goto error_free_wb; 1582 1583 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1584 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 1585 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 1586 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 1587 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 1588 amdgpu_ring_write(ring, 0xDEADBEEF); 1589 amdgpu_ring_commit(ring); 1590 1591 for (i = 0; i < adev->usec_timeout; i++) { 1592 tmp = le32_to_cpu(adev->wb.wb[index]); 1593 if (tmp == 0xDEADBEEF) 1594 break; 1595 udelay(1); 1596 } 1597 1598 if (i >= adev->usec_timeout) 1599 r = -ETIMEDOUT; 1600 1601 error_free_wb: 1602 amdgpu_device_wb_free(adev, index); 1603 return r; 1604 } 1605 1606 /** 1607 * sdma_v4_0_ring_test_ib - test an IB on the DMA engine 1608 * 1609 * @ring: amdgpu_ring structure holding ring information 1610 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 1611 * 1612 * Test a simple IB in the DMA ring (VEGA10). 1613 * Returns 0 on success, error on failure. 1614 */ 1615 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1616 { 1617 struct amdgpu_device *adev = ring->adev; 1618 struct amdgpu_ib ib; 1619 struct dma_fence *f = NULL; 1620 unsigned index; 1621 long r; 1622 u32 tmp = 0; 1623 u64 gpu_addr; 1624 1625 r = amdgpu_device_wb_get(adev, &index); 1626 if (r) 1627 return r; 1628 1629 gpu_addr = adev->wb.gpu_addr + (index * 4); 1630 tmp = 0xCAFEDEAD; 1631 adev->wb.wb[index] = cpu_to_le32(tmp); 1632 memset(&ib, 0, sizeof(ib)); 1633 r = amdgpu_ib_get(adev, NULL, 256, 1634 AMDGPU_IB_POOL_DIRECT, &ib); 1635 if (r) 1636 goto err0; 1637 1638 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1639 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1640 ib.ptr[1] = lower_32_bits(gpu_addr); 1641 ib.ptr[2] = upper_32_bits(gpu_addr); 1642 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1643 ib.ptr[4] = 0xDEADBEEF; 1644 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1645 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1646 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1647 ib.length_dw = 8; 1648 1649 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1650 if (r) 1651 goto err1; 1652 1653 r = dma_fence_wait_timeout(f, false, timeout); 1654 if (r == 0) { 1655 r = -ETIMEDOUT; 1656 goto err1; 1657 } else if (r < 0) { 1658 goto err1; 1659 } 1660 tmp = le32_to_cpu(adev->wb.wb[index]); 1661 if (tmp == 0xDEADBEEF) 1662 r = 0; 1663 else 1664 r = -EINVAL; 1665 1666 err1: 1667 amdgpu_ib_free(adev, &ib, NULL); 1668 dma_fence_put(f); 1669 err0: 1670 amdgpu_device_wb_free(adev, index); 1671 return r; 1672 } 1673 1674 1675 /** 1676 * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART 1677 * 1678 * @ib: indirect buffer to fill with commands 1679 * @pe: addr of the page entry 1680 * @src: src addr to copy from 1681 * @count: number of page entries to update 1682 * 1683 * Update PTEs by copying them from the GART using sDMA (VEGA10). 1684 */ 1685 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib, 1686 uint64_t pe, uint64_t src, 1687 unsigned count) 1688 { 1689 unsigned bytes = count * 8; 1690 1691 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1692 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1693 ib->ptr[ib->length_dw++] = bytes - 1; 1694 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1695 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1696 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1697 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1698 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1699 1700 } 1701 1702 /** 1703 * sdma_v4_0_vm_write_pte - update PTEs by writing them manually 1704 * 1705 * @ib: indirect buffer to fill with commands 1706 * @pe: addr of the page entry 1707 * @value: dst addr to write into pe 1708 * @count: number of page entries to update 1709 * @incr: increase next addr by incr bytes 1710 * 1711 * Update PTEs by writing them manually using sDMA (VEGA10). 1712 */ 1713 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1714 uint64_t value, unsigned count, 1715 uint32_t incr) 1716 { 1717 unsigned ndw = count * 2; 1718 1719 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1720 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1721 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1722 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1723 ib->ptr[ib->length_dw++] = ndw - 1; 1724 for (; ndw > 0; ndw -= 2) { 1725 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1726 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1727 value += incr; 1728 } 1729 } 1730 1731 /** 1732 * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA 1733 * 1734 * @ib: indirect buffer to fill with commands 1735 * @pe: addr of the page entry 1736 * @addr: dst addr to write into pe 1737 * @count: number of page entries to update 1738 * @incr: increase next addr by incr bytes 1739 * @flags: access flags 1740 * 1741 * Update the page tables using sDMA (VEGA10). 1742 */ 1743 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1744 uint64_t pe, 1745 uint64_t addr, unsigned count, 1746 uint32_t incr, uint64_t flags) 1747 { 1748 /* for physically contiguous pages (vram) */ 1749 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1750 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1751 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1752 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1753 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1754 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1755 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1756 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1757 ib->ptr[ib->length_dw++] = 0; 1758 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1759 } 1760 1761 /** 1762 * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw 1763 * 1764 * @ring: amdgpu_ring structure holding ring information 1765 * @ib: indirect buffer to fill with padding 1766 */ 1767 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1768 { 1769 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1770 u32 pad_count; 1771 int i; 1772 1773 pad_count = (-ib->length_dw) & 7; 1774 for (i = 0; i < pad_count; i++) 1775 if (sdma && sdma->burst_nop && (i == 0)) 1776 ib->ptr[ib->length_dw++] = 1777 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1778 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1779 else 1780 ib->ptr[ib->length_dw++] = 1781 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1782 } 1783 1784 1785 /** 1786 * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline 1787 * 1788 * @ring: amdgpu_ring pointer 1789 * 1790 * Make sure all previous operations are completed (CIK). 1791 */ 1792 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1793 { 1794 uint32_t seq = ring->fence_drv.sync_seq; 1795 uint64_t addr = ring->fence_drv.gpu_addr; 1796 1797 /* wait for idle */ 1798 sdma_v4_0_wait_reg_mem(ring, 1, 0, 1799 addr & 0xfffffffc, 1800 upper_32_bits(addr) & 0xffffffff, 1801 seq, 0xffffffff, 4); 1802 } 1803 1804 1805 /** 1806 * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA 1807 * 1808 * @ring: amdgpu_ring pointer 1809 * @vmid: vmid number to use 1810 * @pd_addr: address 1811 * 1812 * Update the page table base and flush the VM TLB 1813 * using sDMA (VEGA10). 1814 */ 1815 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1816 unsigned vmid, uint64_t pd_addr) 1817 { 1818 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1819 } 1820 1821 static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring, 1822 uint32_t reg, uint32_t val) 1823 { 1824 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1825 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1826 amdgpu_ring_write(ring, reg); 1827 amdgpu_ring_write(ring, val); 1828 } 1829 1830 static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1831 uint32_t val, uint32_t mask) 1832 { 1833 sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10); 1834 } 1835 1836 static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev) 1837 { 1838 uint fw_version = adev->sdma.instance[0].fw_version; 1839 1840 switch (adev->ip_versions[SDMA0_HWIP][0]) { 1841 case IP_VERSION(4, 0, 0): 1842 return fw_version >= 430; 1843 case IP_VERSION(4, 0, 1): 1844 /*return fw_version >= 31;*/ 1845 return false; 1846 case IP_VERSION(4, 2, 0): 1847 return fw_version >= 123; 1848 default: 1849 return false; 1850 } 1851 } 1852 1853 static int sdma_v4_0_early_init(void *handle) 1854 { 1855 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1856 int r; 1857 1858 r = sdma_v4_0_init_microcode(adev); 1859 if (r) { 1860 DRM_ERROR("Failed to load sdma firmware!\n"); 1861 return r; 1862 } 1863 1864 /* TODO: Page queue breaks driver reload under SRIOV */ 1865 if ((adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 0, 0)) && 1866 amdgpu_sriov_vf((adev))) 1867 adev->sdma.has_page_queue = false; 1868 else if (sdma_v4_0_fw_support_paging_queue(adev)) 1869 adev->sdma.has_page_queue = true; 1870 1871 sdma_v4_0_set_ring_funcs(adev); 1872 sdma_v4_0_set_buffer_funcs(adev); 1873 sdma_v4_0_set_vm_pte_funcs(adev); 1874 sdma_v4_0_set_irq_funcs(adev); 1875 sdma_v4_0_set_ras_funcs(adev); 1876 1877 return 0; 1878 } 1879 1880 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev, 1881 void *err_data, 1882 struct amdgpu_iv_entry *entry); 1883 1884 static int sdma_v4_0_late_init(void *handle) 1885 { 1886 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1887 1888 sdma_v4_0_setup_ulv(adev); 1889 1890 if (!amdgpu_persistent_edc_harvesting_supported(adev)) { 1891 if (adev->sdma.ras && adev->sdma.ras->ras_block.hw_ops && 1892 adev->sdma.ras->ras_block.hw_ops->reset_ras_error_count) 1893 adev->sdma.ras->ras_block.hw_ops->reset_ras_error_count(adev); 1894 } 1895 1896 return 0; 1897 } 1898 1899 static int sdma_v4_0_sw_init(void *handle) 1900 { 1901 struct amdgpu_ring *ring; 1902 int r, i; 1903 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1904 1905 /* SDMA trap event */ 1906 for (i = 0; i < adev->sdma.num_instances; i++) { 1907 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1908 SDMA0_4_0__SRCID__SDMA_TRAP, 1909 &adev->sdma.trap_irq); 1910 if (r) 1911 return r; 1912 } 1913 1914 /* SDMA SRAM ECC event */ 1915 for (i = 0; i < adev->sdma.num_instances; i++) { 1916 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1917 SDMA0_4_0__SRCID__SDMA_SRAM_ECC, 1918 &adev->sdma.ecc_irq); 1919 if (r) 1920 return r; 1921 } 1922 1923 /* SDMA VM_HOLE/DOORBELL_INV/POLL_TIMEOUT/SRBM_WRITE_PROTECTION event*/ 1924 for (i = 0; i < adev->sdma.num_instances; i++) { 1925 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1926 SDMA0_4_0__SRCID__SDMA_VM_HOLE, 1927 &adev->sdma.vm_hole_irq); 1928 if (r) 1929 return r; 1930 1931 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1932 SDMA0_4_0__SRCID__SDMA_DOORBELL_INVALID, 1933 &adev->sdma.doorbell_invalid_irq); 1934 if (r) 1935 return r; 1936 1937 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1938 SDMA0_4_0__SRCID__SDMA_POLL_TIMEOUT, 1939 &adev->sdma.pool_timeout_irq); 1940 if (r) 1941 return r; 1942 1943 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1944 SDMA0_4_0__SRCID__SDMA_SRBMWRITE, 1945 &adev->sdma.srbm_write_irq); 1946 if (r) 1947 return r; 1948 } 1949 1950 for (i = 0; i < adev->sdma.num_instances; i++) { 1951 ring = &adev->sdma.instance[i].ring; 1952 ring->ring_obj = NULL; 1953 ring->use_doorbell = true; 1954 1955 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1956 ring->use_doorbell?"true":"false"); 1957 1958 /* doorbell size is 2 dwords, get DWORD offset */ 1959 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1; 1960 1961 sprintf(ring->name, "sdma%d", i); 1962 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1963 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1964 AMDGPU_RING_PRIO_DEFAULT, NULL); 1965 if (r) 1966 return r; 1967 1968 if (adev->sdma.has_page_queue) { 1969 ring = &adev->sdma.instance[i].page; 1970 ring->ring_obj = NULL; 1971 ring->use_doorbell = true; 1972 1973 /* paging queue use same doorbell index/routing as gfx queue 1974 * with 0x400 (4096 dwords) offset on second doorbell page 1975 */ 1976 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1; 1977 ring->doorbell_index += 0x400; 1978 1979 sprintf(ring->name, "page%d", i); 1980 r = amdgpu_ring_init(adev, ring, 1024, 1981 &adev->sdma.trap_irq, 1982 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1983 AMDGPU_RING_PRIO_DEFAULT, NULL); 1984 if (r) 1985 return r; 1986 } 1987 } 1988 1989 return r; 1990 } 1991 1992 static int sdma_v4_0_sw_fini(void *handle) 1993 { 1994 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1995 int i; 1996 1997 for (i = 0; i < adev->sdma.num_instances; i++) { 1998 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1999 if (adev->sdma.has_page_queue) 2000 amdgpu_ring_fini(&adev->sdma.instance[i].page); 2001 } 2002 2003 sdma_v4_0_destroy_inst_ctx(adev); 2004 2005 return 0; 2006 } 2007 2008 static int sdma_v4_0_hw_init(void *handle) 2009 { 2010 int r; 2011 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2012 2013 if (adev->flags & AMD_IS_APU) 2014 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false); 2015 2016 if (!amdgpu_sriov_vf(adev)) 2017 sdma_v4_0_init_golden_registers(adev); 2018 2019 r = sdma_v4_0_start(adev); 2020 2021 return r; 2022 } 2023 2024 static int sdma_v4_0_hw_fini(void *handle) 2025 { 2026 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2027 int i; 2028 2029 if (amdgpu_sriov_vf(adev)) 2030 return 0; 2031 2032 for (i = 0; i < adev->sdma.num_instances; i++) { 2033 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, 2034 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 2035 } 2036 2037 sdma_v4_0_ctx_switch_enable(adev, false); 2038 sdma_v4_0_enable(adev, false); 2039 2040 if (adev->flags & AMD_IS_APU) 2041 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true); 2042 2043 return 0; 2044 } 2045 2046 static int sdma_v4_0_suspend(void *handle) 2047 { 2048 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2049 2050 /* SMU saves SDMA state for us */ 2051 if (adev->in_s0ix) 2052 return 0; 2053 2054 return sdma_v4_0_hw_fini(adev); 2055 } 2056 2057 static int sdma_v4_0_resume(void *handle) 2058 { 2059 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2060 2061 /* SMU restores SDMA state for us */ 2062 if (adev->in_s0ix) 2063 return 0; 2064 2065 return sdma_v4_0_hw_init(adev); 2066 } 2067 2068 static bool sdma_v4_0_is_idle(void *handle) 2069 { 2070 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2071 u32 i; 2072 2073 for (i = 0; i < adev->sdma.num_instances; i++) { 2074 u32 tmp = RREG32_SDMA(i, mmSDMA0_STATUS_REG); 2075 2076 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 2077 return false; 2078 } 2079 2080 return true; 2081 } 2082 2083 static int sdma_v4_0_wait_for_idle(void *handle) 2084 { 2085 unsigned i, j; 2086 u32 sdma[AMDGPU_MAX_SDMA_INSTANCES]; 2087 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2088 2089 for (i = 0; i < adev->usec_timeout; i++) { 2090 for (j = 0; j < adev->sdma.num_instances; j++) { 2091 sdma[j] = RREG32_SDMA(j, mmSDMA0_STATUS_REG); 2092 if (!(sdma[j] & SDMA0_STATUS_REG__IDLE_MASK)) 2093 break; 2094 } 2095 if (j == adev->sdma.num_instances) 2096 return 0; 2097 udelay(1); 2098 } 2099 return -ETIMEDOUT; 2100 } 2101 2102 static int sdma_v4_0_soft_reset(void *handle) 2103 { 2104 /* todo */ 2105 2106 return 0; 2107 } 2108 2109 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev, 2110 struct amdgpu_irq_src *source, 2111 unsigned type, 2112 enum amdgpu_interrupt_state state) 2113 { 2114 u32 sdma_cntl; 2115 2116 sdma_cntl = RREG32_SDMA(type, mmSDMA0_CNTL); 2117 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 2118 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2119 WREG32_SDMA(type, mmSDMA0_CNTL, sdma_cntl); 2120 2121 return 0; 2122 } 2123 2124 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev, 2125 struct amdgpu_irq_src *source, 2126 struct amdgpu_iv_entry *entry) 2127 { 2128 uint32_t instance; 2129 2130 DRM_DEBUG("IH: SDMA trap\n"); 2131 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 2132 switch (entry->ring_id) { 2133 case 0: 2134 amdgpu_fence_process(&adev->sdma.instance[instance].ring); 2135 break; 2136 case 1: 2137 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 0)) 2138 amdgpu_fence_process(&adev->sdma.instance[instance].page); 2139 break; 2140 case 2: 2141 /* XXX compute */ 2142 break; 2143 case 3: 2144 if (adev->ip_versions[SDMA0_HWIP][0] != IP_VERSION(4, 2, 0)) 2145 amdgpu_fence_process(&adev->sdma.instance[instance].page); 2146 break; 2147 } 2148 return 0; 2149 } 2150 2151 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev, 2152 void *err_data, 2153 struct amdgpu_iv_entry *entry) 2154 { 2155 int instance; 2156 2157 /* When “Full RAS” is enabled, the per-IP interrupt sources should 2158 * be disabled and the driver should only look for the aggregated 2159 * interrupt via sync flood 2160 */ 2161 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 2162 goto out; 2163 2164 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 2165 if (instance < 0) 2166 goto out; 2167 2168 amdgpu_sdma_process_ras_data_cb(adev, err_data, entry); 2169 2170 out: 2171 return AMDGPU_RAS_SUCCESS; 2172 } 2173 2174 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev, 2175 struct amdgpu_irq_src *source, 2176 struct amdgpu_iv_entry *entry) 2177 { 2178 int instance; 2179 2180 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 2181 2182 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 2183 if (instance < 0) 2184 return 0; 2185 2186 switch (entry->ring_id) { 2187 case 0: 2188 drm_sched_fault(&adev->sdma.instance[instance].ring.sched); 2189 break; 2190 } 2191 return 0; 2192 } 2193 2194 static int sdma_v4_0_set_ecc_irq_state(struct amdgpu_device *adev, 2195 struct amdgpu_irq_src *source, 2196 unsigned type, 2197 enum amdgpu_interrupt_state state) 2198 { 2199 u32 sdma_edc_config; 2200 2201 sdma_edc_config = RREG32_SDMA(type, mmSDMA0_EDC_CONFIG); 2202 sdma_edc_config = REG_SET_FIELD(sdma_edc_config, SDMA0_EDC_CONFIG, ECC_INT_ENABLE, 2203 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2204 WREG32_SDMA(type, mmSDMA0_EDC_CONFIG, sdma_edc_config); 2205 2206 return 0; 2207 } 2208 2209 static int sdma_v4_0_print_iv_entry(struct amdgpu_device *adev, 2210 struct amdgpu_iv_entry *entry) 2211 { 2212 int instance; 2213 struct amdgpu_task_info task_info; 2214 u64 addr; 2215 2216 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 2217 if (instance < 0 || instance >= adev->sdma.num_instances) { 2218 dev_err(adev->dev, "sdma instance invalid %d\n", instance); 2219 return -EINVAL; 2220 } 2221 2222 addr = (u64)entry->src_data[0] << 12; 2223 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 2224 2225 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 2226 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 2227 2228 dev_dbg_ratelimited(adev->dev, 2229 "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u " 2230 "pasid:%u, for process %s pid %d thread %s pid %d\n", 2231 instance, addr, entry->src_id, entry->ring_id, entry->vmid, 2232 entry->pasid, task_info.process_name, task_info.tgid, 2233 task_info.task_name, task_info.pid); 2234 return 0; 2235 } 2236 2237 static int sdma_v4_0_process_vm_hole_irq(struct amdgpu_device *adev, 2238 struct amdgpu_irq_src *source, 2239 struct amdgpu_iv_entry *entry) 2240 { 2241 dev_dbg_ratelimited(adev->dev, "MC or SEM address in VM hole\n"); 2242 sdma_v4_0_print_iv_entry(adev, entry); 2243 return 0; 2244 } 2245 2246 static int sdma_v4_0_process_doorbell_invalid_irq(struct amdgpu_device *adev, 2247 struct amdgpu_irq_src *source, 2248 struct amdgpu_iv_entry *entry) 2249 { 2250 dev_dbg_ratelimited(adev->dev, "SDMA received a doorbell from BIF with byte_enable !=0xff\n"); 2251 sdma_v4_0_print_iv_entry(adev, entry); 2252 return 0; 2253 } 2254 2255 static int sdma_v4_0_process_pool_timeout_irq(struct amdgpu_device *adev, 2256 struct amdgpu_irq_src *source, 2257 struct amdgpu_iv_entry *entry) 2258 { 2259 dev_dbg_ratelimited(adev->dev, 2260 "Polling register/memory timeout executing POLL_REG/MEM with finite timer\n"); 2261 sdma_v4_0_print_iv_entry(adev, entry); 2262 return 0; 2263 } 2264 2265 static int sdma_v4_0_process_srbm_write_irq(struct amdgpu_device *adev, 2266 struct amdgpu_irq_src *source, 2267 struct amdgpu_iv_entry *entry) 2268 { 2269 dev_dbg_ratelimited(adev->dev, 2270 "SDMA gets an Register Write SRBM_WRITE command in non-privilege command buffer\n"); 2271 sdma_v4_0_print_iv_entry(adev, entry); 2272 return 0; 2273 } 2274 2275 static void sdma_v4_0_update_medium_grain_clock_gating( 2276 struct amdgpu_device *adev, 2277 bool enable) 2278 { 2279 uint32_t data, def; 2280 int i; 2281 2282 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 2283 for (i = 0; i < adev->sdma.num_instances; i++) { 2284 def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL); 2285 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 2286 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 2287 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 2288 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 2289 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 2290 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 2291 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 2292 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 2293 if (def != data) 2294 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data); 2295 } 2296 } else { 2297 for (i = 0; i < adev->sdma.num_instances; i++) { 2298 def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL); 2299 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 2300 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 2301 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 2302 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 2303 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 2304 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 2305 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 2306 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 2307 if (def != data) 2308 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data); 2309 } 2310 } 2311 } 2312 2313 2314 static void sdma_v4_0_update_medium_grain_light_sleep( 2315 struct amdgpu_device *adev, 2316 bool enable) 2317 { 2318 uint32_t data, def; 2319 int i; 2320 2321 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 2322 for (i = 0; i < adev->sdma.num_instances; i++) { 2323 /* 1-not override: enable sdma mem light sleep */ 2324 def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL); 2325 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 2326 if (def != data) 2327 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data); 2328 } 2329 } else { 2330 for (i = 0; i < adev->sdma.num_instances; i++) { 2331 /* 0-override:disable sdma mem light sleep */ 2332 def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL); 2333 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 2334 if (def != data) 2335 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data); 2336 } 2337 } 2338 } 2339 2340 static int sdma_v4_0_set_clockgating_state(void *handle, 2341 enum amd_clockgating_state state) 2342 { 2343 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2344 2345 if (amdgpu_sriov_vf(adev)) 2346 return 0; 2347 2348 sdma_v4_0_update_medium_grain_clock_gating(adev, 2349 state == AMD_CG_STATE_GATE); 2350 sdma_v4_0_update_medium_grain_light_sleep(adev, 2351 state == AMD_CG_STATE_GATE); 2352 return 0; 2353 } 2354 2355 static int sdma_v4_0_set_powergating_state(void *handle, 2356 enum amd_powergating_state state) 2357 { 2358 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2359 2360 switch (adev->ip_versions[SDMA0_HWIP][0]) { 2361 case IP_VERSION(4, 1, 0): 2362 case IP_VERSION(4, 1, 1): 2363 case IP_VERSION(4, 1, 2): 2364 sdma_v4_1_update_power_gating(adev, 2365 state == AMD_PG_STATE_GATE); 2366 break; 2367 default: 2368 break; 2369 } 2370 2371 return 0; 2372 } 2373 2374 static void sdma_v4_0_get_clockgating_state(void *handle, u64 *flags) 2375 { 2376 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2377 int data; 2378 2379 if (amdgpu_sriov_vf(adev)) 2380 *flags = 0; 2381 2382 /* AMD_CG_SUPPORT_SDMA_MGCG */ 2383 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 2384 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK)) 2385 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 2386 2387 /* AMD_CG_SUPPORT_SDMA_LS */ 2388 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 2389 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 2390 *flags |= AMD_CG_SUPPORT_SDMA_LS; 2391 } 2392 2393 const struct amd_ip_funcs sdma_v4_0_ip_funcs = { 2394 .name = "sdma_v4_0", 2395 .early_init = sdma_v4_0_early_init, 2396 .late_init = sdma_v4_0_late_init, 2397 .sw_init = sdma_v4_0_sw_init, 2398 .sw_fini = sdma_v4_0_sw_fini, 2399 .hw_init = sdma_v4_0_hw_init, 2400 .hw_fini = sdma_v4_0_hw_fini, 2401 .suspend = sdma_v4_0_suspend, 2402 .resume = sdma_v4_0_resume, 2403 .is_idle = sdma_v4_0_is_idle, 2404 .wait_for_idle = sdma_v4_0_wait_for_idle, 2405 .soft_reset = sdma_v4_0_soft_reset, 2406 .set_clockgating_state = sdma_v4_0_set_clockgating_state, 2407 .set_powergating_state = sdma_v4_0_set_powergating_state, 2408 .get_clockgating_state = sdma_v4_0_get_clockgating_state, 2409 }; 2410 2411 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = { 2412 .type = AMDGPU_RING_TYPE_SDMA, 2413 .align_mask = 0xf, 2414 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2415 .support_64bit_ptrs = true, 2416 .secure_submission_supported = true, 2417 .vmhub = AMDGPU_MMHUB_0, 2418 .get_rptr = sdma_v4_0_ring_get_rptr, 2419 .get_wptr = sdma_v4_0_ring_get_wptr, 2420 .set_wptr = sdma_v4_0_ring_set_wptr, 2421 .emit_frame_size = 2422 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2423 3 + /* hdp invalidate */ 2424 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2425 /* sdma_v4_0_ring_emit_vm_flush */ 2426 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2427 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2428 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2429 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2430 .emit_ib = sdma_v4_0_ring_emit_ib, 2431 .emit_fence = sdma_v4_0_ring_emit_fence, 2432 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2433 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2434 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2435 .test_ring = sdma_v4_0_ring_test_ring, 2436 .test_ib = sdma_v4_0_ring_test_ib, 2437 .insert_nop = sdma_v4_0_ring_insert_nop, 2438 .pad_ib = sdma_v4_0_ring_pad_ib, 2439 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2440 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2441 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2442 }; 2443 2444 /* 2445 * On Arcturus, SDMA instance 5~7 has a different vmhub type(AMDGPU_MMHUB_1). 2446 * So create a individual constant ring_funcs for those instances. 2447 */ 2448 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs_2nd_mmhub = { 2449 .type = AMDGPU_RING_TYPE_SDMA, 2450 .align_mask = 0xf, 2451 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2452 .support_64bit_ptrs = true, 2453 .secure_submission_supported = true, 2454 .vmhub = AMDGPU_MMHUB_1, 2455 .get_rptr = sdma_v4_0_ring_get_rptr, 2456 .get_wptr = sdma_v4_0_ring_get_wptr, 2457 .set_wptr = sdma_v4_0_ring_set_wptr, 2458 .emit_frame_size = 2459 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2460 3 + /* hdp invalidate */ 2461 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2462 /* sdma_v4_0_ring_emit_vm_flush */ 2463 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2464 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2465 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2466 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2467 .emit_ib = sdma_v4_0_ring_emit_ib, 2468 .emit_fence = sdma_v4_0_ring_emit_fence, 2469 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2470 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2471 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2472 .test_ring = sdma_v4_0_ring_test_ring, 2473 .test_ib = sdma_v4_0_ring_test_ib, 2474 .insert_nop = sdma_v4_0_ring_insert_nop, 2475 .pad_ib = sdma_v4_0_ring_pad_ib, 2476 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2477 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2478 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2479 }; 2480 2481 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = { 2482 .type = AMDGPU_RING_TYPE_SDMA, 2483 .align_mask = 0xf, 2484 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2485 .support_64bit_ptrs = true, 2486 .secure_submission_supported = true, 2487 .vmhub = AMDGPU_MMHUB_0, 2488 .get_rptr = sdma_v4_0_ring_get_rptr, 2489 .get_wptr = sdma_v4_0_page_ring_get_wptr, 2490 .set_wptr = sdma_v4_0_page_ring_set_wptr, 2491 .emit_frame_size = 2492 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2493 3 + /* hdp invalidate */ 2494 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2495 /* sdma_v4_0_ring_emit_vm_flush */ 2496 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2497 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2498 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2499 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2500 .emit_ib = sdma_v4_0_ring_emit_ib, 2501 .emit_fence = sdma_v4_0_ring_emit_fence, 2502 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2503 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2504 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2505 .test_ring = sdma_v4_0_ring_test_ring, 2506 .test_ib = sdma_v4_0_ring_test_ib, 2507 .insert_nop = sdma_v4_0_ring_insert_nop, 2508 .pad_ib = sdma_v4_0_ring_pad_ib, 2509 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2510 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2511 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2512 }; 2513 2514 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs_2nd_mmhub = { 2515 .type = AMDGPU_RING_TYPE_SDMA, 2516 .align_mask = 0xf, 2517 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2518 .support_64bit_ptrs = true, 2519 .secure_submission_supported = true, 2520 .vmhub = AMDGPU_MMHUB_1, 2521 .get_rptr = sdma_v4_0_ring_get_rptr, 2522 .get_wptr = sdma_v4_0_page_ring_get_wptr, 2523 .set_wptr = sdma_v4_0_page_ring_set_wptr, 2524 .emit_frame_size = 2525 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2526 3 + /* hdp invalidate */ 2527 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2528 /* sdma_v4_0_ring_emit_vm_flush */ 2529 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2530 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2531 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2532 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2533 .emit_ib = sdma_v4_0_ring_emit_ib, 2534 .emit_fence = sdma_v4_0_ring_emit_fence, 2535 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2536 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2537 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2538 .test_ring = sdma_v4_0_ring_test_ring, 2539 .test_ib = sdma_v4_0_ring_test_ib, 2540 .insert_nop = sdma_v4_0_ring_insert_nop, 2541 .pad_ib = sdma_v4_0_ring_pad_ib, 2542 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2543 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2544 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2545 }; 2546 2547 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev) 2548 { 2549 int i; 2550 2551 for (i = 0; i < adev->sdma.num_instances; i++) { 2552 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) && i >= 5) 2553 adev->sdma.instance[i].ring.funcs = 2554 &sdma_v4_0_ring_funcs_2nd_mmhub; 2555 else 2556 adev->sdma.instance[i].ring.funcs = 2557 &sdma_v4_0_ring_funcs; 2558 adev->sdma.instance[i].ring.me = i; 2559 if (adev->sdma.has_page_queue) { 2560 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) && i >= 5) 2561 adev->sdma.instance[i].page.funcs = 2562 &sdma_v4_0_page_ring_funcs_2nd_mmhub; 2563 else 2564 adev->sdma.instance[i].page.funcs = 2565 &sdma_v4_0_page_ring_funcs; 2566 adev->sdma.instance[i].page.me = i; 2567 } 2568 } 2569 } 2570 2571 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = { 2572 .set = sdma_v4_0_set_trap_irq_state, 2573 .process = sdma_v4_0_process_trap_irq, 2574 }; 2575 2576 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = { 2577 .process = sdma_v4_0_process_illegal_inst_irq, 2578 }; 2579 2580 static const struct amdgpu_irq_src_funcs sdma_v4_0_ecc_irq_funcs = { 2581 .set = sdma_v4_0_set_ecc_irq_state, 2582 .process = amdgpu_sdma_process_ecc_irq, 2583 }; 2584 2585 static const struct amdgpu_irq_src_funcs sdma_v4_0_vm_hole_irq_funcs = { 2586 .process = sdma_v4_0_process_vm_hole_irq, 2587 }; 2588 2589 static const struct amdgpu_irq_src_funcs sdma_v4_0_doorbell_invalid_irq_funcs = { 2590 .process = sdma_v4_0_process_doorbell_invalid_irq, 2591 }; 2592 2593 static const struct amdgpu_irq_src_funcs sdma_v4_0_pool_timeout_irq_funcs = { 2594 .process = sdma_v4_0_process_pool_timeout_irq, 2595 }; 2596 2597 static const struct amdgpu_irq_src_funcs sdma_v4_0_srbm_write_irq_funcs = { 2598 .process = sdma_v4_0_process_srbm_write_irq, 2599 }; 2600 2601 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev) 2602 { 2603 adev->sdma.trap_irq.num_types = adev->sdma.num_instances; 2604 adev->sdma.ecc_irq.num_types = adev->sdma.num_instances; 2605 /*For Arcturus and Aldebaran, add another 4 irq handler*/ 2606 switch (adev->sdma.num_instances) { 2607 case 5: 2608 case 8: 2609 adev->sdma.vm_hole_irq.num_types = adev->sdma.num_instances; 2610 adev->sdma.doorbell_invalid_irq.num_types = adev->sdma.num_instances; 2611 adev->sdma.pool_timeout_irq.num_types = adev->sdma.num_instances; 2612 adev->sdma.srbm_write_irq.num_types = adev->sdma.num_instances; 2613 break; 2614 default: 2615 break; 2616 } 2617 adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs; 2618 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs; 2619 adev->sdma.ecc_irq.funcs = &sdma_v4_0_ecc_irq_funcs; 2620 adev->sdma.vm_hole_irq.funcs = &sdma_v4_0_vm_hole_irq_funcs; 2621 adev->sdma.doorbell_invalid_irq.funcs = &sdma_v4_0_doorbell_invalid_irq_funcs; 2622 adev->sdma.pool_timeout_irq.funcs = &sdma_v4_0_pool_timeout_irq_funcs; 2623 adev->sdma.srbm_write_irq.funcs = &sdma_v4_0_srbm_write_irq_funcs; 2624 } 2625 2626 /** 2627 * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine 2628 * 2629 * @ib: indirect buffer to copy to 2630 * @src_offset: src GPU address 2631 * @dst_offset: dst GPU address 2632 * @byte_count: number of bytes to xfer 2633 * @tmz: if a secure copy should be used 2634 * 2635 * Copy GPU buffers using the DMA engine (VEGA10/12). 2636 * Used by the amdgpu ttm implementation to move pages if 2637 * registered as the asic copy callback. 2638 */ 2639 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib, 2640 uint64_t src_offset, 2641 uint64_t dst_offset, 2642 uint32_t byte_count, 2643 bool tmz) 2644 { 2645 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 2646 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 2647 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0); 2648 ib->ptr[ib->length_dw++] = byte_count - 1; 2649 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 2650 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 2651 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 2652 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2653 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2654 } 2655 2656 /** 2657 * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine 2658 * 2659 * @ib: indirect buffer to copy to 2660 * @src_data: value to write to buffer 2661 * @dst_offset: dst GPU address 2662 * @byte_count: number of bytes to xfer 2663 * 2664 * Fill GPU buffers using the DMA engine (VEGA10/12). 2665 */ 2666 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib, 2667 uint32_t src_data, 2668 uint64_t dst_offset, 2669 uint32_t byte_count) 2670 { 2671 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 2672 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2673 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2674 ib->ptr[ib->length_dw++] = src_data; 2675 ib->ptr[ib->length_dw++] = byte_count - 1; 2676 } 2677 2678 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = { 2679 .copy_max_bytes = 0x400000, 2680 .copy_num_dw = 7, 2681 .emit_copy_buffer = sdma_v4_0_emit_copy_buffer, 2682 2683 .fill_max_bytes = 0x400000, 2684 .fill_num_dw = 5, 2685 .emit_fill_buffer = sdma_v4_0_emit_fill_buffer, 2686 }; 2687 2688 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev) 2689 { 2690 adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs; 2691 if (adev->sdma.has_page_queue) 2692 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page; 2693 else 2694 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 2695 } 2696 2697 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = { 2698 .copy_pte_num_dw = 7, 2699 .copy_pte = sdma_v4_0_vm_copy_pte, 2700 2701 .write_pte = sdma_v4_0_vm_write_pte, 2702 .set_pte_pde = sdma_v4_0_vm_set_pte_pde, 2703 }; 2704 2705 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev) 2706 { 2707 struct drm_gpu_scheduler *sched; 2708 unsigned i; 2709 2710 adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs; 2711 for (i = 0; i < adev->sdma.num_instances; i++) { 2712 if (adev->sdma.has_page_queue) 2713 sched = &adev->sdma.instance[i].page.sched; 2714 else 2715 sched = &adev->sdma.instance[i].ring.sched; 2716 adev->vm_manager.vm_pte_scheds[i] = sched; 2717 } 2718 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 2719 } 2720 2721 static void sdma_v4_0_get_ras_error_count(uint32_t value, 2722 uint32_t instance, 2723 uint32_t *sec_count) 2724 { 2725 uint32_t i; 2726 uint32_t sec_cnt; 2727 2728 /* double bits error (multiple bits) error detection is not supported */ 2729 for (i = 0; i < ARRAY_SIZE(sdma_v4_0_ras_fields); i++) { 2730 /* the SDMA_EDC_COUNTER register in each sdma instance 2731 * shares the same sed shift_mask 2732 * */ 2733 sec_cnt = (value & 2734 sdma_v4_0_ras_fields[i].sec_count_mask) >> 2735 sdma_v4_0_ras_fields[i].sec_count_shift; 2736 if (sec_cnt) { 2737 DRM_INFO("Detected %s in SDMA%d, SED %d\n", 2738 sdma_v4_0_ras_fields[i].name, 2739 instance, sec_cnt); 2740 *sec_count += sec_cnt; 2741 } 2742 } 2743 } 2744 2745 static int sdma_v4_0_query_ras_error_count_by_instance(struct amdgpu_device *adev, 2746 uint32_t instance, void *ras_error_status) 2747 { 2748 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 2749 uint32_t sec_count = 0; 2750 uint32_t reg_value = 0; 2751 2752 reg_value = RREG32_SDMA(instance, mmSDMA0_EDC_COUNTER); 2753 /* double bit error is not supported */ 2754 if (reg_value) 2755 sdma_v4_0_get_ras_error_count(reg_value, 2756 instance, &sec_count); 2757 /* err_data->ce_count should be initialized to 0 2758 * before calling into this function */ 2759 err_data->ce_count += sec_count; 2760 /* double bit error is not supported 2761 * set ue count to 0 */ 2762 err_data->ue_count = 0; 2763 2764 return 0; 2765 }; 2766 2767 static void sdma_v4_0_query_ras_error_count(struct amdgpu_device *adev, void *ras_error_status) 2768 { 2769 int i = 0; 2770 2771 for (i = 0; i < adev->sdma.num_instances; i++) { 2772 if (sdma_v4_0_query_ras_error_count_by_instance(adev, i, ras_error_status)) { 2773 dev_err(adev->dev, "Query ras error count failed in SDMA%d\n", i); 2774 return; 2775 } 2776 } 2777 } 2778 2779 static void sdma_v4_0_reset_ras_error_count(struct amdgpu_device *adev) 2780 { 2781 int i; 2782 2783 /* read back edc counter registers to clear the counters */ 2784 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 2785 for (i = 0; i < adev->sdma.num_instances; i++) 2786 RREG32_SDMA(i, mmSDMA0_EDC_COUNTER); 2787 } 2788 } 2789 2790 const struct amdgpu_ras_block_hw_ops sdma_v4_0_ras_hw_ops = { 2791 .query_ras_error_count = sdma_v4_0_query_ras_error_count, 2792 .reset_ras_error_count = sdma_v4_0_reset_ras_error_count, 2793 }; 2794 2795 static struct amdgpu_sdma_ras sdma_v4_0_ras = { 2796 .ras_block = { 2797 .hw_ops = &sdma_v4_0_ras_hw_ops, 2798 .ras_cb = sdma_v4_0_process_ras_data_cb, 2799 }, 2800 }; 2801 2802 static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev) 2803 { 2804 switch (adev->ip_versions[SDMA0_HWIP][0]) { 2805 case IP_VERSION(4, 2, 0): 2806 case IP_VERSION(4, 2, 2): 2807 adev->sdma.ras = &sdma_v4_0_ras; 2808 break; 2809 case IP_VERSION(4, 4, 0): 2810 adev->sdma.ras = &sdma_v4_4_ras; 2811 break; 2812 default: 2813 break; 2814 } 2815 2816 if (adev->sdma.ras) { 2817 amdgpu_ras_register_ras_block(adev, &adev->sdma.ras->ras_block); 2818 2819 strcpy(adev->sdma.ras->ras_block.ras_comm.name, "sdma"); 2820 adev->sdma.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__SDMA; 2821 adev->sdma.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; 2822 adev->sdma.ras_if = &adev->sdma.ras->ras_block.ras_comm; 2823 2824 /* If don't define special ras_late_init function, use default ras_late_init */ 2825 if (!adev->sdma.ras->ras_block.ras_late_init) 2826 adev->sdma.ras->ras_block.ras_late_init = amdgpu_sdma_ras_late_init; 2827 2828 /* If not defined special ras_cb function, use default ras_cb */ 2829 if (!adev->sdma.ras->ras_block.ras_cb) 2830 adev->sdma.ras->ras_block.ras_cb = amdgpu_sdma_process_ras_data_cb; 2831 } 2832 } 2833 2834 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = { 2835 .type = AMD_IP_BLOCK_TYPE_SDMA, 2836 .major = 4, 2837 .minor = 0, 2838 .rev = 0, 2839 .funcs = &sdma_v4_0_ip_funcs, 2840 }; 2841