1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_ucode.h" 28 #include "amdgpu_trace.h" 29 30 #include "vega10/soc15ip.h" 31 #include "vega10/SDMA0/sdma0_4_0_offset.h" 32 #include "vega10/SDMA0/sdma0_4_0_sh_mask.h" 33 #include "vega10/SDMA1/sdma1_4_0_offset.h" 34 #include "vega10/SDMA1/sdma1_4_0_sh_mask.h" 35 #include "vega10/MMHUB/mmhub_1_0_offset.h" 36 #include "vega10/MMHUB/mmhub_1_0_sh_mask.h" 37 #include "vega10/HDP/hdp_4_0_offset.h" 38 #include "raven1/SDMA0/sdma0_4_1_default.h" 39 40 #include "soc15_common.h" 41 #include "soc15.h" 42 #include "vega10_sdma_pkt_open.h" 43 44 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin"); 45 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin"); 46 MODULE_FIRMWARE("amdgpu/raven_sdma.bin"); 47 48 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L 49 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L 50 51 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev); 52 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev); 53 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev); 54 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev); 55 56 static const u32 golden_settings_sdma_4[] = { 57 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CHICKEN_BITS), 0xfe931f07, 0x02831f07, 58 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), 0xff000ff0, 0x3f000100, 59 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_IB_CNTL), 0x800f0100, 0x00000100, 60 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000, 61 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL), 0x800f0100, 0x00000100, 62 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000, 63 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), 0x003ff006, 0x0003c000, 64 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL), 0x800f0100, 0x00000100, 65 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000, 66 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL), 0x800f0100, 0x00000100, 67 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000, 68 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UTCL1_PAGE), 0x000003ff, 0x000003c0, 69 SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CHICKEN_BITS), 0xfe931f07, 0x02831f07, 70 SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), 0xffffffff, 0x3f000100, 71 SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GFX_IB_CNTL), 0x800f0100, 0x00000100, 72 SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000, 73 SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL), 0x800f0100, 0x00000100, 74 SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000, 75 SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), 0x003ff000, 0x0003c000, 76 SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL), 0x800f0100, 0x00000100, 77 SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000, 78 SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL), 0x800f0100, 0x00000100, 79 SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000, 80 SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_UTCL1_PAGE), 0x000003ff, 0x000003c0 81 }; 82 83 static const u32 golden_settings_sdma_vg10[] = { 84 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG), 0x0018773f, 0x00104002, 85 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ), 0x0018773f, 0x00104002, 86 SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG), 0x0018773f, 0x00104002, 87 SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ), 0x0018773f, 0x00104002 88 }; 89 90 static const u32 golden_settings_sdma_4_1[] = 91 { 92 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CHICKEN_BITS), 0xfe931f07, 0x02831f07, 93 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), 0xffffffff, 0x3f000100, 94 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_IB_CNTL), 0x800f0111, 0x00000100, 95 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000, 96 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), 0xfc3fffff, 0x40000051, 97 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL), 0x800f0111, 0x00000100, 98 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000, 99 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL), 0x800f0111, 0x00000100, 100 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000, 101 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UTCL1_PAGE), 0x000003ff, 0x000003c0 102 }; 103 104 static const u32 golden_settings_sdma_rv1[] = 105 { 106 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG), 0x0018773f, 0x00003002, 107 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ), 0x0018773f, 0x00003002 108 }; 109 110 static u32 sdma_v4_0_get_reg_offset(u32 instance, u32 internal_offset) 111 { 112 u32 base = 0; 113 114 switch (instance) { 115 case 0: 116 base = SDMA0_BASE.instance[0].segment[0]; 117 break; 118 case 1: 119 base = SDMA1_BASE.instance[0].segment[0]; 120 break; 121 default: 122 BUG(); 123 break; 124 } 125 126 return base + internal_offset; 127 } 128 129 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) 130 { 131 switch (adev->asic_type) { 132 case CHIP_VEGA10: 133 amdgpu_program_register_sequence(adev, 134 golden_settings_sdma_4, 135 (const u32)ARRAY_SIZE(golden_settings_sdma_4)); 136 amdgpu_program_register_sequence(adev, 137 golden_settings_sdma_vg10, 138 (const u32)ARRAY_SIZE(golden_settings_sdma_vg10)); 139 break; 140 case CHIP_RAVEN: 141 amdgpu_program_register_sequence(adev, 142 golden_settings_sdma_4_1, 143 (const u32)ARRAY_SIZE(golden_settings_sdma_4_1)); 144 amdgpu_program_register_sequence(adev, 145 golden_settings_sdma_rv1, 146 (const u32)ARRAY_SIZE(golden_settings_sdma_rv1)); 147 break; 148 default: 149 break; 150 } 151 } 152 153 static void sdma_v4_0_print_ucode_regs(void *handle) 154 { 155 int i; 156 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 157 158 dev_info(adev->dev, "VEGA10 SDMA ucode registers\n"); 159 for (i = 0; i < adev->sdma.num_instances; i++) { 160 dev_info(adev->dev, " SDMA%d_UCODE_ADDR=0x%08X\n", 161 i, RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_ADDR))); 162 dev_info(adev->dev, " SDMA%d_UCODE_CHECKSUM=0x%08X\n", 163 i, RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_CHECKSUM))); 164 } 165 } 166 167 /** 168 * sdma_v4_0_init_microcode - load ucode images from disk 169 * 170 * @adev: amdgpu_device pointer 171 * 172 * Use the firmware interface to load the ucode images into 173 * the driver (not loaded into hw). 174 * Returns 0 on success, error on failure. 175 */ 176 177 // emulation only, won't work on real chip 178 // vega10 real chip need to use PSP to load firmware 179 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev) 180 { 181 const char *chip_name; 182 char fw_name[30]; 183 int err = 0, i; 184 struct amdgpu_firmware_info *info = NULL; 185 const struct common_firmware_header *header = NULL; 186 const struct sdma_firmware_header_v1_0 *hdr; 187 188 DRM_DEBUG("\n"); 189 190 switch (adev->asic_type) { 191 case CHIP_VEGA10: 192 chip_name = "vega10"; 193 break; 194 case CHIP_RAVEN: 195 chip_name = "raven"; 196 break; 197 default: 198 BUG(); 199 } 200 201 for (i = 0; i < adev->sdma.num_instances; i++) { 202 if (i == 0) 203 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 204 else 205 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); 206 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 207 if (err) 208 goto out; 209 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); 210 if (err) 211 goto out; 212 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 213 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 214 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 215 if (adev->sdma.instance[i].feature_version >= 20) 216 adev->sdma.instance[i].burst_nop = true; 217 DRM_DEBUG("psp_load == '%s'\n", 218 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); 219 220 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 221 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 222 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 223 info->fw = adev->sdma.instance[i].fw; 224 header = (const struct common_firmware_header *)info->fw->data; 225 adev->firmware.fw_size += 226 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 227 } 228 } 229 out: 230 if (err) { 231 DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name); 232 for (i = 0; i < adev->sdma.num_instances; i++) { 233 release_firmware(adev->sdma.instance[i].fw); 234 adev->sdma.instance[i].fw = NULL; 235 } 236 } 237 return err; 238 } 239 240 /** 241 * sdma_v4_0_ring_get_rptr - get the current read pointer 242 * 243 * @ring: amdgpu ring pointer 244 * 245 * Get the current rptr from the hardware (VEGA10+). 246 */ 247 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring) 248 { 249 u64 *rptr; 250 251 /* XXX check if swapping is necessary on BE */ 252 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]); 253 254 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 255 return ((*rptr) >> 2); 256 } 257 258 /** 259 * sdma_v4_0_ring_get_wptr - get the current write pointer 260 * 261 * @ring: amdgpu ring pointer 262 * 263 * Get the current wptr from the hardware (VEGA10+). 264 */ 265 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring) 266 { 267 struct amdgpu_device *adev = ring->adev; 268 u64 *wptr = NULL; 269 uint64_t local_wptr = 0; 270 271 if (ring->use_doorbell) { 272 /* XXX check if swapping is necessary on BE */ 273 wptr = ((u64 *)&adev->wb.wb[ring->wptr_offs]); 274 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", *wptr); 275 *wptr = (*wptr) >> 2; 276 DRM_DEBUG("wptr/doorbell after shift == 0x%016llx\n", *wptr); 277 } else { 278 u32 lowbit, highbit; 279 int me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1; 280 281 wptr = &local_wptr; 282 lowbit = RREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR)) >> 2; 283 highbit = RREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2; 284 285 DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n", 286 me, highbit, lowbit); 287 *wptr = highbit; 288 *wptr = (*wptr) << 32; 289 *wptr |= lowbit; 290 } 291 292 return *wptr; 293 } 294 295 /** 296 * sdma_v4_0_ring_set_wptr - commit the write pointer 297 * 298 * @ring: amdgpu ring pointer 299 * 300 * Write the wptr back to the hardware (VEGA10+). 301 */ 302 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring) 303 { 304 struct amdgpu_device *adev = ring->adev; 305 306 DRM_DEBUG("Setting write pointer\n"); 307 if (ring->use_doorbell) { 308 DRM_DEBUG("Using doorbell -- " 309 "wptr_offs == 0x%08x " 310 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 311 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 312 ring->wptr_offs, 313 lower_32_bits(ring->wptr << 2), 314 upper_32_bits(ring->wptr << 2)); 315 /* XXX check if swapping is necessary on BE */ 316 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2); 317 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2); 318 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 319 ring->doorbell_index, ring->wptr << 2); 320 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 321 } else { 322 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1; 323 324 DRM_DEBUG("Not using doorbell -- " 325 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 326 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 327 me, 328 lower_32_bits(ring->wptr << 2), 329 me, 330 upper_32_bits(ring->wptr << 2)); 331 WREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2)); 332 WREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2)); 333 } 334 } 335 336 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 337 { 338 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); 339 int i; 340 341 for (i = 0; i < count; i++) 342 if (sdma && sdma->burst_nop && (i == 0)) 343 amdgpu_ring_write(ring, ring->funcs->nop | 344 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 345 else 346 amdgpu_ring_write(ring, ring->funcs->nop); 347 } 348 349 /** 350 * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine 351 * 352 * @ring: amdgpu ring pointer 353 * @ib: IB object to schedule 354 * 355 * Schedule an IB in the DMA ring (VEGA10). 356 */ 357 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring, 358 struct amdgpu_ib *ib, 359 unsigned vm_id, bool ctx_switch) 360 { 361 u32 vmid = vm_id & 0xf; 362 363 /* IB packet must end on a 8 DW boundary */ 364 sdma_v4_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8); 365 366 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 367 SDMA_PKT_INDIRECT_HEADER_VMID(vmid)); 368 /* base must be 32 byte aligned */ 369 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 370 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 371 amdgpu_ring_write(ring, ib->length_dw); 372 amdgpu_ring_write(ring, 0); 373 amdgpu_ring_write(ring, 0); 374 375 } 376 377 /** 378 * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 379 * 380 * @ring: amdgpu ring pointer 381 * 382 * Emit an hdp flush packet on the requested DMA ring. 383 */ 384 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 385 { 386 u32 ref_and_mask = 0; 387 struct nbio_hdp_flush_reg *nbio_hf_reg; 388 389 if (ring->adev->flags & AMD_IS_APU) 390 nbio_hf_reg = &nbio_v7_0_hdp_flush_reg; 391 else 392 nbio_hf_reg = &nbio_v6_1_hdp_flush_reg; 393 394 if (ring == &ring->adev->sdma.instance[0].ring) 395 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0; 396 else 397 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1; 398 399 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 400 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 401 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 402 amdgpu_ring_write(ring, nbio_hf_reg->hdp_flush_done_offset << 2); 403 amdgpu_ring_write(ring, nbio_hf_reg->hdp_flush_req_offset << 2); 404 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 405 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 406 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 407 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 408 } 409 410 static void sdma_v4_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) 411 { 412 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 413 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 414 amdgpu_ring_write(ring, SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0)); 415 amdgpu_ring_write(ring, 1); 416 } 417 418 /** 419 * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring 420 * 421 * @ring: amdgpu ring pointer 422 * @fence: amdgpu fence object 423 * 424 * Add a DMA fence packet to the ring to write 425 * the fence seq number and DMA trap packet to generate 426 * an interrupt if needed (VEGA10). 427 */ 428 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 429 unsigned flags) 430 { 431 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 432 /* write the fence */ 433 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 434 /* zero in first two bits */ 435 BUG_ON(addr & 0x3); 436 amdgpu_ring_write(ring, lower_32_bits(addr)); 437 amdgpu_ring_write(ring, upper_32_bits(addr)); 438 amdgpu_ring_write(ring, lower_32_bits(seq)); 439 440 /* optionally write high bits as well */ 441 if (write64bit) { 442 addr += 4; 443 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 444 /* zero in first two bits */ 445 BUG_ON(addr & 0x3); 446 amdgpu_ring_write(ring, lower_32_bits(addr)); 447 amdgpu_ring_write(ring, upper_32_bits(addr)); 448 amdgpu_ring_write(ring, upper_32_bits(seq)); 449 } 450 451 /* generate an interrupt */ 452 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 453 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 454 } 455 456 457 /** 458 * sdma_v4_0_gfx_stop - stop the gfx async dma engines 459 * 460 * @adev: amdgpu_device pointer 461 * 462 * Stop the gfx async dma ring buffers (VEGA10). 463 */ 464 static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev) 465 { 466 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 467 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 468 u32 rb_cntl, ib_cntl; 469 int i; 470 471 if ((adev->mman.buffer_funcs_ring == sdma0) || 472 (adev->mman.buffer_funcs_ring == sdma1)) 473 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); 474 475 for (i = 0; i < adev->sdma.num_instances; i++) { 476 rb_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL)); 477 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 478 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 479 ib_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_IB_CNTL)); 480 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 481 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 482 } 483 484 sdma0->ready = false; 485 sdma1->ready = false; 486 } 487 488 /** 489 * sdma_v4_0_rlc_stop - stop the compute async dma engines 490 * 491 * @adev: amdgpu_device pointer 492 * 493 * Stop the compute async dma queues (VEGA10). 494 */ 495 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev) 496 { 497 /* XXX todo */ 498 } 499 500 /** 501 * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch 502 * 503 * @adev: amdgpu_device pointer 504 * @enable: enable/disable the DMA MEs context switch. 505 * 506 * Halt or unhalt the async dma engines context switch (VEGA10). 507 */ 508 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 509 { 510 u32 f32_cntl; 511 int i; 512 513 for (i = 0; i < adev->sdma.num_instances; i++) { 514 f32_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_CNTL)); 515 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 516 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 517 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_CNTL), f32_cntl); 518 } 519 520 } 521 522 /** 523 * sdma_v4_0_enable - stop the async dma engines 524 * 525 * @adev: amdgpu_device pointer 526 * @enable: enable/disable the DMA MEs. 527 * 528 * Halt or unhalt the async dma engines (VEGA10). 529 */ 530 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable) 531 { 532 u32 f32_cntl; 533 int i; 534 535 if (enable == false) { 536 sdma_v4_0_gfx_stop(adev); 537 sdma_v4_0_rlc_stop(adev); 538 } 539 540 for (i = 0; i < adev->sdma.num_instances; i++) { 541 f32_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL)); 542 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 543 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL), f32_cntl); 544 } 545 } 546 547 /** 548 * sdma_v4_0_gfx_resume - setup and start the async dma engines 549 * 550 * @adev: amdgpu_device pointer 551 * 552 * Set up the gfx DMA ring buffers and enable them (VEGA10). 553 * Returns 0 for success, error for failure. 554 */ 555 static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev) 556 { 557 struct amdgpu_ring *ring; 558 u32 rb_cntl, ib_cntl; 559 u32 rb_bufsz; 560 u32 wb_offset; 561 u32 doorbell; 562 u32 doorbell_offset; 563 u32 temp; 564 int i, r; 565 566 for (i = 0; i < adev->sdma.num_instances; i++) { 567 ring = &adev->sdma.instance[i].ring; 568 wb_offset = (ring->rptr_offs * 4); 569 570 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); 571 572 /* Set ring buffer size in dwords */ 573 rb_bufsz = order_base_2(ring->ring_size / 4); 574 rb_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL)); 575 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 576 #ifdef __BIG_ENDIAN 577 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 578 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 579 RPTR_WRITEBACK_SWAP_ENABLE, 1); 580 #endif 581 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 582 583 /* Initialize the ring buffer's read and write pointers */ 584 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_RPTR), 0); 585 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_RPTR_HI), 0); 586 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR), 0); 587 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_HI), 0); 588 589 /* set the wb address whether it's enabled or not */ 590 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), 591 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 592 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), 593 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 594 595 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 596 597 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8); 598 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40); 599 600 ring->wptr = 0; 601 602 /* before programing wptr to a less value, need set minor_ptr_update first */ 603 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); 604 605 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 606 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2); 607 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); 608 } 609 610 doorbell = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL)); 611 doorbell_offset = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL_OFFSET)); 612 613 if (ring->use_doorbell) { 614 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 615 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET, 616 OFFSET, ring->doorbell_index); 617 } else { 618 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 619 } 620 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL), doorbell); 621 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset); 622 if (adev->flags & AMD_IS_APU) 623 nbio_v7_0_sdma_doorbell_range(adev, i, ring->use_doorbell, ring->doorbell_index); 624 else 625 nbio_v6_1_sdma_doorbell_range(adev, i, ring->use_doorbell, ring->doorbell_index); 626 627 if (amdgpu_sriov_vf(adev)) 628 sdma_v4_0_ring_set_wptr(ring); 629 630 /* set minor_ptr_update to 0 after wptr programed */ 631 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); 632 633 /* set utc l1 enable flag always to 1 */ 634 temp = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_CNTL)); 635 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 636 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_CNTL), temp); 637 638 if (!amdgpu_sriov_vf(adev)) { 639 /* unhalt engine */ 640 temp = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL)); 641 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 642 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL), temp); 643 } 644 645 /* enable DMA RB */ 646 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 647 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 648 649 ib_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_IB_CNTL)); 650 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 651 #ifdef __BIG_ENDIAN 652 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 653 #endif 654 /* enable DMA IBs */ 655 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 656 657 ring->ready = true; 658 659 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ 660 sdma_v4_0_ctx_switch_enable(adev, true); 661 sdma_v4_0_enable(adev, true); 662 } 663 664 r = amdgpu_ring_test_ring(ring); 665 if (r) { 666 ring->ready = false; 667 return r; 668 } 669 670 if (adev->mman.buffer_funcs_ring == ring) 671 amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size); 672 } 673 674 return 0; 675 } 676 677 static void 678 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable) 679 { 680 uint32_t def, data; 681 682 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) { 683 /* disable idle interrupt */ 684 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 685 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 686 687 if (data != def) 688 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 689 } else { 690 /* disable idle interrupt */ 691 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 692 data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 693 if (data != def) 694 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 695 } 696 } 697 698 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev) 699 { 700 uint32_t def, data; 701 702 /* Enable HW based PG. */ 703 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 704 data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK; 705 if (data != def) 706 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 707 708 /* enable interrupt */ 709 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 710 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 711 if (data != def) 712 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 713 714 /* Configure hold time to filter in-valid power on/off request. Use default right now */ 715 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 716 data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK; 717 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK); 718 /* Configure switch time for hysteresis purpose. Use default right now */ 719 data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK; 720 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK); 721 if(data != def) 722 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 723 } 724 725 static void sdma_v4_0_init_pg(struct amdgpu_device *adev) 726 { 727 if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA)) 728 return; 729 730 switch (adev->asic_type) { 731 case CHIP_RAVEN: 732 sdma_v4_1_init_power_gating(adev); 733 sdma_v4_1_update_power_gating(adev, true); 734 break; 735 default: 736 break; 737 } 738 } 739 740 /** 741 * sdma_v4_0_rlc_resume - setup and start the async dma engines 742 * 743 * @adev: amdgpu_device pointer 744 * 745 * Set up the compute DMA queues and enable them (VEGA10). 746 * Returns 0 for success, error for failure. 747 */ 748 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev) 749 { 750 sdma_v4_0_init_pg(adev); 751 752 return 0; 753 } 754 755 /** 756 * sdma_v4_0_load_microcode - load the sDMA ME ucode 757 * 758 * @adev: amdgpu_device pointer 759 * 760 * Loads the sDMA0/1 ucode. 761 * Returns 0 for success, -EINVAL if the ucode is not available. 762 */ 763 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev) 764 { 765 const struct sdma_firmware_header_v1_0 *hdr; 766 const __le32 *fw_data; 767 u32 fw_size; 768 u32 digest_size = 0; 769 int i, j; 770 771 /* halt the MEs */ 772 sdma_v4_0_enable(adev, false); 773 774 for (i = 0; i < adev->sdma.num_instances; i++) { 775 uint16_t version_major; 776 uint16_t version_minor; 777 if (!adev->sdma.instance[i].fw) 778 return -EINVAL; 779 780 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 781 amdgpu_ucode_print_sdma_hdr(&hdr->header); 782 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 783 784 version_major = le16_to_cpu(hdr->header.header_version_major); 785 version_minor = le16_to_cpu(hdr->header.header_version_minor); 786 787 if (version_major == 1 && version_minor >= 1) { 788 const struct sdma_firmware_header_v1_1 *sdma_v1_1_hdr = (const struct sdma_firmware_header_v1_1 *) hdr; 789 digest_size = le32_to_cpu(sdma_v1_1_hdr->digest_size); 790 } 791 792 fw_size -= digest_size; 793 794 fw_data = (const __le32 *) 795 (adev->sdma.instance[i].fw->data + 796 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 797 798 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_ADDR), 0); 799 800 801 for (j = 0; j < fw_size; j++) 802 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 803 804 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version); 805 } 806 807 sdma_v4_0_print_ucode_regs(adev); 808 809 return 0; 810 } 811 812 /** 813 * sdma_v4_0_start - setup and start the async dma engines 814 * 815 * @adev: amdgpu_device pointer 816 * 817 * Set up the DMA engines and enable them (VEGA10). 818 * Returns 0 for success, error for failure. 819 */ 820 static int sdma_v4_0_start(struct amdgpu_device *adev) 821 { 822 int r = 0; 823 824 if (amdgpu_sriov_vf(adev)) { 825 sdma_v4_0_ctx_switch_enable(adev, false); 826 sdma_v4_0_enable(adev, false); 827 828 /* set RB registers */ 829 r = sdma_v4_0_gfx_resume(adev); 830 return r; 831 } 832 833 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 834 DRM_INFO("Loading via direct write\n"); 835 r = sdma_v4_0_load_microcode(adev); 836 if (r) 837 return r; 838 } 839 840 /* unhalt the MEs */ 841 sdma_v4_0_enable(adev, true); 842 /* enable sdma ring preemption */ 843 sdma_v4_0_ctx_switch_enable(adev, true); 844 845 /* start the gfx rings and rlc compute queues */ 846 r = sdma_v4_0_gfx_resume(adev); 847 if (r) 848 return r; 849 r = sdma_v4_0_rlc_resume(adev); 850 851 return r; 852 } 853 854 /** 855 * sdma_v4_0_ring_test_ring - simple async dma engine test 856 * 857 * @ring: amdgpu_ring structure holding ring information 858 * 859 * Test the DMA engine by writing using it to write an 860 * value to memory. (VEGA10). 861 * Returns 0 for success, error for failure. 862 */ 863 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring) 864 { 865 struct amdgpu_device *adev = ring->adev; 866 unsigned i; 867 unsigned index; 868 int r; 869 u32 tmp; 870 u64 gpu_addr; 871 872 DRM_INFO("In Ring test func\n"); 873 874 r = amdgpu_wb_get(adev, &index); 875 if (r) { 876 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 877 return r; 878 } 879 880 gpu_addr = adev->wb.gpu_addr + (index * 4); 881 tmp = 0xCAFEDEAD; 882 adev->wb.wb[index] = cpu_to_le32(tmp); 883 884 r = amdgpu_ring_alloc(ring, 5); 885 if (r) { 886 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 887 amdgpu_wb_free(adev, index); 888 return r; 889 } 890 891 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 892 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 893 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 894 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 895 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 896 amdgpu_ring_write(ring, 0xDEADBEEF); 897 amdgpu_ring_commit(ring); 898 899 for (i = 0; i < adev->usec_timeout; i++) { 900 tmp = le32_to_cpu(adev->wb.wb[index]); 901 if (tmp == 0xDEADBEEF) 902 break; 903 DRM_UDELAY(1); 904 } 905 906 if (i < adev->usec_timeout) { 907 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 908 } else { 909 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 910 ring->idx, tmp); 911 r = -EINVAL; 912 } 913 amdgpu_wb_free(adev, index); 914 915 return r; 916 } 917 918 /** 919 * sdma_v4_0_ring_test_ib - test an IB on the DMA engine 920 * 921 * @ring: amdgpu_ring structure holding ring information 922 * 923 * Test a simple IB in the DMA ring (VEGA10). 924 * Returns 0 on success, error on failure. 925 */ 926 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 927 { 928 struct amdgpu_device *adev = ring->adev; 929 struct amdgpu_ib ib; 930 struct dma_fence *f = NULL; 931 unsigned index; 932 long r; 933 u32 tmp = 0; 934 u64 gpu_addr; 935 936 r = amdgpu_wb_get(adev, &index); 937 if (r) { 938 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 939 return r; 940 } 941 942 gpu_addr = adev->wb.gpu_addr + (index * 4); 943 tmp = 0xCAFEDEAD; 944 adev->wb.wb[index] = cpu_to_le32(tmp); 945 memset(&ib, 0, sizeof(ib)); 946 r = amdgpu_ib_get(adev, NULL, 256, &ib); 947 if (r) { 948 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 949 goto err0; 950 } 951 952 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 953 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 954 ib.ptr[1] = lower_32_bits(gpu_addr); 955 ib.ptr[2] = upper_32_bits(gpu_addr); 956 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 957 ib.ptr[4] = 0xDEADBEEF; 958 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 959 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 960 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 961 ib.length_dw = 8; 962 963 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 964 if (r) 965 goto err1; 966 967 r = dma_fence_wait_timeout(f, false, timeout); 968 if (r == 0) { 969 DRM_ERROR("amdgpu: IB test timed out\n"); 970 r = -ETIMEDOUT; 971 goto err1; 972 } else if (r < 0) { 973 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 974 goto err1; 975 } 976 tmp = le32_to_cpu(adev->wb.wb[index]); 977 if (tmp == 0xDEADBEEF) { 978 DRM_INFO("ib test on ring %d succeeded\n", ring->idx); 979 r = 0; 980 } else { 981 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); 982 r = -EINVAL; 983 } 984 err1: 985 amdgpu_ib_free(adev, &ib, NULL); 986 dma_fence_put(f); 987 err0: 988 amdgpu_wb_free(adev, index); 989 return r; 990 } 991 992 993 /** 994 * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART 995 * 996 * @ib: indirect buffer to fill with commands 997 * @pe: addr of the page entry 998 * @src: src addr to copy from 999 * @count: number of page entries to update 1000 * 1001 * Update PTEs by copying them from the GART using sDMA (VEGA10). 1002 */ 1003 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib, 1004 uint64_t pe, uint64_t src, 1005 unsigned count) 1006 { 1007 unsigned bytes = count * 8; 1008 1009 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1010 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1011 ib->ptr[ib->length_dw++] = bytes - 1; 1012 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1013 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1014 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1015 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1016 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1017 1018 } 1019 1020 /** 1021 * sdma_v4_0_vm_write_pte - update PTEs by writing them manually 1022 * 1023 * @ib: indirect buffer to fill with commands 1024 * @pe: addr of the page entry 1025 * @addr: dst addr to write into pe 1026 * @count: number of page entries to update 1027 * @incr: increase next addr by incr bytes 1028 * @flags: access flags 1029 * 1030 * Update PTEs by writing them manually using sDMA (VEGA10). 1031 */ 1032 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1033 uint64_t value, unsigned count, 1034 uint32_t incr) 1035 { 1036 unsigned ndw = count * 2; 1037 1038 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1039 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1040 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1041 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1042 ib->ptr[ib->length_dw++] = ndw - 1; 1043 for (; ndw > 0; ndw -= 2) { 1044 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1045 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1046 value += incr; 1047 } 1048 } 1049 1050 /** 1051 * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA 1052 * 1053 * @ib: indirect buffer to fill with commands 1054 * @pe: addr of the page entry 1055 * @addr: dst addr to write into pe 1056 * @count: number of page entries to update 1057 * @incr: increase next addr by incr bytes 1058 * @flags: access flags 1059 * 1060 * Update the page tables using sDMA (VEGA10). 1061 */ 1062 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1063 uint64_t pe, 1064 uint64_t addr, unsigned count, 1065 uint32_t incr, uint64_t flags) 1066 { 1067 /* for physically contiguous pages (vram) */ 1068 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1069 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1070 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1071 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1072 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1073 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1074 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1075 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1076 ib->ptr[ib->length_dw++] = 0; 1077 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1078 } 1079 1080 /** 1081 * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw 1082 * 1083 * @ib: indirect buffer to fill with padding 1084 * 1085 */ 1086 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1087 { 1088 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); 1089 u32 pad_count; 1090 int i; 1091 1092 pad_count = (8 - (ib->length_dw & 0x7)) % 8; 1093 for (i = 0; i < pad_count; i++) 1094 if (sdma && sdma->burst_nop && (i == 0)) 1095 ib->ptr[ib->length_dw++] = 1096 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1097 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1098 else 1099 ib->ptr[ib->length_dw++] = 1100 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1101 } 1102 1103 1104 /** 1105 * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline 1106 * 1107 * @ring: amdgpu_ring pointer 1108 * 1109 * Make sure all previous operations are completed (CIK). 1110 */ 1111 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1112 { 1113 uint32_t seq = ring->fence_drv.sync_seq; 1114 uint64_t addr = ring->fence_drv.gpu_addr; 1115 1116 /* wait for idle */ 1117 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1118 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1119 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1120 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1121 amdgpu_ring_write(ring, addr & 0xfffffffc); 1122 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1123 amdgpu_ring_write(ring, seq); /* reference */ 1124 amdgpu_ring_write(ring, 0xfffffff); /* mask */ 1125 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1126 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1127 } 1128 1129 1130 /** 1131 * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA 1132 * 1133 * @ring: amdgpu_ring pointer 1134 * @vm: amdgpu_vm pointer 1135 * 1136 * Update the page table base and flush the VM TLB 1137 * using sDMA (VEGA10). 1138 */ 1139 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1140 unsigned vm_id, uint64_t pd_addr) 1141 { 1142 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1143 uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id); 1144 unsigned eng = ring->vm_inv_eng; 1145 1146 pd_addr = pd_addr | 0x1; /* valid bit */ 1147 /* now only use physical base address of PDE and valid */ 1148 BUG_ON(pd_addr & 0xFFFF00000000003EULL); 1149 1150 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1151 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1152 amdgpu_ring_write(ring, hub->ctx0_ptb_addr_lo32 + vm_id * 2); 1153 amdgpu_ring_write(ring, lower_32_bits(pd_addr)); 1154 1155 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1156 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1157 amdgpu_ring_write(ring, hub->ctx0_ptb_addr_hi32 + vm_id * 2); 1158 amdgpu_ring_write(ring, upper_32_bits(pd_addr)); 1159 1160 /* flush TLB */ 1161 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1162 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1163 amdgpu_ring_write(ring, hub->vm_inv_eng0_req + eng); 1164 amdgpu_ring_write(ring, req); 1165 1166 /* wait for flush */ 1167 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1168 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1169 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ 1170 amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2); 1171 amdgpu_ring_write(ring, 0); 1172 amdgpu_ring_write(ring, 1 << vm_id); /* reference */ 1173 amdgpu_ring_write(ring, 1 << vm_id); /* mask */ 1174 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1175 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); 1176 } 1177 1178 static int sdma_v4_0_early_init(void *handle) 1179 { 1180 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1181 1182 if (adev->asic_type == CHIP_RAVEN) 1183 adev->sdma.num_instances = 1; 1184 else 1185 adev->sdma.num_instances = 2; 1186 1187 sdma_v4_0_set_ring_funcs(adev); 1188 sdma_v4_0_set_buffer_funcs(adev); 1189 sdma_v4_0_set_vm_pte_funcs(adev); 1190 sdma_v4_0_set_irq_funcs(adev); 1191 1192 return 0; 1193 } 1194 1195 1196 static int sdma_v4_0_sw_init(void *handle) 1197 { 1198 struct amdgpu_ring *ring; 1199 int r, i; 1200 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1201 1202 /* SDMA trap event */ 1203 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_SDMA0, 224, 1204 &adev->sdma.trap_irq); 1205 if (r) 1206 return r; 1207 1208 /* SDMA trap event */ 1209 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_SDMA1, 224, 1210 &adev->sdma.trap_irq); 1211 if (r) 1212 return r; 1213 1214 r = sdma_v4_0_init_microcode(adev); 1215 if (r) { 1216 DRM_ERROR("Failed to load sdma firmware!\n"); 1217 return r; 1218 } 1219 1220 for (i = 0; i < adev->sdma.num_instances; i++) { 1221 ring = &adev->sdma.instance[i].ring; 1222 ring->ring_obj = NULL; 1223 ring->use_doorbell = true; 1224 1225 DRM_INFO("use_doorbell being set to: [%s]\n", 1226 ring->use_doorbell?"true":"false"); 1227 1228 ring->doorbell_index = (i == 0) ? 1229 (AMDGPU_DOORBELL64_sDMA_ENGINE0 << 1) //get DWORD offset 1230 : (AMDGPU_DOORBELL64_sDMA_ENGINE1 << 1); // get DWORD offset 1231 1232 sprintf(ring->name, "sdma%d", i); 1233 r = amdgpu_ring_init(adev, ring, 1024, 1234 &adev->sdma.trap_irq, 1235 (i == 0) ? 1236 AMDGPU_SDMA_IRQ_TRAP0 : 1237 AMDGPU_SDMA_IRQ_TRAP1); 1238 if (r) 1239 return r; 1240 } 1241 1242 return r; 1243 } 1244 1245 static int sdma_v4_0_sw_fini(void *handle) 1246 { 1247 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1248 int i; 1249 1250 for (i = 0; i < adev->sdma.num_instances; i++) 1251 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1252 1253 return 0; 1254 } 1255 1256 static int sdma_v4_0_hw_init(void *handle) 1257 { 1258 int r; 1259 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1260 1261 sdma_v4_0_init_golden_registers(adev); 1262 1263 r = sdma_v4_0_start(adev); 1264 1265 return r; 1266 } 1267 1268 static int sdma_v4_0_hw_fini(void *handle) 1269 { 1270 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1271 1272 if (amdgpu_sriov_vf(adev)) 1273 return 0; 1274 1275 sdma_v4_0_ctx_switch_enable(adev, false); 1276 sdma_v4_0_enable(adev, false); 1277 1278 return 0; 1279 } 1280 1281 static int sdma_v4_0_suspend(void *handle) 1282 { 1283 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1284 1285 return sdma_v4_0_hw_fini(adev); 1286 } 1287 1288 static int sdma_v4_0_resume(void *handle) 1289 { 1290 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1291 1292 return sdma_v4_0_hw_init(adev); 1293 } 1294 1295 static bool sdma_v4_0_is_idle(void *handle) 1296 { 1297 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1298 u32 i; 1299 1300 for (i = 0; i < adev->sdma.num_instances; i++) { 1301 u32 tmp = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_STATUS_REG)); 1302 1303 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1304 return false; 1305 } 1306 1307 return true; 1308 } 1309 1310 static int sdma_v4_0_wait_for_idle(void *handle) 1311 { 1312 unsigned i; 1313 u32 sdma0, sdma1; 1314 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1315 1316 for (i = 0; i < adev->usec_timeout; i++) { 1317 sdma0 = RREG32(sdma_v4_0_get_reg_offset(0, mmSDMA0_STATUS_REG)); 1318 sdma1 = RREG32(sdma_v4_0_get_reg_offset(1, mmSDMA0_STATUS_REG)); 1319 1320 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK) 1321 return 0; 1322 udelay(1); 1323 } 1324 return -ETIMEDOUT; 1325 } 1326 1327 static int sdma_v4_0_soft_reset(void *handle) 1328 { 1329 /* todo */ 1330 1331 return 0; 1332 } 1333 1334 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev, 1335 struct amdgpu_irq_src *source, 1336 unsigned type, 1337 enum amdgpu_interrupt_state state) 1338 { 1339 u32 sdma_cntl; 1340 1341 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_TRAP0) ? 1342 sdma_v4_0_get_reg_offset(0, mmSDMA0_CNTL) : 1343 sdma_v4_0_get_reg_offset(1, mmSDMA0_CNTL); 1344 1345 sdma_cntl = RREG32(reg_offset); 1346 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1347 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1348 WREG32(reg_offset, sdma_cntl); 1349 1350 return 0; 1351 } 1352 1353 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev, 1354 struct amdgpu_irq_src *source, 1355 struct amdgpu_iv_entry *entry) 1356 { 1357 DRM_DEBUG("IH: SDMA trap\n"); 1358 switch (entry->client_id) { 1359 case AMDGPU_IH_CLIENTID_SDMA0: 1360 switch (entry->ring_id) { 1361 case 0: 1362 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1363 break; 1364 case 1: 1365 /* XXX compute */ 1366 break; 1367 case 2: 1368 /* XXX compute */ 1369 break; 1370 case 3: 1371 /* XXX page queue*/ 1372 break; 1373 } 1374 break; 1375 case AMDGPU_IH_CLIENTID_SDMA1: 1376 switch (entry->ring_id) { 1377 case 0: 1378 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1379 break; 1380 case 1: 1381 /* XXX compute */ 1382 break; 1383 case 2: 1384 /* XXX compute */ 1385 break; 1386 case 3: 1387 /* XXX page queue*/ 1388 break; 1389 } 1390 break; 1391 } 1392 return 0; 1393 } 1394 1395 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1396 struct amdgpu_irq_src *source, 1397 struct amdgpu_iv_entry *entry) 1398 { 1399 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1400 schedule_work(&adev->reset_work); 1401 return 0; 1402 } 1403 1404 1405 static void sdma_v4_0_update_medium_grain_clock_gating( 1406 struct amdgpu_device *adev, 1407 bool enable) 1408 { 1409 uint32_t data, def; 1410 1411 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1412 /* enable sdma0 clock gating */ 1413 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 1414 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1415 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1416 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1417 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1418 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1419 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1420 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1421 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1422 if (def != data) 1423 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data); 1424 1425 if (adev->asic_type == CHIP_VEGA10) { 1426 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL)); 1427 data &= ~(SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1428 SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1429 SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1430 SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1431 SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1432 SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1433 SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1434 SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1435 if (def != data) 1436 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data); 1437 } 1438 } else { 1439 /* disable sdma0 clock gating */ 1440 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 1441 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1442 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1443 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1444 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1445 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1446 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1447 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1448 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1449 1450 if (def != data) 1451 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data); 1452 1453 if (adev->asic_type == CHIP_VEGA10) { 1454 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL)); 1455 data |= (SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1456 SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1457 SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1458 SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1459 SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1460 SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1461 SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1462 SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1463 if (def != data) 1464 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data); 1465 } 1466 } 1467 } 1468 1469 1470 static void sdma_v4_0_update_medium_grain_light_sleep( 1471 struct amdgpu_device *adev, 1472 bool enable) 1473 { 1474 uint32_t data, def; 1475 1476 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1477 /* 1-not override: enable sdma0 mem light sleep */ 1478 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1479 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1480 if (def != data) 1481 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1482 1483 /* 1-not override: enable sdma1 mem light sleep */ 1484 if (adev->asic_type == CHIP_VEGA10) { 1485 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL)); 1486 data |= SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1487 if (def != data) 1488 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data); 1489 } 1490 } else { 1491 /* 0-override:disable sdma0 mem light sleep */ 1492 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1493 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1494 if (def != data) 1495 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1496 1497 /* 0-override:disable sdma1 mem light sleep */ 1498 if (adev->asic_type == CHIP_VEGA10) { 1499 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL)); 1500 data &= ~SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1501 if (def != data) 1502 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data); 1503 } 1504 } 1505 } 1506 1507 static int sdma_v4_0_set_clockgating_state(void *handle, 1508 enum amd_clockgating_state state) 1509 { 1510 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1511 1512 if (amdgpu_sriov_vf(adev)) 1513 return 0; 1514 1515 switch (adev->asic_type) { 1516 case CHIP_VEGA10: 1517 case CHIP_RAVEN: 1518 sdma_v4_0_update_medium_grain_clock_gating(adev, 1519 state == AMD_CG_STATE_GATE ? true : false); 1520 sdma_v4_0_update_medium_grain_light_sleep(adev, 1521 state == AMD_CG_STATE_GATE ? true : false); 1522 break; 1523 default: 1524 break; 1525 } 1526 return 0; 1527 } 1528 1529 static int sdma_v4_0_set_powergating_state(void *handle, 1530 enum amd_powergating_state state) 1531 { 1532 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1533 1534 switch (adev->asic_type) { 1535 case CHIP_RAVEN: 1536 sdma_v4_1_update_power_gating(adev, 1537 state == AMD_PG_STATE_GATE ? true : false); 1538 break; 1539 default: 1540 break; 1541 } 1542 1543 return 0; 1544 } 1545 1546 static void sdma_v4_0_get_clockgating_state(void *handle, u32 *flags) 1547 { 1548 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1549 int data; 1550 1551 if (amdgpu_sriov_vf(adev)) 1552 *flags = 0; 1553 1554 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1555 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 1556 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK)) 1557 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1558 1559 /* AMD_CG_SUPPORT_SDMA_LS */ 1560 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1561 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1562 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1563 } 1564 1565 const struct amd_ip_funcs sdma_v4_0_ip_funcs = { 1566 .name = "sdma_v4_0", 1567 .early_init = sdma_v4_0_early_init, 1568 .late_init = NULL, 1569 .sw_init = sdma_v4_0_sw_init, 1570 .sw_fini = sdma_v4_0_sw_fini, 1571 .hw_init = sdma_v4_0_hw_init, 1572 .hw_fini = sdma_v4_0_hw_fini, 1573 .suspend = sdma_v4_0_suspend, 1574 .resume = sdma_v4_0_resume, 1575 .is_idle = sdma_v4_0_is_idle, 1576 .wait_for_idle = sdma_v4_0_wait_for_idle, 1577 .soft_reset = sdma_v4_0_soft_reset, 1578 .set_clockgating_state = sdma_v4_0_set_clockgating_state, 1579 .set_powergating_state = sdma_v4_0_set_powergating_state, 1580 .get_clockgating_state = sdma_v4_0_get_clockgating_state, 1581 }; 1582 1583 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = { 1584 .type = AMDGPU_RING_TYPE_SDMA, 1585 .align_mask = 0xf, 1586 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1587 .support_64bit_ptrs = true, 1588 .vmhub = AMDGPU_MMHUB, 1589 .get_rptr = sdma_v4_0_ring_get_rptr, 1590 .get_wptr = sdma_v4_0_ring_get_wptr, 1591 .set_wptr = sdma_v4_0_ring_set_wptr, 1592 .emit_frame_size = 1593 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 1594 3 + /* sdma_v4_0_ring_emit_hdp_invalidate */ 1595 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 1596 18 + /* sdma_v4_0_ring_emit_vm_flush */ 1597 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 1598 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 1599 .emit_ib = sdma_v4_0_ring_emit_ib, 1600 .emit_fence = sdma_v4_0_ring_emit_fence, 1601 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 1602 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 1603 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 1604 .emit_hdp_invalidate = sdma_v4_0_ring_emit_hdp_invalidate, 1605 .test_ring = sdma_v4_0_ring_test_ring, 1606 .test_ib = sdma_v4_0_ring_test_ib, 1607 .insert_nop = sdma_v4_0_ring_insert_nop, 1608 .pad_ib = sdma_v4_0_ring_pad_ib, 1609 }; 1610 1611 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev) 1612 { 1613 int i; 1614 1615 for (i = 0; i < adev->sdma.num_instances; i++) 1616 adev->sdma.instance[i].ring.funcs = &sdma_v4_0_ring_funcs; 1617 } 1618 1619 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = { 1620 .set = sdma_v4_0_set_trap_irq_state, 1621 .process = sdma_v4_0_process_trap_irq, 1622 }; 1623 1624 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = { 1625 .process = sdma_v4_0_process_illegal_inst_irq, 1626 }; 1627 1628 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev) 1629 { 1630 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 1631 adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs; 1632 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs; 1633 } 1634 1635 /** 1636 * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine 1637 * 1638 * @ring: amdgpu_ring structure holding ring information 1639 * @src_offset: src GPU address 1640 * @dst_offset: dst GPU address 1641 * @byte_count: number of bytes to xfer 1642 * 1643 * Copy GPU buffers using the DMA engine (VEGA10). 1644 * Used by the amdgpu ttm implementation to move pages if 1645 * registered as the asic copy callback. 1646 */ 1647 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib, 1648 uint64_t src_offset, 1649 uint64_t dst_offset, 1650 uint32_t byte_count) 1651 { 1652 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1653 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1654 ib->ptr[ib->length_dw++] = byte_count - 1; 1655 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1656 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1657 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1658 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1659 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1660 } 1661 1662 /** 1663 * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine 1664 * 1665 * @ring: amdgpu_ring structure holding ring information 1666 * @src_data: value to write to buffer 1667 * @dst_offset: dst GPU address 1668 * @byte_count: number of bytes to xfer 1669 * 1670 * Fill GPU buffers using the DMA engine (VEGA10). 1671 */ 1672 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib, 1673 uint32_t src_data, 1674 uint64_t dst_offset, 1675 uint32_t byte_count) 1676 { 1677 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1678 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1679 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1680 ib->ptr[ib->length_dw++] = src_data; 1681 ib->ptr[ib->length_dw++] = byte_count - 1; 1682 } 1683 1684 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = { 1685 .copy_max_bytes = 0x400000, 1686 .copy_num_dw = 7, 1687 .emit_copy_buffer = sdma_v4_0_emit_copy_buffer, 1688 1689 .fill_max_bytes = 0x400000, 1690 .fill_num_dw = 5, 1691 .emit_fill_buffer = sdma_v4_0_emit_fill_buffer, 1692 }; 1693 1694 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev) 1695 { 1696 if (adev->mman.buffer_funcs == NULL) { 1697 adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs; 1698 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1699 } 1700 } 1701 1702 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = { 1703 .copy_pte = sdma_v4_0_vm_copy_pte, 1704 .write_pte = sdma_v4_0_vm_write_pte, 1705 .set_pte_pde = sdma_v4_0_vm_set_pte_pde, 1706 }; 1707 1708 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1709 { 1710 unsigned i; 1711 1712 if (adev->vm_manager.vm_pte_funcs == NULL) { 1713 adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs; 1714 for (i = 0; i < adev->sdma.num_instances; i++) 1715 adev->vm_manager.vm_pte_rings[i] = 1716 &adev->sdma.instance[i].ring; 1717 1718 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances; 1719 } 1720 } 1721 1722 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = { 1723 .type = AMD_IP_BLOCK_TYPE_SDMA, 1724 .major = 4, 1725 .minor = 0, 1726 .rev = 0, 1727 .funcs = &sdma_v4_0_ip_funcs, 1728 }; 1729