1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_ucode.h" 28 #include "amdgpu_trace.h" 29 30 #include "sdma0/sdma0_4_2_offset.h" 31 #include "sdma0/sdma0_4_2_sh_mask.h" 32 #include "sdma1/sdma1_4_2_offset.h" 33 #include "sdma1/sdma1_4_2_sh_mask.h" 34 #include "hdp/hdp_4_0_offset.h" 35 #include "sdma0/sdma0_4_1_default.h" 36 37 #include "soc15_common.h" 38 #include "soc15.h" 39 #include "vega10_sdma_pkt_open.h" 40 41 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h" 42 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h" 43 44 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin"); 45 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin"); 46 MODULE_FIRMWARE("amdgpu/vega12_sdma.bin"); 47 MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin"); 48 MODULE_FIRMWARE("amdgpu/vega20_sdma.bin"); 49 MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin"); 50 MODULE_FIRMWARE("amdgpu/raven_sdma.bin"); 51 MODULE_FIRMWARE("amdgpu/picasso_sdma.bin"); 52 MODULE_FIRMWARE("amdgpu/raven2_sdma.bin"); 53 54 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L 55 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L 56 57 #define WREG32_SDMA(instance, offset, value) \ 58 WREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)), value) 59 #define RREG32_SDMA(instance, offset) \ 60 RREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset))) 61 62 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev); 63 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev); 64 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev); 65 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev); 66 67 static const struct soc15_reg_golden golden_settings_sdma_4[] = { 68 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 69 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100), 70 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100), 71 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 72 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 73 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 74 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000), 75 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 76 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 77 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 78 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 79 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 80 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000), 81 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 82 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), 83 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100), 84 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 85 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 86 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 87 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000), 88 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 89 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 90 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 91 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 92 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0), 93 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xfc000000, 0x00000000) 94 }; 95 96 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = { 97 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 98 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 99 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 100 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002) 101 }; 102 103 static const struct soc15_reg_golden golden_settings_sdma_vg12[] = { 104 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), 105 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001), 106 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), 107 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001) 108 }; 109 110 static const struct soc15_reg_golden golden_settings_sdma_4_1[] = { 111 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 112 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 113 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100), 114 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 115 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051), 116 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100), 117 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 118 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100), 119 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 120 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 121 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000) 122 }; 123 124 static const struct soc15_reg_golden golden_settings_sdma0_4_2_init[] = { 125 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 126 }; 127 128 static const struct soc15_reg_golden golden_settings_sdma0_4_2[] = 129 { 130 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 131 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 132 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 133 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 134 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 135 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 136 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 137 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 138 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RD_BURST_CNTL, 0x0000000f, 0x00000003), 139 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 140 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 141 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 142 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 143 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 144 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 145 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 146 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 147 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 148 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 149 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 150 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 151 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 152 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 153 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 154 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 155 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 156 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xFE000000, 0x00000000), 157 }; 158 159 static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = { 160 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 161 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), 162 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 163 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 164 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 165 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 166 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 167 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 168 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RD_BURST_CNTL, 0x0000000f, 0x00000003), 169 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 170 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 171 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 172 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 173 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 174 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 175 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 176 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 177 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 178 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 179 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 180 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 181 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 182 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 183 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 184 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 185 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0), 186 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xFE000000, 0x00000000), 187 }; 188 189 static const struct soc15_reg_golden golden_settings_sdma_rv1[] = 190 { 191 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002), 192 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002) 193 }; 194 195 static const struct soc15_reg_golden golden_settings_sdma_rv2[] = 196 { 197 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00003001), 198 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003001) 199 }; 200 201 static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev, 202 u32 instance, u32 offset) 203 { 204 return ( 0 == instance ? (adev->reg_offset[SDMA0_HWIP][0][0] + offset) : 205 (adev->reg_offset[SDMA1_HWIP][0][0] + offset)); 206 } 207 208 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) 209 { 210 switch (adev->asic_type) { 211 case CHIP_VEGA10: 212 soc15_program_register_sequence(adev, 213 golden_settings_sdma_4, 214 ARRAY_SIZE(golden_settings_sdma_4)); 215 soc15_program_register_sequence(adev, 216 golden_settings_sdma_vg10, 217 ARRAY_SIZE(golden_settings_sdma_vg10)); 218 break; 219 case CHIP_VEGA12: 220 soc15_program_register_sequence(adev, 221 golden_settings_sdma_4, 222 ARRAY_SIZE(golden_settings_sdma_4)); 223 soc15_program_register_sequence(adev, 224 golden_settings_sdma_vg12, 225 ARRAY_SIZE(golden_settings_sdma_vg12)); 226 break; 227 case CHIP_VEGA20: 228 soc15_program_register_sequence(adev, 229 golden_settings_sdma0_4_2_init, 230 ARRAY_SIZE(golden_settings_sdma0_4_2_init)); 231 soc15_program_register_sequence(adev, 232 golden_settings_sdma0_4_2, 233 ARRAY_SIZE(golden_settings_sdma0_4_2)); 234 soc15_program_register_sequence(adev, 235 golden_settings_sdma1_4_2, 236 ARRAY_SIZE(golden_settings_sdma1_4_2)); 237 break; 238 case CHIP_RAVEN: 239 soc15_program_register_sequence(adev, 240 golden_settings_sdma_4_1, 241 ARRAY_SIZE(golden_settings_sdma_4_1)); 242 if (adev->rev_id >= 8) 243 soc15_program_register_sequence(adev, 244 golden_settings_sdma_rv2, 245 ARRAY_SIZE(golden_settings_sdma_rv2)); 246 else 247 soc15_program_register_sequence(adev, 248 golden_settings_sdma_rv1, 249 ARRAY_SIZE(golden_settings_sdma_rv1)); 250 break; 251 default: 252 break; 253 } 254 } 255 256 /** 257 * sdma_v4_0_init_microcode - load ucode images from disk 258 * 259 * @adev: amdgpu_device pointer 260 * 261 * Use the firmware interface to load the ucode images into 262 * the driver (not loaded into hw). 263 * Returns 0 on success, error on failure. 264 */ 265 266 // emulation only, won't work on real chip 267 // vega10 real chip need to use PSP to load firmware 268 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev) 269 { 270 const char *chip_name; 271 char fw_name[30]; 272 int err = 0, i; 273 struct amdgpu_firmware_info *info = NULL; 274 const struct common_firmware_header *header = NULL; 275 const struct sdma_firmware_header_v1_0 *hdr; 276 277 DRM_DEBUG("\n"); 278 279 switch (adev->asic_type) { 280 case CHIP_VEGA10: 281 chip_name = "vega10"; 282 break; 283 case CHIP_VEGA12: 284 chip_name = "vega12"; 285 break; 286 case CHIP_VEGA20: 287 chip_name = "vega20"; 288 break; 289 case CHIP_RAVEN: 290 if (adev->rev_id >= 8) 291 chip_name = "raven2"; 292 else if (adev->pdev->device == 0x15d8) 293 chip_name = "picasso"; 294 else 295 chip_name = "raven"; 296 break; 297 default: 298 BUG(); 299 } 300 301 for (i = 0; i < adev->sdma.num_instances; i++) { 302 if (i == 0) 303 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 304 else 305 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); 306 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 307 if (err) 308 goto out; 309 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); 310 if (err) 311 goto out; 312 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 313 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 314 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 315 if (adev->sdma.instance[i].feature_version >= 20) 316 adev->sdma.instance[i].burst_nop = true; 317 DRM_DEBUG("psp_load == '%s'\n", 318 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); 319 320 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 321 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 322 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 323 info->fw = adev->sdma.instance[i].fw; 324 header = (const struct common_firmware_header *)info->fw->data; 325 adev->firmware.fw_size += 326 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 327 } 328 } 329 out: 330 if (err) { 331 DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name); 332 for (i = 0; i < adev->sdma.num_instances; i++) { 333 release_firmware(adev->sdma.instance[i].fw); 334 adev->sdma.instance[i].fw = NULL; 335 } 336 } 337 return err; 338 } 339 340 /** 341 * sdma_v4_0_ring_get_rptr - get the current read pointer 342 * 343 * @ring: amdgpu ring pointer 344 * 345 * Get the current rptr from the hardware (VEGA10+). 346 */ 347 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring) 348 { 349 u64 *rptr; 350 351 /* XXX check if swapping is necessary on BE */ 352 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]); 353 354 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 355 return ((*rptr) >> 2); 356 } 357 358 /** 359 * sdma_v4_0_ring_get_wptr - get the current write pointer 360 * 361 * @ring: amdgpu ring pointer 362 * 363 * Get the current wptr from the hardware (VEGA10+). 364 */ 365 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring) 366 { 367 struct amdgpu_device *adev = ring->adev; 368 u64 wptr; 369 370 if (ring->use_doorbell) { 371 /* XXX check if swapping is necessary on BE */ 372 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 373 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 374 } else { 375 wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI); 376 wptr = wptr << 32; 377 wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR); 378 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", 379 ring->me, wptr); 380 } 381 382 return wptr >> 2; 383 } 384 385 /** 386 * sdma_v4_0_ring_set_wptr - commit the write pointer 387 * 388 * @ring: amdgpu ring pointer 389 * 390 * Write the wptr back to the hardware (VEGA10+). 391 */ 392 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring) 393 { 394 struct amdgpu_device *adev = ring->adev; 395 396 DRM_DEBUG("Setting write pointer\n"); 397 if (ring->use_doorbell) { 398 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 399 400 DRM_DEBUG("Using doorbell -- " 401 "wptr_offs == 0x%08x " 402 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 403 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 404 ring->wptr_offs, 405 lower_32_bits(ring->wptr << 2), 406 upper_32_bits(ring->wptr << 2)); 407 /* XXX check if swapping is necessary on BE */ 408 WRITE_ONCE(*wb, (ring->wptr << 2)); 409 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 410 ring->doorbell_index, ring->wptr << 2); 411 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 412 } else { 413 DRM_DEBUG("Not using doorbell -- " 414 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 415 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 416 ring->me, 417 lower_32_bits(ring->wptr << 2), 418 ring->me, 419 upper_32_bits(ring->wptr << 2)); 420 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR, 421 lower_32_bits(ring->wptr << 2)); 422 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI, 423 upper_32_bits(ring->wptr << 2)); 424 } 425 } 426 427 /** 428 * sdma_v4_0_page_ring_get_wptr - get the current write pointer 429 * 430 * @ring: amdgpu ring pointer 431 * 432 * Get the current wptr from the hardware (VEGA10+). 433 */ 434 static uint64_t sdma_v4_0_page_ring_get_wptr(struct amdgpu_ring *ring) 435 { 436 struct amdgpu_device *adev = ring->adev; 437 u64 wptr; 438 439 if (ring->use_doorbell) { 440 /* XXX check if swapping is necessary on BE */ 441 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 442 } else { 443 wptr = RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI); 444 wptr = wptr << 32; 445 wptr |= RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR); 446 } 447 448 return wptr >> 2; 449 } 450 451 /** 452 * sdma_v4_0_ring_set_wptr - commit the write pointer 453 * 454 * @ring: amdgpu ring pointer 455 * 456 * Write the wptr back to the hardware (VEGA10+). 457 */ 458 static void sdma_v4_0_page_ring_set_wptr(struct amdgpu_ring *ring) 459 { 460 struct amdgpu_device *adev = ring->adev; 461 462 if (ring->use_doorbell) { 463 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 464 465 /* XXX check if swapping is necessary on BE */ 466 WRITE_ONCE(*wb, (ring->wptr << 2)); 467 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 468 } else { 469 uint64_t wptr = ring->wptr << 2; 470 471 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR, 472 lower_32_bits(wptr)); 473 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI, 474 upper_32_bits(wptr)); 475 } 476 } 477 478 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 479 { 480 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 481 int i; 482 483 for (i = 0; i < count; i++) 484 if (sdma && sdma->burst_nop && (i == 0)) 485 amdgpu_ring_write(ring, ring->funcs->nop | 486 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 487 else 488 amdgpu_ring_write(ring, ring->funcs->nop); 489 } 490 491 /** 492 * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine 493 * 494 * @ring: amdgpu ring pointer 495 * @ib: IB object to schedule 496 * 497 * Schedule an IB in the DMA ring (VEGA10). 498 */ 499 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring, 500 struct amdgpu_job *job, 501 struct amdgpu_ib *ib, 502 bool ctx_switch) 503 { 504 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 505 506 /* IB packet must end on a 8 DW boundary */ 507 sdma_v4_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8); 508 509 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 510 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 511 /* base must be 32 byte aligned */ 512 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 513 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 514 amdgpu_ring_write(ring, ib->length_dw); 515 amdgpu_ring_write(ring, 0); 516 amdgpu_ring_write(ring, 0); 517 518 } 519 520 static void sdma_v4_0_wait_reg_mem(struct amdgpu_ring *ring, 521 int mem_space, int hdp, 522 uint32_t addr0, uint32_t addr1, 523 uint32_t ref, uint32_t mask, 524 uint32_t inv) 525 { 526 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 527 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) | 528 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) | 529 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 530 if (mem_space) { 531 /* memory */ 532 amdgpu_ring_write(ring, addr0); 533 amdgpu_ring_write(ring, addr1); 534 } else { 535 /* registers */ 536 amdgpu_ring_write(ring, addr0 << 2); 537 amdgpu_ring_write(ring, addr1 << 2); 538 } 539 amdgpu_ring_write(ring, ref); /* reference */ 540 amdgpu_ring_write(ring, mask); /* mask */ 541 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 542 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */ 543 } 544 545 /** 546 * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 547 * 548 * @ring: amdgpu ring pointer 549 * 550 * Emit an hdp flush packet on the requested DMA ring. 551 */ 552 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 553 { 554 struct amdgpu_device *adev = ring->adev; 555 u32 ref_and_mask = 0; 556 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg; 557 558 if (ring->me == 0) 559 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0; 560 else 561 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1; 562 563 sdma_v4_0_wait_reg_mem(ring, 0, 1, 564 adev->nbio_funcs->get_hdp_flush_done_offset(adev), 565 adev->nbio_funcs->get_hdp_flush_req_offset(adev), 566 ref_and_mask, ref_and_mask, 10); 567 } 568 569 /** 570 * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring 571 * 572 * @ring: amdgpu ring pointer 573 * @fence: amdgpu fence object 574 * 575 * Add a DMA fence packet to the ring to write 576 * the fence seq number and DMA trap packet to generate 577 * an interrupt if needed (VEGA10). 578 */ 579 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 580 unsigned flags) 581 { 582 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 583 /* write the fence */ 584 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 585 /* zero in first two bits */ 586 BUG_ON(addr & 0x3); 587 amdgpu_ring_write(ring, lower_32_bits(addr)); 588 amdgpu_ring_write(ring, upper_32_bits(addr)); 589 amdgpu_ring_write(ring, lower_32_bits(seq)); 590 591 /* optionally write high bits as well */ 592 if (write64bit) { 593 addr += 4; 594 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 595 /* zero in first two bits */ 596 BUG_ON(addr & 0x3); 597 amdgpu_ring_write(ring, lower_32_bits(addr)); 598 amdgpu_ring_write(ring, upper_32_bits(addr)); 599 amdgpu_ring_write(ring, upper_32_bits(seq)); 600 } 601 602 /* generate an interrupt */ 603 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 604 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 605 } 606 607 608 /** 609 * sdma_v4_0_gfx_stop - stop the gfx async dma engines 610 * 611 * @adev: amdgpu_device pointer 612 * 613 * Stop the gfx async dma ring buffers (VEGA10). 614 */ 615 static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev) 616 { 617 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 618 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 619 u32 rb_cntl, ib_cntl; 620 int i; 621 622 if ((adev->mman.buffer_funcs_ring == sdma0) || 623 (adev->mman.buffer_funcs_ring == sdma1)) 624 amdgpu_ttm_set_buffer_funcs_status(adev, false); 625 626 for (i = 0; i < adev->sdma.num_instances; i++) { 627 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL); 628 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 629 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 630 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL); 631 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 632 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl); 633 } 634 635 sdma0->sched.ready = false; 636 sdma1->sched.ready = false; 637 } 638 639 /** 640 * sdma_v4_0_rlc_stop - stop the compute async dma engines 641 * 642 * @adev: amdgpu_device pointer 643 * 644 * Stop the compute async dma queues (VEGA10). 645 */ 646 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev) 647 { 648 /* XXX todo */ 649 } 650 651 /** 652 * sdma_v4_0_page_stop - stop the page async dma engines 653 * 654 * @adev: amdgpu_device pointer 655 * 656 * Stop the page async dma ring buffers (VEGA10). 657 */ 658 static void sdma_v4_0_page_stop(struct amdgpu_device *adev) 659 { 660 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].page; 661 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].page; 662 u32 rb_cntl, ib_cntl; 663 int i; 664 665 if ((adev->mman.buffer_funcs_ring == sdma0) || 666 (adev->mman.buffer_funcs_ring == sdma1)) 667 amdgpu_ttm_set_buffer_funcs_status(adev, false); 668 669 for (i = 0; i < adev->sdma.num_instances; i++) { 670 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL); 671 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, 672 RB_ENABLE, 0); 673 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 674 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL); 675 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, 676 IB_ENABLE, 0); 677 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl); 678 } 679 680 sdma0->sched.ready = false; 681 sdma1->sched.ready = false; 682 } 683 684 /** 685 * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch 686 * 687 * @adev: amdgpu_device pointer 688 * @enable: enable/disable the DMA MEs context switch. 689 * 690 * Halt or unhalt the async dma engines context switch (VEGA10). 691 */ 692 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 693 { 694 u32 f32_cntl, phase_quantum = 0; 695 int i; 696 697 if (amdgpu_sdma_phase_quantum) { 698 unsigned value = amdgpu_sdma_phase_quantum; 699 unsigned unit = 0; 700 701 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 702 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 703 value = (value + 1) >> 1; 704 unit++; 705 } 706 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 707 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 708 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 709 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 710 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 711 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 712 WARN_ONCE(1, 713 "clamping sdma_phase_quantum to %uK clock cycles\n", 714 value << unit); 715 } 716 phase_quantum = 717 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 718 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 719 } 720 721 for (i = 0; i < adev->sdma.num_instances; i++) { 722 f32_cntl = RREG32_SDMA(i, mmSDMA0_CNTL); 723 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 724 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 725 if (enable && amdgpu_sdma_phase_quantum) { 726 WREG32_SDMA(i, mmSDMA0_PHASE0_QUANTUM, phase_quantum); 727 WREG32_SDMA(i, mmSDMA0_PHASE1_QUANTUM, phase_quantum); 728 WREG32_SDMA(i, mmSDMA0_PHASE2_QUANTUM, phase_quantum); 729 } 730 WREG32_SDMA(i, mmSDMA0_CNTL, f32_cntl); 731 } 732 733 } 734 735 /** 736 * sdma_v4_0_enable - stop the async dma engines 737 * 738 * @adev: amdgpu_device pointer 739 * @enable: enable/disable the DMA MEs. 740 * 741 * Halt or unhalt the async dma engines (VEGA10). 742 */ 743 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable) 744 { 745 u32 f32_cntl; 746 int i; 747 748 if (enable == false) { 749 sdma_v4_0_gfx_stop(adev); 750 sdma_v4_0_rlc_stop(adev); 751 if (adev->sdma.has_page_queue) 752 sdma_v4_0_page_stop(adev); 753 } 754 755 for (i = 0; i < adev->sdma.num_instances; i++) { 756 f32_cntl = RREG32_SDMA(i, mmSDMA0_F32_CNTL); 757 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 758 WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl); 759 } 760 } 761 762 /** 763 * sdma_v4_0_rb_cntl - get parameters for rb_cntl 764 */ 765 static uint32_t sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl) 766 { 767 /* Set ring buffer size in dwords */ 768 uint32_t rb_bufsz = order_base_2(ring->ring_size / 4); 769 770 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 771 #ifdef __BIG_ENDIAN 772 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 773 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 774 RPTR_WRITEBACK_SWAP_ENABLE, 1); 775 #endif 776 return rb_cntl; 777 } 778 779 /** 780 * sdma_v4_0_gfx_resume - setup and start the async dma engines 781 * 782 * @adev: amdgpu_device pointer 783 * @i: instance to resume 784 * 785 * Set up the gfx DMA ring buffers and enable them (VEGA10). 786 * Returns 0 for success, error for failure. 787 */ 788 static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i) 789 { 790 struct amdgpu_ring *ring = &adev->sdma.instance[i].ring; 791 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 792 u32 wb_offset; 793 u32 doorbell; 794 u32 doorbell_offset; 795 u64 wptr_gpu_addr; 796 797 wb_offset = (ring->rptr_offs * 4); 798 799 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL); 800 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl); 801 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 802 803 /* Initialize the ring buffer's read and write pointers */ 804 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR, 0); 805 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_HI, 0); 806 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR, 0); 807 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_HI, 0); 808 809 /* set the wb address whether it's enabled or not */ 810 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI, 811 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 812 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 813 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 814 815 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 816 RPTR_WRITEBACK_ENABLE, 1); 817 818 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE, ring->gpu_addr >> 8); 819 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE_HI, ring->gpu_addr >> 40); 820 821 ring->wptr = 0; 822 823 /* before programing wptr to a less value, need set minor_ptr_update first */ 824 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 1); 825 826 doorbell = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL); 827 doorbell_offset = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET); 828 829 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 830 ring->use_doorbell); 831 doorbell_offset = REG_SET_FIELD(doorbell_offset, 832 SDMA0_GFX_DOORBELL_OFFSET, 833 OFFSET, ring->doorbell_index); 834 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL, doorbell); 835 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET, doorbell_offset); 836 adev->nbio_funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 837 ring->doorbell_index); 838 839 sdma_v4_0_ring_set_wptr(ring); 840 841 /* set minor_ptr_update to 0 after wptr programed */ 842 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 0); 843 844 /* setup the wptr shadow polling */ 845 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 846 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO, 847 lower_32_bits(wptr_gpu_addr)); 848 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI, 849 upper_32_bits(wptr_gpu_addr)); 850 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL); 851 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 852 SDMA0_GFX_RB_WPTR_POLL_CNTL, 853 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)); 854 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 855 856 /* enable DMA RB */ 857 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 858 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 859 860 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL); 861 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 862 #ifdef __BIG_ENDIAN 863 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 864 #endif 865 /* enable DMA IBs */ 866 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl); 867 868 ring->sched.ready = true; 869 } 870 871 /** 872 * sdma_v4_0_page_resume - setup and start the async dma engines 873 * 874 * @adev: amdgpu_device pointer 875 * @i: instance to resume 876 * 877 * Set up the page DMA ring buffers and enable them (VEGA10). 878 * Returns 0 for success, error for failure. 879 */ 880 static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i) 881 { 882 struct amdgpu_ring *ring = &adev->sdma.instance[i].page; 883 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 884 u32 wb_offset; 885 u32 doorbell; 886 u32 doorbell_offset; 887 u64 wptr_gpu_addr; 888 889 wb_offset = (ring->rptr_offs * 4); 890 891 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL); 892 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl); 893 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 894 895 /* Initialize the ring buffer's read and write pointers */ 896 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR, 0); 897 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_HI, 0); 898 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR, 0); 899 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_HI, 0); 900 901 /* set the wb address whether it's enabled or not */ 902 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_HI, 903 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 904 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 905 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 906 907 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, 908 RPTR_WRITEBACK_ENABLE, 1); 909 910 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE, ring->gpu_addr >> 8); 911 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE_HI, ring->gpu_addr >> 40); 912 913 ring->wptr = 0; 914 915 /* before programing wptr to a less value, need set minor_ptr_update first */ 916 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 1); 917 918 doorbell = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL); 919 doorbell_offset = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET); 920 921 doorbell = REG_SET_FIELD(doorbell, SDMA0_PAGE_DOORBELL, ENABLE, 922 ring->use_doorbell); 923 doorbell_offset = REG_SET_FIELD(doorbell_offset, 924 SDMA0_PAGE_DOORBELL_OFFSET, 925 OFFSET, ring->doorbell_index); 926 WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL, doorbell); 927 WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET, doorbell_offset); 928 929 /* paging queue doorbell range is setup at sdma_v4_0_gfx_resume */ 930 sdma_v4_0_page_ring_set_wptr(ring); 931 932 /* set minor_ptr_update to 0 after wptr programed */ 933 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 0); 934 935 /* setup the wptr shadow polling */ 936 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 937 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO, 938 lower_32_bits(wptr_gpu_addr)); 939 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI, 940 upper_32_bits(wptr_gpu_addr)); 941 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL); 942 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 943 SDMA0_PAGE_RB_WPTR_POLL_CNTL, 944 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)); 945 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 946 947 /* enable DMA RB */ 948 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, RB_ENABLE, 1); 949 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 950 951 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL); 952 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_ENABLE, 1); 953 #ifdef __BIG_ENDIAN 954 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1); 955 #endif 956 /* enable DMA IBs */ 957 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl); 958 959 ring->sched.ready = true; 960 } 961 962 static void 963 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable) 964 { 965 uint32_t def, data; 966 967 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) { 968 /* enable idle interrupt */ 969 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 970 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 971 972 if (data != def) 973 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 974 } else { 975 /* disable idle interrupt */ 976 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 977 data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 978 if (data != def) 979 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 980 } 981 } 982 983 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev) 984 { 985 uint32_t def, data; 986 987 /* Enable HW based PG. */ 988 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 989 data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK; 990 if (data != def) 991 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 992 993 /* enable interrupt */ 994 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 995 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 996 if (data != def) 997 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 998 999 /* Configure hold time to filter in-valid power on/off request. Use default right now */ 1000 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1001 data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK; 1002 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK); 1003 /* Configure switch time for hysteresis purpose. Use default right now */ 1004 data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK; 1005 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK); 1006 if(data != def) 1007 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1008 } 1009 1010 static void sdma_v4_0_init_pg(struct amdgpu_device *adev) 1011 { 1012 if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA)) 1013 return; 1014 1015 switch (adev->asic_type) { 1016 case CHIP_RAVEN: 1017 sdma_v4_1_init_power_gating(adev); 1018 sdma_v4_1_update_power_gating(adev, true); 1019 break; 1020 default: 1021 break; 1022 } 1023 } 1024 1025 /** 1026 * sdma_v4_0_rlc_resume - setup and start the async dma engines 1027 * 1028 * @adev: amdgpu_device pointer 1029 * 1030 * Set up the compute DMA queues and enable them (VEGA10). 1031 * Returns 0 for success, error for failure. 1032 */ 1033 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev) 1034 { 1035 sdma_v4_0_init_pg(adev); 1036 1037 return 0; 1038 } 1039 1040 /** 1041 * sdma_v4_0_load_microcode - load the sDMA ME ucode 1042 * 1043 * @adev: amdgpu_device pointer 1044 * 1045 * Loads the sDMA0/1 ucode. 1046 * Returns 0 for success, -EINVAL if the ucode is not available. 1047 */ 1048 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev) 1049 { 1050 const struct sdma_firmware_header_v1_0 *hdr; 1051 const __le32 *fw_data; 1052 u32 fw_size; 1053 int i, j; 1054 1055 /* halt the MEs */ 1056 sdma_v4_0_enable(adev, false); 1057 1058 for (i = 0; i < adev->sdma.num_instances; i++) { 1059 if (!adev->sdma.instance[i].fw) 1060 return -EINVAL; 1061 1062 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 1063 amdgpu_ucode_print_sdma_hdr(&hdr->header); 1064 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1065 1066 fw_data = (const __le32 *) 1067 (adev->sdma.instance[i].fw->data + 1068 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1069 1070 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 0); 1071 1072 for (j = 0; j < fw_size; j++) 1073 WREG32_SDMA(i, mmSDMA0_UCODE_DATA, 1074 le32_to_cpup(fw_data++)); 1075 1076 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 1077 adev->sdma.instance[i].fw_version); 1078 } 1079 1080 return 0; 1081 } 1082 1083 /** 1084 * sdma_v4_0_start - setup and start the async dma engines 1085 * 1086 * @adev: amdgpu_device pointer 1087 * 1088 * Set up the DMA engines and enable them (VEGA10). 1089 * Returns 0 for success, error for failure. 1090 */ 1091 static int sdma_v4_0_start(struct amdgpu_device *adev) 1092 { 1093 struct amdgpu_ring *ring; 1094 int i, r; 1095 1096 if (amdgpu_sriov_vf(adev)) { 1097 sdma_v4_0_ctx_switch_enable(adev, false); 1098 sdma_v4_0_enable(adev, false); 1099 } else { 1100 1101 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1102 r = sdma_v4_0_load_microcode(adev); 1103 if (r) 1104 return r; 1105 } 1106 1107 /* unhalt the MEs */ 1108 sdma_v4_0_enable(adev, true); 1109 /* enable sdma ring preemption */ 1110 sdma_v4_0_ctx_switch_enable(adev, true); 1111 } 1112 1113 /* start the gfx rings and rlc compute queues */ 1114 for (i = 0; i < adev->sdma.num_instances; i++) { 1115 uint32_t temp; 1116 1117 WREG32_SDMA(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL, 0); 1118 sdma_v4_0_gfx_resume(adev, i); 1119 if (adev->sdma.has_page_queue) 1120 sdma_v4_0_page_resume(adev, i); 1121 1122 /* set utc l1 enable flag always to 1 */ 1123 temp = RREG32_SDMA(i, mmSDMA0_CNTL); 1124 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 1125 WREG32_SDMA(i, mmSDMA0_CNTL, temp); 1126 1127 if (!amdgpu_sriov_vf(adev)) { 1128 /* unhalt engine */ 1129 temp = RREG32_SDMA(i, mmSDMA0_F32_CNTL); 1130 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 1131 WREG32_SDMA(i, mmSDMA0_F32_CNTL, temp); 1132 } 1133 } 1134 1135 if (amdgpu_sriov_vf(adev)) { 1136 sdma_v4_0_ctx_switch_enable(adev, true); 1137 sdma_v4_0_enable(adev, true); 1138 } else { 1139 r = sdma_v4_0_rlc_resume(adev); 1140 if (r) 1141 return r; 1142 } 1143 1144 for (i = 0; i < adev->sdma.num_instances; i++) { 1145 ring = &adev->sdma.instance[i].ring; 1146 1147 r = amdgpu_ring_test_helper(ring); 1148 if (r) 1149 return r; 1150 1151 if (adev->sdma.has_page_queue) { 1152 struct amdgpu_ring *page = &adev->sdma.instance[i].page; 1153 1154 r = amdgpu_ring_test_helper(page); 1155 if (r) 1156 return r; 1157 1158 if (adev->mman.buffer_funcs_ring == page) 1159 amdgpu_ttm_set_buffer_funcs_status(adev, true); 1160 } 1161 1162 if (adev->mman.buffer_funcs_ring == ring) 1163 amdgpu_ttm_set_buffer_funcs_status(adev, true); 1164 } 1165 1166 return r; 1167 } 1168 1169 /** 1170 * sdma_v4_0_ring_test_ring - simple async dma engine test 1171 * 1172 * @ring: amdgpu_ring structure holding ring information 1173 * 1174 * Test the DMA engine by writing using it to write an 1175 * value to memory. (VEGA10). 1176 * Returns 0 for success, error for failure. 1177 */ 1178 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring) 1179 { 1180 struct amdgpu_device *adev = ring->adev; 1181 unsigned i; 1182 unsigned index; 1183 int r; 1184 u32 tmp; 1185 u64 gpu_addr; 1186 1187 r = amdgpu_device_wb_get(adev, &index); 1188 if (r) 1189 return r; 1190 1191 gpu_addr = adev->wb.gpu_addr + (index * 4); 1192 tmp = 0xCAFEDEAD; 1193 adev->wb.wb[index] = cpu_to_le32(tmp); 1194 1195 r = amdgpu_ring_alloc(ring, 5); 1196 if (r) 1197 goto error_free_wb; 1198 1199 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1200 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 1201 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 1202 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 1203 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 1204 amdgpu_ring_write(ring, 0xDEADBEEF); 1205 amdgpu_ring_commit(ring); 1206 1207 for (i = 0; i < adev->usec_timeout; i++) { 1208 tmp = le32_to_cpu(adev->wb.wb[index]); 1209 if (tmp == 0xDEADBEEF) 1210 break; 1211 DRM_UDELAY(1); 1212 } 1213 1214 if (i >= adev->usec_timeout) 1215 r = -ETIMEDOUT; 1216 1217 error_free_wb: 1218 amdgpu_device_wb_free(adev, index); 1219 return r; 1220 } 1221 1222 /** 1223 * sdma_v4_0_ring_test_ib - test an IB on the DMA engine 1224 * 1225 * @ring: amdgpu_ring structure holding ring information 1226 * 1227 * Test a simple IB in the DMA ring (VEGA10). 1228 * Returns 0 on success, error on failure. 1229 */ 1230 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1231 { 1232 struct amdgpu_device *adev = ring->adev; 1233 struct amdgpu_ib ib; 1234 struct dma_fence *f = NULL; 1235 unsigned index; 1236 long r; 1237 u32 tmp = 0; 1238 u64 gpu_addr; 1239 1240 r = amdgpu_device_wb_get(adev, &index); 1241 if (r) 1242 return r; 1243 1244 gpu_addr = adev->wb.gpu_addr + (index * 4); 1245 tmp = 0xCAFEDEAD; 1246 adev->wb.wb[index] = cpu_to_le32(tmp); 1247 memset(&ib, 0, sizeof(ib)); 1248 r = amdgpu_ib_get(adev, NULL, 256, &ib); 1249 if (r) 1250 goto err0; 1251 1252 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1253 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1254 ib.ptr[1] = lower_32_bits(gpu_addr); 1255 ib.ptr[2] = upper_32_bits(gpu_addr); 1256 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1257 ib.ptr[4] = 0xDEADBEEF; 1258 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1259 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1260 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1261 ib.length_dw = 8; 1262 1263 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1264 if (r) 1265 goto err1; 1266 1267 r = dma_fence_wait_timeout(f, false, timeout); 1268 if (r == 0) { 1269 r = -ETIMEDOUT; 1270 goto err1; 1271 } else if (r < 0) { 1272 goto err1; 1273 } 1274 tmp = le32_to_cpu(adev->wb.wb[index]); 1275 if (tmp == 0xDEADBEEF) 1276 r = 0; 1277 else 1278 r = -EINVAL; 1279 1280 err1: 1281 amdgpu_ib_free(adev, &ib, NULL); 1282 dma_fence_put(f); 1283 err0: 1284 amdgpu_device_wb_free(adev, index); 1285 return r; 1286 } 1287 1288 1289 /** 1290 * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART 1291 * 1292 * @ib: indirect buffer to fill with commands 1293 * @pe: addr of the page entry 1294 * @src: src addr to copy from 1295 * @count: number of page entries to update 1296 * 1297 * Update PTEs by copying them from the GART using sDMA (VEGA10). 1298 */ 1299 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib, 1300 uint64_t pe, uint64_t src, 1301 unsigned count) 1302 { 1303 unsigned bytes = count * 8; 1304 1305 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1306 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1307 ib->ptr[ib->length_dw++] = bytes - 1; 1308 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1309 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1310 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1311 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1312 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1313 1314 } 1315 1316 /** 1317 * sdma_v4_0_vm_write_pte - update PTEs by writing them manually 1318 * 1319 * @ib: indirect buffer to fill with commands 1320 * @pe: addr of the page entry 1321 * @addr: dst addr to write into pe 1322 * @count: number of page entries to update 1323 * @incr: increase next addr by incr bytes 1324 * @flags: access flags 1325 * 1326 * Update PTEs by writing them manually using sDMA (VEGA10). 1327 */ 1328 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1329 uint64_t value, unsigned count, 1330 uint32_t incr) 1331 { 1332 unsigned ndw = count * 2; 1333 1334 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1335 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1336 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1337 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1338 ib->ptr[ib->length_dw++] = ndw - 1; 1339 for (; ndw > 0; ndw -= 2) { 1340 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1341 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1342 value += incr; 1343 } 1344 } 1345 1346 /** 1347 * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA 1348 * 1349 * @ib: indirect buffer to fill with commands 1350 * @pe: addr of the page entry 1351 * @addr: dst addr to write into pe 1352 * @count: number of page entries to update 1353 * @incr: increase next addr by incr bytes 1354 * @flags: access flags 1355 * 1356 * Update the page tables using sDMA (VEGA10). 1357 */ 1358 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1359 uint64_t pe, 1360 uint64_t addr, unsigned count, 1361 uint32_t incr, uint64_t flags) 1362 { 1363 /* for physically contiguous pages (vram) */ 1364 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1365 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1366 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1367 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1368 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1369 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1370 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1371 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1372 ib->ptr[ib->length_dw++] = 0; 1373 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1374 } 1375 1376 /** 1377 * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw 1378 * 1379 * @ib: indirect buffer to fill with padding 1380 * 1381 */ 1382 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1383 { 1384 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1385 u32 pad_count; 1386 int i; 1387 1388 pad_count = (8 - (ib->length_dw & 0x7)) % 8; 1389 for (i = 0; i < pad_count; i++) 1390 if (sdma && sdma->burst_nop && (i == 0)) 1391 ib->ptr[ib->length_dw++] = 1392 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1393 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1394 else 1395 ib->ptr[ib->length_dw++] = 1396 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1397 } 1398 1399 1400 /** 1401 * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline 1402 * 1403 * @ring: amdgpu_ring pointer 1404 * 1405 * Make sure all previous operations are completed (CIK). 1406 */ 1407 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1408 { 1409 uint32_t seq = ring->fence_drv.sync_seq; 1410 uint64_t addr = ring->fence_drv.gpu_addr; 1411 1412 /* wait for idle */ 1413 sdma_v4_0_wait_reg_mem(ring, 1, 0, 1414 addr & 0xfffffffc, 1415 upper_32_bits(addr) & 0xffffffff, 1416 seq, 0xffffffff, 4); 1417 } 1418 1419 1420 /** 1421 * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA 1422 * 1423 * @ring: amdgpu_ring pointer 1424 * @vm: amdgpu_vm pointer 1425 * 1426 * Update the page table base and flush the VM TLB 1427 * using sDMA (VEGA10). 1428 */ 1429 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1430 unsigned vmid, uint64_t pd_addr) 1431 { 1432 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1433 } 1434 1435 static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring, 1436 uint32_t reg, uint32_t val) 1437 { 1438 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1439 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1440 amdgpu_ring_write(ring, reg); 1441 amdgpu_ring_write(ring, val); 1442 } 1443 1444 static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1445 uint32_t val, uint32_t mask) 1446 { 1447 sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10); 1448 } 1449 1450 static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev) 1451 { 1452 uint fw_version = adev->sdma.instance[0].fw_version; 1453 1454 switch (adev->asic_type) { 1455 case CHIP_VEGA10: 1456 return fw_version >= 430; 1457 case CHIP_VEGA12: 1458 /*return fw_version >= 31;*/ 1459 return false; 1460 case CHIP_VEGA20: 1461 /*return fw_version >= 115;*/ 1462 return false; 1463 default: 1464 return false; 1465 } 1466 } 1467 1468 static int sdma_v4_0_early_init(void *handle) 1469 { 1470 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1471 int r; 1472 1473 if (adev->asic_type == CHIP_RAVEN) 1474 adev->sdma.num_instances = 1; 1475 else 1476 adev->sdma.num_instances = 2; 1477 1478 r = sdma_v4_0_init_microcode(adev); 1479 if (r) { 1480 DRM_ERROR("Failed to load sdma firmware!\n"); 1481 return r; 1482 } 1483 1484 /* TODO: Page queue breaks driver reload under SRIOV */ 1485 if ((adev->asic_type == CHIP_VEGA10) && amdgpu_sriov_vf((adev))) 1486 adev->sdma.has_page_queue = false; 1487 else if (sdma_v4_0_fw_support_paging_queue(adev)) 1488 adev->sdma.has_page_queue = true; 1489 1490 sdma_v4_0_set_ring_funcs(adev); 1491 sdma_v4_0_set_buffer_funcs(adev); 1492 sdma_v4_0_set_vm_pte_funcs(adev); 1493 sdma_v4_0_set_irq_funcs(adev); 1494 1495 return 0; 1496 } 1497 1498 static int sdma_v4_0_sw_init(void *handle) 1499 { 1500 struct amdgpu_ring *ring; 1501 int r, i; 1502 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1503 1504 /* SDMA trap event */ 1505 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0, SDMA0_4_0__SRCID__SDMA_TRAP, 1506 &adev->sdma.trap_irq); 1507 if (r) 1508 return r; 1509 1510 /* SDMA trap event */ 1511 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1, SDMA1_4_0__SRCID__SDMA_TRAP, 1512 &adev->sdma.trap_irq); 1513 if (r) 1514 return r; 1515 1516 for (i = 0; i < adev->sdma.num_instances; i++) { 1517 ring = &adev->sdma.instance[i].ring; 1518 ring->ring_obj = NULL; 1519 ring->use_doorbell = true; 1520 1521 DRM_INFO("use_doorbell being set to: [%s]\n", 1522 ring->use_doorbell?"true":"false"); 1523 1524 /* doorbell size is 2 dwords, get DWORD offset */ 1525 ring->doorbell_index = (i == 0) ? 1526 (adev->doorbell_index.sdma_engine0 << 1) 1527 : (adev->doorbell_index.sdma_engine1 << 1); 1528 1529 sprintf(ring->name, "sdma%d", i); 1530 r = amdgpu_ring_init(adev, ring, 1024, 1531 &adev->sdma.trap_irq, 1532 (i == 0) ? 1533 AMDGPU_SDMA_IRQ_TRAP0 : 1534 AMDGPU_SDMA_IRQ_TRAP1); 1535 if (r) 1536 return r; 1537 1538 if (adev->sdma.has_page_queue) { 1539 ring = &adev->sdma.instance[i].page; 1540 ring->ring_obj = NULL; 1541 ring->use_doorbell = true; 1542 1543 /* paging queue use same doorbell index/routing as gfx queue 1544 * with 0x400 (4096 dwords) offset on second doorbell page 1545 */ 1546 ring->doorbell_index = (i == 0) ? 1547 (adev->doorbell_index.sdma_engine0 << 1) 1548 : (adev->doorbell_index.sdma_engine1 << 1); 1549 ring->doorbell_index += 0x400; 1550 1551 sprintf(ring->name, "page%d", i); 1552 r = amdgpu_ring_init(adev, ring, 1024, 1553 &adev->sdma.trap_irq, 1554 (i == 0) ? 1555 AMDGPU_SDMA_IRQ_TRAP0 : 1556 AMDGPU_SDMA_IRQ_TRAP1); 1557 if (r) 1558 return r; 1559 } 1560 } 1561 1562 return r; 1563 } 1564 1565 static int sdma_v4_0_sw_fini(void *handle) 1566 { 1567 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1568 int i; 1569 1570 for (i = 0; i < adev->sdma.num_instances; i++) { 1571 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1572 if (adev->sdma.has_page_queue) 1573 amdgpu_ring_fini(&adev->sdma.instance[i].page); 1574 } 1575 1576 for (i = 0; i < adev->sdma.num_instances; i++) { 1577 release_firmware(adev->sdma.instance[i].fw); 1578 adev->sdma.instance[i].fw = NULL; 1579 } 1580 1581 return 0; 1582 } 1583 1584 static int sdma_v4_0_hw_init(void *handle) 1585 { 1586 int r; 1587 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1588 1589 if (adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs && 1590 adev->powerplay.pp_funcs->set_powergating_by_smu) 1591 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false); 1592 1593 sdma_v4_0_init_golden_registers(adev); 1594 1595 r = sdma_v4_0_start(adev); 1596 1597 return r; 1598 } 1599 1600 static int sdma_v4_0_hw_fini(void *handle) 1601 { 1602 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1603 1604 if (amdgpu_sriov_vf(adev)) 1605 return 0; 1606 1607 sdma_v4_0_ctx_switch_enable(adev, false); 1608 sdma_v4_0_enable(adev, false); 1609 1610 if (adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs 1611 && adev->powerplay.pp_funcs->set_powergating_by_smu) 1612 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true); 1613 1614 return 0; 1615 } 1616 1617 static int sdma_v4_0_suspend(void *handle) 1618 { 1619 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1620 1621 return sdma_v4_0_hw_fini(adev); 1622 } 1623 1624 static int sdma_v4_0_resume(void *handle) 1625 { 1626 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1627 1628 return sdma_v4_0_hw_init(adev); 1629 } 1630 1631 static bool sdma_v4_0_is_idle(void *handle) 1632 { 1633 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1634 u32 i; 1635 1636 for (i = 0; i < adev->sdma.num_instances; i++) { 1637 u32 tmp = RREG32_SDMA(i, mmSDMA0_STATUS_REG); 1638 1639 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1640 return false; 1641 } 1642 1643 return true; 1644 } 1645 1646 static int sdma_v4_0_wait_for_idle(void *handle) 1647 { 1648 unsigned i; 1649 u32 sdma0, sdma1; 1650 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1651 1652 for (i = 0; i < adev->usec_timeout; i++) { 1653 sdma0 = RREG32_SDMA(0, mmSDMA0_STATUS_REG); 1654 sdma1 = RREG32_SDMA(1, mmSDMA0_STATUS_REG); 1655 1656 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK) 1657 return 0; 1658 udelay(1); 1659 } 1660 return -ETIMEDOUT; 1661 } 1662 1663 static int sdma_v4_0_soft_reset(void *handle) 1664 { 1665 /* todo */ 1666 1667 return 0; 1668 } 1669 1670 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev, 1671 struct amdgpu_irq_src *source, 1672 unsigned type, 1673 enum amdgpu_interrupt_state state) 1674 { 1675 unsigned int instance = (type == AMDGPU_SDMA_IRQ_TRAP0) ? 0 : 1; 1676 u32 sdma_cntl; 1677 1678 sdma_cntl = RREG32_SDMA(instance, mmSDMA0_CNTL); 1679 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1680 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1681 WREG32_SDMA(instance, mmSDMA0_CNTL, sdma_cntl); 1682 1683 return 0; 1684 } 1685 1686 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev, 1687 struct amdgpu_irq_src *source, 1688 struct amdgpu_iv_entry *entry) 1689 { 1690 uint32_t instance; 1691 1692 DRM_DEBUG("IH: SDMA trap\n"); 1693 switch (entry->client_id) { 1694 case SOC15_IH_CLIENTID_SDMA0: 1695 instance = 0; 1696 break; 1697 case SOC15_IH_CLIENTID_SDMA1: 1698 instance = 1; 1699 break; 1700 default: 1701 return 0; 1702 } 1703 1704 switch (entry->ring_id) { 1705 case 0: 1706 amdgpu_fence_process(&adev->sdma.instance[instance].ring); 1707 break; 1708 case 1: 1709 /* XXX compute */ 1710 break; 1711 case 2: 1712 /* XXX compute */ 1713 break; 1714 case 3: 1715 amdgpu_fence_process(&adev->sdma.instance[instance].page); 1716 break; 1717 } 1718 return 0; 1719 } 1720 1721 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1722 struct amdgpu_irq_src *source, 1723 struct amdgpu_iv_entry *entry) 1724 { 1725 int instance; 1726 1727 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1728 1729 switch (entry->client_id) { 1730 case SOC15_IH_CLIENTID_SDMA0: 1731 instance = 0; 1732 break; 1733 case SOC15_IH_CLIENTID_SDMA1: 1734 instance = 1; 1735 break; 1736 default: 1737 return 0; 1738 } 1739 1740 switch (entry->ring_id) { 1741 case 0: 1742 drm_sched_fault(&adev->sdma.instance[instance].ring.sched); 1743 break; 1744 } 1745 return 0; 1746 } 1747 1748 static void sdma_v4_0_update_medium_grain_clock_gating( 1749 struct amdgpu_device *adev, 1750 bool enable) 1751 { 1752 uint32_t data, def; 1753 1754 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1755 /* enable sdma0 clock gating */ 1756 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 1757 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1758 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1759 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1760 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1761 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1762 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1763 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1764 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1765 if (def != data) 1766 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data); 1767 1768 if (adev->sdma.num_instances > 1) { 1769 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL)); 1770 data &= ~(SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1771 SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1772 SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1773 SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1774 SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1775 SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1776 SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1777 SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1778 if (def != data) 1779 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data); 1780 } 1781 } else { 1782 /* disable sdma0 clock gating */ 1783 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 1784 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1785 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1786 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1787 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1788 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1789 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1790 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1791 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1792 1793 if (def != data) 1794 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data); 1795 1796 if (adev->sdma.num_instances > 1) { 1797 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL)); 1798 data |= (SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1799 SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1800 SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1801 SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1802 SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1803 SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1804 SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1805 SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1806 if (def != data) 1807 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data); 1808 } 1809 } 1810 } 1811 1812 1813 static void sdma_v4_0_update_medium_grain_light_sleep( 1814 struct amdgpu_device *adev, 1815 bool enable) 1816 { 1817 uint32_t data, def; 1818 1819 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1820 /* 1-not override: enable sdma0 mem light sleep */ 1821 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1822 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1823 if (def != data) 1824 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1825 1826 /* 1-not override: enable sdma1 mem light sleep */ 1827 if (adev->sdma.num_instances > 1) { 1828 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL)); 1829 data |= SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1830 if (def != data) 1831 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data); 1832 } 1833 } else { 1834 /* 0-override:disable sdma0 mem light sleep */ 1835 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1836 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1837 if (def != data) 1838 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1839 1840 /* 0-override:disable sdma1 mem light sleep */ 1841 if (adev->sdma.num_instances > 1) { 1842 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL)); 1843 data &= ~SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1844 if (def != data) 1845 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data); 1846 } 1847 } 1848 } 1849 1850 static int sdma_v4_0_set_clockgating_state(void *handle, 1851 enum amd_clockgating_state state) 1852 { 1853 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1854 1855 if (amdgpu_sriov_vf(adev)) 1856 return 0; 1857 1858 switch (adev->asic_type) { 1859 case CHIP_VEGA10: 1860 case CHIP_VEGA12: 1861 case CHIP_VEGA20: 1862 case CHIP_RAVEN: 1863 sdma_v4_0_update_medium_grain_clock_gating(adev, 1864 state == AMD_CG_STATE_GATE ? true : false); 1865 sdma_v4_0_update_medium_grain_light_sleep(adev, 1866 state == AMD_CG_STATE_GATE ? true : false); 1867 break; 1868 default: 1869 break; 1870 } 1871 return 0; 1872 } 1873 1874 static int sdma_v4_0_set_powergating_state(void *handle, 1875 enum amd_powergating_state state) 1876 { 1877 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1878 1879 switch (adev->asic_type) { 1880 case CHIP_RAVEN: 1881 sdma_v4_1_update_power_gating(adev, 1882 state == AMD_PG_STATE_GATE ? true : false); 1883 break; 1884 default: 1885 break; 1886 } 1887 1888 return 0; 1889 } 1890 1891 static void sdma_v4_0_get_clockgating_state(void *handle, u32 *flags) 1892 { 1893 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1894 int data; 1895 1896 if (amdgpu_sriov_vf(adev)) 1897 *flags = 0; 1898 1899 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1900 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 1901 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK)) 1902 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1903 1904 /* AMD_CG_SUPPORT_SDMA_LS */ 1905 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1906 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1907 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1908 } 1909 1910 const struct amd_ip_funcs sdma_v4_0_ip_funcs = { 1911 .name = "sdma_v4_0", 1912 .early_init = sdma_v4_0_early_init, 1913 .late_init = NULL, 1914 .sw_init = sdma_v4_0_sw_init, 1915 .sw_fini = sdma_v4_0_sw_fini, 1916 .hw_init = sdma_v4_0_hw_init, 1917 .hw_fini = sdma_v4_0_hw_fini, 1918 .suspend = sdma_v4_0_suspend, 1919 .resume = sdma_v4_0_resume, 1920 .is_idle = sdma_v4_0_is_idle, 1921 .wait_for_idle = sdma_v4_0_wait_for_idle, 1922 .soft_reset = sdma_v4_0_soft_reset, 1923 .set_clockgating_state = sdma_v4_0_set_clockgating_state, 1924 .set_powergating_state = sdma_v4_0_set_powergating_state, 1925 .get_clockgating_state = sdma_v4_0_get_clockgating_state, 1926 }; 1927 1928 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = { 1929 .type = AMDGPU_RING_TYPE_SDMA, 1930 .align_mask = 0xf, 1931 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1932 .support_64bit_ptrs = true, 1933 .vmhub = AMDGPU_MMHUB, 1934 .get_rptr = sdma_v4_0_ring_get_rptr, 1935 .get_wptr = sdma_v4_0_ring_get_wptr, 1936 .set_wptr = sdma_v4_0_ring_set_wptr, 1937 .emit_frame_size = 1938 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 1939 3 + /* hdp invalidate */ 1940 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 1941 /* sdma_v4_0_ring_emit_vm_flush */ 1942 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1943 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1944 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 1945 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 1946 .emit_ib = sdma_v4_0_ring_emit_ib, 1947 .emit_fence = sdma_v4_0_ring_emit_fence, 1948 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 1949 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 1950 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 1951 .test_ring = sdma_v4_0_ring_test_ring, 1952 .test_ib = sdma_v4_0_ring_test_ib, 1953 .insert_nop = sdma_v4_0_ring_insert_nop, 1954 .pad_ib = sdma_v4_0_ring_pad_ib, 1955 .emit_wreg = sdma_v4_0_ring_emit_wreg, 1956 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 1957 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1958 }; 1959 1960 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = { 1961 .type = AMDGPU_RING_TYPE_SDMA, 1962 .align_mask = 0xf, 1963 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1964 .support_64bit_ptrs = true, 1965 .vmhub = AMDGPU_MMHUB, 1966 .get_rptr = sdma_v4_0_ring_get_rptr, 1967 .get_wptr = sdma_v4_0_page_ring_get_wptr, 1968 .set_wptr = sdma_v4_0_page_ring_set_wptr, 1969 .emit_frame_size = 1970 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 1971 3 + /* hdp invalidate */ 1972 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 1973 /* sdma_v4_0_ring_emit_vm_flush */ 1974 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1975 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1976 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 1977 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 1978 .emit_ib = sdma_v4_0_ring_emit_ib, 1979 .emit_fence = sdma_v4_0_ring_emit_fence, 1980 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 1981 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 1982 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 1983 .test_ring = sdma_v4_0_ring_test_ring, 1984 .test_ib = sdma_v4_0_ring_test_ib, 1985 .insert_nop = sdma_v4_0_ring_insert_nop, 1986 .pad_ib = sdma_v4_0_ring_pad_ib, 1987 .emit_wreg = sdma_v4_0_ring_emit_wreg, 1988 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 1989 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1990 }; 1991 1992 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev) 1993 { 1994 int i; 1995 1996 for (i = 0; i < adev->sdma.num_instances; i++) { 1997 adev->sdma.instance[i].ring.funcs = &sdma_v4_0_ring_funcs; 1998 adev->sdma.instance[i].ring.me = i; 1999 if (adev->sdma.has_page_queue) { 2000 adev->sdma.instance[i].page.funcs = &sdma_v4_0_page_ring_funcs; 2001 adev->sdma.instance[i].page.me = i; 2002 } 2003 } 2004 } 2005 2006 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = { 2007 .set = sdma_v4_0_set_trap_irq_state, 2008 .process = sdma_v4_0_process_trap_irq, 2009 }; 2010 2011 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = { 2012 .process = sdma_v4_0_process_illegal_inst_irq, 2013 }; 2014 2015 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev) 2016 { 2017 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 2018 adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs; 2019 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs; 2020 } 2021 2022 /** 2023 * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine 2024 * 2025 * @ring: amdgpu_ring structure holding ring information 2026 * @src_offset: src GPU address 2027 * @dst_offset: dst GPU address 2028 * @byte_count: number of bytes to xfer 2029 * 2030 * Copy GPU buffers using the DMA engine (VEGA10/12). 2031 * Used by the amdgpu ttm implementation to move pages if 2032 * registered as the asic copy callback. 2033 */ 2034 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib, 2035 uint64_t src_offset, 2036 uint64_t dst_offset, 2037 uint32_t byte_count) 2038 { 2039 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 2040 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 2041 ib->ptr[ib->length_dw++] = byte_count - 1; 2042 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 2043 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 2044 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 2045 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2046 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2047 } 2048 2049 /** 2050 * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine 2051 * 2052 * @ring: amdgpu_ring structure holding ring information 2053 * @src_data: value to write to buffer 2054 * @dst_offset: dst GPU address 2055 * @byte_count: number of bytes to xfer 2056 * 2057 * Fill GPU buffers using the DMA engine (VEGA10/12). 2058 */ 2059 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib, 2060 uint32_t src_data, 2061 uint64_t dst_offset, 2062 uint32_t byte_count) 2063 { 2064 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 2065 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2066 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2067 ib->ptr[ib->length_dw++] = src_data; 2068 ib->ptr[ib->length_dw++] = byte_count - 1; 2069 } 2070 2071 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = { 2072 .copy_max_bytes = 0x400000, 2073 .copy_num_dw = 7, 2074 .emit_copy_buffer = sdma_v4_0_emit_copy_buffer, 2075 2076 .fill_max_bytes = 0x400000, 2077 .fill_num_dw = 5, 2078 .emit_fill_buffer = sdma_v4_0_emit_fill_buffer, 2079 }; 2080 2081 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev) 2082 { 2083 adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs; 2084 if (adev->sdma.has_page_queue) 2085 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page; 2086 else 2087 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 2088 } 2089 2090 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = { 2091 .copy_pte_num_dw = 7, 2092 .copy_pte = sdma_v4_0_vm_copy_pte, 2093 2094 .write_pte = sdma_v4_0_vm_write_pte, 2095 .set_pte_pde = sdma_v4_0_vm_set_pte_pde, 2096 }; 2097 2098 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev) 2099 { 2100 struct drm_gpu_scheduler *sched; 2101 unsigned i; 2102 2103 adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs; 2104 for (i = 0; i < adev->sdma.num_instances; i++) { 2105 if (adev->sdma.has_page_queue) 2106 sched = &adev->sdma.instance[i].page.sched; 2107 else 2108 sched = &adev->sdma.instance[i].ring.sched; 2109 adev->vm_manager.vm_pte_rqs[i] = 2110 &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL]; 2111 } 2112 adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances; 2113 } 2114 2115 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = { 2116 .type = AMD_IP_BLOCK_TYPE_SDMA, 2117 .major = 4, 2118 .minor = 0, 2119 .rev = 0, 2120 .funcs = &sdma_v4_0_ip_funcs, 2121 }; 2122