1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_ucode.h" 28 #include "amdgpu_trace.h" 29 30 #include "sdma0/sdma0_4_2_offset.h" 31 #include "sdma0/sdma0_4_2_sh_mask.h" 32 #include "sdma1/sdma1_4_2_offset.h" 33 #include "sdma1/sdma1_4_2_sh_mask.h" 34 #include "hdp/hdp_4_0_offset.h" 35 #include "sdma0/sdma0_4_1_default.h" 36 37 #include "soc15_common.h" 38 #include "soc15.h" 39 #include "vega10_sdma_pkt_open.h" 40 41 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h" 42 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h" 43 44 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin"); 45 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin"); 46 MODULE_FIRMWARE("amdgpu/vega12_sdma.bin"); 47 MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin"); 48 MODULE_FIRMWARE("amdgpu/vega20_sdma.bin"); 49 MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin"); 50 MODULE_FIRMWARE("amdgpu/raven_sdma.bin"); 51 MODULE_FIRMWARE("amdgpu/picasso_sdma.bin"); 52 MODULE_FIRMWARE("amdgpu/raven2_sdma.bin"); 53 54 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L 55 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L 56 57 #define WREG32_SDMA(instance, offset, value) \ 58 WREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)), value) 59 #define RREG32_SDMA(instance, offset) \ 60 RREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset))) 61 62 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev); 63 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev); 64 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev); 65 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev); 66 67 static const struct soc15_reg_golden golden_settings_sdma_4[] = { 68 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 69 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100), 70 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100), 71 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 72 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 73 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 74 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000), 75 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 76 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 77 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 78 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 79 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 80 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000), 81 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), 82 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100), 83 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 84 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 85 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 86 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000), 87 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 88 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 89 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 90 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 91 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0), 92 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xfc000000, 0x00000000) 93 }; 94 95 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = { 96 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 97 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 98 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 99 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 100 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002) 101 }; 102 103 static const struct soc15_reg_golden golden_settings_sdma_vg12[] = { 104 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), 105 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001), 106 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 107 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), 108 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001) 109 }; 110 111 static const struct soc15_reg_golden golden_settings_sdma_4_1[] = { 112 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 113 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 114 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100), 115 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 116 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051), 117 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100), 118 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 119 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100), 120 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 121 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 122 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000) 123 }; 124 125 static const struct soc15_reg_golden golden_settings_sdma0_4_2_init[] = { 126 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 127 }; 128 129 static const struct soc15_reg_golden golden_settings_sdma0_4_2[] = 130 { 131 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 132 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 133 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 134 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 135 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 136 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 137 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 138 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 139 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RD_BURST_CNTL, 0x0000000f, 0x00000003), 140 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 141 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 142 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 143 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 144 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 145 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 146 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 147 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 148 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 149 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 150 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 151 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 152 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 153 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 154 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 155 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 156 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 157 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xFE000000, 0x00000000), 158 }; 159 160 static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = { 161 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 162 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), 163 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 164 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 165 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 166 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 167 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 168 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 169 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RD_BURST_CNTL, 0x0000000f, 0x00000003), 170 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 171 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 172 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 173 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 174 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 175 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 176 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 177 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 178 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 179 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 180 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 181 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 182 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 183 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 184 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 185 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 186 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0), 187 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xFE000000, 0x00000000), 188 }; 189 190 static const struct soc15_reg_golden golden_settings_sdma_rv1[] = 191 { 192 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002), 193 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002) 194 }; 195 196 static const struct soc15_reg_golden golden_settings_sdma_rv2[] = 197 { 198 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00003001), 199 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003001) 200 }; 201 202 static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev, 203 u32 instance, u32 offset) 204 { 205 return ( 0 == instance ? (adev->reg_offset[SDMA0_HWIP][0][0] + offset) : 206 (adev->reg_offset[SDMA1_HWIP][0][0] + offset)); 207 } 208 209 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) 210 { 211 switch (adev->asic_type) { 212 case CHIP_VEGA10: 213 soc15_program_register_sequence(adev, 214 golden_settings_sdma_4, 215 ARRAY_SIZE(golden_settings_sdma_4)); 216 soc15_program_register_sequence(adev, 217 golden_settings_sdma_vg10, 218 ARRAY_SIZE(golden_settings_sdma_vg10)); 219 break; 220 case CHIP_VEGA12: 221 soc15_program_register_sequence(adev, 222 golden_settings_sdma_4, 223 ARRAY_SIZE(golden_settings_sdma_4)); 224 soc15_program_register_sequence(adev, 225 golden_settings_sdma_vg12, 226 ARRAY_SIZE(golden_settings_sdma_vg12)); 227 break; 228 case CHIP_VEGA20: 229 soc15_program_register_sequence(adev, 230 golden_settings_sdma0_4_2_init, 231 ARRAY_SIZE(golden_settings_sdma0_4_2_init)); 232 soc15_program_register_sequence(adev, 233 golden_settings_sdma0_4_2, 234 ARRAY_SIZE(golden_settings_sdma0_4_2)); 235 soc15_program_register_sequence(adev, 236 golden_settings_sdma1_4_2, 237 ARRAY_SIZE(golden_settings_sdma1_4_2)); 238 break; 239 case CHIP_RAVEN: 240 soc15_program_register_sequence(adev, 241 golden_settings_sdma_4_1, 242 ARRAY_SIZE(golden_settings_sdma_4_1)); 243 if (adev->rev_id >= 8) 244 soc15_program_register_sequence(adev, 245 golden_settings_sdma_rv2, 246 ARRAY_SIZE(golden_settings_sdma_rv2)); 247 else 248 soc15_program_register_sequence(adev, 249 golden_settings_sdma_rv1, 250 ARRAY_SIZE(golden_settings_sdma_rv1)); 251 break; 252 default: 253 break; 254 } 255 } 256 257 /** 258 * sdma_v4_0_init_microcode - load ucode images from disk 259 * 260 * @adev: amdgpu_device pointer 261 * 262 * Use the firmware interface to load the ucode images into 263 * the driver (not loaded into hw). 264 * Returns 0 on success, error on failure. 265 */ 266 267 // emulation only, won't work on real chip 268 // vega10 real chip need to use PSP to load firmware 269 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev) 270 { 271 const char *chip_name; 272 char fw_name[30]; 273 int err = 0, i; 274 struct amdgpu_firmware_info *info = NULL; 275 const struct common_firmware_header *header = NULL; 276 const struct sdma_firmware_header_v1_0 *hdr; 277 278 DRM_DEBUG("\n"); 279 280 switch (adev->asic_type) { 281 case CHIP_VEGA10: 282 chip_name = "vega10"; 283 break; 284 case CHIP_VEGA12: 285 chip_name = "vega12"; 286 break; 287 case CHIP_VEGA20: 288 chip_name = "vega20"; 289 break; 290 case CHIP_RAVEN: 291 if (adev->rev_id >= 8) 292 chip_name = "raven2"; 293 else if (adev->pdev->device == 0x15d8) 294 chip_name = "picasso"; 295 else 296 chip_name = "raven"; 297 break; 298 default: 299 BUG(); 300 } 301 302 for (i = 0; i < adev->sdma.num_instances; i++) { 303 if (i == 0) 304 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 305 else 306 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); 307 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 308 if (err) 309 goto out; 310 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); 311 if (err) 312 goto out; 313 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 314 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 315 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 316 if (adev->sdma.instance[i].feature_version >= 20) 317 adev->sdma.instance[i].burst_nop = true; 318 DRM_DEBUG("psp_load == '%s'\n", 319 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); 320 321 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 322 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 323 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 324 info->fw = adev->sdma.instance[i].fw; 325 header = (const struct common_firmware_header *)info->fw->data; 326 adev->firmware.fw_size += 327 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 328 } 329 } 330 out: 331 if (err) { 332 DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name); 333 for (i = 0; i < adev->sdma.num_instances; i++) { 334 release_firmware(adev->sdma.instance[i].fw); 335 adev->sdma.instance[i].fw = NULL; 336 } 337 } 338 return err; 339 } 340 341 /** 342 * sdma_v4_0_ring_get_rptr - get the current read pointer 343 * 344 * @ring: amdgpu ring pointer 345 * 346 * Get the current rptr from the hardware (VEGA10+). 347 */ 348 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring) 349 { 350 u64 *rptr; 351 352 /* XXX check if swapping is necessary on BE */ 353 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]); 354 355 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 356 return ((*rptr) >> 2); 357 } 358 359 /** 360 * sdma_v4_0_ring_get_wptr - get the current write pointer 361 * 362 * @ring: amdgpu ring pointer 363 * 364 * Get the current wptr from the hardware (VEGA10+). 365 */ 366 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring) 367 { 368 struct amdgpu_device *adev = ring->adev; 369 u64 wptr; 370 371 if (ring->use_doorbell) { 372 /* XXX check if swapping is necessary on BE */ 373 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 374 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 375 } else { 376 wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI); 377 wptr = wptr << 32; 378 wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR); 379 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", 380 ring->me, wptr); 381 } 382 383 return wptr >> 2; 384 } 385 386 /** 387 * sdma_v4_0_ring_set_wptr - commit the write pointer 388 * 389 * @ring: amdgpu ring pointer 390 * 391 * Write the wptr back to the hardware (VEGA10+). 392 */ 393 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring) 394 { 395 struct amdgpu_device *adev = ring->adev; 396 397 DRM_DEBUG("Setting write pointer\n"); 398 if (ring->use_doorbell) { 399 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 400 401 DRM_DEBUG("Using doorbell -- " 402 "wptr_offs == 0x%08x " 403 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 404 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 405 ring->wptr_offs, 406 lower_32_bits(ring->wptr << 2), 407 upper_32_bits(ring->wptr << 2)); 408 /* XXX check if swapping is necessary on BE */ 409 WRITE_ONCE(*wb, (ring->wptr << 2)); 410 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 411 ring->doorbell_index, ring->wptr << 2); 412 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 413 } else { 414 DRM_DEBUG("Not using doorbell -- " 415 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 416 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 417 ring->me, 418 lower_32_bits(ring->wptr << 2), 419 ring->me, 420 upper_32_bits(ring->wptr << 2)); 421 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR, 422 lower_32_bits(ring->wptr << 2)); 423 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI, 424 upper_32_bits(ring->wptr << 2)); 425 } 426 } 427 428 /** 429 * sdma_v4_0_page_ring_get_wptr - get the current write pointer 430 * 431 * @ring: amdgpu ring pointer 432 * 433 * Get the current wptr from the hardware (VEGA10+). 434 */ 435 static uint64_t sdma_v4_0_page_ring_get_wptr(struct amdgpu_ring *ring) 436 { 437 struct amdgpu_device *adev = ring->adev; 438 u64 wptr; 439 440 if (ring->use_doorbell) { 441 /* XXX check if swapping is necessary on BE */ 442 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 443 } else { 444 wptr = RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI); 445 wptr = wptr << 32; 446 wptr |= RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR); 447 } 448 449 return wptr >> 2; 450 } 451 452 /** 453 * sdma_v4_0_ring_set_wptr - commit the write pointer 454 * 455 * @ring: amdgpu ring pointer 456 * 457 * Write the wptr back to the hardware (VEGA10+). 458 */ 459 static void sdma_v4_0_page_ring_set_wptr(struct amdgpu_ring *ring) 460 { 461 struct amdgpu_device *adev = ring->adev; 462 463 if (ring->use_doorbell) { 464 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 465 466 /* XXX check if swapping is necessary on BE */ 467 WRITE_ONCE(*wb, (ring->wptr << 2)); 468 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 469 } else { 470 uint64_t wptr = ring->wptr << 2; 471 472 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR, 473 lower_32_bits(wptr)); 474 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI, 475 upper_32_bits(wptr)); 476 } 477 } 478 479 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 480 { 481 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 482 int i; 483 484 for (i = 0; i < count; i++) 485 if (sdma && sdma->burst_nop && (i == 0)) 486 amdgpu_ring_write(ring, ring->funcs->nop | 487 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 488 else 489 amdgpu_ring_write(ring, ring->funcs->nop); 490 } 491 492 /** 493 * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine 494 * 495 * @ring: amdgpu ring pointer 496 * @ib: IB object to schedule 497 * 498 * Schedule an IB in the DMA ring (VEGA10). 499 */ 500 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring, 501 struct amdgpu_job *job, 502 struct amdgpu_ib *ib, 503 bool ctx_switch) 504 { 505 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 506 507 /* IB packet must end on a 8 DW boundary */ 508 sdma_v4_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8); 509 510 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 511 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 512 /* base must be 32 byte aligned */ 513 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 514 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 515 amdgpu_ring_write(ring, ib->length_dw); 516 amdgpu_ring_write(ring, 0); 517 amdgpu_ring_write(ring, 0); 518 519 } 520 521 static void sdma_v4_0_wait_reg_mem(struct amdgpu_ring *ring, 522 int mem_space, int hdp, 523 uint32_t addr0, uint32_t addr1, 524 uint32_t ref, uint32_t mask, 525 uint32_t inv) 526 { 527 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 528 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) | 529 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) | 530 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 531 if (mem_space) { 532 /* memory */ 533 amdgpu_ring_write(ring, addr0); 534 amdgpu_ring_write(ring, addr1); 535 } else { 536 /* registers */ 537 amdgpu_ring_write(ring, addr0 << 2); 538 amdgpu_ring_write(ring, addr1 << 2); 539 } 540 amdgpu_ring_write(ring, ref); /* reference */ 541 amdgpu_ring_write(ring, mask); /* mask */ 542 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 543 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */ 544 } 545 546 /** 547 * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 548 * 549 * @ring: amdgpu ring pointer 550 * 551 * Emit an hdp flush packet on the requested DMA ring. 552 */ 553 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 554 { 555 struct amdgpu_device *adev = ring->adev; 556 u32 ref_and_mask = 0; 557 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg; 558 559 if (ring->me == 0) 560 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0; 561 else 562 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1; 563 564 sdma_v4_0_wait_reg_mem(ring, 0, 1, 565 adev->nbio_funcs->get_hdp_flush_done_offset(adev), 566 adev->nbio_funcs->get_hdp_flush_req_offset(adev), 567 ref_and_mask, ref_and_mask, 10); 568 } 569 570 /** 571 * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring 572 * 573 * @ring: amdgpu ring pointer 574 * @fence: amdgpu fence object 575 * 576 * Add a DMA fence packet to the ring to write 577 * the fence seq number and DMA trap packet to generate 578 * an interrupt if needed (VEGA10). 579 */ 580 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 581 unsigned flags) 582 { 583 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 584 /* write the fence */ 585 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 586 /* zero in first two bits */ 587 BUG_ON(addr & 0x3); 588 amdgpu_ring_write(ring, lower_32_bits(addr)); 589 amdgpu_ring_write(ring, upper_32_bits(addr)); 590 amdgpu_ring_write(ring, lower_32_bits(seq)); 591 592 /* optionally write high bits as well */ 593 if (write64bit) { 594 addr += 4; 595 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 596 /* zero in first two bits */ 597 BUG_ON(addr & 0x3); 598 amdgpu_ring_write(ring, lower_32_bits(addr)); 599 amdgpu_ring_write(ring, upper_32_bits(addr)); 600 amdgpu_ring_write(ring, upper_32_bits(seq)); 601 } 602 603 /* generate an interrupt */ 604 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 605 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 606 } 607 608 609 /** 610 * sdma_v4_0_gfx_stop - stop the gfx async dma engines 611 * 612 * @adev: amdgpu_device pointer 613 * 614 * Stop the gfx async dma ring buffers (VEGA10). 615 */ 616 static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev) 617 { 618 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 619 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 620 u32 rb_cntl, ib_cntl; 621 int i; 622 623 if ((adev->mman.buffer_funcs_ring == sdma0) || 624 (adev->mman.buffer_funcs_ring == sdma1)) 625 amdgpu_ttm_set_buffer_funcs_status(adev, false); 626 627 for (i = 0; i < adev->sdma.num_instances; i++) { 628 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL); 629 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 630 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 631 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL); 632 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 633 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl); 634 } 635 636 sdma0->sched.ready = false; 637 sdma1->sched.ready = false; 638 } 639 640 /** 641 * sdma_v4_0_rlc_stop - stop the compute async dma engines 642 * 643 * @adev: amdgpu_device pointer 644 * 645 * Stop the compute async dma queues (VEGA10). 646 */ 647 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev) 648 { 649 /* XXX todo */ 650 } 651 652 /** 653 * sdma_v4_0_page_stop - stop the page async dma engines 654 * 655 * @adev: amdgpu_device pointer 656 * 657 * Stop the page async dma ring buffers (VEGA10). 658 */ 659 static void sdma_v4_0_page_stop(struct amdgpu_device *adev) 660 { 661 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].page; 662 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].page; 663 u32 rb_cntl, ib_cntl; 664 int i; 665 666 if ((adev->mman.buffer_funcs_ring == sdma0) || 667 (adev->mman.buffer_funcs_ring == sdma1)) 668 amdgpu_ttm_set_buffer_funcs_status(adev, false); 669 670 for (i = 0; i < adev->sdma.num_instances; i++) { 671 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL); 672 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, 673 RB_ENABLE, 0); 674 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 675 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL); 676 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, 677 IB_ENABLE, 0); 678 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl); 679 } 680 681 sdma0->sched.ready = false; 682 sdma1->sched.ready = false; 683 } 684 685 /** 686 * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch 687 * 688 * @adev: amdgpu_device pointer 689 * @enable: enable/disable the DMA MEs context switch. 690 * 691 * Halt or unhalt the async dma engines context switch (VEGA10). 692 */ 693 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 694 { 695 u32 f32_cntl, phase_quantum = 0; 696 int i; 697 698 if (amdgpu_sdma_phase_quantum) { 699 unsigned value = amdgpu_sdma_phase_quantum; 700 unsigned unit = 0; 701 702 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 703 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 704 value = (value + 1) >> 1; 705 unit++; 706 } 707 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 708 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 709 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 710 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 711 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 712 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 713 WARN_ONCE(1, 714 "clamping sdma_phase_quantum to %uK clock cycles\n", 715 value << unit); 716 } 717 phase_quantum = 718 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 719 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 720 } 721 722 for (i = 0; i < adev->sdma.num_instances; i++) { 723 f32_cntl = RREG32_SDMA(i, mmSDMA0_CNTL); 724 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 725 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 726 if (enable && amdgpu_sdma_phase_quantum) { 727 WREG32_SDMA(i, mmSDMA0_PHASE0_QUANTUM, phase_quantum); 728 WREG32_SDMA(i, mmSDMA0_PHASE1_QUANTUM, phase_quantum); 729 WREG32_SDMA(i, mmSDMA0_PHASE2_QUANTUM, phase_quantum); 730 } 731 WREG32_SDMA(i, mmSDMA0_CNTL, f32_cntl); 732 } 733 734 } 735 736 /** 737 * sdma_v4_0_enable - stop the async dma engines 738 * 739 * @adev: amdgpu_device pointer 740 * @enable: enable/disable the DMA MEs. 741 * 742 * Halt or unhalt the async dma engines (VEGA10). 743 */ 744 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable) 745 { 746 u32 f32_cntl; 747 int i; 748 749 if (enable == false) { 750 sdma_v4_0_gfx_stop(adev); 751 sdma_v4_0_rlc_stop(adev); 752 if (adev->sdma.has_page_queue) 753 sdma_v4_0_page_stop(adev); 754 } 755 756 for (i = 0; i < adev->sdma.num_instances; i++) { 757 f32_cntl = RREG32_SDMA(i, mmSDMA0_F32_CNTL); 758 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 759 WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl); 760 } 761 } 762 763 /** 764 * sdma_v4_0_rb_cntl - get parameters for rb_cntl 765 */ 766 static uint32_t sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl) 767 { 768 /* Set ring buffer size in dwords */ 769 uint32_t rb_bufsz = order_base_2(ring->ring_size / 4); 770 771 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 772 #ifdef __BIG_ENDIAN 773 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 774 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 775 RPTR_WRITEBACK_SWAP_ENABLE, 1); 776 #endif 777 return rb_cntl; 778 } 779 780 /** 781 * sdma_v4_0_gfx_resume - setup and start the async dma engines 782 * 783 * @adev: amdgpu_device pointer 784 * @i: instance to resume 785 * 786 * Set up the gfx DMA ring buffers and enable them (VEGA10). 787 * Returns 0 for success, error for failure. 788 */ 789 static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i) 790 { 791 struct amdgpu_ring *ring = &adev->sdma.instance[i].ring; 792 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 793 u32 wb_offset; 794 u32 doorbell; 795 u32 doorbell_offset; 796 u64 wptr_gpu_addr; 797 798 wb_offset = (ring->rptr_offs * 4); 799 800 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL); 801 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl); 802 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 803 804 /* Initialize the ring buffer's read and write pointers */ 805 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR, 0); 806 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_HI, 0); 807 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR, 0); 808 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_HI, 0); 809 810 /* set the wb address whether it's enabled or not */ 811 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI, 812 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 813 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 814 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 815 816 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 817 RPTR_WRITEBACK_ENABLE, 1); 818 819 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE, ring->gpu_addr >> 8); 820 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE_HI, ring->gpu_addr >> 40); 821 822 ring->wptr = 0; 823 824 /* before programing wptr to a less value, need set minor_ptr_update first */ 825 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 1); 826 827 doorbell = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL); 828 doorbell_offset = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET); 829 830 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 831 ring->use_doorbell); 832 doorbell_offset = REG_SET_FIELD(doorbell_offset, 833 SDMA0_GFX_DOORBELL_OFFSET, 834 OFFSET, ring->doorbell_index); 835 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL, doorbell); 836 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET, doorbell_offset); 837 adev->nbio_funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 838 ring->doorbell_index); 839 840 sdma_v4_0_ring_set_wptr(ring); 841 842 /* set minor_ptr_update to 0 after wptr programed */ 843 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 0); 844 845 /* setup the wptr shadow polling */ 846 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 847 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO, 848 lower_32_bits(wptr_gpu_addr)); 849 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI, 850 upper_32_bits(wptr_gpu_addr)); 851 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL); 852 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 853 SDMA0_GFX_RB_WPTR_POLL_CNTL, 854 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)); 855 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 856 857 /* enable DMA RB */ 858 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 859 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 860 861 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL); 862 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 863 #ifdef __BIG_ENDIAN 864 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 865 #endif 866 /* enable DMA IBs */ 867 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl); 868 869 ring->sched.ready = true; 870 } 871 872 /** 873 * sdma_v4_0_page_resume - setup and start the async dma engines 874 * 875 * @adev: amdgpu_device pointer 876 * @i: instance to resume 877 * 878 * Set up the page DMA ring buffers and enable them (VEGA10). 879 * Returns 0 for success, error for failure. 880 */ 881 static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i) 882 { 883 struct amdgpu_ring *ring = &adev->sdma.instance[i].page; 884 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 885 u32 wb_offset; 886 u32 doorbell; 887 u32 doorbell_offset; 888 u64 wptr_gpu_addr; 889 890 wb_offset = (ring->rptr_offs * 4); 891 892 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL); 893 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl); 894 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 895 896 /* Initialize the ring buffer's read and write pointers */ 897 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR, 0); 898 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_HI, 0); 899 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR, 0); 900 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_HI, 0); 901 902 /* set the wb address whether it's enabled or not */ 903 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_HI, 904 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 905 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 906 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 907 908 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, 909 RPTR_WRITEBACK_ENABLE, 1); 910 911 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE, ring->gpu_addr >> 8); 912 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE_HI, ring->gpu_addr >> 40); 913 914 ring->wptr = 0; 915 916 /* before programing wptr to a less value, need set minor_ptr_update first */ 917 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 1); 918 919 doorbell = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL); 920 doorbell_offset = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET); 921 922 doorbell = REG_SET_FIELD(doorbell, SDMA0_PAGE_DOORBELL, ENABLE, 923 ring->use_doorbell); 924 doorbell_offset = REG_SET_FIELD(doorbell_offset, 925 SDMA0_PAGE_DOORBELL_OFFSET, 926 OFFSET, ring->doorbell_index); 927 WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL, doorbell); 928 WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET, doorbell_offset); 929 930 /* paging queue doorbell range is setup at sdma_v4_0_gfx_resume */ 931 sdma_v4_0_page_ring_set_wptr(ring); 932 933 /* set minor_ptr_update to 0 after wptr programed */ 934 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 0); 935 936 /* setup the wptr shadow polling */ 937 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 938 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO, 939 lower_32_bits(wptr_gpu_addr)); 940 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI, 941 upper_32_bits(wptr_gpu_addr)); 942 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL); 943 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 944 SDMA0_PAGE_RB_WPTR_POLL_CNTL, 945 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)); 946 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 947 948 /* enable DMA RB */ 949 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, RB_ENABLE, 1); 950 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 951 952 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL); 953 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_ENABLE, 1); 954 #ifdef __BIG_ENDIAN 955 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1); 956 #endif 957 /* enable DMA IBs */ 958 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl); 959 960 ring->sched.ready = true; 961 } 962 963 static void 964 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable) 965 { 966 uint32_t def, data; 967 968 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) { 969 /* enable idle interrupt */ 970 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 971 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 972 973 if (data != def) 974 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 975 } else { 976 /* disable idle interrupt */ 977 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 978 data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 979 if (data != def) 980 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 981 } 982 } 983 984 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev) 985 { 986 uint32_t def, data; 987 988 /* Enable HW based PG. */ 989 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 990 data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK; 991 if (data != def) 992 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 993 994 /* enable interrupt */ 995 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 996 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 997 if (data != def) 998 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 999 1000 /* Configure hold time to filter in-valid power on/off request. Use default right now */ 1001 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1002 data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK; 1003 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK); 1004 /* Configure switch time for hysteresis purpose. Use default right now */ 1005 data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK; 1006 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK); 1007 if(data != def) 1008 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1009 } 1010 1011 static void sdma_v4_0_init_pg(struct amdgpu_device *adev) 1012 { 1013 if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA)) 1014 return; 1015 1016 switch (adev->asic_type) { 1017 case CHIP_RAVEN: 1018 sdma_v4_1_init_power_gating(adev); 1019 sdma_v4_1_update_power_gating(adev, true); 1020 break; 1021 default: 1022 break; 1023 } 1024 } 1025 1026 /** 1027 * sdma_v4_0_rlc_resume - setup and start the async dma engines 1028 * 1029 * @adev: amdgpu_device pointer 1030 * 1031 * Set up the compute DMA queues and enable them (VEGA10). 1032 * Returns 0 for success, error for failure. 1033 */ 1034 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev) 1035 { 1036 sdma_v4_0_init_pg(adev); 1037 1038 return 0; 1039 } 1040 1041 /** 1042 * sdma_v4_0_load_microcode - load the sDMA ME ucode 1043 * 1044 * @adev: amdgpu_device pointer 1045 * 1046 * Loads the sDMA0/1 ucode. 1047 * Returns 0 for success, -EINVAL if the ucode is not available. 1048 */ 1049 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev) 1050 { 1051 const struct sdma_firmware_header_v1_0 *hdr; 1052 const __le32 *fw_data; 1053 u32 fw_size; 1054 int i, j; 1055 1056 /* halt the MEs */ 1057 sdma_v4_0_enable(adev, false); 1058 1059 for (i = 0; i < adev->sdma.num_instances; i++) { 1060 if (!adev->sdma.instance[i].fw) 1061 return -EINVAL; 1062 1063 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 1064 amdgpu_ucode_print_sdma_hdr(&hdr->header); 1065 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1066 1067 fw_data = (const __le32 *) 1068 (adev->sdma.instance[i].fw->data + 1069 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1070 1071 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 0); 1072 1073 for (j = 0; j < fw_size; j++) 1074 WREG32_SDMA(i, mmSDMA0_UCODE_DATA, 1075 le32_to_cpup(fw_data++)); 1076 1077 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 1078 adev->sdma.instance[i].fw_version); 1079 } 1080 1081 return 0; 1082 } 1083 1084 /** 1085 * sdma_v4_0_start - setup and start the async dma engines 1086 * 1087 * @adev: amdgpu_device pointer 1088 * 1089 * Set up the DMA engines and enable them (VEGA10). 1090 * Returns 0 for success, error for failure. 1091 */ 1092 static int sdma_v4_0_start(struct amdgpu_device *adev) 1093 { 1094 struct amdgpu_ring *ring; 1095 int i, r; 1096 1097 if (amdgpu_sriov_vf(adev)) { 1098 sdma_v4_0_ctx_switch_enable(adev, false); 1099 sdma_v4_0_enable(adev, false); 1100 } else { 1101 1102 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1103 r = sdma_v4_0_load_microcode(adev); 1104 if (r) 1105 return r; 1106 } 1107 1108 /* unhalt the MEs */ 1109 sdma_v4_0_enable(adev, true); 1110 /* enable sdma ring preemption */ 1111 sdma_v4_0_ctx_switch_enable(adev, true); 1112 } 1113 1114 /* start the gfx rings and rlc compute queues */ 1115 for (i = 0; i < adev->sdma.num_instances; i++) { 1116 uint32_t temp; 1117 1118 WREG32_SDMA(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL, 0); 1119 sdma_v4_0_gfx_resume(adev, i); 1120 if (adev->sdma.has_page_queue) 1121 sdma_v4_0_page_resume(adev, i); 1122 1123 /* set utc l1 enable flag always to 1 */ 1124 temp = RREG32_SDMA(i, mmSDMA0_CNTL); 1125 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 1126 WREG32_SDMA(i, mmSDMA0_CNTL, temp); 1127 1128 if (!amdgpu_sriov_vf(adev)) { 1129 /* unhalt engine */ 1130 temp = RREG32_SDMA(i, mmSDMA0_F32_CNTL); 1131 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 1132 WREG32_SDMA(i, mmSDMA0_F32_CNTL, temp); 1133 } 1134 } 1135 1136 if (amdgpu_sriov_vf(adev)) { 1137 sdma_v4_0_ctx_switch_enable(adev, true); 1138 sdma_v4_0_enable(adev, true); 1139 } else { 1140 r = sdma_v4_0_rlc_resume(adev); 1141 if (r) 1142 return r; 1143 } 1144 1145 for (i = 0; i < adev->sdma.num_instances; i++) { 1146 ring = &adev->sdma.instance[i].ring; 1147 1148 r = amdgpu_ring_test_helper(ring); 1149 if (r) 1150 return r; 1151 1152 if (adev->sdma.has_page_queue) { 1153 struct amdgpu_ring *page = &adev->sdma.instance[i].page; 1154 1155 r = amdgpu_ring_test_helper(page); 1156 if (r) 1157 return r; 1158 1159 if (adev->mman.buffer_funcs_ring == page) 1160 amdgpu_ttm_set_buffer_funcs_status(adev, true); 1161 } 1162 1163 if (adev->mman.buffer_funcs_ring == ring) 1164 amdgpu_ttm_set_buffer_funcs_status(adev, true); 1165 } 1166 1167 return r; 1168 } 1169 1170 /** 1171 * sdma_v4_0_ring_test_ring - simple async dma engine test 1172 * 1173 * @ring: amdgpu_ring structure holding ring information 1174 * 1175 * Test the DMA engine by writing using it to write an 1176 * value to memory. (VEGA10). 1177 * Returns 0 for success, error for failure. 1178 */ 1179 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring) 1180 { 1181 struct amdgpu_device *adev = ring->adev; 1182 unsigned i; 1183 unsigned index; 1184 int r; 1185 u32 tmp; 1186 u64 gpu_addr; 1187 1188 r = amdgpu_device_wb_get(adev, &index); 1189 if (r) 1190 return r; 1191 1192 gpu_addr = adev->wb.gpu_addr + (index * 4); 1193 tmp = 0xCAFEDEAD; 1194 adev->wb.wb[index] = cpu_to_le32(tmp); 1195 1196 r = amdgpu_ring_alloc(ring, 5); 1197 if (r) 1198 goto error_free_wb; 1199 1200 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1201 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 1202 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 1203 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 1204 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 1205 amdgpu_ring_write(ring, 0xDEADBEEF); 1206 amdgpu_ring_commit(ring); 1207 1208 for (i = 0; i < adev->usec_timeout; i++) { 1209 tmp = le32_to_cpu(adev->wb.wb[index]); 1210 if (tmp == 0xDEADBEEF) 1211 break; 1212 DRM_UDELAY(1); 1213 } 1214 1215 if (i >= adev->usec_timeout) 1216 r = -ETIMEDOUT; 1217 1218 error_free_wb: 1219 amdgpu_device_wb_free(adev, index); 1220 return r; 1221 } 1222 1223 /** 1224 * sdma_v4_0_ring_test_ib - test an IB on the DMA engine 1225 * 1226 * @ring: amdgpu_ring structure holding ring information 1227 * 1228 * Test a simple IB in the DMA ring (VEGA10). 1229 * Returns 0 on success, error on failure. 1230 */ 1231 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1232 { 1233 struct amdgpu_device *adev = ring->adev; 1234 struct amdgpu_ib ib; 1235 struct dma_fence *f = NULL; 1236 unsigned index; 1237 long r; 1238 u32 tmp = 0; 1239 u64 gpu_addr; 1240 1241 r = amdgpu_device_wb_get(adev, &index); 1242 if (r) 1243 return r; 1244 1245 gpu_addr = adev->wb.gpu_addr + (index * 4); 1246 tmp = 0xCAFEDEAD; 1247 adev->wb.wb[index] = cpu_to_le32(tmp); 1248 memset(&ib, 0, sizeof(ib)); 1249 r = amdgpu_ib_get(adev, NULL, 256, &ib); 1250 if (r) 1251 goto err0; 1252 1253 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1254 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1255 ib.ptr[1] = lower_32_bits(gpu_addr); 1256 ib.ptr[2] = upper_32_bits(gpu_addr); 1257 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1258 ib.ptr[4] = 0xDEADBEEF; 1259 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1260 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1261 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1262 ib.length_dw = 8; 1263 1264 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1265 if (r) 1266 goto err1; 1267 1268 r = dma_fence_wait_timeout(f, false, timeout); 1269 if (r == 0) { 1270 r = -ETIMEDOUT; 1271 goto err1; 1272 } else if (r < 0) { 1273 goto err1; 1274 } 1275 tmp = le32_to_cpu(adev->wb.wb[index]); 1276 if (tmp == 0xDEADBEEF) 1277 r = 0; 1278 else 1279 r = -EINVAL; 1280 1281 err1: 1282 amdgpu_ib_free(adev, &ib, NULL); 1283 dma_fence_put(f); 1284 err0: 1285 amdgpu_device_wb_free(adev, index); 1286 return r; 1287 } 1288 1289 1290 /** 1291 * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART 1292 * 1293 * @ib: indirect buffer to fill with commands 1294 * @pe: addr of the page entry 1295 * @src: src addr to copy from 1296 * @count: number of page entries to update 1297 * 1298 * Update PTEs by copying them from the GART using sDMA (VEGA10). 1299 */ 1300 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib, 1301 uint64_t pe, uint64_t src, 1302 unsigned count) 1303 { 1304 unsigned bytes = count * 8; 1305 1306 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1307 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1308 ib->ptr[ib->length_dw++] = bytes - 1; 1309 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1310 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1311 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1312 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1313 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1314 1315 } 1316 1317 /** 1318 * sdma_v4_0_vm_write_pte - update PTEs by writing them manually 1319 * 1320 * @ib: indirect buffer to fill with commands 1321 * @pe: addr of the page entry 1322 * @addr: dst addr to write into pe 1323 * @count: number of page entries to update 1324 * @incr: increase next addr by incr bytes 1325 * @flags: access flags 1326 * 1327 * Update PTEs by writing them manually using sDMA (VEGA10). 1328 */ 1329 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1330 uint64_t value, unsigned count, 1331 uint32_t incr) 1332 { 1333 unsigned ndw = count * 2; 1334 1335 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1336 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1337 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1338 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1339 ib->ptr[ib->length_dw++] = ndw - 1; 1340 for (; ndw > 0; ndw -= 2) { 1341 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1342 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1343 value += incr; 1344 } 1345 } 1346 1347 /** 1348 * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA 1349 * 1350 * @ib: indirect buffer to fill with commands 1351 * @pe: addr of the page entry 1352 * @addr: dst addr to write into pe 1353 * @count: number of page entries to update 1354 * @incr: increase next addr by incr bytes 1355 * @flags: access flags 1356 * 1357 * Update the page tables using sDMA (VEGA10). 1358 */ 1359 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1360 uint64_t pe, 1361 uint64_t addr, unsigned count, 1362 uint32_t incr, uint64_t flags) 1363 { 1364 /* for physically contiguous pages (vram) */ 1365 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1366 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1367 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1368 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1369 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1370 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1371 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1372 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1373 ib->ptr[ib->length_dw++] = 0; 1374 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1375 } 1376 1377 /** 1378 * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw 1379 * 1380 * @ib: indirect buffer to fill with padding 1381 * 1382 */ 1383 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1384 { 1385 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1386 u32 pad_count; 1387 int i; 1388 1389 pad_count = (8 - (ib->length_dw & 0x7)) % 8; 1390 for (i = 0; i < pad_count; i++) 1391 if (sdma && sdma->burst_nop && (i == 0)) 1392 ib->ptr[ib->length_dw++] = 1393 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1394 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1395 else 1396 ib->ptr[ib->length_dw++] = 1397 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1398 } 1399 1400 1401 /** 1402 * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline 1403 * 1404 * @ring: amdgpu_ring pointer 1405 * 1406 * Make sure all previous operations are completed (CIK). 1407 */ 1408 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1409 { 1410 uint32_t seq = ring->fence_drv.sync_seq; 1411 uint64_t addr = ring->fence_drv.gpu_addr; 1412 1413 /* wait for idle */ 1414 sdma_v4_0_wait_reg_mem(ring, 1, 0, 1415 addr & 0xfffffffc, 1416 upper_32_bits(addr) & 0xffffffff, 1417 seq, 0xffffffff, 4); 1418 } 1419 1420 1421 /** 1422 * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA 1423 * 1424 * @ring: amdgpu_ring pointer 1425 * @vm: amdgpu_vm pointer 1426 * 1427 * Update the page table base and flush the VM TLB 1428 * using sDMA (VEGA10). 1429 */ 1430 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1431 unsigned vmid, uint64_t pd_addr) 1432 { 1433 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1434 } 1435 1436 static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring, 1437 uint32_t reg, uint32_t val) 1438 { 1439 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1440 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1441 amdgpu_ring_write(ring, reg); 1442 amdgpu_ring_write(ring, val); 1443 } 1444 1445 static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1446 uint32_t val, uint32_t mask) 1447 { 1448 sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10); 1449 } 1450 1451 static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev) 1452 { 1453 uint fw_version = adev->sdma.instance[0].fw_version; 1454 1455 switch (adev->asic_type) { 1456 case CHIP_VEGA10: 1457 return fw_version >= 430; 1458 case CHIP_VEGA12: 1459 /*return fw_version >= 31;*/ 1460 return false; 1461 case CHIP_VEGA20: 1462 return fw_version >= 123; 1463 default: 1464 return false; 1465 } 1466 } 1467 1468 static int sdma_v4_0_early_init(void *handle) 1469 { 1470 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1471 int r; 1472 1473 if (adev->asic_type == CHIP_RAVEN) 1474 adev->sdma.num_instances = 1; 1475 else 1476 adev->sdma.num_instances = 2; 1477 1478 r = sdma_v4_0_init_microcode(adev); 1479 if (r) { 1480 DRM_ERROR("Failed to load sdma firmware!\n"); 1481 return r; 1482 } 1483 1484 /* TODO: Page queue breaks driver reload under SRIOV */ 1485 if ((adev->asic_type == CHIP_VEGA10) && amdgpu_sriov_vf((adev))) 1486 adev->sdma.has_page_queue = false; 1487 else if (sdma_v4_0_fw_support_paging_queue(adev)) 1488 adev->sdma.has_page_queue = true; 1489 1490 sdma_v4_0_set_ring_funcs(adev); 1491 sdma_v4_0_set_buffer_funcs(adev); 1492 sdma_v4_0_set_vm_pte_funcs(adev); 1493 sdma_v4_0_set_irq_funcs(adev); 1494 1495 return 0; 1496 } 1497 1498 static int sdma_v4_0_sw_init(void *handle) 1499 { 1500 struct amdgpu_ring *ring; 1501 int r, i; 1502 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1503 1504 /* SDMA trap event */ 1505 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0, SDMA0_4_0__SRCID__SDMA_TRAP, 1506 &adev->sdma.trap_irq); 1507 if (r) 1508 return r; 1509 1510 /* SDMA trap event */ 1511 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1, SDMA1_4_0__SRCID__SDMA_TRAP, 1512 &adev->sdma.trap_irq); 1513 if (r) 1514 return r; 1515 1516 for (i = 0; i < adev->sdma.num_instances; i++) { 1517 ring = &adev->sdma.instance[i].ring; 1518 ring->ring_obj = NULL; 1519 ring->use_doorbell = true; 1520 1521 DRM_INFO("use_doorbell being set to: [%s]\n", 1522 ring->use_doorbell?"true":"false"); 1523 1524 /* doorbell size is 2 dwords, get DWORD offset */ 1525 ring->doorbell_index = (i == 0) ? 1526 (adev->doorbell_index.sdma_engine0 << 1) 1527 : (adev->doorbell_index.sdma_engine1 << 1); 1528 1529 sprintf(ring->name, "sdma%d", i); 1530 r = amdgpu_ring_init(adev, ring, 1024, 1531 &adev->sdma.trap_irq, 1532 (i == 0) ? 1533 AMDGPU_SDMA_IRQ_TRAP0 : 1534 AMDGPU_SDMA_IRQ_TRAP1); 1535 if (r) 1536 return r; 1537 1538 if (adev->sdma.has_page_queue) { 1539 ring = &adev->sdma.instance[i].page; 1540 ring->ring_obj = NULL; 1541 ring->use_doorbell = true; 1542 1543 /* paging queue use same doorbell index/routing as gfx queue 1544 * with 0x400 (4096 dwords) offset on second doorbell page 1545 */ 1546 ring->doorbell_index = (i == 0) ? 1547 (adev->doorbell_index.sdma_engine0 << 1) 1548 : (adev->doorbell_index.sdma_engine1 << 1); 1549 ring->doorbell_index += 0x400; 1550 1551 sprintf(ring->name, "page%d", i); 1552 r = amdgpu_ring_init(adev, ring, 1024, 1553 &adev->sdma.trap_irq, 1554 (i == 0) ? 1555 AMDGPU_SDMA_IRQ_TRAP0 : 1556 AMDGPU_SDMA_IRQ_TRAP1); 1557 if (r) 1558 return r; 1559 } 1560 } 1561 1562 return r; 1563 } 1564 1565 static int sdma_v4_0_sw_fini(void *handle) 1566 { 1567 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1568 int i; 1569 1570 for (i = 0; i < adev->sdma.num_instances; i++) { 1571 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1572 if (adev->sdma.has_page_queue) 1573 amdgpu_ring_fini(&adev->sdma.instance[i].page); 1574 } 1575 1576 for (i = 0; i < adev->sdma.num_instances; i++) { 1577 release_firmware(adev->sdma.instance[i].fw); 1578 adev->sdma.instance[i].fw = NULL; 1579 } 1580 1581 return 0; 1582 } 1583 1584 static int sdma_v4_0_hw_init(void *handle) 1585 { 1586 int r; 1587 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1588 1589 if (adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs && 1590 adev->powerplay.pp_funcs->set_powergating_by_smu) 1591 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false); 1592 1593 sdma_v4_0_init_golden_registers(adev); 1594 1595 r = sdma_v4_0_start(adev); 1596 1597 return r; 1598 } 1599 1600 static int sdma_v4_0_hw_fini(void *handle) 1601 { 1602 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1603 1604 if (amdgpu_sriov_vf(adev)) 1605 return 0; 1606 1607 sdma_v4_0_ctx_switch_enable(adev, false); 1608 sdma_v4_0_enable(adev, false); 1609 1610 if (adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs 1611 && adev->powerplay.pp_funcs->set_powergating_by_smu) 1612 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true); 1613 1614 return 0; 1615 } 1616 1617 static int sdma_v4_0_suspend(void *handle) 1618 { 1619 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1620 1621 return sdma_v4_0_hw_fini(adev); 1622 } 1623 1624 static int sdma_v4_0_resume(void *handle) 1625 { 1626 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1627 1628 return sdma_v4_0_hw_init(adev); 1629 } 1630 1631 static bool sdma_v4_0_is_idle(void *handle) 1632 { 1633 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1634 u32 i; 1635 1636 for (i = 0; i < adev->sdma.num_instances; i++) { 1637 u32 tmp = RREG32_SDMA(i, mmSDMA0_STATUS_REG); 1638 1639 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1640 return false; 1641 } 1642 1643 return true; 1644 } 1645 1646 static int sdma_v4_0_wait_for_idle(void *handle) 1647 { 1648 unsigned i; 1649 u32 sdma0, sdma1; 1650 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1651 1652 for (i = 0; i < adev->usec_timeout; i++) { 1653 sdma0 = RREG32_SDMA(0, mmSDMA0_STATUS_REG); 1654 sdma1 = RREG32_SDMA(1, mmSDMA0_STATUS_REG); 1655 1656 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK) 1657 return 0; 1658 udelay(1); 1659 } 1660 return -ETIMEDOUT; 1661 } 1662 1663 static int sdma_v4_0_soft_reset(void *handle) 1664 { 1665 /* todo */ 1666 1667 return 0; 1668 } 1669 1670 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev, 1671 struct amdgpu_irq_src *source, 1672 unsigned type, 1673 enum amdgpu_interrupt_state state) 1674 { 1675 unsigned int instance = (type == AMDGPU_SDMA_IRQ_TRAP0) ? 0 : 1; 1676 u32 sdma_cntl; 1677 1678 sdma_cntl = RREG32_SDMA(instance, mmSDMA0_CNTL); 1679 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1680 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1681 WREG32_SDMA(instance, mmSDMA0_CNTL, sdma_cntl); 1682 1683 return 0; 1684 } 1685 1686 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev, 1687 struct amdgpu_irq_src *source, 1688 struct amdgpu_iv_entry *entry) 1689 { 1690 uint32_t instance; 1691 1692 DRM_DEBUG("IH: SDMA trap\n"); 1693 switch (entry->client_id) { 1694 case SOC15_IH_CLIENTID_SDMA0: 1695 instance = 0; 1696 break; 1697 case SOC15_IH_CLIENTID_SDMA1: 1698 instance = 1; 1699 break; 1700 default: 1701 return 0; 1702 } 1703 1704 switch (entry->ring_id) { 1705 case 0: 1706 amdgpu_fence_process(&adev->sdma.instance[instance].ring); 1707 break; 1708 case 1: 1709 if (adev->asic_type == CHIP_VEGA20) 1710 amdgpu_fence_process(&adev->sdma.instance[instance].page); 1711 break; 1712 case 2: 1713 /* XXX compute */ 1714 break; 1715 case 3: 1716 if (adev->asic_type != CHIP_VEGA20) 1717 amdgpu_fence_process(&adev->sdma.instance[instance].page); 1718 break; 1719 } 1720 return 0; 1721 } 1722 1723 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1724 struct amdgpu_irq_src *source, 1725 struct amdgpu_iv_entry *entry) 1726 { 1727 int instance; 1728 1729 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1730 1731 switch (entry->client_id) { 1732 case SOC15_IH_CLIENTID_SDMA0: 1733 instance = 0; 1734 break; 1735 case SOC15_IH_CLIENTID_SDMA1: 1736 instance = 1; 1737 break; 1738 default: 1739 return 0; 1740 } 1741 1742 switch (entry->ring_id) { 1743 case 0: 1744 drm_sched_fault(&adev->sdma.instance[instance].ring.sched); 1745 break; 1746 } 1747 return 0; 1748 } 1749 1750 static void sdma_v4_0_update_medium_grain_clock_gating( 1751 struct amdgpu_device *adev, 1752 bool enable) 1753 { 1754 uint32_t data, def; 1755 1756 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1757 /* enable sdma0 clock gating */ 1758 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 1759 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1760 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1761 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1762 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1763 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1764 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1765 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1766 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1767 if (def != data) 1768 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data); 1769 1770 if (adev->sdma.num_instances > 1) { 1771 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL)); 1772 data &= ~(SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1773 SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1774 SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1775 SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1776 SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1777 SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1778 SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1779 SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1780 if (def != data) 1781 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data); 1782 } 1783 } else { 1784 /* disable sdma0 clock gating */ 1785 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 1786 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1787 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1788 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1789 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1790 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1791 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1792 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1793 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1794 1795 if (def != data) 1796 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data); 1797 1798 if (adev->sdma.num_instances > 1) { 1799 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL)); 1800 data |= (SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1801 SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1802 SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1803 SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1804 SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1805 SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1806 SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1807 SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1808 if (def != data) 1809 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data); 1810 } 1811 } 1812 } 1813 1814 1815 static void sdma_v4_0_update_medium_grain_light_sleep( 1816 struct amdgpu_device *adev, 1817 bool enable) 1818 { 1819 uint32_t data, def; 1820 1821 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1822 /* 1-not override: enable sdma0 mem light sleep */ 1823 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1824 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1825 if (def != data) 1826 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1827 1828 /* 1-not override: enable sdma1 mem light sleep */ 1829 if (adev->sdma.num_instances > 1) { 1830 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL)); 1831 data |= SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1832 if (def != data) 1833 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data); 1834 } 1835 } else { 1836 /* 0-override:disable sdma0 mem light sleep */ 1837 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1838 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1839 if (def != data) 1840 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1841 1842 /* 0-override:disable sdma1 mem light sleep */ 1843 if (adev->sdma.num_instances > 1) { 1844 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL)); 1845 data &= ~SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1846 if (def != data) 1847 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data); 1848 } 1849 } 1850 } 1851 1852 static int sdma_v4_0_set_clockgating_state(void *handle, 1853 enum amd_clockgating_state state) 1854 { 1855 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1856 1857 if (amdgpu_sriov_vf(adev)) 1858 return 0; 1859 1860 switch (adev->asic_type) { 1861 case CHIP_VEGA10: 1862 case CHIP_VEGA12: 1863 case CHIP_VEGA20: 1864 case CHIP_RAVEN: 1865 sdma_v4_0_update_medium_grain_clock_gating(adev, 1866 state == AMD_CG_STATE_GATE ? true : false); 1867 sdma_v4_0_update_medium_grain_light_sleep(adev, 1868 state == AMD_CG_STATE_GATE ? true : false); 1869 break; 1870 default: 1871 break; 1872 } 1873 return 0; 1874 } 1875 1876 static int sdma_v4_0_set_powergating_state(void *handle, 1877 enum amd_powergating_state state) 1878 { 1879 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1880 1881 switch (adev->asic_type) { 1882 case CHIP_RAVEN: 1883 sdma_v4_1_update_power_gating(adev, 1884 state == AMD_PG_STATE_GATE ? true : false); 1885 break; 1886 default: 1887 break; 1888 } 1889 1890 return 0; 1891 } 1892 1893 static void sdma_v4_0_get_clockgating_state(void *handle, u32 *flags) 1894 { 1895 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1896 int data; 1897 1898 if (amdgpu_sriov_vf(adev)) 1899 *flags = 0; 1900 1901 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1902 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 1903 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK)) 1904 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1905 1906 /* AMD_CG_SUPPORT_SDMA_LS */ 1907 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1908 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1909 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1910 } 1911 1912 const struct amd_ip_funcs sdma_v4_0_ip_funcs = { 1913 .name = "sdma_v4_0", 1914 .early_init = sdma_v4_0_early_init, 1915 .late_init = NULL, 1916 .sw_init = sdma_v4_0_sw_init, 1917 .sw_fini = sdma_v4_0_sw_fini, 1918 .hw_init = sdma_v4_0_hw_init, 1919 .hw_fini = sdma_v4_0_hw_fini, 1920 .suspend = sdma_v4_0_suspend, 1921 .resume = sdma_v4_0_resume, 1922 .is_idle = sdma_v4_0_is_idle, 1923 .wait_for_idle = sdma_v4_0_wait_for_idle, 1924 .soft_reset = sdma_v4_0_soft_reset, 1925 .set_clockgating_state = sdma_v4_0_set_clockgating_state, 1926 .set_powergating_state = sdma_v4_0_set_powergating_state, 1927 .get_clockgating_state = sdma_v4_0_get_clockgating_state, 1928 }; 1929 1930 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = { 1931 .type = AMDGPU_RING_TYPE_SDMA, 1932 .align_mask = 0xf, 1933 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1934 .support_64bit_ptrs = true, 1935 .vmhub = AMDGPU_MMHUB, 1936 .get_rptr = sdma_v4_0_ring_get_rptr, 1937 .get_wptr = sdma_v4_0_ring_get_wptr, 1938 .set_wptr = sdma_v4_0_ring_set_wptr, 1939 .emit_frame_size = 1940 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 1941 3 + /* hdp invalidate */ 1942 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 1943 /* sdma_v4_0_ring_emit_vm_flush */ 1944 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1945 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1946 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 1947 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 1948 .emit_ib = sdma_v4_0_ring_emit_ib, 1949 .emit_fence = sdma_v4_0_ring_emit_fence, 1950 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 1951 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 1952 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 1953 .test_ring = sdma_v4_0_ring_test_ring, 1954 .test_ib = sdma_v4_0_ring_test_ib, 1955 .insert_nop = sdma_v4_0_ring_insert_nop, 1956 .pad_ib = sdma_v4_0_ring_pad_ib, 1957 .emit_wreg = sdma_v4_0_ring_emit_wreg, 1958 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 1959 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1960 }; 1961 1962 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = { 1963 .type = AMDGPU_RING_TYPE_SDMA, 1964 .align_mask = 0xf, 1965 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1966 .support_64bit_ptrs = true, 1967 .vmhub = AMDGPU_MMHUB, 1968 .get_rptr = sdma_v4_0_ring_get_rptr, 1969 .get_wptr = sdma_v4_0_page_ring_get_wptr, 1970 .set_wptr = sdma_v4_0_page_ring_set_wptr, 1971 .emit_frame_size = 1972 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 1973 3 + /* hdp invalidate */ 1974 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 1975 /* sdma_v4_0_ring_emit_vm_flush */ 1976 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1977 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1978 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 1979 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 1980 .emit_ib = sdma_v4_0_ring_emit_ib, 1981 .emit_fence = sdma_v4_0_ring_emit_fence, 1982 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 1983 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 1984 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 1985 .test_ring = sdma_v4_0_ring_test_ring, 1986 .test_ib = sdma_v4_0_ring_test_ib, 1987 .insert_nop = sdma_v4_0_ring_insert_nop, 1988 .pad_ib = sdma_v4_0_ring_pad_ib, 1989 .emit_wreg = sdma_v4_0_ring_emit_wreg, 1990 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 1991 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1992 }; 1993 1994 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev) 1995 { 1996 int i; 1997 1998 for (i = 0; i < adev->sdma.num_instances; i++) { 1999 adev->sdma.instance[i].ring.funcs = &sdma_v4_0_ring_funcs; 2000 adev->sdma.instance[i].ring.me = i; 2001 if (adev->sdma.has_page_queue) { 2002 adev->sdma.instance[i].page.funcs = &sdma_v4_0_page_ring_funcs; 2003 adev->sdma.instance[i].page.me = i; 2004 } 2005 } 2006 } 2007 2008 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = { 2009 .set = sdma_v4_0_set_trap_irq_state, 2010 .process = sdma_v4_0_process_trap_irq, 2011 }; 2012 2013 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = { 2014 .process = sdma_v4_0_process_illegal_inst_irq, 2015 }; 2016 2017 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev) 2018 { 2019 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 2020 adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs; 2021 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs; 2022 } 2023 2024 /** 2025 * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine 2026 * 2027 * @ring: amdgpu_ring structure holding ring information 2028 * @src_offset: src GPU address 2029 * @dst_offset: dst GPU address 2030 * @byte_count: number of bytes to xfer 2031 * 2032 * Copy GPU buffers using the DMA engine (VEGA10/12). 2033 * Used by the amdgpu ttm implementation to move pages if 2034 * registered as the asic copy callback. 2035 */ 2036 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib, 2037 uint64_t src_offset, 2038 uint64_t dst_offset, 2039 uint32_t byte_count) 2040 { 2041 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 2042 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 2043 ib->ptr[ib->length_dw++] = byte_count - 1; 2044 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 2045 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 2046 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 2047 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2048 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2049 } 2050 2051 /** 2052 * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine 2053 * 2054 * @ring: amdgpu_ring structure holding ring information 2055 * @src_data: value to write to buffer 2056 * @dst_offset: dst GPU address 2057 * @byte_count: number of bytes to xfer 2058 * 2059 * Fill GPU buffers using the DMA engine (VEGA10/12). 2060 */ 2061 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib, 2062 uint32_t src_data, 2063 uint64_t dst_offset, 2064 uint32_t byte_count) 2065 { 2066 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 2067 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2068 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2069 ib->ptr[ib->length_dw++] = src_data; 2070 ib->ptr[ib->length_dw++] = byte_count - 1; 2071 } 2072 2073 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = { 2074 .copy_max_bytes = 0x400000, 2075 .copy_num_dw = 7, 2076 .emit_copy_buffer = sdma_v4_0_emit_copy_buffer, 2077 2078 .fill_max_bytes = 0x400000, 2079 .fill_num_dw = 5, 2080 .emit_fill_buffer = sdma_v4_0_emit_fill_buffer, 2081 }; 2082 2083 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev) 2084 { 2085 adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs; 2086 if (adev->sdma.has_page_queue) 2087 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page; 2088 else 2089 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 2090 } 2091 2092 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = { 2093 .copy_pte_num_dw = 7, 2094 .copy_pte = sdma_v4_0_vm_copy_pte, 2095 2096 .write_pte = sdma_v4_0_vm_write_pte, 2097 .set_pte_pde = sdma_v4_0_vm_set_pte_pde, 2098 }; 2099 2100 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev) 2101 { 2102 struct drm_gpu_scheduler *sched; 2103 unsigned i; 2104 2105 adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs; 2106 for (i = 0; i < adev->sdma.num_instances; i++) { 2107 if (adev->sdma.has_page_queue) 2108 sched = &adev->sdma.instance[i].page.sched; 2109 else 2110 sched = &adev->sdma.instance[i].ring.sched; 2111 adev->vm_manager.vm_pte_rqs[i] = 2112 &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL]; 2113 } 2114 adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances; 2115 } 2116 2117 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = { 2118 .type = AMD_IP_BLOCK_TYPE_SDMA, 2119 .major = 4, 2120 .minor = 0, 2121 .rev = 0, 2122 .funcs = &sdma_v4_0_ip_funcs, 2123 }; 2124