1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_ucode.h" 28 #include "amdgpu_trace.h" 29 30 #include "sdma0/sdma0_4_2_offset.h" 31 #include "sdma0/sdma0_4_2_sh_mask.h" 32 #include "sdma1/sdma1_4_2_offset.h" 33 #include "sdma1/sdma1_4_2_sh_mask.h" 34 #include "hdp/hdp_4_0_offset.h" 35 #include "sdma0/sdma0_4_1_default.h" 36 37 #include "soc15_common.h" 38 #include "soc15.h" 39 #include "vega10_sdma_pkt_open.h" 40 41 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h" 42 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h" 43 44 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin"); 45 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin"); 46 MODULE_FIRMWARE("amdgpu/vega12_sdma.bin"); 47 MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin"); 48 MODULE_FIRMWARE("amdgpu/vega20_sdma.bin"); 49 MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin"); 50 MODULE_FIRMWARE("amdgpu/raven_sdma.bin"); 51 MODULE_FIRMWARE("amdgpu/picasso_sdma.bin"); 52 MODULE_FIRMWARE("amdgpu/raven2_sdma.bin"); 53 54 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L 55 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L 56 57 #define WREG32_SDMA(instance, offset, value) \ 58 WREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)), value) 59 #define RREG32_SDMA(instance, offset) \ 60 RREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset))) 61 62 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev); 63 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev); 64 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev); 65 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev); 66 67 static const struct soc15_reg_golden golden_settings_sdma_4[] = { 68 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 69 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100), 70 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100), 71 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 72 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 73 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 74 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000), 75 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 76 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 77 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 78 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 79 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 80 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000), 81 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), 82 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100), 83 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 84 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 85 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 86 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000), 87 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 88 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 89 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 90 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 91 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0), 92 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xfc000000, 0x00000000) 93 }; 94 95 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = { 96 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 97 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 98 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 99 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 100 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002) 101 }; 102 103 static const struct soc15_reg_golden golden_settings_sdma_vg12[] = { 104 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), 105 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001), 106 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 107 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), 108 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001) 109 }; 110 111 static const struct soc15_reg_golden golden_settings_sdma_4_1[] = { 112 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 113 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 114 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100), 115 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 116 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051), 117 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100), 118 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 119 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100), 120 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 121 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 122 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000) 123 }; 124 125 static const struct soc15_reg_golden golden_settings_sdma0_4_2_init[] = { 126 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 127 }; 128 129 static const struct soc15_reg_golden golden_settings_sdma0_4_2[] = 130 { 131 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 132 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 133 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 134 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 135 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 136 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 137 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 138 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 139 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RD_BURST_CNTL, 0x0000000f, 0x00000003), 140 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 141 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 142 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 143 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 144 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 145 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 146 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 147 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 148 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 149 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 150 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 151 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 152 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 153 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 154 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 155 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 156 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 157 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xFE000000, 0x00000000), 158 }; 159 160 static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = { 161 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 162 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), 163 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 164 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 165 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 166 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 167 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 168 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 169 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RD_BURST_CNTL, 0x0000000f, 0x00000003), 170 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 171 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 172 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 173 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 174 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 175 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 176 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 177 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 178 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 179 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 180 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 181 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 182 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 183 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 184 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 185 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 186 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0), 187 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xFE000000, 0x00000000), 188 }; 189 190 static const struct soc15_reg_golden golden_settings_sdma_rv1[] = 191 { 192 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002), 193 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002) 194 }; 195 196 static const struct soc15_reg_golden golden_settings_sdma_rv2[] = 197 { 198 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00003001), 199 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003001) 200 }; 201 202 static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev, 203 u32 instance, u32 offset) 204 { 205 return ( 0 == instance ? (adev->reg_offset[SDMA0_HWIP][0][0] + offset) : 206 (adev->reg_offset[SDMA1_HWIP][0][0] + offset)); 207 } 208 209 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) 210 { 211 switch (adev->asic_type) { 212 case CHIP_VEGA10: 213 soc15_program_register_sequence(adev, 214 golden_settings_sdma_4, 215 ARRAY_SIZE(golden_settings_sdma_4)); 216 soc15_program_register_sequence(adev, 217 golden_settings_sdma_vg10, 218 ARRAY_SIZE(golden_settings_sdma_vg10)); 219 break; 220 case CHIP_VEGA12: 221 soc15_program_register_sequence(adev, 222 golden_settings_sdma_4, 223 ARRAY_SIZE(golden_settings_sdma_4)); 224 soc15_program_register_sequence(adev, 225 golden_settings_sdma_vg12, 226 ARRAY_SIZE(golden_settings_sdma_vg12)); 227 break; 228 case CHIP_VEGA20: 229 soc15_program_register_sequence(adev, 230 golden_settings_sdma0_4_2_init, 231 ARRAY_SIZE(golden_settings_sdma0_4_2_init)); 232 soc15_program_register_sequence(adev, 233 golden_settings_sdma0_4_2, 234 ARRAY_SIZE(golden_settings_sdma0_4_2)); 235 soc15_program_register_sequence(adev, 236 golden_settings_sdma1_4_2, 237 ARRAY_SIZE(golden_settings_sdma1_4_2)); 238 break; 239 case CHIP_RAVEN: 240 soc15_program_register_sequence(adev, 241 golden_settings_sdma_4_1, 242 ARRAY_SIZE(golden_settings_sdma_4_1)); 243 if (adev->rev_id >= 8) 244 soc15_program_register_sequence(adev, 245 golden_settings_sdma_rv2, 246 ARRAY_SIZE(golden_settings_sdma_rv2)); 247 else 248 soc15_program_register_sequence(adev, 249 golden_settings_sdma_rv1, 250 ARRAY_SIZE(golden_settings_sdma_rv1)); 251 break; 252 default: 253 break; 254 } 255 } 256 257 /** 258 * sdma_v4_0_init_microcode - load ucode images from disk 259 * 260 * @adev: amdgpu_device pointer 261 * 262 * Use the firmware interface to load the ucode images into 263 * the driver (not loaded into hw). 264 * Returns 0 on success, error on failure. 265 */ 266 267 // emulation only, won't work on real chip 268 // vega10 real chip need to use PSP to load firmware 269 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev) 270 { 271 const char *chip_name; 272 char fw_name[30]; 273 int err = 0, i; 274 struct amdgpu_firmware_info *info = NULL; 275 const struct common_firmware_header *header = NULL; 276 const struct sdma_firmware_header_v1_0 *hdr; 277 278 DRM_DEBUG("\n"); 279 280 switch (adev->asic_type) { 281 case CHIP_VEGA10: 282 chip_name = "vega10"; 283 break; 284 case CHIP_VEGA12: 285 chip_name = "vega12"; 286 break; 287 case CHIP_VEGA20: 288 chip_name = "vega20"; 289 break; 290 case CHIP_RAVEN: 291 if (adev->rev_id >= 8) 292 chip_name = "raven2"; 293 else if (adev->pdev->device == 0x15d8) 294 chip_name = "picasso"; 295 else 296 chip_name = "raven"; 297 break; 298 default: 299 BUG(); 300 } 301 302 for (i = 0; i < adev->sdma.num_instances; i++) { 303 if (i == 0) 304 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 305 else 306 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); 307 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 308 if (err) 309 goto out; 310 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); 311 if (err) 312 goto out; 313 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 314 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 315 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 316 if (adev->sdma.instance[i].feature_version >= 20) 317 adev->sdma.instance[i].burst_nop = true; 318 DRM_DEBUG("psp_load == '%s'\n", 319 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); 320 321 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 322 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 323 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 324 info->fw = adev->sdma.instance[i].fw; 325 header = (const struct common_firmware_header *)info->fw->data; 326 adev->firmware.fw_size += 327 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 328 } 329 } 330 out: 331 if (err) { 332 DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name); 333 for (i = 0; i < adev->sdma.num_instances; i++) { 334 release_firmware(adev->sdma.instance[i].fw); 335 adev->sdma.instance[i].fw = NULL; 336 } 337 } 338 return err; 339 } 340 341 /** 342 * sdma_v4_0_ring_get_rptr - get the current read pointer 343 * 344 * @ring: amdgpu ring pointer 345 * 346 * Get the current rptr from the hardware (VEGA10+). 347 */ 348 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring) 349 { 350 u64 *rptr; 351 352 /* XXX check if swapping is necessary on BE */ 353 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]); 354 355 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 356 return ((*rptr) >> 2); 357 } 358 359 /** 360 * sdma_v4_0_ring_get_wptr - get the current write pointer 361 * 362 * @ring: amdgpu ring pointer 363 * 364 * Get the current wptr from the hardware (VEGA10+). 365 */ 366 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring) 367 { 368 struct amdgpu_device *adev = ring->adev; 369 u64 wptr; 370 371 if (ring->use_doorbell) { 372 /* XXX check if swapping is necessary on BE */ 373 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 374 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 375 } else { 376 wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI); 377 wptr = wptr << 32; 378 wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR); 379 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", 380 ring->me, wptr); 381 } 382 383 return wptr >> 2; 384 } 385 386 /** 387 * sdma_v4_0_ring_set_wptr - commit the write pointer 388 * 389 * @ring: amdgpu ring pointer 390 * 391 * Write the wptr back to the hardware (VEGA10+). 392 */ 393 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring) 394 { 395 struct amdgpu_device *adev = ring->adev; 396 397 DRM_DEBUG("Setting write pointer\n"); 398 if (ring->use_doorbell) { 399 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 400 401 DRM_DEBUG("Using doorbell -- " 402 "wptr_offs == 0x%08x " 403 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 404 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 405 ring->wptr_offs, 406 lower_32_bits(ring->wptr << 2), 407 upper_32_bits(ring->wptr << 2)); 408 /* XXX check if swapping is necessary on BE */ 409 WRITE_ONCE(*wb, (ring->wptr << 2)); 410 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 411 ring->doorbell_index, ring->wptr << 2); 412 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 413 } else { 414 DRM_DEBUG("Not using doorbell -- " 415 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 416 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 417 ring->me, 418 lower_32_bits(ring->wptr << 2), 419 ring->me, 420 upper_32_bits(ring->wptr << 2)); 421 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR, 422 lower_32_bits(ring->wptr << 2)); 423 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI, 424 upper_32_bits(ring->wptr << 2)); 425 } 426 } 427 428 /** 429 * sdma_v4_0_page_ring_get_wptr - get the current write pointer 430 * 431 * @ring: amdgpu ring pointer 432 * 433 * Get the current wptr from the hardware (VEGA10+). 434 */ 435 static uint64_t sdma_v4_0_page_ring_get_wptr(struct amdgpu_ring *ring) 436 { 437 struct amdgpu_device *adev = ring->adev; 438 u64 wptr; 439 440 if (ring->use_doorbell) { 441 /* XXX check if swapping is necessary on BE */ 442 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 443 } else { 444 wptr = RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI); 445 wptr = wptr << 32; 446 wptr |= RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR); 447 } 448 449 return wptr >> 2; 450 } 451 452 /** 453 * sdma_v4_0_ring_set_wptr - commit the write pointer 454 * 455 * @ring: amdgpu ring pointer 456 * 457 * Write the wptr back to the hardware (VEGA10+). 458 */ 459 static void sdma_v4_0_page_ring_set_wptr(struct amdgpu_ring *ring) 460 { 461 struct amdgpu_device *adev = ring->adev; 462 463 if (ring->use_doorbell) { 464 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 465 466 /* XXX check if swapping is necessary on BE */ 467 WRITE_ONCE(*wb, (ring->wptr << 2)); 468 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 469 } else { 470 uint64_t wptr = ring->wptr << 2; 471 472 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR, 473 lower_32_bits(wptr)); 474 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI, 475 upper_32_bits(wptr)); 476 } 477 } 478 479 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 480 { 481 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 482 int i; 483 484 for (i = 0; i < count; i++) 485 if (sdma && sdma->burst_nop && (i == 0)) 486 amdgpu_ring_write(ring, ring->funcs->nop | 487 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 488 else 489 amdgpu_ring_write(ring, ring->funcs->nop); 490 } 491 492 /** 493 * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine 494 * 495 * @ring: amdgpu ring pointer 496 * @ib: IB object to schedule 497 * 498 * Schedule an IB in the DMA ring (VEGA10). 499 */ 500 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring, 501 struct amdgpu_job *job, 502 struct amdgpu_ib *ib, 503 uint32_t flags) 504 { 505 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 506 507 /* IB packet must end on a 8 DW boundary */ 508 sdma_v4_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8); 509 510 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 511 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 512 /* base must be 32 byte aligned */ 513 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 514 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 515 amdgpu_ring_write(ring, ib->length_dw); 516 amdgpu_ring_write(ring, 0); 517 amdgpu_ring_write(ring, 0); 518 519 } 520 521 static void sdma_v4_0_wait_reg_mem(struct amdgpu_ring *ring, 522 int mem_space, int hdp, 523 uint32_t addr0, uint32_t addr1, 524 uint32_t ref, uint32_t mask, 525 uint32_t inv) 526 { 527 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 528 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) | 529 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) | 530 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 531 if (mem_space) { 532 /* memory */ 533 amdgpu_ring_write(ring, addr0); 534 amdgpu_ring_write(ring, addr1); 535 } else { 536 /* registers */ 537 amdgpu_ring_write(ring, addr0 << 2); 538 amdgpu_ring_write(ring, addr1 << 2); 539 } 540 amdgpu_ring_write(ring, ref); /* reference */ 541 amdgpu_ring_write(ring, mask); /* mask */ 542 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 543 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */ 544 } 545 546 /** 547 * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 548 * 549 * @ring: amdgpu ring pointer 550 * 551 * Emit an hdp flush packet on the requested DMA ring. 552 */ 553 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 554 { 555 struct amdgpu_device *adev = ring->adev; 556 u32 ref_and_mask = 0; 557 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg; 558 559 if (ring->me == 0) 560 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0; 561 else 562 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1; 563 564 sdma_v4_0_wait_reg_mem(ring, 0, 1, 565 adev->nbio_funcs->get_hdp_flush_done_offset(adev), 566 adev->nbio_funcs->get_hdp_flush_req_offset(adev), 567 ref_and_mask, ref_and_mask, 10); 568 } 569 570 /** 571 * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring 572 * 573 * @ring: amdgpu ring pointer 574 * @fence: amdgpu fence object 575 * 576 * Add a DMA fence packet to the ring to write 577 * the fence seq number and DMA trap packet to generate 578 * an interrupt if needed (VEGA10). 579 */ 580 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 581 unsigned flags) 582 { 583 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 584 /* write the fence */ 585 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 586 /* zero in first two bits */ 587 BUG_ON(addr & 0x3); 588 amdgpu_ring_write(ring, lower_32_bits(addr)); 589 amdgpu_ring_write(ring, upper_32_bits(addr)); 590 amdgpu_ring_write(ring, lower_32_bits(seq)); 591 592 /* optionally write high bits as well */ 593 if (write64bit) { 594 addr += 4; 595 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 596 /* zero in first two bits */ 597 BUG_ON(addr & 0x3); 598 amdgpu_ring_write(ring, lower_32_bits(addr)); 599 amdgpu_ring_write(ring, upper_32_bits(addr)); 600 amdgpu_ring_write(ring, upper_32_bits(seq)); 601 } 602 603 /* generate an interrupt */ 604 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 605 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 606 } 607 608 609 /** 610 * sdma_v4_0_gfx_stop - stop the gfx async dma engines 611 * 612 * @adev: amdgpu_device pointer 613 * 614 * Stop the gfx async dma ring buffers (VEGA10). 615 */ 616 static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev) 617 { 618 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 619 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 620 u32 rb_cntl, ib_cntl; 621 int i; 622 623 if ((adev->mman.buffer_funcs_ring == sdma0) || 624 (adev->mman.buffer_funcs_ring == sdma1)) 625 amdgpu_ttm_set_buffer_funcs_status(adev, false); 626 627 for (i = 0; i < adev->sdma.num_instances; i++) { 628 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL); 629 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 630 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 631 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL); 632 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 633 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl); 634 } 635 636 sdma0->sched.ready = false; 637 sdma1->sched.ready = false; 638 } 639 640 /** 641 * sdma_v4_0_rlc_stop - stop the compute async dma engines 642 * 643 * @adev: amdgpu_device pointer 644 * 645 * Stop the compute async dma queues (VEGA10). 646 */ 647 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev) 648 { 649 /* XXX todo */ 650 } 651 652 /** 653 * sdma_v4_0_page_stop - stop the page async dma engines 654 * 655 * @adev: amdgpu_device pointer 656 * 657 * Stop the page async dma ring buffers (VEGA10). 658 */ 659 static void sdma_v4_0_page_stop(struct amdgpu_device *adev) 660 { 661 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].page; 662 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].page; 663 u32 rb_cntl, ib_cntl; 664 int i; 665 666 if ((adev->mman.buffer_funcs_ring == sdma0) || 667 (adev->mman.buffer_funcs_ring == sdma1)) 668 amdgpu_ttm_set_buffer_funcs_status(adev, false); 669 670 for (i = 0; i < adev->sdma.num_instances; i++) { 671 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL); 672 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, 673 RB_ENABLE, 0); 674 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 675 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL); 676 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, 677 IB_ENABLE, 0); 678 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl); 679 } 680 681 sdma0->sched.ready = false; 682 sdma1->sched.ready = false; 683 } 684 685 /** 686 * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch 687 * 688 * @adev: amdgpu_device pointer 689 * @enable: enable/disable the DMA MEs context switch. 690 * 691 * Halt or unhalt the async dma engines context switch (VEGA10). 692 */ 693 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 694 { 695 u32 f32_cntl, phase_quantum = 0; 696 int i; 697 698 if (amdgpu_sdma_phase_quantum) { 699 unsigned value = amdgpu_sdma_phase_quantum; 700 unsigned unit = 0; 701 702 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 703 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 704 value = (value + 1) >> 1; 705 unit++; 706 } 707 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 708 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 709 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 710 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 711 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 712 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 713 WARN_ONCE(1, 714 "clamping sdma_phase_quantum to %uK clock cycles\n", 715 value << unit); 716 } 717 phase_quantum = 718 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 719 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 720 } 721 722 for (i = 0; i < adev->sdma.num_instances; i++) { 723 f32_cntl = RREG32_SDMA(i, mmSDMA0_CNTL); 724 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 725 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 726 if (enable && amdgpu_sdma_phase_quantum) { 727 WREG32_SDMA(i, mmSDMA0_PHASE0_QUANTUM, phase_quantum); 728 WREG32_SDMA(i, mmSDMA0_PHASE1_QUANTUM, phase_quantum); 729 WREG32_SDMA(i, mmSDMA0_PHASE2_QUANTUM, phase_quantum); 730 } 731 WREG32_SDMA(i, mmSDMA0_CNTL, f32_cntl); 732 } 733 734 } 735 736 /** 737 * sdma_v4_0_enable - stop the async dma engines 738 * 739 * @adev: amdgpu_device pointer 740 * @enable: enable/disable the DMA MEs. 741 * 742 * Halt or unhalt the async dma engines (VEGA10). 743 */ 744 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable) 745 { 746 u32 f32_cntl; 747 int i; 748 749 if (enable == false) { 750 sdma_v4_0_gfx_stop(adev); 751 sdma_v4_0_rlc_stop(adev); 752 if (adev->sdma.has_page_queue) 753 sdma_v4_0_page_stop(adev); 754 } 755 756 for (i = 0; i < adev->sdma.num_instances; i++) { 757 f32_cntl = RREG32_SDMA(i, mmSDMA0_F32_CNTL); 758 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 759 WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl); 760 } 761 } 762 763 /** 764 * sdma_v4_0_rb_cntl - get parameters for rb_cntl 765 */ 766 static uint32_t sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl) 767 { 768 /* Set ring buffer size in dwords */ 769 uint32_t rb_bufsz = order_base_2(ring->ring_size / 4); 770 771 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 772 #ifdef __BIG_ENDIAN 773 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 774 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 775 RPTR_WRITEBACK_SWAP_ENABLE, 1); 776 #endif 777 return rb_cntl; 778 } 779 780 /** 781 * sdma_v4_0_gfx_resume - setup and start the async dma engines 782 * 783 * @adev: amdgpu_device pointer 784 * @i: instance to resume 785 * 786 * Set up the gfx DMA ring buffers and enable them (VEGA10). 787 * Returns 0 for success, error for failure. 788 */ 789 static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i) 790 { 791 struct amdgpu_ring *ring = &adev->sdma.instance[i].ring; 792 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 793 u32 wb_offset; 794 u32 doorbell; 795 u32 doorbell_offset; 796 u64 wptr_gpu_addr; 797 798 wb_offset = (ring->rptr_offs * 4); 799 800 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL); 801 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl); 802 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 803 804 /* Initialize the ring buffer's read and write pointers */ 805 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR, 0); 806 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_HI, 0); 807 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR, 0); 808 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_HI, 0); 809 810 /* set the wb address whether it's enabled or not */ 811 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI, 812 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 813 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 814 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 815 816 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 817 RPTR_WRITEBACK_ENABLE, 1); 818 819 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE, ring->gpu_addr >> 8); 820 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE_HI, ring->gpu_addr >> 40); 821 822 ring->wptr = 0; 823 824 /* before programing wptr to a less value, need set minor_ptr_update first */ 825 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 1); 826 827 doorbell = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL); 828 doorbell_offset = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET); 829 830 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 831 ring->use_doorbell); 832 doorbell_offset = REG_SET_FIELD(doorbell_offset, 833 SDMA0_GFX_DOORBELL_OFFSET, 834 OFFSET, ring->doorbell_index); 835 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL, doorbell); 836 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET, doorbell_offset); 837 838 sdma_v4_0_ring_set_wptr(ring); 839 840 /* set minor_ptr_update to 0 after wptr programed */ 841 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 0); 842 843 /* setup the wptr shadow polling */ 844 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 845 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO, 846 lower_32_bits(wptr_gpu_addr)); 847 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI, 848 upper_32_bits(wptr_gpu_addr)); 849 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL); 850 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 851 SDMA0_GFX_RB_WPTR_POLL_CNTL, 852 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)); 853 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 854 855 /* enable DMA RB */ 856 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 857 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 858 859 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL); 860 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 861 #ifdef __BIG_ENDIAN 862 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 863 #endif 864 /* enable DMA IBs */ 865 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl); 866 867 ring->sched.ready = true; 868 } 869 870 /** 871 * sdma_v4_0_page_resume - setup and start the async dma engines 872 * 873 * @adev: amdgpu_device pointer 874 * @i: instance to resume 875 * 876 * Set up the page DMA ring buffers and enable them (VEGA10). 877 * Returns 0 for success, error for failure. 878 */ 879 static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i) 880 { 881 struct amdgpu_ring *ring = &adev->sdma.instance[i].page; 882 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 883 u32 wb_offset; 884 u32 doorbell; 885 u32 doorbell_offset; 886 u64 wptr_gpu_addr; 887 888 wb_offset = (ring->rptr_offs * 4); 889 890 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL); 891 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl); 892 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 893 894 /* Initialize the ring buffer's read and write pointers */ 895 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR, 0); 896 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_HI, 0); 897 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR, 0); 898 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_HI, 0); 899 900 /* set the wb address whether it's enabled or not */ 901 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_HI, 902 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 903 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 904 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 905 906 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, 907 RPTR_WRITEBACK_ENABLE, 1); 908 909 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE, ring->gpu_addr >> 8); 910 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE_HI, ring->gpu_addr >> 40); 911 912 ring->wptr = 0; 913 914 /* before programing wptr to a less value, need set minor_ptr_update first */ 915 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 1); 916 917 doorbell = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL); 918 doorbell_offset = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET); 919 920 doorbell = REG_SET_FIELD(doorbell, SDMA0_PAGE_DOORBELL, ENABLE, 921 ring->use_doorbell); 922 doorbell_offset = REG_SET_FIELD(doorbell_offset, 923 SDMA0_PAGE_DOORBELL_OFFSET, 924 OFFSET, ring->doorbell_index); 925 WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL, doorbell); 926 WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET, doorbell_offset); 927 928 /* paging queue doorbell range is setup at sdma_v4_0_gfx_resume */ 929 sdma_v4_0_page_ring_set_wptr(ring); 930 931 /* set minor_ptr_update to 0 after wptr programed */ 932 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 0); 933 934 /* setup the wptr shadow polling */ 935 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 936 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO, 937 lower_32_bits(wptr_gpu_addr)); 938 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI, 939 upper_32_bits(wptr_gpu_addr)); 940 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL); 941 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 942 SDMA0_PAGE_RB_WPTR_POLL_CNTL, 943 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)); 944 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 945 946 /* enable DMA RB */ 947 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, RB_ENABLE, 1); 948 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 949 950 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL); 951 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_ENABLE, 1); 952 #ifdef __BIG_ENDIAN 953 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1); 954 #endif 955 /* enable DMA IBs */ 956 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl); 957 958 ring->sched.ready = true; 959 } 960 961 static void 962 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable) 963 { 964 uint32_t def, data; 965 966 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) { 967 /* enable idle interrupt */ 968 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 969 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 970 971 if (data != def) 972 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 973 } else { 974 /* disable idle interrupt */ 975 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 976 data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 977 if (data != def) 978 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 979 } 980 } 981 982 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev) 983 { 984 uint32_t def, data; 985 986 /* Enable HW based PG. */ 987 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 988 data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK; 989 if (data != def) 990 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 991 992 /* enable interrupt */ 993 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 994 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 995 if (data != def) 996 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 997 998 /* Configure hold time to filter in-valid power on/off request. Use default right now */ 999 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1000 data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK; 1001 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK); 1002 /* Configure switch time for hysteresis purpose. Use default right now */ 1003 data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK; 1004 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK); 1005 if(data != def) 1006 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1007 } 1008 1009 static void sdma_v4_0_init_pg(struct amdgpu_device *adev) 1010 { 1011 if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA)) 1012 return; 1013 1014 switch (adev->asic_type) { 1015 case CHIP_RAVEN: 1016 sdma_v4_1_init_power_gating(adev); 1017 sdma_v4_1_update_power_gating(adev, true); 1018 break; 1019 default: 1020 break; 1021 } 1022 } 1023 1024 /** 1025 * sdma_v4_0_rlc_resume - setup and start the async dma engines 1026 * 1027 * @adev: amdgpu_device pointer 1028 * 1029 * Set up the compute DMA queues and enable them (VEGA10). 1030 * Returns 0 for success, error for failure. 1031 */ 1032 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev) 1033 { 1034 sdma_v4_0_init_pg(adev); 1035 1036 return 0; 1037 } 1038 1039 /** 1040 * sdma_v4_0_load_microcode - load the sDMA ME ucode 1041 * 1042 * @adev: amdgpu_device pointer 1043 * 1044 * Loads the sDMA0/1 ucode. 1045 * Returns 0 for success, -EINVAL if the ucode is not available. 1046 */ 1047 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev) 1048 { 1049 const struct sdma_firmware_header_v1_0 *hdr; 1050 const __le32 *fw_data; 1051 u32 fw_size; 1052 int i, j; 1053 1054 /* halt the MEs */ 1055 sdma_v4_0_enable(adev, false); 1056 1057 for (i = 0; i < adev->sdma.num_instances; i++) { 1058 if (!adev->sdma.instance[i].fw) 1059 return -EINVAL; 1060 1061 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 1062 amdgpu_ucode_print_sdma_hdr(&hdr->header); 1063 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1064 1065 fw_data = (const __le32 *) 1066 (adev->sdma.instance[i].fw->data + 1067 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1068 1069 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 0); 1070 1071 for (j = 0; j < fw_size; j++) 1072 WREG32_SDMA(i, mmSDMA0_UCODE_DATA, 1073 le32_to_cpup(fw_data++)); 1074 1075 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 1076 adev->sdma.instance[i].fw_version); 1077 } 1078 1079 return 0; 1080 } 1081 1082 /** 1083 * sdma_v4_0_start - setup and start the async dma engines 1084 * 1085 * @adev: amdgpu_device pointer 1086 * 1087 * Set up the DMA engines and enable them (VEGA10). 1088 * Returns 0 for success, error for failure. 1089 */ 1090 static int sdma_v4_0_start(struct amdgpu_device *adev) 1091 { 1092 struct amdgpu_ring *ring; 1093 int i, r; 1094 1095 if (amdgpu_sriov_vf(adev)) { 1096 sdma_v4_0_ctx_switch_enable(adev, false); 1097 sdma_v4_0_enable(adev, false); 1098 } else { 1099 1100 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1101 r = sdma_v4_0_load_microcode(adev); 1102 if (r) 1103 return r; 1104 } 1105 1106 /* unhalt the MEs */ 1107 sdma_v4_0_enable(adev, true); 1108 /* enable sdma ring preemption */ 1109 sdma_v4_0_ctx_switch_enable(adev, true); 1110 } 1111 1112 /* start the gfx rings and rlc compute queues */ 1113 for (i = 0; i < adev->sdma.num_instances; i++) { 1114 uint32_t temp; 1115 1116 WREG32_SDMA(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL, 0); 1117 sdma_v4_0_gfx_resume(adev, i); 1118 if (adev->sdma.has_page_queue) 1119 sdma_v4_0_page_resume(adev, i); 1120 1121 /* set utc l1 enable flag always to 1 */ 1122 temp = RREG32_SDMA(i, mmSDMA0_CNTL); 1123 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 1124 WREG32_SDMA(i, mmSDMA0_CNTL, temp); 1125 1126 if (!amdgpu_sriov_vf(adev)) { 1127 /* unhalt engine */ 1128 temp = RREG32_SDMA(i, mmSDMA0_F32_CNTL); 1129 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 1130 WREG32_SDMA(i, mmSDMA0_F32_CNTL, temp); 1131 } 1132 } 1133 1134 if (amdgpu_sriov_vf(adev)) { 1135 sdma_v4_0_ctx_switch_enable(adev, true); 1136 sdma_v4_0_enable(adev, true); 1137 } else { 1138 r = sdma_v4_0_rlc_resume(adev); 1139 if (r) 1140 return r; 1141 } 1142 1143 for (i = 0; i < adev->sdma.num_instances; i++) { 1144 ring = &adev->sdma.instance[i].ring; 1145 1146 r = amdgpu_ring_test_helper(ring); 1147 if (r) 1148 return r; 1149 1150 if (adev->sdma.has_page_queue) { 1151 struct amdgpu_ring *page = &adev->sdma.instance[i].page; 1152 1153 r = amdgpu_ring_test_helper(page); 1154 if (r) 1155 return r; 1156 1157 if (adev->mman.buffer_funcs_ring == page) 1158 amdgpu_ttm_set_buffer_funcs_status(adev, true); 1159 } 1160 1161 if (adev->mman.buffer_funcs_ring == ring) 1162 amdgpu_ttm_set_buffer_funcs_status(adev, true); 1163 } 1164 1165 return r; 1166 } 1167 1168 /** 1169 * sdma_v4_0_ring_test_ring - simple async dma engine test 1170 * 1171 * @ring: amdgpu_ring structure holding ring information 1172 * 1173 * Test the DMA engine by writing using it to write an 1174 * value to memory. (VEGA10). 1175 * Returns 0 for success, error for failure. 1176 */ 1177 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring) 1178 { 1179 struct amdgpu_device *adev = ring->adev; 1180 unsigned i; 1181 unsigned index; 1182 int r; 1183 u32 tmp; 1184 u64 gpu_addr; 1185 1186 r = amdgpu_device_wb_get(adev, &index); 1187 if (r) 1188 return r; 1189 1190 gpu_addr = adev->wb.gpu_addr + (index * 4); 1191 tmp = 0xCAFEDEAD; 1192 adev->wb.wb[index] = cpu_to_le32(tmp); 1193 1194 r = amdgpu_ring_alloc(ring, 5); 1195 if (r) 1196 goto error_free_wb; 1197 1198 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1199 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 1200 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 1201 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 1202 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 1203 amdgpu_ring_write(ring, 0xDEADBEEF); 1204 amdgpu_ring_commit(ring); 1205 1206 for (i = 0; i < adev->usec_timeout; i++) { 1207 tmp = le32_to_cpu(adev->wb.wb[index]); 1208 if (tmp == 0xDEADBEEF) 1209 break; 1210 DRM_UDELAY(1); 1211 } 1212 1213 if (i >= adev->usec_timeout) 1214 r = -ETIMEDOUT; 1215 1216 error_free_wb: 1217 amdgpu_device_wb_free(adev, index); 1218 return r; 1219 } 1220 1221 /** 1222 * sdma_v4_0_ring_test_ib - test an IB on the DMA engine 1223 * 1224 * @ring: amdgpu_ring structure holding ring information 1225 * 1226 * Test a simple IB in the DMA ring (VEGA10). 1227 * Returns 0 on success, error on failure. 1228 */ 1229 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1230 { 1231 struct amdgpu_device *adev = ring->adev; 1232 struct amdgpu_ib ib; 1233 struct dma_fence *f = NULL; 1234 unsigned index; 1235 long r; 1236 u32 tmp = 0; 1237 u64 gpu_addr; 1238 1239 r = amdgpu_device_wb_get(adev, &index); 1240 if (r) 1241 return r; 1242 1243 gpu_addr = adev->wb.gpu_addr + (index * 4); 1244 tmp = 0xCAFEDEAD; 1245 adev->wb.wb[index] = cpu_to_le32(tmp); 1246 memset(&ib, 0, sizeof(ib)); 1247 r = amdgpu_ib_get(adev, NULL, 256, &ib); 1248 if (r) 1249 goto err0; 1250 1251 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1252 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1253 ib.ptr[1] = lower_32_bits(gpu_addr); 1254 ib.ptr[2] = upper_32_bits(gpu_addr); 1255 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1256 ib.ptr[4] = 0xDEADBEEF; 1257 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1258 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1259 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1260 ib.length_dw = 8; 1261 1262 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1263 if (r) 1264 goto err1; 1265 1266 r = dma_fence_wait_timeout(f, false, timeout); 1267 if (r == 0) { 1268 r = -ETIMEDOUT; 1269 goto err1; 1270 } else if (r < 0) { 1271 goto err1; 1272 } 1273 tmp = le32_to_cpu(adev->wb.wb[index]); 1274 if (tmp == 0xDEADBEEF) 1275 r = 0; 1276 else 1277 r = -EINVAL; 1278 1279 err1: 1280 amdgpu_ib_free(adev, &ib, NULL); 1281 dma_fence_put(f); 1282 err0: 1283 amdgpu_device_wb_free(adev, index); 1284 return r; 1285 } 1286 1287 1288 /** 1289 * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART 1290 * 1291 * @ib: indirect buffer to fill with commands 1292 * @pe: addr of the page entry 1293 * @src: src addr to copy from 1294 * @count: number of page entries to update 1295 * 1296 * Update PTEs by copying them from the GART using sDMA (VEGA10). 1297 */ 1298 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib, 1299 uint64_t pe, uint64_t src, 1300 unsigned count) 1301 { 1302 unsigned bytes = count * 8; 1303 1304 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1305 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1306 ib->ptr[ib->length_dw++] = bytes - 1; 1307 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1308 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1309 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1310 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1311 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1312 1313 } 1314 1315 /** 1316 * sdma_v4_0_vm_write_pte - update PTEs by writing them manually 1317 * 1318 * @ib: indirect buffer to fill with commands 1319 * @pe: addr of the page entry 1320 * @addr: dst addr to write into pe 1321 * @count: number of page entries to update 1322 * @incr: increase next addr by incr bytes 1323 * @flags: access flags 1324 * 1325 * Update PTEs by writing them manually using sDMA (VEGA10). 1326 */ 1327 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1328 uint64_t value, unsigned count, 1329 uint32_t incr) 1330 { 1331 unsigned ndw = count * 2; 1332 1333 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1334 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1335 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1336 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1337 ib->ptr[ib->length_dw++] = ndw - 1; 1338 for (; ndw > 0; ndw -= 2) { 1339 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1340 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1341 value += incr; 1342 } 1343 } 1344 1345 /** 1346 * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA 1347 * 1348 * @ib: indirect buffer to fill with commands 1349 * @pe: addr of the page entry 1350 * @addr: dst addr to write into pe 1351 * @count: number of page entries to update 1352 * @incr: increase next addr by incr bytes 1353 * @flags: access flags 1354 * 1355 * Update the page tables using sDMA (VEGA10). 1356 */ 1357 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1358 uint64_t pe, 1359 uint64_t addr, unsigned count, 1360 uint32_t incr, uint64_t flags) 1361 { 1362 /* for physically contiguous pages (vram) */ 1363 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1364 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1365 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1366 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1367 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1368 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1369 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1370 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1371 ib->ptr[ib->length_dw++] = 0; 1372 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1373 } 1374 1375 /** 1376 * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw 1377 * 1378 * @ib: indirect buffer to fill with padding 1379 * 1380 */ 1381 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1382 { 1383 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1384 u32 pad_count; 1385 int i; 1386 1387 pad_count = (8 - (ib->length_dw & 0x7)) % 8; 1388 for (i = 0; i < pad_count; i++) 1389 if (sdma && sdma->burst_nop && (i == 0)) 1390 ib->ptr[ib->length_dw++] = 1391 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1392 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1393 else 1394 ib->ptr[ib->length_dw++] = 1395 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1396 } 1397 1398 1399 /** 1400 * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline 1401 * 1402 * @ring: amdgpu_ring pointer 1403 * 1404 * Make sure all previous operations are completed (CIK). 1405 */ 1406 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1407 { 1408 uint32_t seq = ring->fence_drv.sync_seq; 1409 uint64_t addr = ring->fence_drv.gpu_addr; 1410 1411 /* wait for idle */ 1412 sdma_v4_0_wait_reg_mem(ring, 1, 0, 1413 addr & 0xfffffffc, 1414 upper_32_bits(addr) & 0xffffffff, 1415 seq, 0xffffffff, 4); 1416 } 1417 1418 1419 /** 1420 * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA 1421 * 1422 * @ring: amdgpu_ring pointer 1423 * @vm: amdgpu_vm pointer 1424 * 1425 * Update the page table base and flush the VM TLB 1426 * using sDMA (VEGA10). 1427 */ 1428 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1429 unsigned vmid, uint64_t pd_addr) 1430 { 1431 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1432 } 1433 1434 static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring, 1435 uint32_t reg, uint32_t val) 1436 { 1437 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1438 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1439 amdgpu_ring_write(ring, reg); 1440 amdgpu_ring_write(ring, val); 1441 } 1442 1443 static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1444 uint32_t val, uint32_t mask) 1445 { 1446 sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10); 1447 } 1448 1449 static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev) 1450 { 1451 uint fw_version = adev->sdma.instance[0].fw_version; 1452 1453 switch (adev->asic_type) { 1454 case CHIP_VEGA10: 1455 return fw_version >= 430; 1456 case CHIP_VEGA12: 1457 /*return fw_version >= 31;*/ 1458 return false; 1459 case CHIP_VEGA20: 1460 return fw_version >= 123; 1461 default: 1462 return false; 1463 } 1464 } 1465 1466 static int sdma_v4_0_early_init(void *handle) 1467 { 1468 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1469 int r; 1470 1471 if (adev->asic_type == CHIP_RAVEN) 1472 adev->sdma.num_instances = 1; 1473 else 1474 adev->sdma.num_instances = 2; 1475 1476 r = sdma_v4_0_init_microcode(adev); 1477 if (r) { 1478 DRM_ERROR("Failed to load sdma firmware!\n"); 1479 return r; 1480 } 1481 1482 /* TODO: Page queue breaks driver reload under SRIOV */ 1483 if ((adev->asic_type == CHIP_VEGA10) && amdgpu_sriov_vf((adev))) 1484 adev->sdma.has_page_queue = false; 1485 else if (sdma_v4_0_fw_support_paging_queue(adev)) 1486 adev->sdma.has_page_queue = true; 1487 1488 sdma_v4_0_set_ring_funcs(adev); 1489 sdma_v4_0_set_buffer_funcs(adev); 1490 sdma_v4_0_set_vm_pte_funcs(adev); 1491 sdma_v4_0_set_irq_funcs(adev); 1492 1493 return 0; 1494 } 1495 1496 static int sdma_v4_0_sw_init(void *handle) 1497 { 1498 struct amdgpu_ring *ring; 1499 int r, i; 1500 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1501 1502 /* SDMA trap event */ 1503 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0, SDMA0_4_0__SRCID__SDMA_TRAP, 1504 &adev->sdma.trap_irq); 1505 if (r) 1506 return r; 1507 1508 /* SDMA trap event */ 1509 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1, SDMA1_4_0__SRCID__SDMA_TRAP, 1510 &adev->sdma.trap_irq); 1511 if (r) 1512 return r; 1513 1514 for (i = 0; i < adev->sdma.num_instances; i++) { 1515 ring = &adev->sdma.instance[i].ring; 1516 ring->ring_obj = NULL; 1517 ring->use_doorbell = true; 1518 1519 DRM_INFO("use_doorbell being set to: [%s]\n", 1520 ring->use_doorbell?"true":"false"); 1521 1522 /* doorbell size is 2 dwords, get DWORD offset */ 1523 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1; 1524 1525 sprintf(ring->name, "sdma%d", i); 1526 r = amdgpu_ring_init(adev, ring, 1024, 1527 &adev->sdma.trap_irq, 1528 (i == 0) ? 1529 AMDGPU_SDMA_IRQ_TRAP0 : 1530 AMDGPU_SDMA_IRQ_TRAP1); 1531 if (r) 1532 return r; 1533 1534 if (adev->sdma.has_page_queue) { 1535 ring = &adev->sdma.instance[i].page; 1536 ring->ring_obj = NULL; 1537 ring->use_doorbell = true; 1538 1539 /* paging queue use same doorbell index/routing as gfx queue 1540 * with 0x400 (4096 dwords) offset on second doorbell page 1541 */ 1542 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1; 1543 ring->doorbell_index += 0x400; 1544 1545 sprintf(ring->name, "page%d", i); 1546 r = amdgpu_ring_init(adev, ring, 1024, 1547 &adev->sdma.trap_irq, 1548 (i == 0) ? 1549 AMDGPU_SDMA_IRQ_TRAP0 : 1550 AMDGPU_SDMA_IRQ_TRAP1); 1551 if (r) 1552 return r; 1553 } 1554 } 1555 1556 return r; 1557 } 1558 1559 static int sdma_v4_0_sw_fini(void *handle) 1560 { 1561 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1562 int i; 1563 1564 for (i = 0; i < adev->sdma.num_instances; i++) { 1565 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1566 if (adev->sdma.has_page_queue) 1567 amdgpu_ring_fini(&adev->sdma.instance[i].page); 1568 } 1569 1570 for (i = 0; i < adev->sdma.num_instances; i++) { 1571 release_firmware(adev->sdma.instance[i].fw); 1572 adev->sdma.instance[i].fw = NULL; 1573 } 1574 1575 return 0; 1576 } 1577 1578 static int sdma_v4_0_hw_init(void *handle) 1579 { 1580 int r; 1581 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1582 1583 if (adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs && 1584 adev->powerplay.pp_funcs->set_powergating_by_smu) 1585 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false); 1586 1587 sdma_v4_0_init_golden_registers(adev); 1588 1589 r = sdma_v4_0_start(adev); 1590 1591 return r; 1592 } 1593 1594 static int sdma_v4_0_hw_fini(void *handle) 1595 { 1596 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1597 1598 if (amdgpu_sriov_vf(adev)) 1599 return 0; 1600 1601 sdma_v4_0_ctx_switch_enable(adev, false); 1602 sdma_v4_0_enable(adev, false); 1603 1604 if (adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs 1605 && adev->powerplay.pp_funcs->set_powergating_by_smu) 1606 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true); 1607 1608 return 0; 1609 } 1610 1611 static int sdma_v4_0_suspend(void *handle) 1612 { 1613 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1614 1615 return sdma_v4_0_hw_fini(adev); 1616 } 1617 1618 static int sdma_v4_0_resume(void *handle) 1619 { 1620 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1621 1622 return sdma_v4_0_hw_init(adev); 1623 } 1624 1625 static bool sdma_v4_0_is_idle(void *handle) 1626 { 1627 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1628 u32 i; 1629 1630 for (i = 0; i < adev->sdma.num_instances; i++) { 1631 u32 tmp = RREG32_SDMA(i, mmSDMA0_STATUS_REG); 1632 1633 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1634 return false; 1635 } 1636 1637 return true; 1638 } 1639 1640 static int sdma_v4_0_wait_for_idle(void *handle) 1641 { 1642 unsigned i; 1643 u32 sdma0, sdma1; 1644 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1645 1646 for (i = 0; i < adev->usec_timeout; i++) { 1647 sdma0 = RREG32_SDMA(0, mmSDMA0_STATUS_REG); 1648 sdma1 = RREG32_SDMA(1, mmSDMA0_STATUS_REG); 1649 1650 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK) 1651 return 0; 1652 udelay(1); 1653 } 1654 return -ETIMEDOUT; 1655 } 1656 1657 static int sdma_v4_0_soft_reset(void *handle) 1658 { 1659 /* todo */ 1660 1661 return 0; 1662 } 1663 1664 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev, 1665 struct amdgpu_irq_src *source, 1666 unsigned type, 1667 enum amdgpu_interrupt_state state) 1668 { 1669 unsigned int instance = (type == AMDGPU_SDMA_IRQ_TRAP0) ? 0 : 1; 1670 u32 sdma_cntl; 1671 1672 sdma_cntl = RREG32_SDMA(instance, mmSDMA0_CNTL); 1673 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1674 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1675 WREG32_SDMA(instance, mmSDMA0_CNTL, sdma_cntl); 1676 1677 return 0; 1678 } 1679 1680 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev, 1681 struct amdgpu_irq_src *source, 1682 struct amdgpu_iv_entry *entry) 1683 { 1684 uint32_t instance; 1685 1686 DRM_DEBUG("IH: SDMA trap\n"); 1687 switch (entry->client_id) { 1688 case SOC15_IH_CLIENTID_SDMA0: 1689 instance = 0; 1690 break; 1691 case SOC15_IH_CLIENTID_SDMA1: 1692 instance = 1; 1693 break; 1694 default: 1695 return 0; 1696 } 1697 1698 switch (entry->ring_id) { 1699 case 0: 1700 amdgpu_fence_process(&adev->sdma.instance[instance].ring); 1701 break; 1702 case 1: 1703 if (adev->asic_type == CHIP_VEGA20) 1704 amdgpu_fence_process(&adev->sdma.instance[instance].page); 1705 break; 1706 case 2: 1707 /* XXX compute */ 1708 break; 1709 case 3: 1710 if (adev->asic_type != CHIP_VEGA20) 1711 amdgpu_fence_process(&adev->sdma.instance[instance].page); 1712 break; 1713 } 1714 return 0; 1715 } 1716 1717 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1718 struct amdgpu_irq_src *source, 1719 struct amdgpu_iv_entry *entry) 1720 { 1721 int instance; 1722 1723 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1724 1725 switch (entry->client_id) { 1726 case SOC15_IH_CLIENTID_SDMA0: 1727 instance = 0; 1728 break; 1729 case SOC15_IH_CLIENTID_SDMA1: 1730 instance = 1; 1731 break; 1732 default: 1733 return 0; 1734 } 1735 1736 switch (entry->ring_id) { 1737 case 0: 1738 drm_sched_fault(&adev->sdma.instance[instance].ring.sched); 1739 break; 1740 } 1741 return 0; 1742 } 1743 1744 static void sdma_v4_0_update_medium_grain_clock_gating( 1745 struct amdgpu_device *adev, 1746 bool enable) 1747 { 1748 uint32_t data, def; 1749 1750 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1751 /* enable sdma0 clock gating */ 1752 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 1753 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1754 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1755 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1756 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1757 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1758 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1759 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1760 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1761 if (def != data) 1762 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data); 1763 1764 if (adev->sdma.num_instances > 1) { 1765 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL)); 1766 data &= ~(SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1767 SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1768 SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1769 SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1770 SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1771 SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1772 SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1773 SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1774 if (def != data) 1775 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data); 1776 } 1777 } else { 1778 /* disable sdma0 clock gating */ 1779 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 1780 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1781 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1782 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1783 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1784 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1785 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1786 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1787 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1788 1789 if (def != data) 1790 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data); 1791 1792 if (adev->sdma.num_instances > 1) { 1793 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL)); 1794 data |= (SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1795 SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1796 SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1797 SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1798 SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1799 SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1800 SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1801 SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1802 if (def != data) 1803 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data); 1804 } 1805 } 1806 } 1807 1808 1809 static void sdma_v4_0_update_medium_grain_light_sleep( 1810 struct amdgpu_device *adev, 1811 bool enable) 1812 { 1813 uint32_t data, def; 1814 1815 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1816 /* 1-not override: enable sdma0 mem light sleep */ 1817 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1818 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1819 if (def != data) 1820 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1821 1822 /* 1-not override: enable sdma1 mem light sleep */ 1823 if (adev->sdma.num_instances > 1) { 1824 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL)); 1825 data |= SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1826 if (def != data) 1827 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data); 1828 } 1829 } else { 1830 /* 0-override:disable sdma0 mem light sleep */ 1831 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1832 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1833 if (def != data) 1834 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1835 1836 /* 0-override:disable sdma1 mem light sleep */ 1837 if (adev->sdma.num_instances > 1) { 1838 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL)); 1839 data &= ~SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1840 if (def != data) 1841 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data); 1842 } 1843 } 1844 } 1845 1846 static int sdma_v4_0_set_clockgating_state(void *handle, 1847 enum amd_clockgating_state state) 1848 { 1849 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1850 1851 if (amdgpu_sriov_vf(adev)) 1852 return 0; 1853 1854 switch (adev->asic_type) { 1855 case CHIP_VEGA10: 1856 case CHIP_VEGA12: 1857 case CHIP_VEGA20: 1858 case CHIP_RAVEN: 1859 sdma_v4_0_update_medium_grain_clock_gating(adev, 1860 state == AMD_CG_STATE_GATE ? true : false); 1861 sdma_v4_0_update_medium_grain_light_sleep(adev, 1862 state == AMD_CG_STATE_GATE ? true : false); 1863 break; 1864 default: 1865 break; 1866 } 1867 return 0; 1868 } 1869 1870 static int sdma_v4_0_set_powergating_state(void *handle, 1871 enum amd_powergating_state state) 1872 { 1873 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1874 1875 switch (adev->asic_type) { 1876 case CHIP_RAVEN: 1877 sdma_v4_1_update_power_gating(adev, 1878 state == AMD_PG_STATE_GATE ? true : false); 1879 break; 1880 default: 1881 break; 1882 } 1883 1884 return 0; 1885 } 1886 1887 static void sdma_v4_0_get_clockgating_state(void *handle, u32 *flags) 1888 { 1889 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1890 int data; 1891 1892 if (amdgpu_sriov_vf(adev)) 1893 *flags = 0; 1894 1895 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1896 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 1897 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK)) 1898 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1899 1900 /* AMD_CG_SUPPORT_SDMA_LS */ 1901 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1902 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1903 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1904 } 1905 1906 const struct amd_ip_funcs sdma_v4_0_ip_funcs = { 1907 .name = "sdma_v4_0", 1908 .early_init = sdma_v4_0_early_init, 1909 .late_init = NULL, 1910 .sw_init = sdma_v4_0_sw_init, 1911 .sw_fini = sdma_v4_0_sw_fini, 1912 .hw_init = sdma_v4_0_hw_init, 1913 .hw_fini = sdma_v4_0_hw_fini, 1914 .suspend = sdma_v4_0_suspend, 1915 .resume = sdma_v4_0_resume, 1916 .is_idle = sdma_v4_0_is_idle, 1917 .wait_for_idle = sdma_v4_0_wait_for_idle, 1918 .soft_reset = sdma_v4_0_soft_reset, 1919 .set_clockgating_state = sdma_v4_0_set_clockgating_state, 1920 .set_powergating_state = sdma_v4_0_set_powergating_state, 1921 .get_clockgating_state = sdma_v4_0_get_clockgating_state, 1922 }; 1923 1924 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = { 1925 .type = AMDGPU_RING_TYPE_SDMA, 1926 .align_mask = 0xf, 1927 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1928 .support_64bit_ptrs = true, 1929 .vmhub = AMDGPU_MMHUB, 1930 .get_rptr = sdma_v4_0_ring_get_rptr, 1931 .get_wptr = sdma_v4_0_ring_get_wptr, 1932 .set_wptr = sdma_v4_0_ring_set_wptr, 1933 .emit_frame_size = 1934 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 1935 3 + /* hdp invalidate */ 1936 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 1937 /* sdma_v4_0_ring_emit_vm_flush */ 1938 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1939 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1940 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 1941 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 1942 .emit_ib = sdma_v4_0_ring_emit_ib, 1943 .emit_fence = sdma_v4_0_ring_emit_fence, 1944 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 1945 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 1946 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 1947 .test_ring = sdma_v4_0_ring_test_ring, 1948 .test_ib = sdma_v4_0_ring_test_ib, 1949 .insert_nop = sdma_v4_0_ring_insert_nop, 1950 .pad_ib = sdma_v4_0_ring_pad_ib, 1951 .emit_wreg = sdma_v4_0_ring_emit_wreg, 1952 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 1953 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1954 }; 1955 1956 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = { 1957 .type = AMDGPU_RING_TYPE_SDMA, 1958 .align_mask = 0xf, 1959 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1960 .support_64bit_ptrs = true, 1961 .vmhub = AMDGPU_MMHUB, 1962 .get_rptr = sdma_v4_0_ring_get_rptr, 1963 .get_wptr = sdma_v4_0_page_ring_get_wptr, 1964 .set_wptr = sdma_v4_0_page_ring_set_wptr, 1965 .emit_frame_size = 1966 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 1967 3 + /* hdp invalidate */ 1968 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 1969 /* sdma_v4_0_ring_emit_vm_flush */ 1970 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1971 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1972 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 1973 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 1974 .emit_ib = sdma_v4_0_ring_emit_ib, 1975 .emit_fence = sdma_v4_0_ring_emit_fence, 1976 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 1977 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 1978 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 1979 .test_ring = sdma_v4_0_ring_test_ring, 1980 .test_ib = sdma_v4_0_ring_test_ib, 1981 .insert_nop = sdma_v4_0_ring_insert_nop, 1982 .pad_ib = sdma_v4_0_ring_pad_ib, 1983 .emit_wreg = sdma_v4_0_ring_emit_wreg, 1984 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 1985 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1986 }; 1987 1988 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev) 1989 { 1990 int i; 1991 1992 for (i = 0; i < adev->sdma.num_instances; i++) { 1993 adev->sdma.instance[i].ring.funcs = &sdma_v4_0_ring_funcs; 1994 adev->sdma.instance[i].ring.me = i; 1995 if (adev->sdma.has_page_queue) { 1996 adev->sdma.instance[i].page.funcs = &sdma_v4_0_page_ring_funcs; 1997 adev->sdma.instance[i].page.me = i; 1998 } 1999 } 2000 } 2001 2002 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = { 2003 .set = sdma_v4_0_set_trap_irq_state, 2004 .process = sdma_v4_0_process_trap_irq, 2005 }; 2006 2007 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = { 2008 .process = sdma_v4_0_process_illegal_inst_irq, 2009 }; 2010 2011 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev) 2012 { 2013 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 2014 adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs; 2015 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs; 2016 } 2017 2018 /** 2019 * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine 2020 * 2021 * @ring: amdgpu_ring structure holding ring information 2022 * @src_offset: src GPU address 2023 * @dst_offset: dst GPU address 2024 * @byte_count: number of bytes to xfer 2025 * 2026 * Copy GPU buffers using the DMA engine (VEGA10/12). 2027 * Used by the amdgpu ttm implementation to move pages if 2028 * registered as the asic copy callback. 2029 */ 2030 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib, 2031 uint64_t src_offset, 2032 uint64_t dst_offset, 2033 uint32_t byte_count) 2034 { 2035 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 2036 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 2037 ib->ptr[ib->length_dw++] = byte_count - 1; 2038 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 2039 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 2040 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 2041 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2042 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2043 } 2044 2045 /** 2046 * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine 2047 * 2048 * @ring: amdgpu_ring structure holding ring information 2049 * @src_data: value to write to buffer 2050 * @dst_offset: dst GPU address 2051 * @byte_count: number of bytes to xfer 2052 * 2053 * Fill GPU buffers using the DMA engine (VEGA10/12). 2054 */ 2055 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib, 2056 uint32_t src_data, 2057 uint64_t dst_offset, 2058 uint32_t byte_count) 2059 { 2060 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 2061 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2062 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2063 ib->ptr[ib->length_dw++] = src_data; 2064 ib->ptr[ib->length_dw++] = byte_count - 1; 2065 } 2066 2067 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = { 2068 .copy_max_bytes = 0x400000, 2069 .copy_num_dw = 7, 2070 .emit_copy_buffer = sdma_v4_0_emit_copy_buffer, 2071 2072 .fill_max_bytes = 0x400000, 2073 .fill_num_dw = 5, 2074 .emit_fill_buffer = sdma_v4_0_emit_fill_buffer, 2075 }; 2076 2077 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev) 2078 { 2079 adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs; 2080 if (adev->sdma.has_page_queue) 2081 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page; 2082 else 2083 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 2084 } 2085 2086 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = { 2087 .copy_pte_num_dw = 7, 2088 .copy_pte = sdma_v4_0_vm_copy_pte, 2089 2090 .write_pte = sdma_v4_0_vm_write_pte, 2091 .set_pte_pde = sdma_v4_0_vm_set_pte_pde, 2092 }; 2093 2094 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev) 2095 { 2096 struct drm_gpu_scheduler *sched; 2097 unsigned i; 2098 2099 adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs; 2100 for (i = 0; i < adev->sdma.num_instances; i++) { 2101 if (adev->sdma.has_page_queue) 2102 sched = &adev->sdma.instance[i].page.sched; 2103 else 2104 sched = &adev->sdma.instance[i].ring.sched; 2105 adev->vm_manager.vm_pte_rqs[i] = 2106 &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL]; 2107 } 2108 adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances; 2109 } 2110 2111 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = { 2112 .type = AMD_IP_BLOCK_TYPE_SDMA, 2113 .major = 4, 2114 .minor = 0, 2115 .rev = 0, 2116 .funcs = &sdma_v4_0_ip_funcs, 2117 }; 2118