1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "sdma0/sdma0_4_2_offset.h" 34 #include "sdma0/sdma0_4_2_sh_mask.h" 35 #include "sdma1/sdma1_4_2_offset.h" 36 #include "sdma1/sdma1_4_2_sh_mask.h" 37 #include "sdma2/sdma2_4_2_2_offset.h" 38 #include "sdma2/sdma2_4_2_2_sh_mask.h" 39 #include "sdma3/sdma3_4_2_2_offset.h" 40 #include "sdma3/sdma3_4_2_2_sh_mask.h" 41 #include "sdma4/sdma4_4_2_2_offset.h" 42 #include "sdma4/sdma4_4_2_2_sh_mask.h" 43 #include "sdma5/sdma5_4_2_2_offset.h" 44 #include "sdma5/sdma5_4_2_2_sh_mask.h" 45 #include "sdma6/sdma6_4_2_2_offset.h" 46 #include "sdma6/sdma6_4_2_2_sh_mask.h" 47 #include "sdma7/sdma7_4_2_2_offset.h" 48 #include "sdma7/sdma7_4_2_2_sh_mask.h" 49 #include "hdp/hdp_4_0_offset.h" 50 #include "sdma0/sdma0_4_1_default.h" 51 52 #include "soc15_common.h" 53 #include "soc15.h" 54 #include "vega10_sdma_pkt_open.h" 55 56 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h" 57 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h" 58 59 #include "amdgpu_ras.h" 60 61 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin"); 62 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin"); 63 MODULE_FIRMWARE("amdgpu/vega12_sdma.bin"); 64 MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin"); 65 MODULE_FIRMWARE("amdgpu/vega20_sdma.bin"); 66 MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin"); 67 MODULE_FIRMWARE("amdgpu/raven_sdma.bin"); 68 MODULE_FIRMWARE("amdgpu/picasso_sdma.bin"); 69 MODULE_FIRMWARE("amdgpu/raven2_sdma.bin"); 70 MODULE_FIRMWARE("amdgpu/arcturus_sdma.bin"); 71 MODULE_FIRMWARE("amdgpu/renoir_sdma.bin"); 72 73 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L 74 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L 75 76 #define WREG32_SDMA(instance, offset, value) \ 77 WREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)), value) 78 #define RREG32_SDMA(instance, offset) \ 79 RREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset))) 80 81 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev); 82 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev); 83 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev); 84 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev); 85 86 static const struct soc15_reg_golden golden_settings_sdma_4[] = { 87 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 88 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100), 89 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100), 90 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 91 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 92 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 93 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000), 94 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 95 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 96 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 97 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 98 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 99 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000), 100 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), 101 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100), 102 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 103 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 104 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 105 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000), 106 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 107 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 108 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 109 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 110 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0), 111 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xfc000000, 0x00000000) 112 }; 113 114 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = { 115 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 116 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 117 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 118 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 119 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002) 120 }; 121 122 static const struct soc15_reg_golden golden_settings_sdma_vg12[] = { 123 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), 124 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001), 125 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 126 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), 127 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001) 128 }; 129 130 static const struct soc15_reg_golden golden_settings_sdma_4_1[] = { 131 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 132 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 133 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100), 134 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 135 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051), 136 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100), 137 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 138 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100), 139 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 140 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 141 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000) 142 }; 143 144 static const struct soc15_reg_golden golden_settings_sdma0_4_2_init[] = { 145 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 146 }; 147 148 static const struct soc15_reg_golden golden_settings_sdma0_4_2[] = 149 { 150 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 151 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 152 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 153 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 154 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 155 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 156 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 157 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 158 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RD_BURST_CNTL, 0x0000000f, 0x00000003), 159 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 160 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 161 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 162 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 163 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 164 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 165 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 166 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 167 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 168 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 169 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 170 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 171 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 172 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 173 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 174 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 175 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 176 }; 177 178 static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = { 179 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 180 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), 181 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 182 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 183 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 184 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 185 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 186 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 187 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RD_BURST_CNTL, 0x0000000f, 0x00000003), 188 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 189 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 190 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 191 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 192 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 193 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 194 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 195 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 196 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 197 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 198 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 199 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 200 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 201 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 202 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 203 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 204 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0), 205 }; 206 207 static const struct soc15_reg_golden golden_settings_sdma_rv1[] = 208 { 209 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002), 210 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002) 211 }; 212 213 static const struct soc15_reg_golden golden_settings_sdma_rv2[] = 214 { 215 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00003001), 216 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003001) 217 }; 218 219 static const struct soc15_reg_golden golden_settings_sdma_arct[] = 220 { 221 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 222 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 223 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 224 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 225 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 226 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 227 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 228 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 229 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 230 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 231 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 232 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 233 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 234 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 235 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 236 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 237 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 238 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 239 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 240 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 241 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 242 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 243 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 244 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002) 245 }; 246 247 static const struct soc15_reg_golden golden_settings_sdma_4_3[] = { 248 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 249 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 250 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00003002), 251 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003002), 252 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 253 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003fff07, 0x40000051), 254 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 255 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 256 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 257 }; 258 259 static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev, 260 u32 instance, u32 offset) 261 { 262 switch (instance) { 263 case 0: 264 return (adev->reg_offset[SDMA0_HWIP][0][0] + offset); 265 case 1: 266 return (adev->reg_offset[SDMA1_HWIP][0][0] + offset); 267 case 2: 268 return (adev->reg_offset[SDMA2_HWIP][0][1] + offset); 269 case 3: 270 return (adev->reg_offset[SDMA3_HWIP][0][1] + offset); 271 case 4: 272 return (adev->reg_offset[SDMA4_HWIP][0][1] + offset); 273 case 5: 274 return (adev->reg_offset[SDMA5_HWIP][0][1] + offset); 275 case 6: 276 return (adev->reg_offset[SDMA6_HWIP][0][1] + offset); 277 case 7: 278 return (adev->reg_offset[SDMA7_HWIP][0][1] + offset); 279 default: 280 break; 281 } 282 return 0; 283 } 284 285 static unsigned sdma_v4_0_seq_to_irq_id(int seq_num) 286 { 287 switch (seq_num) { 288 case 0: 289 return SOC15_IH_CLIENTID_SDMA0; 290 case 1: 291 return SOC15_IH_CLIENTID_SDMA1; 292 case 2: 293 return SOC15_IH_CLIENTID_SDMA2; 294 case 3: 295 return SOC15_IH_CLIENTID_SDMA3; 296 case 4: 297 return SOC15_IH_CLIENTID_SDMA4; 298 case 5: 299 return SOC15_IH_CLIENTID_SDMA5; 300 case 6: 301 return SOC15_IH_CLIENTID_SDMA6; 302 case 7: 303 return SOC15_IH_CLIENTID_SDMA7; 304 default: 305 break; 306 } 307 return -EINVAL; 308 } 309 310 static int sdma_v4_0_irq_id_to_seq(unsigned client_id) 311 { 312 switch (client_id) { 313 case SOC15_IH_CLIENTID_SDMA0: 314 return 0; 315 case SOC15_IH_CLIENTID_SDMA1: 316 return 1; 317 case SOC15_IH_CLIENTID_SDMA2: 318 return 2; 319 case SOC15_IH_CLIENTID_SDMA3: 320 return 3; 321 case SOC15_IH_CLIENTID_SDMA4: 322 return 4; 323 case SOC15_IH_CLIENTID_SDMA5: 324 return 5; 325 case SOC15_IH_CLIENTID_SDMA6: 326 return 6; 327 case SOC15_IH_CLIENTID_SDMA7: 328 return 7; 329 default: 330 break; 331 } 332 return -EINVAL; 333 } 334 335 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) 336 { 337 switch (adev->asic_type) { 338 case CHIP_VEGA10: 339 soc15_program_register_sequence(adev, 340 golden_settings_sdma_4, 341 ARRAY_SIZE(golden_settings_sdma_4)); 342 soc15_program_register_sequence(adev, 343 golden_settings_sdma_vg10, 344 ARRAY_SIZE(golden_settings_sdma_vg10)); 345 break; 346 case CHIP_VEGA12: 347 soc15_program_register_sequence(adev, 348 golden_settings_sdma_4, 349 ARRAY_SIZE(golden_settings_sdma_4)); 350 soc15_program_register_sequence(adev, 351 golden_settings_sdma_vg12, 352 ARRAY_SIZE(golden_settings_sdma_vg12)); 353 break; 354 case CHIP_VEGA20: 355 soc15_program_register_sequence(adev, 356 golden_settings_sdma0_4_2_init, 357 ARRAY_SIZE(golden_settings_sdma0_4_2_init)); 358 soc15_program_register_sequence(adev, 359 golden_settings_sdma0_4_2, 360 ARRAY_SIZE(golden_settings_sdma0_4_2)); 361 soc15_program_register_sequence(adev, 362 golden_settings_sdma1_4_2, 363 ARRAY_SIZE(golden_settings_sdma1_4_2)); 364 break; 365 case CHIP_ARCTURUS: 366 soc15_program_register_sequence(adev, 367 golden_settings_sdma_arct, 368 ARRAY_SIZE(golden_settings_sdma_arct)); 369 break; 370 case CHIP_RAVEN: 371 soc15_program_register_sequence(adev, 372 golden_settings_sdma_4_1, 373 ARRAY_SIZE(golden_settings_sdma_4_1)); 374 if (adev->rev_id >= 8) 375 soc15_program_register_sequence(adev, 376 golden_settings_sdma_rv2, 377 ARRAY_SIZE(golden_settings_sdma_rv2)); 378 else 379 soc15_program_register_sequence(adev, 380 golden_settings_sdma_rv1, 381 ARRAY_SIZE(golden_settings_sdma_rv1)); 382 break; 383 case CHIP_RENOIR: 384 soc15_program_register_sequence(adev, 385 golden_settings_sdma_4_3, 386 ARRAY_SIZE(golden_settings_sdma_4_3)); 387 break; 388 default: 389 break; 390 } 391 } 392 393 static int sdma_v4_0_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst) 394 { 395 int err = 0; 396 const struct sdma_firmware_header_v1_0 *hdr; 397 398 err = amdgpu_ucode_validate(sdma_inst->fw); 399 if (err) 400 return err; 401 402 hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data; 403 sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version); 404 sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version); 405 406 if (sdma_inst->feature_version >= 20) 407 sdma_inst->burst_nop = true; 408 409 return 0; 410 } 411 412 static void sdma_v4_0_destroy_inst_ctx(struct amdgpu_device *adev) 413 { 414 int i; 415 416 for (i = 0; i < adev->sdma.num_instances; i++) { 417 if (adev->sdma.instance[i].fw != NULL) 418 release_firmware(adev->sdma.instance[i].fw); 419 420 /* arcturus shares the same FW memory across 421 all SDMA isntances */ 422 if (adev->asic_type == CHIP_ARCTURUS) 423 break; 424 } 425 426 memset((void*)adev->sdma.instance, 0, 427 sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES); 428 } 429 430 /** 431 * sdma_v4_0_init_microcode - load ucode images from disk 432 * 433 * @adev: amdgpu_device pointer 434 * 435 * Use the firmware interface to load the ucode images into 436 * the driver (not loaded into hw). 437 * Returns 0 on success, error on failure. 438 */ 439 440 // emulation only, won't work on real chip 441 // vega10 real chip need to use PSP to load firmware 442 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev) 443 { 444 const char *chip_name; 445 char fw_name[30]; 446 int err = 0, i; 447 struct amdgpu_firmware_info *info = NULL; 448 const struct common_firmware_header *header = NULL; 449 450 DRM_DEBUG("\n"); 451 452 switch (adev->asic_type) { 453 case CHIP_VEGA10: 454 chip_name = "vega10"; 455 break; 456 case CHIP_VEGA12: 457 chip_name = "vega12"; 458 break; 459 case CHIP_VEGA20: 460 chip_name = "vega20"; 461 break; 462 case CHIP_RAVEN: 463 if (adev->rev_id >= 8) 464 chip_name = "raven2"; 465 else if (adev->pdev->device == 0x15d8) 466 chip_name = "picasso"; 467 else 468 chip_name = "raven"; 469 break; 470 case CHIP_ARCTURUS: 471 chip_name = "arcturus"; 472 break; 473 case CHIP_RENOIR: 474 chip_name = "renoir"; 475 break; 476 default: 477 BUG(); 478 } 479 480 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 481 482 err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev); 483 if (err) 484 goto out; 485 486 err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[0]); 487 if (err) 488 goto out; 489 490 for (i = 1; i < adev->sdma.num_instances; i++) { 491 if (adev->asic_type == CHIP_ARCTURUS) { 492 /* Acturus will leverage the same FW memory 493 for every SDMA instance */ 494 memcpy((void*)&adev->sdma.instance[i], 495 (void*)&adev->sdma.instance[0], 496 sizeof(struct amdgpu_sdma_instance)); 497 } 498 else { 499 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i); 500 501 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 502 if (err) 503 goto out; 504 505 err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[i]); 506 if (err) 507 goto out; 508 } 509 } 510 511 DRM_DEBUG("psp_load == '%s'\n", 512 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); 513 514 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 515 for (i = 0; i < adev->sdma.num_instances; i++) { 516 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 517 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 518 info->fw = adev->sdma.instance[i].fw; 519 header = (const struct common_firmware_header *)info->fw->data; 520 adev->firmware.fw_size += 521 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 522 } 523 } 524 525 out: 526 if (err) { 527 DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name); 528 sdma_v4_0_destroy_inst_ctx(adev); 529 } 530 return err; 531 } 532 533 /** 534 * sdma_v4_0_ring_get_rptr - get the current read pointer 535 * 536 * @ring: amdgpu ring pointer 537 * 538 * Get the current rptr from the hardware (VEGA10+). 539 */ 540 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring) 541 { 542 u64 *rptr; 543 544 /* XXX check if swapping is necessary on BE */ 545 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]); 546 547 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 548 return ((*rptr) >> 2); 549 } 550 551 /** 552 * sdma_v4_0_ring_get_wptr - get the current write pointer 553 * 554 * @ring: amdgpu ring pointer 555 * 556 * Get the current wptr from the hardware (VEGA10+). 557 */ 558 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring) 559 { 560 struct amdgpu_device *adev = ring->adev; 561 u64 wptr; 562 563 if (ring->use_doorbell) { 564 /* XXX check if swapping is necessary on BE */ 565 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 566 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 567 } else { 568 wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI); 569 wptr = wptr << 32; 570 wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR); 571 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", 572 ring->me, wptr); 573 } 574 575 return wptr >> 2; 576 } 577 578 /** 579 * sdma_v4_0_ring_set_wptr - commit the write pointer 580 * 581 * @ring: amdgpu ring pointer 582 * 583 * Write the wptr back to the hardware (VEGA10+). 584 */ 585 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring) 586 { 587 struct amdgpu_device *adev = ring->adev; 588 589 DRM_DEBUG("Setting write pointer\n"); 590 if (ring->use_doorbell) { 591 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 592 593 DRM_DEBUG("Using doorbell -- " 594 "wptr_offs == 0x%08x " 595 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 596 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 597 ring->wptr_offs, 598 lower_32_bits(ring->wptr << 2), 599 upper_32_bits(ring->wptr << 2)); 600 /* XXX check if swapping is necessary on BE */ 601 WRITE_ONCE(*wb, (ring->wptr << 2)); 602 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 603 ring->doorbell_index, ring->wptr << 2); 604 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 605 } else { 606 DRM_DEBUG("Not using doorbell -- " 607 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 608 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 609 ring->me, 610 lower_32_bits(ring->wptr << 2), 611 ring->me, 612 upper_32_bits(ring->wptr << 2)); 613 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR, 614 lower_32_bits(ring->wptr << 2)); 615 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI, 616 upper_32_bits(ring->wptr << 2)); 617 } 618 } 619 620 /** 621 * sdma_v4_0_page_ring_get_wptr - get the current write pointer 622 * 623 * @ring: amdgpu ring pointer 624 * 625 * Get the current wptr from the hardware (VEGA10+). 626 */ 627 static uint64_t sdma_v4_0_page_ring_get_wptr(struct amdgpu_ring *ring) 628 { 629 struct amdgpu_device *adev = ring->adev; 630 u64 wptr; 631 632 if (ring->use_doorbell) { 633 /* XXX check if swapping is necessary on BE */ 634 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 635 } else { 636 wptr = RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI); 637 wptr = wptr << 32; 638 wptr |= RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR); 639 } 640 641 return wptr >> 2; 642 } 643 644 /** 645 * sdma_v4_0_ring_set_wptr - commit the write pointer 646 * 647 * @ring: amdgpu ring pointer 648 * 649 * Write the wptr back to the hardware (VEGA10+). 650 */ 651 static void sdma_v4_0_page_ring_set_wptr(struct amdgpu_ring *ring) 652 { 653 struct amdgpu_device *adev = ring->adev; 654 655 if (ring->use_doorbell) { 656 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 657 658 /* XXX check if swapping is necessary on BE */ 659 WRITE_ONCE(*wb, (ring->wptr << 2)); 660 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 661 } else { 662 uint64_t wptr = ring->wptr << 2; 663 664 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR, 665 lower_32_bits(wptr)); 666 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI, 667 upper_32_bits(wptr)); 668 } 669 } 670 671 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 672 { 673 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 674 int i; 675 676 for (i = 0; i < count; i++) 677 if (sdma && sdma->burst_nop && (i == 0)) 678 amdgpu_ring_write(ring, ring->funcs->nop | 679 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 680 else 681 amdgpu_ring_write(ring, ring->funcs->nop); 682 } 683 684 /** 685 * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine 686 * 687 * @ring: amdgpu ring pointer 688 * @ib: IB object to schedule 689 * 690 * Schedule an IB in the DMA ring (VEGA10). 691 */ 692 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring, 693 struct amdgpu_job *job, 694 struct amdgpu_ib *ib, 695 uint32_t flags) 696 { 697 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 698 699 /* IB packet must end on a 8 DW boundary */ 700 sdma_v4_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8); 701 702 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 703 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 704 /* base must be 32 byte aligned */ 705 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 706 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 707 amdgpu_ring_write(ring, ib->length_dw); 708 amdgpu_ring_write(ring, 0); 709 amdgpu_ring_write(ring, 0); 710 711 } 712 713 static void sdma_v4_0_wait_reg_mem(struct amdgpu_ring *ring, 714 int mem_space, int hdp, 715 uint32_t addr0, uint32_t addr1, 716 uint32_t ref, uint32_t mask, 717 uint32_t inv) 718 { 719 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 720 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) | 721 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) | 722 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 723 if (mem_space) { 724 /* memory */ 725 amdgpu_ring_write(ring, addr0); 726 amdgpu_ring_write(ring, addr1); 727 } else { 728 /* registers */ 729 amdgpu_ring_write(ring, addr0 << 2); 730 amdgpu_ring_write(ring, addr1 << 2); 731 } 732 amdgpu_ring_write(ring, ref); /* reference */ 733 amdgpu_ring_write(ring, mask); /* mask */ 734 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 735 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */ 736 } 737 738 /** 739 * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 740 * 741 * @ring: amdgpu ring pointer 742 * 743 * Emit an hdp flush packet on the requested DMA ring. 744 */ 745 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 746 { 747 struct amdgpu_device *adev = ring->adev; 748 u32 ref_and_mask = 0; 749 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg; 750 751 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; 752 753 sdma_v4_0_wait_reg_mem(ring, 0, 1, 754 adev->nbio_funcs->get_hdp_flush_done_offset(adev), 755 adev->nbio_funcs->get_hdp_flush_req_offset(adev), 756 ref_and_mask, ref_and_mask, 10); 757 } 758 759 /** 760 * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring 761 * 762 * @ring: amdgpu ring pointer 763 * @fence: amdgpu fence object 764 * 765 * Add a DMA fence packet to the ring to write 766 * the fence seq number and DMA trap packet to generate 767 * an interrupt if needed (VEGA10). 768 */ 769 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 770 unsigned flags) 771 { 772 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 773 /* write the fence */ 774 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 775 /* zero in first two bits */ 776 BUG_ON(addr & 0x3); 777 amdgpu_ring_write(ring, lower_32_bits(addr)); 778 amdgpu_ring_write(ring, upper_32_bits(addr)); 779 amdgpu_ring_write(ring, lower_32_bits(seq)); 780 781 /* optionally write high bits as well */ 782 if (write64bit) { 783 addr += 4; 784 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 785 /* zero in first two bits */ 786 BUG_ON(addr & 0x3); 787 amdgpu_ring_write(ring, lower_32_bits(addr)); 788 amdgpu_ring_write(ring, upper_32_bits(addr)); 789 amdgpu_ring_write(ring, upper_32_bits(seq)); 790 } 791 792 /* generate an interrupt */ 793 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 794 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 795 } 796 797 798 /** 799 * sdma_v4_0_gfx_stop - stop the gfx async dma engines 800 * 801 * @adev: amdgpu_device pointer 802 * 803 * Stop the gfx async dma ring buffers (VEGA10). 804 */ 805 static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev) 806 { 807 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; 808 u32 rb_cntl, ib_cntl; 809 int i, unset = 0; 810 811 for (i = 0; i < adev->sdma.num_instances; i++) { 812 sdma[i] = &adev->sdma.instance[i].ring; 813 814 if ((adev->mman.buffer_funcs_ring == sdma[i]) && unset != 1) { 815 amdgpu_ttm_set_buffer_funcs_status(adev, false); 816 unset = 1; 817 } 818 819 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL); 820 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 821 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 822 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL); 823 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 824 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl); 825 826 sdma[i]->sched.ready = false; 827 } 828 } 829 830 /** 831 * sdma_v4_0_rlc_stop - stop the compute async dma engines 832 * 833 * @adev: amdgpu_device pointer 834 * 835 * Stop the compute async dma queues (VEGA10). 836 */ 837 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev) 838 { 839 /* XXX todo */ 840 } 841 842 /** 843 * sdma_v4_0_page_stop - stop the page async dma engines 844 * 845 * @adev: amdgpu_device pointer 846 * 847 * Stop the page async dma ring buffers (VEGA10). 848 */ 849 static void sdma_v4_0_page_stop(struct amdgpu_device *adev) 850 { 851 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; 852 u32 rb_cntl, ib_cntl; 853 int i; 854 bool unset = false; 855 856 for (i = 0; i < adev->sdma.num_instances; i++) { 857 sdma[i] = &adev->sdma.instance[i].page; 858 859 if ((adev->mman.buffer_funcs_ring == sdma[i]) && 860 (unset == false)) { 861 amdgpu_ttm_set_buffer_funcs_status(adev, false); 862 unset = true; 863 } 864 865 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL); 866 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, 867 RB_ENABLE, 0); 868 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 869 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL); 870 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, 871 IB_ENABLE, 0); 872 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl); 873 874 sdma[i]->sched.ready = false; 875 } 876 } 877 878 /** 879 * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch 880 * 881 * @adev: amdgpu_device pointer 882 * @enable: enable/disable the DMA MEs context switch. 883 * 884 * Halt or unhalt the async dma engines context switch (VEGA10). 885 */ 886 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 887 { 888 u32 f32_cntl, phase_quantum = 0; 889 int i; 890 891 if (amdgpu_sdma_phase_quantum) { 892 unsigned value = amdgpu_sdma_phase_quantum; 893 unsigned unit = 0; 894 895 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 896 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 897 value = (value + 1) >> 1; 898 unit++; 899 } 900 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 901 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 902 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 903 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 904 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 905 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 906 WARN_ONCE(1, 907 "clamping sdma_phase_quantum to %uK clock cycles\n", 908 value << unit); 909 } 910 phase_quantum = 911 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 912 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 913 } 914 915 for (i = 0; i < adev->sdma.num_instances; i++) { 916 f32_cntl = RREG32_SDMA(i, mmSDMA0_CNTL); 917 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 918 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 919 if (enable && amdgpu_sdma_phase_quantum) { 920 WREG32_SDMA(i, mmSDMA0_PHASE0_QUANTUM, phase_quantum); 921 WREG32_SDMA(i, mmSDMA0_PHASE1_QUANTUM, phase_quantum); 922 WREG32_SDMA(i, mmSDMA0_PHASE2_QUANTUM, phase_quantum); 923 } 924 WREG32_SDMA(i, mmSDMA0_CNTL, f32_cntl); 925 } 926 927 } 928 929 /** 930 * sdma_v4_0_enable - stop the async dma engines 931 * 932 * @adev: amdgpu_device pointer 933 * @enable: enable/disable the DMA MEs. 934 * 935 * Halt or unhalt the async dma engines (VEGA10). 936 */ 937 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable) 938 { 939 u32 f32_cntl; 940 int i; 941 942 if (enable == false) { 943 sdma_v4_0_gfx_stop(adev); 944 sdma_v4_0_rlc_stop(adev); 945 if (adev->sdma.has_page_queue) 946 sdma_v4_0_page_stop(adev); 947 } 948 949 for (i = 0; i < adev->sdma.num_instances; i++) { 950 f32_cntl = RREG32_SDMA(i, mmSDMA0_F32_CNTL); 951 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 952 WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl); 953 } 954 } 955 956 /** 957 * sdma_v4_0_rb_cntl - get parameters for rb_cntl 958 */ 959 static uint32_t sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl) 960 { 961 /* Set ring buffer size in dwords */ 962 uint32_t rb_bufsz = order_base_2(ring->ring_size / 4); 963 964 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 965 #ifdef __BIG_ENDIAN 966 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 967 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 968 RPTR_WRITEBACK_SWAP_ENABLE, 1); 969 #endif 970 return rb_cntl; 971 } 972 973 /** 974 * sdma_v4_0_gfx_resume - setup and start the async dma engines 975 * 976 * @adev: amdgpu_device pointer 977 * @i: instance to resume 978 * 979 * Set up the gfx DMA ring buffers and enable them (VEGA10). 980 * Returns 0 for success, error for failure. 981 */ 982 static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i) 983 { 984 struct amdgpu_ring *ring = &adev->sdma.instance[i].ring; 985 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 986 u32 wb_offset; 987 u32 doorbell; 988 u32 doorbell_offset; 989 u64 wptr_gpu_addr; 990 991 wb_offset = (ring->rptr_offs * 4); 992 993 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL); 994 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl); 995 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 996 997 /* Initialize the ring buffer's read and write pointers */ 998 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR, 0); 999 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_HI, 0); 1000 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR, 0); 1001 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_HI, 0); 1002 1003 /* set the wb address whether it's enabled or not */ 1004 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI, 1005 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 1006 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 1007 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 1008 1009 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 1010 RPTR_WRITEBACK_ENABLE, 1); 1011 1012 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE, ring->gpu_addr >> 8); 1013 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE_HI, ring->gpu_addr >> 40); 1014 1015 ring->wptr = 0; 1016 1017 /* before programing wptr to a less value, need set minor_ptr_update first */ 1018 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 1); 1019 1020 doorbell = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL); 1021 doorbell_offset = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET); 1022 1023 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1024 ring->use_doorbell); 1025 doorbell_offset = REG_SET_FIELD(doorbell_offset, 1026 SDMA0_GFX_DOORBELL_OFFSET, 1027 OFFSET, ring->doorbell_index); 1028 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL, doorbell); 1029 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET, doorbell_offset); 1030 1031 sdma_v4_0_ring_set_wptr(ring); 1032 1033 /* set minor_ptr_update to 0 after wptr programed */ 1034 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 0); 1035 1036 /* setup the wptr shadow polling */ 1037 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1038 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO, 1039 lower_32_bits(wptr_gpu_addr)); 1040 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI, 1041 upper_32_bits(wptr_gpu_addr)); 1042 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL); 1043 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 1044 SDMA0_GFX_RB_WPTR_POLL_CNTL, 1045 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 1046 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 1047 1048 /* enable DMA RB */ 1049 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 1050 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 1051 1052 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL); 1053 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 1054 #ifdef __BIG_ENDIAN 1055 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 1056 #endif 1057 /* enable DMA IBs */ 1058 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl); 1059 1060 ring->sched.ready = true; 1061 } 1062 1063 /** 1064 * sdma_v4_0_page_resume - setup and start the async dma engines 1065 * 1066 * @adev: amdgpu_device pointer 1067 * @i: instance to resume 1068 * 1069 * Set up the page DMA ring buffers and enable them (VEGA10). 1070 * Returns 0 for success, error for failure. 1071 */ 1072 static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i) 1073 { 1074 struct amdgpu_ring *ring = &adev->sdma.instance[i].page; 1075 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 1076 u32 wb_offset; 1077 u32 doorbell; 1078 u32 doorbell_offset; 1079 u64 wptr_gpu_addr; 1080 1081 wb_offset = (ring->rptr_offs * 4); 1082 1083 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL); 1084 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl); 1085 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 1086 1087 /* Initialize the ring buffer's read and write pointers */ 1088 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR, 0); 1089 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_HI, 0); 1090 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR, 0); 1091 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_HI, 0); 1092 1093 /* set the wb address whether it's enabled or not */ 1094 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_HI, 1095 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 1096 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 1097 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 1098 1099 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, 1100 RPTR_WRITEBACK_ENABLE, 1); 1101 1102 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE, ring->gpu_addr >> 8); 1103 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE_HI, ring->gpu_addr >> 40); 1104 1105 ring->wptr = 0; 1106 1107 /* before programing wptr to a less value, need set minor_ptr_update first */ 1108 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 1); 1109 1110 doorbell = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL); 1111 doorbell_offset = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET); 1112 1113 doorbell = REG_SET_FIELD(doorbell, SDMA0_PAGE_DOORBELL, ENABLE, 1114 ring->use_doorbell); 1115 doorbell_offset = REG_SET_FIELD(doorbell_offset, 1116 SDMA0_PAGE_DOORBELL_OFFSET, 1117 OFFSET, ring->doorbell_index); 1118 WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL, doorbell); 1119 WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET, doorbell_offset); 1120 1121 /* paging queue doorbell range is setup at sdma_v4_0_gfx_resume */ 1122 sdma_v4_0_page_ring_set_wptr(ring); 1123 1124 /* set minor_ptr_update to 0 after wptr programed */ 1125 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 0); 1126 1127 /* setup the wptr shadow polling */ 1128 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1129 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO, 1130 lower_32_bits(wptr_gpu_addr)); 1131 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI, 1132 upper_32_bits(wptr_gpu_addr)); 1133 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL); 1134 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 1135 SDMA0_PAGE_RB_WPTR_POLL_CNTL, 1136 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 1137 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 1138 1139 /* enable DMA RB */ 1140 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, RB_ENABLE, 1); 1141 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 1142 1143 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL); 1144 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_ENABLE, 1); 1145 #ifdef __BIG_ENDIAN 1146 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1); 1147 #endif 1148 /* enable DMA IBs */ 1149 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl); 1150 1151 ring->sched.ready = true; 1152 } 1153 1154 static void 1155 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable) 1156 { 1157 uint32_t def, data; 1158 1159 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) { 1160 /* enable idle interrupt */ 1161 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 1162 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 1163 1164 if (data != def) 1165 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 1166 } else { 1167 /* disable idle interrupt */ 1168 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 1169 data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 1170 if (data != def) 1171 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 1172 } 1173 } 1174 1175 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev) 1176 { 1177 uint32_t def, data; 1178 1179 /* Enable HW based PG. */ 1180 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1181 data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK; 1182 if (data != def) 1183 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1184 1185 /* enable interrupt */ 1186 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 1187 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 1188 if (data != def) 1189 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 1190 1191 /* Configure hold time to filter in-valid power on/off request. Use default right now */ 1192 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1193 data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK; 1194 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK); 1195 /* Configure switch time for hysteresis purpose. Use default right now */ 1196 data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK; 1197 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK); 1198 if(data != def) 1199 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1200 } 1201 1202 static void sdma_v4_0_init_pg(struct amdgpu_device *adev) 1203 { 1204 if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA)) 1205 return; 1206 1207 switch (adev->asic_type) { 1208 case CHIP_RAVEN: 1209 sdma_v4_1_init_power_gating(adev); 1210 sdma_v4_1_update_power_gating(adev, true); 1211 break; 1212 default: 1213 break; 1214 } 1215 } 1216 1217 /** 1218 * sdma_v4_0_rlc_resume - setup and start the async dma engines 1219 * 1220 * @adev: amdgpu_device pointer 1221 * 1222 * Set up the compute DMA queues and enable them (VEGA10). 1223 * Returns 0 for success, error for failure. 1224 */ 1225 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev) 1226 { 1227 sdma_v4_0_init_pg(adev); 1228 1229 return 0; 1230 } 1231 1232 /** 1233 * sdma_v4_0_load_microcode - load the sDMA ME ucode 1234 * 1235 * @adev: amdgpu_device pointer 1236 * 1237 * Loads the sDMA0/1 ucode. 1238 * Returns 0 for success, -EINVAL if the ucode is not available. 1239 */ 1240 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev) 1241 { 1242 const struct sdma_firmware_header_v1_0 *hdr; 1243 const __le32 *fw_data; 1244 u32 fw_size; 1245 int i, j; 1246 1247 /* halt the MEs */ 1248 sdma_v4_0_enable(adev, false); 1249 1250 for (i = 0; i < adev->sdma.num_instances; i++) { 1251 if (!adev->sdma.instance[i].fw) 1252 return -EINVAL; 1253 1254 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 1255 amdgpu_ucode_print_sdma_hdr(&hdr->header); 1256 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1257 1258 fw_data = (const __le32 *) 1259 (adev->sdma.instance[i].fw->data + 1260 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1261 1262 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 0); 1263 1264 for (j = 0; j < fw_size; j++) 1265 WREG32_SDMA(i, mmSDMA0_UCODE_DATA, 1266 le32_to_cpup(fw_data++)); 1267 1268 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 1269 adev->sdma.instance[i].fw_version); 1270 } 1271 1272 return 0; 1273 } 1274 1275 /** 1276 * sdma_v4_0_start - setup and start the async dma engines 1277 * 1278 * @adev: amdgpu_device pointer 1279 * 1280 * Set up the DMA engines and enable them (VEGA10). 1281 * Returns 0 for success, error for failure. 1282 */ 1283 static int sdma_v4_0_start(struct amdgpu_device *adev) 1284 { 1285 struct amdgpu_ring *ring; 1286 int i, r = 0; 1287 1288 if (amdgpu_sriov_vf(adev)) { 1289 sdma_v4_0_ctx_switch_enable(adev, false); 1290 sdma_v4_0_enable(adev, false); 1291 } else { 1292 1293 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1294 r = sdma_v4_0_load_microcode(adev); 1295 if (r) 1296 return r; 1297 } 1298 1299 /* unhalt the MEs */ 1300 sdma_v4_0_enable(adev, true); 1301 /* enable sdma ring preemption */ 1302 sdma_v4_0_ctx_switch_enable(adev, true); 1303 } 1304 1305 /* start the gfx rings and rlc compute queues */ 1306 for (i = 0; i < adev->sdma.num_instances; i++) { 1307 uint32_t temp; 1308 1309 WREG32_SDMA(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL, 0); 1310 sdma_v4_0_gfx_resume(adev, i); 1311 if (adev->sdma.has_page_queue) 1312 sdma_v4_0_page_resume(adev, i); 1313 1314 /* set utc l1 enable flag always to 1 */ 1315 temp = RREG32_SDMA(i, mmSDMA0_CNTL); 1316 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 1317 WREG32_SDMA(i, mmSDMA0_CNTL, temp); 1318 1319 if (!amdgpu_sriov_vf(adev)) { 1320 /* unhalt engine */ 1321 temp = RREG32_SDMA(i, mmSDMA0_F32_CNTL); 1322 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 1323 WREG32_SDMA(i, mmSDMA0_F32_CNTL, temp); 1324 } 1325 } 1326 1327 if (amdgpu_sriov_vf(adev)) { 1328 sdma_v4_0_ctx_switch_enable(adev, true); 1329 sdma_v4_0_enable(adev, true); 1330 } else { 1331 r = sdma_v4_0_rlc_resume(adev); 1332 if (r) 1333 return r; 1334 } 1335 1336 for (i = 0; i < adev->sdma.num_instances; i++) { 1337 ring = &adev->sdma.instance[i].ring; 1338 1339 r = amdgpu_ring_test_helper(ring); 1340 if (r) 1341 return r; 1342 1343 if (adev->sdma.has_page_queue) { 1344 struct amdgpu_ring *page = &adev->sdma.instance[i].page; 1345 1346 r = amdgpu_ring_test_helper(page); 1347 if (r) 1348 return r; 1349 1350 if (adev->mman.buffer_funcs_ring == page) 1351 amdgpu_ttm_set_buffer_funcs_status(adev, true); 1352 } 1353 1354 if (adev->mman.buffer_funcs_ring == ring) 1355 amdgpu_ttm_set_buffer_funcs_status(adev, true); 1356 } 1357 1358 return r; 1359 } 1360 1361 /** 1362 * sdma_v4_0_ring_test_ring - simple async dma engine test 1363 * 1364 * @ring: amdgpu_ring structure holding ring information 1365 * 1366 * Test the DMA engine by writing using it to write an 1367 * value to memory. (VEGA10). 1368 * Returns 0 for success, error for failure. 1369 */ 1370 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring) 1371 { 1372 struct amdgpu_device *adev = ring->adev; 1373 unsigned i; 1374 unsigned index; 1375 int r; 1376 u32 tmp; 1377 u64 gpu_addr; 1378 1379 r = amdgpu_device_wb_get(adev, &index); 1380 if (r) 1381 return r; 1382 1383 gpu_addr = adev->wb.gpu_addr + (index * 4); 1384 tmp = 0xCAFEDEAD; 1385 adev->wb.wb[index] = cpu_to_le32(tmp); 1386 1387 r = amdgpu_ring_alloc(ring, 5); 1388 if (r) 1389 goto error_free_wb; 1390 1391 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1392 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 1393 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 1394 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 1395 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 1396 amdgpu_ring_write(ring, 0xDEADBEEF); 1397 amdgpu_ring_commit(ring); 1398 1399 for (i = 0; i < adev->usec_timeout; i++) { 1400 tmp = le32_to_cpu(adev->wb.wb[index]); 1401 if (tmp == 0xDEADBEEF) 1402 break; 1403 udelay(1); 1404 } 1405 1406 if (i >= adev->usec_timeout) 1407 r = -ETIMEDOUT; 1408 1409 error_free_wb: 1410 amdgpu_device_wb_free(adev, index); 1411 return r; 1412 } 1413 1414 /** 1415 * sdma_v4_0_ring_test_ib - test an IB on the DMA engine 1416 * 1417 * @ring: amdgpu_ring structure holding ring information 1418 * 1419 * Test a simple IB in the DMA ring (VEGA10). 1420 * Returns 0 on success, error on failure. 1421 */ 1422 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1423 { 1424 struct amdgpu_device *adev = ring->adev; 1425 struct amdgpu_ib ib; 1426 struct dma_fence *f = NULL; 1427 unsigned index; 1428 long r; 1429 u32 tmp = 0; 1430 u64 gpu_addr; 1431 1432 r = amdgpu_device_wb_get(adev, &index); 1433 if (r) 1434 return r; 1435 1436 gpu_addr = adev->wb.gpu_addr + (index * 4); 1437 tmp = 0xCAFEDEAD; 1438 adev->wb.wb[index] = cpu_to_le32(tmp); 1439 memset(&ib, 0, sizeof(ib)); 1440 r = amdgpu_ib_get(adev, NULL, 256, &ib); 1441 if (r) 1442 goto err0; 1443 1444 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1445 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1446 ib.ptr[1] = lower_32_bits(gpu_addr); 1447 ib.ptr[2] = upper_32_bits(gpu_addr); 1448 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1449 ib.ptr[4] = 0xDEADBEEF; 1450 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1451 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1452 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1453 ib.length_dw = 8; 1454 1455 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1456 if (r) 1457 goto err1; 1458 1459 r = dma_fence_wait_timeout(f, false, timeout); 1460 if (r == 0) { 1461 r = -ETIMEDOUT; 1462 goto err1; 1463 } else if (r < 0) { 1464 goto err1; 1465 } 1466 tmp = le32_to_cpu(adev->wb.wb[index]); 1467 if (tmp == 0xDEADBEEF) 1468 r = 0; 1469 else 1470 r = -EINVAL; 1471 1472 err1: 1473 amdgpu_ib_free(adev, &ib, NULL); 1474 dma_fence_put(f); 1475 err0: 1476 amdgpu_device_wb_free(adev, index); 1477 return r; 1478 } 1479 1480 1481 /** 1482 * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART 1483 * 1484 * @ib: indirect buffer to fill with commands 1485 * @pe: addr of the page entry 1486 * @src: src addr to copy from 1487 * @count: number of page entries to update 1488 * 1489 * Update PTEs by copying them from the GART using sDMA (VEGA10). 1490 */ 1491 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib, 1492 uint64_t pe, uint64_t src, 1493 unsigned count) 1494 { 1495 unsigned bytes = count * 8; 1496 1497 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1498 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1499 ib->ptr[ib->length_dw++] = bytes - 1; 1500 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1501 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1502 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1503 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1504 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1505 1506 } 1507 1508 /** 1509 * sdma_v4_0_vm_write_pte - update PTEs by writing them manually 1510 * 1511 * @ib: indirect buffer to fill with commands 1512 * @pe: addr of the page entry 1513 * @addr: dst addr to write into pe 1514 * @count: number of page entries to update 1515 * @incr: increase next addr by incr bytes 1516 * @flags: access flags 1517 * 1518 * Update PTEs by writing them manually using sDMA (VEGA10). 1519 */ 1520 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1521 uint64_t value, unsigned count, 1522 uint32_t incr) 1523 { 1524 unsigned ndw = count * 2; 1525 1526 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1527 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1528 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1529 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1530 ib->ptr[ib->length_dw++] = ndw - 1; 1531 for (; ndw > 0; ndw -= 2) { 1532 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1533 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1534 value += incr; 1535 } 1536 } 1537 1538 /** 1539 * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA 1540 * 1541 * @ib: indirect buffer to fill with commands 1542 * @pe: addr of the page entry 1543 * @addr: dst addr to write into pe 1544 * @count: number of page entries to update 1545 * @incr: increase next addr by incr bytes 1546 * @flags: access flags 1547 * 1548 * Update the page tables using sDMA (VEGA10). 1549 */ 1550 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1551 uint64_t pe, 1552 uint64_t addr, unsigned count, 1553 uint32_t incr, uint64_t flags) 1554 { 1555 /* for physically contiguous pages (vram) */ 1556 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1557 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1558 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1559 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1560 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1561 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1562 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1563 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1564 ib->ptr[ib->length_dw++] = 0; 1565 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1566 } 1567 1568 /** 1569 * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw 1570 * 1571 * @ib: indirect buffer to fill with padding 1572 * 1573 */ 1574 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1575 { 1576 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1577 u32 pad_count; 1578 int i; 1579 1580 pad_count = (8 - (ib->length_dw & 0x7)) % 8; 1581 for (i = 0; i < pad_count; i++) 1582 if (sdma && sdma->burst_nop && (i == 0)) 1583 ib->ptr[ib->length_dw++] = 1584 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1585 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1586 else 1587 ib->ptr[ib->length_dw++] = 1588 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1589 } 1590 1591 1592 /** 1593 * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline 1594 * 1595 * @ring: amdgpu_ring pointer 1596 * 1597 * Make sure all previous operations are completed (CIK). 1598 */ 1599 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1600 { 1601 uint32_t seq = ring->fence_drv.sync_seq; 1602 uint64_t addr = ring->fence_drv.gpu_addr; 1603 1604 /* wait for idle */ 1605 sdma_v4_0_wait_reg_mem(ring, 1, 0, 1606 addr & 0xfffffffc, 1607 upper_32_bits(addr) & 0xffffffff, 1608 seq, 0xffffffff, 4); 1609 } 1610 1611 1612 /** 1613 * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA 1614 * 1615 * @ring: amdgpu_ring pointer 1616 * @vm: amdgpu_vm pointer 1617 * 1618 * Update the page table base and flush the VM TLB 1619 * using sDMA (VEGA10). 1620 */ 1621 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1622 unsigned vmid, uint64_t pd_addr) 1623 { 1624 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1625 } 1626 1627 static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring, 1628 uint32_t reg, uint32_t val) 1629 { 1630 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1631 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1632 amdgpu_ring_write(ring, reg); 1633 amdgpu_ring_write(ring, val); 1634 } 1635 1636 static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1637 uint32_t val, uint32_t mask) 1638 { 1639 sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10); 1640 } 1641 1642 static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev) 1643 { 1644 uint fw_version = adev->sdma.instance[0].fw_version; 1645 1646 switch (adev->asic_type) { 1647 case CHIP_VEGA10: 1648 return fw_version >= 430; 1649 case CHIP_VEGA12: 1650 /*return fw_version >= 31;*/ 1651 return false; 1652 case CHIP_VEGA20: 1653 return fw_version >= 123; 1654 default: 1655 return false; 1656 } 1657 } 1658 1659 static int sdma_v4_0_early_init(void *handle) 1660 { 1661 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1662 int r; 1663 1664 if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_RENOIR) 1665 adev->sdma.num_instances = 1; 1666 else if (adev->asic_type == CHIP_ARCTURUS) 1667 adev->sdma.num_instances = 8; 1668 else 1669 adev->sdma.num_instances = 2; 1670 1671 r = sdma_v4_0_init_microcode(adev); 1672 if (r) { 1673 DRM_ERROR("Failed to load sdma firmware!\n"); 1674 return r; 1675 } 1676 1677 /* TODO: Page queue breaks driver reload under SRIOV */ 1678 if ((adev->asic_type == CHIP_VEGA10) && amdgpu_sriov_vf((adev))) 1679 adev->sdma.has_page_queue = false; 1680 else if (sdma_v4_0_fw_support_paging_queue(adev)) 1681 adev->sdma.has_page_queue = true; 1682 1683 sdma_v4_0_set_ring_funcs(adev); 1684 sdma_v4_0_set_buffer_funcs(adev); 1685 sdma_v4_0_set_vm_pte_funcs(adev); 1686 sdma_v4_0_set_irq_funcs(adev); 1687 1688 return 0; 1689 } 1690 1691 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev, 1692 struct ras_err_data *err_data, 1693 struct amdgpu_iv_entry *entry); 1694 1695 static int sdma_v4_0_late_init(void *handle) 1696 { 1697 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1698 struct ras_common_if **ras_if = &adev->sdma.ras_if; 1699 struct ras_ih_if ih_info = { 1700 .cb = sdma_v4_0_process_ras_data_cb, 1701 }; 1702 struct ras_fs_if fs_info = { 1703 .sysfs_name = "sdma_err_count", 1704 .debugfs_name = "sdma_err_inject", 1705 }; 1706 struct ras_common_if ras_block = { 1707 .block = AMDGPU_RAS_BLOCK__SDMA, 1708 .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 1709 .sub_block_index = 0, 1710 .name = "sdma", 1711 }; 1712 int r, i; 1713 1714 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 1715 amdgpu_ras_feature_enable_on_boot(adev, &ras_block, 0); 1716 return 0; 1717 } 1718 1719 /* handle resume path. */ 1720 if (*ras_if) { 1721 /* resend ras TA enable cmd during resume. 1722 * prepare to handle failure. 1723 */ 1724 ih_info.head = **ras_if; 1725 r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1); 1726 if (r) { 1727 if (r == -EAGAIN) { 1728 /* request a gpu reset. will run again. */ 1729 amdgpu_ras_request_reset_on_boot(adev, 1730 AMDGPU_RAS_BLOCK__SDMA); 1731 return 0; 1732 } 1733 /* fail to enable ras, cleanup all. */ 1734 goto irq; 1735 } 1736 /* enable successfully. continue. */ 1737 goto resume; 1738 } 1739 1740 *ras_if = kmalloc(sizeof(**ras_if), GFP_KERNEL); 1741 if (!*ras_if) 1742 return -ENOMEM; 1743 1744 **ras_if = ras_block; 1745 1746 r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1); 1747 if (r) { 1748 if (r == -EAGAIN) { 1749 amdgpu_ras_request_reset_on_boot(adev, 1750 AMDGPU_RAS_BLOCK__SDMA); 1751 r = 0; 1752 } 1753 goto feature; 1754 } 1755 1756 ih_info.head = **ras_if; 1757 fs_info.head = **ras_if; 1758 1759 r = amdgpu_ras_interrupt_add_handler(adev, &ih_info); 1760 if (r) 1761 goto interrupt; 1762 1763 amdgpu_ras_debugfs_create(adev, &fs_info); 1764 1765 r = amdgpu_ras_sysfs_create(adev, &fs_info); 1766 if (r) 1767 goto sysfs; 1768 resume: 1769 for (i = 0; i < adev->sdma.num_instances; i++) { 1770 r = amdgpu_irq_get(adev, &adev->sdma.ecc_irq, 1771 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 1772 if (r) 1773 goto irq; 1774 } 1775 1776 return 0; 1777 irq: 1778 amdgpu_ras_sysfs_remove(adev, *ras_if); 1779 sysfs: 1780 amdgpu_ras_debugfs_remove(adev, *ras_if); 1781 amdgpu_ras_interrupt_remove_handler(adev, &ih_info); 1782 interrupt: 1783 amdgpu_ras_feature_enable(adev, *ras_if, 0); 1784 feature: 1785 kfree(*ras_if); 1786 *ras_if = NULL; 1787 return r; 1788 } 1789 1790 static int sdma_v4_0_sw_init(void *handle) 1791 { 1792 struct amdgpu_ring *ring; 1793 int r, i; 1794 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1795 1796 /* SDMA trap event */ 1797 for (i = 0; i < adev->sdma.num_instances; i++) { 1798 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1799 SDMA0_4_0__SRCID__SDMA_TRAP, 1800 &adev->sdma.trap_irq); 1801 if (r) 1802 return r; 1803 } 1804 1805 /* SDMA SRAM ECC event */ 1806 for (i = 0; i < adev->sdma.num_instances; i++) { 1807 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1808 SDMA0_4_0__SRCID__SDMA_SRAM_ECC, 1809 &adev->sdma.ecc_irq); 1810 if (r) 1811 return r; 1812 } 1813 1814 for (i = 0; i < adev->sdma.num_instances; i++) { 1815 ring = &adev->sdma.instance[i].ring; 1816 ring->ring_obj = NULL; 1817 ring->use_doorbell = true; 1818 1819 DRM_INFO("use_doorbell being set to: [%s]\n", 1820 ring->use_doorbell?"true":"false"); 1821 1822 /* doorbell size is 2 dwords, get DWORD offset */ 1823 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1; 1824 1825 sprintf(ring->name, "sdma%d", i); 1826 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1827 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 1828 if (r) 1829 return r; 1830 1831 if (adev->sdma.has_page_queue) { 1832 ring = &adev->sdma.instance[i].page; 1833 ring->ring_obj = NULL; 1834 ring->use_doorbell = true; 1835 1836 /* paging queue use same doorbell index/routing as gfx queue 1837 * with 0x400 (4096 dwords) offset on second doorbell page 1838 */ 1839 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1; 1840 ring->doorbell_index += 0x400; 1841 1842 sprintf(ring->name, "page%d", i); 1843 r = amdgpu_ring_init(adev, ring, 1024, 1844 &adev->sdma.trap_irq, 1845 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 1846 if (r) 1847 return r; 1848 } 1849 } 1850 1851 return r; 1852 } 1853 1854 static int sdma_v4_0_sw_fini(void *handle) 1855 { 1856 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1857 int i; 1858 1859 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA) && 1860 adev->sdma.ras_if) { 1861 struct ras_common_if *ras_if = adev->sdma.ras_if; 1862 struct ras_ih_if ih_info = { 1863 .head = *ras_if, 1864 }; 1865 1866 /*remove fs first*/ 1867 amdgpu_ras_debugfs_remove(adev, ras_if); 1868 amdgpu_ras_sysfs_remove(adev, ras_if); 1869 /*remove the IH*/ 1870 amdgpu_ras_interrupt_remove_handler(adev, &ih_info); 1871 amdgpu_ras_feature_enable(adev, ras_if, 0); 1872 kfree(ras_if); 1873 } 1874 1875 for (i = 0; i < adev->sdma.num_instances; i++) { 1876 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1877 if (adev->sdma.has_page_queue) 1878 amdgpu_ring_fini(&adev->sdma.instance[i].page); 1879 } 1880 1881 sdma_v4_0_destroy_inst_ctx(adev); 1882 1883 return 0; 1884 } 1885 1886 static int sdma_v4_0_hw_init(void *handle) 1887 { 1888 int r; 1889 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1890 1891 if (adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs && 1892 adev->powerplay.pp_funcs->set_powergating_by_smu) 1893 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false); 1894 1895 if (!amdgpu_sriov_vf(adev)) 1896 sdma_v4_0_init_golden_registers(adev); 1897 1898 r = sdma_v4_0_start(adev); 1899 1900 return r; 1901 } 1902 1903 static int sdma_v4_0_hw_fini(void *handle) 1904 { 1905 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1906 int i; 1907 1908 if (amdgpu_sriov_vf(adev)) 1909 return 0; 1910 1911 for (i = 0; i < adev->sdma.num_instances; i++) { 1912 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, 1913 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 1914 } 1915 1916 sdma_v4_0_ctx_switch_enable(adev, false); 1917 sdma_v4_0_enable(adev, false); 1918 1919 if (adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs 1920 && adev->powerplay.pp_funcs->set_powergating_by_smu) 1921 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true); 1922 1923 return 0; 1924 } 1925 1926 static int sdma_v4_0_suspend(void *handle) 1927 { 1928 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1929 1930 return sdma_v4_0_hw_fini(adev); 1931 } 1932 1933 static int sdma_v4_0_resume(void *handle) 1934 { 1935 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1936 1937 return sdma_v4_0_hw_init(adev); 1938 } 1939 1940 static bool sdma_v4_0_is_idle(void *handle) 1941 { 1942 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1943 u32 i; 1944 1945 for (i = 0; i < adev->sdma.num_instances; i++) { 1946 u32 tmp = RREG32_SDMA(i, mmSDMA0_STATUS_REG); 1947 1948 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1949 return false; 1950 } 1951 1952 return true; 1953 } 1954 1955 static int sdma_v4_0_wait_for_idle(void *handle) 1956 { 1957 unsigned i, j; 1958 u32 sdma[AMDGPU_MAX_SDMA_INSTANCES]; 1959 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1960 1961 for (i = 0; i < adev->usec_timeout; i++) { 1962 for (j = 0; j < adev->sdma.num_instances; j++) { 1963 sdma[j] = RREG32_SDMA(j, mmSDMA0_STATUS_REG); 1964 if (!(sdma[j] & SDMA0_STATUS_REG__IDLE_MASK)) 1965 break; 1966 } 1967 if (j == adev->sdma.num_instances) 1968 return 0; 1969 udelay(1); 1970 } 1971 return -ETIMEDOUT; 1972 } 1973 1974 static int sdma_v4_0_soft_reset(void *handle) 1975 { 1976 /* todo */ 1977 1978 return 0; 1979 } 1980 1981 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev, 1982 struct amdgpu_irq_src *source, 1983 unsigned type, 1984 enum amdgpu_interrupt_state state) 1985 { 1986 u32 sdma_cntl; 1987 1988 sdma_cntl = RREG32_SDMA(type, mmSDMA0_CNTL); 1989 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1990 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1991 WREG32_SDMA(type, mmSDMA0_CNTL, sdma_cntl); 1992 1993 return 0; 1994 } 1995 1996 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev, 1997 struct amdgpu_irq_src *source, 1998 struct amdgpu_iv_entry *entry) 1999 { 2000 uint32_t instance; 2001 2002 DRM_DEBUG("IH: SDMA trap\n"); 2003 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 2004 switch (entry->ring_id) { 2005 case 0: 2006 amdgpu_fence_process(&adev->sdma.instance[instance].ring); 2007 break; 2008 case 1: 2009 if (adev->asic_type == CHIP_VEGA20) 2010 amdgpu_fence_process(&adev->sdma.instance[instance].page); 2011 break; 2012 case 2: 2013 /* XXX compute */ 2014 break; 2015 case 3: 2016 if (adev->asic_type != CHIP_VEGA20) 2017 amdgpu_fence_process(&adev->sdma.instance[instance].page); 2018 break; 2019 } 2020 return 0; 2021 } 2022 2023 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev, 2024 struct ras_err_data *err_data, 2025 struct amdgpu_iv_entry *entry) 2026 { 2027 uint32_t err_source; 2028 int instance; 2029 2030 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 2031 if (instance < 0) 2032 return 0; 2033 2034 switch (entry->src_id) { 2035 case SDMA0_4_0__SRCID__SDMA_SRAM_ECC: 2036 err_source = 0; 2037 break; 2038 case SDMA0_4_0__SRCID__SDMA_ECC: 2039 err_source = 1; 2040 break; 2041 default: 2042 return 0; 2043 } 2044 2045 kgd2kfd_set_sram_ecc_flag(adev->kfd.dev); 2046 2047 amdgpu_ras_reset_gpu(adev, 0); 2048 2049 return AMDGPU_RAS_SUCCESS; 2050 } 2051 2052 static int sdma_v4_0_process_ecc_irq(struct amdgpu_device *adev, 2053 struct amdgpu_irq_src *source, 2054 struct amdgpu_iv_entry *entry) 2055 { 2056 struct ras_common_if *ras_if = adev->sdma.ras_if; 2057 struct ras_dispatch_if ih_data = { 2058 .entry = entry, 2059 }; 2060 2061 if (!ras_if) 2062 return 0; 2063 2064 ih_data.head = *ras_if; 2065 2066 amdgpu_ras_interrupt_dispatch(adev, &ih_data); 2067 return 0; 2068 } 2069 2070 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev, 2071 struct amdgpu_irq_src *source, 2072 struct amdgpu_iv_entry *entry) 2073 { 2074 int instance; 2075 2076 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 2077 2078 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 2079 if (instance < 0) 2080 return 0; 2081 2082 switch (entry->ring_id) { 2083 case 0: 2084 drm_sched_fault(&adev->sdma.instance[instance].ring.sched); 2085 break; 2086 } 2087 return 0; 2088 } 2089 2090 static int sdma_v4_0_set_ecc_irq_state(struct amdgpu_device *adev, 2091 struct amdgpu_irq_src *source, 2092 unsigned type, 2093 enum amdgpu_interrupt_state state) 2094 { 2095 u32 sdma_edc_config; 2096 2097 sdma_edc_config = RREG32_SDMA(type, mmSDMA0_EDC_CONFIG); 2098 sdma_edc_config = REG_SET_FIELD(sdma_edc_config, SDMA0_EDC_CONFIG, ECC_INT_ENABLE, 2099 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2100 WREG32_SDMA(type, mmSDMA0_EDC_CONFIG, sdma_edc_config); 2101 2102 return 0; 2103 } 2104 2105 static void sdma_v4_0_update_medium_grain_clock_gating( 2106 struct amdgpu_device *adev, 2107 bool enable) 2108 { 2109 uint32_t data, def; 2110 int i; 2111 2112 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 2113 for (i = 0; i < adev->sdma.num_instances; i++) { 2114 def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL); 2115 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 2116 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 2117 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 2118 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 2119 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 2120 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 2121 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 2122 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 2123 if (def != data) 2124 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data); 2125 } 2126 } else { 2127 for (i = 0; i < adev->sdma.num_instances; i++) { 2128 def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL); 2129 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 2130 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 2131 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 2132 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 2133 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 2134 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 2135 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 2136 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 2137 if (def != data) 2138 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data); 2139 } 2140 } 2141 } 2142 2143 2144 static void sdma_v4_0_update_medium_grain_light_sleep( 2145 struct amdgpu_device *adev, 2146 bool enable) 2147 { 2148 uint32_t data, def; 2149 int i; 2150 2151 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 2152 for (i = 0; i < adev->sdma.num_instances; i++) { 2153 /* 1-not override: enable sdma mem light sleep */ 2154 def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL); 2155 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 2156 if (def != data) 2157 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data); 2158 } 2159 } else { 2160 for (i = 0; i < adev->sdma.num_instances; i++) { 2161 /* 0-override:disable sdma mem light sleep */ 2162 def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL); 2163 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 2164 if (def != data) 2165 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data); 2166 } 2167 } 2168 } 2169 2170 static int sdma_v4_0_set_clockgating_state(void *handle, 2171 enum amd_clockgating_state state) 2172 { 2173 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2174 2175 if (amdgpu_sriov_vf(adev)) 2176 return 0; 2177 2178 switch (adev->asic_type) { 2179 case CHIP_VEGA10: 2180 case CHIP_VEGA12: 2181 case CHIP_VEGA20: 2182 case CHIP_RAVEN: 2183 case CHIP_ARCTURUS: 2184 sdma_v4_0_update_medium_grain_clock_gating(adev, 2185 state == AMD_CG_STATE_GATE ? true : false); 2186 sdma_v4_0_update_medium_grain_light_sleep(adev, 2187 state == AMD_CG_STATE_GATE ? true : false); 2188 break; 2189 default: 2190 break; 2191 } 2192 return 0; 2193 } 2194 2195 static int sdma_v4_0_set_powergating_state(void *handle, 2196 enum amd_powergating_state state) 2197 { 2198 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2199 2200 switch (adev->asic_type) { 2201 case CHIP_RAVEN: 2202 sdma_v4_1_update_power_gating(adev, 2203 state == AMD_PG_STATE_GATE ? true : false); 2204 break; 2205 default: 2206 break; 2207 } 2208 2209 return 0; 2210 } 2211 2212 static void sdma_v4_0_get_clockgating_state(void *handle, u32 *flags) 2213 { 2214 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2215 int data; 2216 2217 if (amdgpu_sriov_vf(adev)) 2218 *flags = 0; 2219 2220 /* AMD_CG_SUPPORT_SDMA_MGCG */ 2221 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 2222 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK)) 2223 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 2224 2225 /* AMD_CG_SUPPORT_SDMA_LS */ 2226 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 2227 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 2228 *flags |= AMD_CG_SUPPORT_SDMA_LS; 2229 } 2230 2231 const struct amd_ip_funcs sdma_v4_0_ip_funcs = { 2232 .name = "sdma_v4_0", 2233 .early_init = sdma_v4_0_early_init, 2234 .late_init = sdma_v4_0_late_init, 2235 .sw_init = sdma_v4_0_sw_init, 2236 .sw_fini = sdma_v4_0_sw_fini, 2237 .hw_init = sdma_v4_0_hw_init, 2238 .hw_fini = sdma_v4_0_hw_fini, 2239 .suspend = sdma_v4_0_suspend, 2240 .resume = sdma_v4_0_resume, 2241 .is_idle = sdma_v4_0_is_idle, 2242 .wait_for_idle = sdma_v4_0_wait_for_idle, 2243 .soft_reset = sdma_v4_0_soft_reset, 2244 .set_clockgating_state = sdma_v4_0_set_clockgating_state, 2245 .set_powergating_state = sdma_v4_0_set_powergating_state, 2246 .get_clockgating_state = sdma_v4_0_get_clockgating_state, 2247 }; 2248 2249 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = { 2250 .type = AMDGPU_RING_TYPE_SDMA, 2251 .align_mask = 0xf, 2252 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2253 .support_64bit_ptrs = true, 2254 .vmhub = AMDGPU_MMHUB_0, 2255 .get_rptr = sdma_v4_0_ring_get_rptr, 2256 .get_wptr = sdma_v4_0_ring_get_wptr, 2257 .set_wptr = sdma_v4_0_ring_set_wptr, 2258 .emit_frame_size = 2259 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2260 3 + /* hdp invalidate */ 2261 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2262 /* sdma_v4_0_ring_emit_vm_flush */ 2263 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2264 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2265 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2266 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2267 .emit_ib = sdma_v4_0_ring_emit_ib, 2268 .emit_fence = sdma_v4_0_ring_emit_fence, 2269 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2270 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2271 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2272 .test_ring = sdma_v4_0_ring_test_ring, 2273 .test_ib = sdma_v4_0_ring_test_ib, 2274 .insert_nop = sdma_v4_0_ring_insert_nop, 2275 .pad_ib = sdma_v4_0_ring_pad_ib, 2276 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2277 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2278 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2279 }; 2280 2281 /* 2282 * On Arcturus, SDMA instance 5~7 has a different vmhub type(AMDGPU_MMHUB_1). 2283 * So create a individual constant ring_funcs for those instances. 2284 */ 2285 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs_2nd_mmhub = { 2286 .type = AMDGPU_RING_TYPE_SDMA, 2287 .align_mask = 0xf, 2288 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2289 .support_64bit_ptrs = true, 2290 .vmhub = AMDGPU_MMHUB_1, 2291 .get_rptr = sdma_v4_0_ring_get_rptr, 2292 .get_wptr = sdma_v4_0_ring_get_wptr, 2293 .set_wptr = sdma_v4_0_ring_set_wptr, 2294 .emit_frame_size = 2295 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2296 3 + /* hdp invalidate */ 2297 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2298 /* sdma_v4_0_ring_emit_vm_flush */ 2299 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2300 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2301 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2302 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2303 .emit_ib = sdma_v4_0_ring_emit_ib, 2304 .emit_fence = sdma_v4_0_ring_emit_fence, 2305 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2306 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2307 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2308 .test_ring = sdma_v4_0_ring_test_ring, 2309 .test_ib = sdma_v4_0_ring_test_ib, 2310 .insert_nop = sdma_v4_0_ring_insert_nop, 2311 .pad_ib = sdma_v4_0_ring_pad_ib, 2312 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2313 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2314 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2315 }; 2316 2317 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = { 2318 .type = AMDGPU_RING_TYPE_SDMA, 2319 .align_mask = 0xf, 2320 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2321 .support_64bit_ptrs = true, 2322 .vmhub = AMDGPU_MMHUB_0, 2323 .get_rptr = sdma_v4_0_ring_get_rptr, 2324 .get_wptr = sdma_v4_0_page_ring_get_wptr, 2325 .set_wptr = sdma_v4_0_page_ring_set_wptr, 2326 .emit_frame_size = 2327 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2328 3 + /* hdp invalidate */ 2329 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2330 /* sdma_v4_0_ring_emit_vm_flush */ 2331 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2332 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2333 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2334 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2335 .emit_ib = sdma_v4_0_ring_emit_ib, 2336 .emit_fence = sdma_v4_0_ring_emit_fence, 2337 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2338 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2339 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2340 .test_ring = sdma_v4_0_ring_test_ring, 2341 .test_ib = sdma_v4_0_ring_test_ib, 2342 .insert_nop = sdma_v4_0_ring_insert_nop, 2343 .pad_ib = sdma_v4_0_ring_pad_ib, 2344 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2345 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2346 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2347 }; 2348 2349 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs_2nd_mmhub = { 2350 .type = AMDGPU_RING_TYPE_SDMA, 2351 .align_mask = 0xf, 2352 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2353 .support_64bit_ptrs = true, 2354 .vmhub = AMDGPU_MMHUB_1, 2355 .get_rptr = sdma_v4_0_ring_get_rptr, 2356 .get_wptr = sdma_v4_0_page_ring_get_wptr, 2357 .set_wptr = sdma_v4_0_page_ring_set_wptr, 2358 .emit_frame_size = 2359 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2360 3 + /* hdp invalidate */ 2361 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2362 /* sdma_v4_0_ring_emit_vm_flush */ 2363 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2364 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2365 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2366 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2367 .emit_ib = sdma_v4_0_ring_emit_ib, 2368 .emit_fence = sdma_v4_0_ring_emit_fence, 2369 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2370 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2371 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2372 .test_ring = sdma_v4_0_ring_test_ring, 2373 .test_ib = sdma_v4_0_ring_test_ib, 2374 .insert_nop = sdma_v4_0_ring_insert_nop, 2375 .pad_ib = sdma_v4_0_ring_pad_ib, 2376 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2377 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2378 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2379 }; 2380 2381 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev) 2382 { 2383 int i; 2384 2385 for (i = 0; i < adev->sdma.num_instances; i++) { 2386 if (adev->asic_type == CHIP_ARCTURUS && i >= 5) 2387 adev->sdma.instance[i].ring.funcs = 2388 &sdma_v4_0_ring_funcs_2nd_mmhub; 2389 else 2390 adev->sdma.instance[i].ring.funcs = 2391 &sdma_v4_0_ring_funcs; 2392 adev->sdma.instance[i].ring.me = i; 2393 if (adev->sdma.has_page_queue) { 2394 if (adev->asic_type == CHIP_ARCTURUS && i >= 5) 2395 adev->sdma.instance[i].page.funcs = 2396 &sdma_v4_0_page_ring_funcs_2nd_mmhub; 2397 else 2398 adev->sdma.instance[i].page.funcs = 2399 &sdma_v4_0_page_ring_funcs; 2400 adev->sdma.instance[i].page.me = i; 2401 } 2402 } 2403 } 2404 2405 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = { 2406 .set = sdma_v4_0_set_trap_irq_state, 2407 .process = sdma_v4_0_process_trap_irq, 2408 }; 2409 2410 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = { 2411 .process = sdma_v4_0_process_illegal_inst_irq, 2412 }; 2413 2414 static const struct amdgpu_irq_src_funcs sdma_v4_0_ecc_irq_funcs = { 2415 .set = sdma_v4_0_set_ecc_irq_state, 2416 .process = sdma_v4_0_process_ecc_irq, 2417 }; 2418 2419 2420 2421 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev) 2422 { 2423 switch (adev->sdma.num_instances) { 2424 case 1: 2425 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1; 2426 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1; 2427 break; 2428 case 8: 2429 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 2430 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 2431 break; 2432 case 2: 2433 default: 2434 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2; 2435 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2; 2436 break; 2437 } 2438 adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs; 2439 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs; 2440 adev->sdma.ecc_irq.funcs = &sdma_v4_0_ecc_irq_funcs; 2441 } 2442 2443 /** 2444 * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine 2445 * 2446 * @ring: amdgpu_ring structure holding ring information 2447 * @src_offset: src GPU address 2448 * @dst_offset: dst GPU address 2449 * @byte_count: number of bytes to xfer 2450 * 2451 * Copy GPU buffers using the DMA engine (VEGA10/12). 2452 * Used by the amdgpu ttm implementation to move pages if 2453 * registered as the asic copy callback. 2454 */ 2455 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib, 2456 uint64_t src_offset, 2457 uint64_t dst_offset, 2458 uint32_t byte_count) 2459 { 2460 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 2461 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 2462 ib->ptr[ib->length_dw++] = byte_count - 1; 2463 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 2464 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 2465 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 2466 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2467 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2468 } 2469 2470 /** 2471 * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine 2472 * 2473 * @ring: amdgpu_ring structure holding ring information 2474 * @src_data: value to write to buffer 2475 * @dst_offset: dst GPU address 2476 * @byte_count: number of bytes to xfer 2477 * 2478 * Fill GPU buffers using the DMA engine (VEGA10/12). 2479 */ 2480 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib, 2481 uint32_t src_data, 2482 uint64_t dst_offset, 2483 uint32_t byte_count) 2484 { 2485 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 2486 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2487 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2488 ib->ptr[ib->length_dw++] = src_data; 2489 ib->ptr[ib->length_dw++] = byte_count - 1; 2490 } 2491 2492 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = { 2493 .copy_max_bytes = 0x400000, 2494 .copy_num_dw = 7, 2495 .emit_copy_buffer = sdma_v4_0_emit_copy_buffer, 2496 2497 .fill_max_bytes = 0x400000, 2498 .fill_num_dw = 5, 2499 .emit_fill_buffer = sdma_v4_0_emit_fill_buffer, 2500 }; 2501 2502 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev) 2503 { 2504 adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs; 2505 if (adev->sdma.has_page_queue && adev->sdma.num_instances > 1) 2506 adev->mman.buffer_funcs_ring = &adev->sdma.instance[1].page; 2507 else 2508 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 2509 } 2510 2511 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = { 2512 .copy_pte_num_dw = 7, 2513 .copy_pte = sdma_v4_0_vm_copy_pte, 2514 2515 .write_pte = sdma_v4_0_vm_write_pte, 2516 .set_pte_pde = sdma_v4_0_vm_set_pte_pde, 2517 }; 2518 2519 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev) 2520 { 2521 struct drm_gpu_scheduler *sched; 2522 unsigned i; 2523 2524 adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs; 2525 if (adev->sdma.has_page_queue && adev->sdma.num_instances > 1) { 2526 for (i = 1; i < adev->sdma.num_instances; i++) { 2527 sched = &adev->sdma.instance[i].page.sched; 2528 adev->vm_manager.vm_pte_rqs[i - 1] = 2529 &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL]; 2530 } 2531 adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances - 1; 2532 adev->vm_manager.page_fault = &adev->sdma.instance[0].page; 2533 } else { 2534 for (i = 0; i < adev->sdma.num_instances; i++) { 2535 sched = &adev->sdma.instance[i].ring.sched; 2536 adev->vm_manager.vm_pte_rqs[i] = 2537 &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL]; 2538 } 2539 adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances; 2540 } 2541 } 2542 2543 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = { 2544 .type = AMD_IP_BLOCK_TYPE_SDMA, 2545 .major = 4, 2546 .minor = 0, 2547 .rev = 0, 2548 .funcs = &sdma_v4_0_ip_funcs, 2549 }; 2550