1 /*
2  * Copyright 2016 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #include <linux/delay.h>
25 #include <linux/firmware.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 
29 #include "amdgpu.h"
30 #include "amdgpu_ucode.h"
31 #include "amdgpu_trace.h"
32 
33 #include "sdma0/sdma0_4_2_offset.h"
34 #include "sdma0/sdma0_4_2_sh_mask.h"
35 #include "sdma1/sdma1_4_2_offset.h"
36 #include "sdma1/sdma1_4_2_sh_mask.h"
37 #include "sdma2/sdma2_4_2_2_offset.h"
38 #include "sdma2/sdma2_4_2_2_sh_mask.h"
39 #include "sdma3/sdma3_4_2_2_offset.h"
40 #include "sdma3/sdma3_4_2_2_sh_mask.h"
41 #include "sdma4/sdma4_4_2_2_offset.h"
42 #include "sdma4/sdma4_4_2_2_sh_mask.h"
43 #include "sdma5/sdma5_4_2_2_offset.h"
44 #include "sdma5/sdma5_4_2_2_sh_mask.h"
45 #include "sdma6/sdma6_4_2_2_offset.h"
46 #include "sdma6/sdma6_4_2_2_sh_mask.h"
47 #include "sdma7/sdma7_4_2_2_offset.h"
48 #include "sdma7/sdma7_4_2_2_sh_mask.h"
49 #include "sdma0/sdma0_4_1_default.h"
50 
51 #include "soc15_common.h"
52 #include "soc15.h"
53 #include "vega10_sdma_pkt_open.h"
54 
55 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h"
56 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h"
57 
58 #include "amdgpu_ras.h"
59 #include "sdma_v4_4.h"
60 
61 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin");
62 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin");
63 MODULE_FIRMWARE("amdgpu/vega12_sdma.bin");
64 MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin");
65 MODULE_FIRMWARE("amdgpu/vega20_sdma.bin");
66 MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin");
67 MODULE_FIRMWARE("amdgpu/raven_sdma.bin");
68 MODULE_FIRMWARE("amdgpu/picasso_sdma.bin");
69 MODULE_FIRMWARE("amdgpu/raven2_sdma.bin");
70 MODULE_FIRMWARE("amdgpu/arcturus_sdma.bin");
71 MODULE_FIRMWARE("amdgpu/renoir_sdma.bin");
72 MODULE_FIRMWARE("amdgpu/green_sardine_sdma.bin");
73 MODULE_FIRMWARE("amdgpu/aldebaran_sdma.bin");
74 
75 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK  0x000000F8L
76 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
77 
78 #define WREG32_SDMA(instance, offset, value) \
79 	WREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)), value)
80 #define RREG32_SDMA(instance, offset) \
81 	RREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)))
82 
83 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev);
84 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev);
85 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev);
86 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev);
87 static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev);
88 
89 static const struct soc15_reg_golden golden_settings_sdma_4[] = {
90 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
91 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100),
92 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100),
93 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
94 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
95 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
96 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000),
97 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
98 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
99 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
100 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
101 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
102 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000),
103 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
104 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100),
105 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
106 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
107 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
108 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000),
109 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
110 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
111 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
112 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
113 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0),
114 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xfc000000, 0x00000000)
115 };
116 
117 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = {
118 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
119 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
120 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
121 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
122 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
123 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
124 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
125 };
126 
127 static const struct soc15_reg_golden golden_settings_sdma_vg12[] = {
128 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
129 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001),
130 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
131 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
132 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
133 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001),
134 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
135 };
136 
137 static const struct soc15_reg_golden golden_settings_sdma_4_1[] = {
138 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
139 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
140 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100),
141 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
142 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051),
143 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100),
144 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
145 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100),
146 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
147 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003e0),
148 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000)
149 };
150 
151 static const struct soc15_reg_golden golden_settings_sdma0_4_2_init[] = {
152 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
153 };
154 
155 static const struct soc15_reg_golden golden_settings_sdma0_4_2[] =
156 {
157 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
158 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
159 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
160 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
161 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
162 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
163 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
164 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
165 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RD_BURST_CNTL, 0x0000000f, 0x00000003),
166 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
167 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
168 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
169 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
170 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
171 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
172 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
173 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
174 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
175 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
176 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
177 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
178 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
179 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
180 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
181 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
182 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
183 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
184 };
185 
186 static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = {
187 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
188 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
189 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
190 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
191 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
192 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
193 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
194 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
195 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RD_BURST_CNTL, 0x0000000f, 0x00000003),
196 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
197 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
198 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
199 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
200 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
201 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
202 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
203 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
204 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
205 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
206 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
207 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
208 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
209 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
210 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
211 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
212 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0),
213 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
214 };
215 
216 static const struct soc15_reg_golden golden_settings_sdma_rv1[] =
217 {
218 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002),
219 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002)
220 };
221 
222 static const struct soc15_reg_golden golden_settings_sdma_rv2[] =
223 {
224 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00003001),
225 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003001)
226 };
227 
228 static const struct soc15_reg_golden golden_settings_sdma_arct[] =
229 {
230 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
231 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
232 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
233 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
234 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
235 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
236 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
237 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
238 	SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
239 	SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
240 	SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
241 	SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
242 	SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
243 	SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
244 	SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
245 	SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
246 	SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
247 	SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
248 	SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
249 	SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
250 	SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
251 	SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
252 	SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
253 	SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
254 	SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
255 	SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
256 	SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
257 	SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
258 	SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
259 	SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
260 	SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
261 	SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_UTCL1_TIMEOUT, 0xffffffff, 0x00010001)
262 };
263 
264 static const struct soc15_reg_golden golden_settings_sdma_aldebaran[] = {
265 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
266 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
267 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
268 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
269 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
270 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
271 	SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
272 	SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
273 	SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA2_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
274 	SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
275 	SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
276 	SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
277 	SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
278 	SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
279 	SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
280 };
281 
282 static const struct soc15_reg_golden golden_settings_sdma_4_3[] = {
283 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
284 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
285 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002),
286 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002),
287 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
288 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003fff07, 0x40000051),
289 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
290 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
291 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003e0),
292 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x03fbe1fe)
293 };
294 
295 static const struct soc15_ras_field_entry sdma_v4_0_ras_fields[] = {
296 	{ "SDMA_UCODE_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
297 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UCODE_BUF_SED),
298 	0, 0,
299 	},
300 	{ "SDMA_RB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
301 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_RB_CMD_BUF_SED),
302 	0, 0,
303 	},
304 	{ "SDMA_IB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
305 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_IB_CMD_BUF_SED),
306 	0, 0,
307 	},
308 	{ "SDMA_UTCL1_RD_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
309 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UTCL1_RD_FIFO_SED),
310 	0, 0,
311 	},
312 	{ "SDMA_UTCL1_RDBST_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
313 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UTCL1_RDBST_FIFO_SED),
314 	0, 0,
315 	},
316 	{ "SDMA_DATA_LUT_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
317 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_DATA_LUT_FIFO_SED),
318 	0, 0,
319 	},
320 	{ "SDMA_MBANK_DATA_BUF0_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
321 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF0_SED),
322 	0, 0,
323 	},
324 	{ "SDMA_MBANK_DATA_BUF1_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
325 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF1_SED),
326 	0, 0,
327 	},
328 	{ "SDMA_MBANK_DATA_BUF2_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
329 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF2_SED),
330 	0, 0,
331 	},
332 	{ "SDMA_MBANK_DATA_BUF3_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
333 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF3_SED),
334 	0, 0,
335 	},
336 	{ "SDMA_MBANK_DATA_BUF4_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
337 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF4_SED),
338 	0, 0,
339 	},
340 	{ "SDMA_MBANK_DATA_BUF5_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
341 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF5_SED),
342 	0, 0,
343 	},
344 	{ "SDMA_MBANK_DATA_BUF6_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
345 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF6_SED),
346 	0, 0,
347 	},
348 	{ "SDMA_MBANK_DATA_BUF7_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
349 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF7_SED),
350 	0, 0,
351 	},
352 	{ "SDMA_MBANK_DATA_BUF8_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
353 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF8_SED),
354 	0, 0,
355 	},
356 	{ "SDMA_MBANK_DATA_BUF9_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
357 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF9_SED),
358 	0, 0,
359 	},
360 	{ "SDMA_MBANK_DATA_BUF10_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
361 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF10_SED),
362 	0, 0,
363 	},
364 	{ "SDMA_MBANK_DATA_BUF11_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
365 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF11_SED),
366 	0, 0,
367 	},
368 	{ "SDMA_MBANK_DATA_BUF12_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
369 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF12_SED),
370 	0, 0,
371 	},
372 	{ "SDMA_MBANK_DATA_BUF13_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
373 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF13_SED),
374 	0, 0,
375 	},
376 	{ "SDMA_MBANK_DATA_BUF14_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
377 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF14_SED),
378 	0, 0,
379 	},
380 	{ "SDMA_MBANK_DATA_BUF15_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
381 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF15_SED),
382 	0, 0,
383 	},
384 	{ "SDMA_SPLIT_DAT_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
385 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_SPLIT_DAT_BUF_SED),
386 	0, 0,
387 	},
388 	{ "SDMA_MC_WR_ADDR_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
389 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MC_WR_ADDR_FIFO_SED),
390 	0, 0,
391 	},
392 };
393 
394 static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev,
395 		u32 instance, u32 offset)
396 {
397 	switch (instance) {
398 	case 0:
399 		return (adev->reg_offset[SDMA0_HWIP][0][0] + offset);
400 	case 1:
401 		return (adev->reg_offset[SDMA1_HWIP][0][0] + offset);
402 	case 2:
403 		return (adev->reg_offset[SDMA2_HWIP][0][1] + offset);
404 	case 3:
405 		return (adev->reg_offset[SDMA3_HWIP][0][1] + offset);
406 	case 4:
407 		return (adev->reg_offset[SDMA4_HWIP][0][1] + offset);
408 	case 5:
409 		return (adev->reg_offset[SDMA5_HWIP][0][1] + offset);
410 	case 6:
411 		return (adev->reg_offset[SDMA6_HWIP][0][1] + offset);
412 	case 7:
413 		return (adev->reg_offset[SDMA7_HWIP][0][1] + offset);
414 	default:
415 		break;
416 	}
417 	return 0;
418 }
419 
420 static unsigned sdma_v4_0_seq_to_irq_id(int seq_num)
421 {
422 	switch (seq_num) {
423 	case 0:
424 		return SOC15_IH_CLIENTID_SDMA0;
425 	case 1:
426 		return SOC15_IH_CLIENTID_SDMA1;
427 	case 2:
428 		return SOC15_IH_CLIENTID_SDMA2;
429 	case 3:
430 		return SOC15_IH_CLIENTID_SDMA3;
431 	case 4:
432 		return SOC15_IH_CLIENTID_SDMA4;
433 	case 5:
434 		return SOC15_IH_CLIENTID_SDMA5;
435 	case 6:
436 		return SOC15_IH_CLIENTID_SDMA6;
437 	case 7:
438 		return SOC15_IH_CLIENTID_SDMA7;
439 	default:
440 		break;
441 	}
442 	return -EINVAL;
443 }
444 
445 static int sdma_v4_0_irq_id_to_seq(unsigned client_id)
446 {
447 	switch (client_id) {
448 	case SOC15_IH_CLIENTID_SDMA0:
449 		return 0;
450 	case SOC15_IH_CLIENTID_SDMA1:
451 		return 1;
452 	case SOC15_IH_CLIENTID_SDMA2:
453 		return 2;
454 	case SOC15_IH_CLIENTID_SDMA3:
455 		return 3;
456 	case SOC15_IH_CLIENTID_SDMA4:
457 		return 4;
458 	case SOC15_IH_CLIENTID_SDMA5:
459 		return 5;
460 	case SOC15_IH_CLIENTID_SDMA6:
461 		return 6;
462 	case SOC15_IH_CLIENTID_SDMA7:
463 		return 7;
464 	default:
465 		break;
466 	}
467 	return -EINVAL;
468 }
469 
470 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
471 {
472 	switch (adev->asic_type) {
473 	case CHIP_VEGA10:
474 		soc15_program_register_sequence(adev,
475 						golden_settings_sdma_4,
476 						ARRAY_SIZE(golden_settings_sdma_4));
477 		soc15_program_register_sequence(adev,
478 						golden_settings_sdma_vg10,
479 						ARRAY_SIZE(golden_settings_sdma_vg10));
480 		break;
481 	case CHIP_VEGA12:
482 		soc15_program_register_sequence(adev,
483 						golden_settings_sdma_4,
484 						ARRAY_SIZE(golden_settings_sdma_4));
485 		soc15_program_register_sequence(adev,
486 						golden_settings_sdma_vg12,
487 						ARRAY_SIZE(golden_settings_sdma_vg12));
488 		break;
489 	case CHIP_VEGA20:
490 		soc15_program_register_sequence(adev,
491 						golden_settings_sdma0_4_2_init,
492 						ARRAY_SIZE(golden_settings_sdma0_4_2_init));
493 		soc15_program_register_sequence(adev,
494 						golden_settings_sdma0_4_2,
495 						ARRAY_SIZE(golden_settings_sdma0_4_2));
496 		soc15_program_register_sequence(adev,
497 						golden_settings_sdma1_4_2,
498 						ARRAY_SIZE(golden_settings_sdma1_4_2));
499 		break;
500 	case CHIP_ARCTURUS:
501 		soc15_program_register_sequence(adev,
502 						golden_settings_sdma_arct,
503 						ARRAY_SIZE(golden_settings_sdma_arct));
504 		break;
505 	case CHIP_ALDEBARAN:
506 		soc15_program_register_sequence(adev,
507 						golden_settings_sdma_aldebaran,
508 						ARRAY_SIZE(golden_settings_sdma_aldebaran));
509 		break;
510 	case CHIP_RAVEN:
511 		soc15_program_register_sequence(adev,
512 						golden_settings_sdma_4_1,
513 						ARRAY_SIZE(golden_settings_sdma_4_1));
514 		if (adev->apu_flags & AMD_APU_IS_RAVEN2)
515 			soc15_program_register_sequence(adev,
516 							golden_settings_sdma_rv2,
517 							ARRAY_SIZE(golden_settings_sdma_rv2));
518 		else
519 			soc15_program_register_sequence(adev,
520 							golden_settings_sdma_rv1,
521 							ARRAY_SIZE(golden_settings_sdma_rv1));
522 		break;
523 	case CHIP_RENOIR:
524 		soc15_program_register_sequence(adev,
525 						golden_settings_sdma_4_3,
526 						ARRAY_SIZE(golden_settings_sdma_4_3));
527 		break;
528 	default:
529 		break;
530 	}
531 }
532 
533 static void sdma_v4_0_setup_ulv(struct amdgpu_device *adev)
534 {
535 	int i;
536 
537 	/*
538 	 * The only chips with SDMAv4 and ULV are VG10 and VG20.
539 	 * Server SKUs take a different hysteresis setting from other SKUs.
540 	 */
541 	switch (adev->asic_type) {
542 	case CHIP_VEGA10:
543 		if (adev->pdev->device == 0x6860)
544 			break;
545 		return;
546 	case CHIP_VEGA20:
547 		if (adev->pdev->device == 0x66a1)
548 			break;
549 		return;
550 	default:
551 		return;
552 	}
553 
554 	for (i = 0; i < adev->sdma.num_instances; i++) {
555 		uint32_t temp;
556 
557 		temp = RREG32_SDMA(i, mmSDMA0_ULV_CNTL);
558 		temp = REG_SET_FIELD(temp, SDMA0_ULV_CNTL, HYSTERESIS, 0x0);
559 		WREG32_SDMA(i, mmSDMA0_ULV_CNTL, temp);
560 	}
561 }
562 
563 static int sdma_v4_0_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst)
564 {
565 	int err = 0;
566 	const struct sdma_firmware_header_v1_0 *hdr;
567 
568 	err = amdgpu_ucode_validate(sdma_inst->fw);
569 	if (err)
570 		return err;
571 
572 	hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data;
573 	sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version);
574 	sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version);
575 
576 	if (sdma_inst->feature_version >= 20)
577 		sdma_inst->burst_nop = true;
578 
579 	return 0;
580 }
581 
582 static void sdma_v4_0_destroy_inst_ctx(struct amdgpu_device *adev)
583 {
584 	int i;
585 
586 	for (i = 0; i < adev->sdma.num_instances; i++) {
587 		release_firmware(adev->sdma.instance[i].fw);
588 		adev->sdma.instance[i].fw = NULL;
589 
590 		/* arcturus shares the same FW memory across
591 		   all SDMA isntances */
592 		if (adev->asic_type == CHIP_ARCTURUS ||
593 		    adev->asic_type == CHIP_ALDEBARAN)
594 			break;
595 	}
596 
597 	memset((void *)adev->sdma.instance, 0,
598 		sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES);
599 }
600 
601 /**
602  * sdma_v4_0_init_microcode - load ucode images from disk
603  *
604  * @adev: amdgpu_device pointer
605  *
606  * Use the firmware interface to load the ucode images into
607  * the driver (not loaded into hw).
608  * Returns 0 on success, error on failure.
609  */
610 
611 // emulation only, won't work on real chip
612 // vega10 real chip need to use PSP to load firmware
613 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
614 {
615 	const char *chip_name;
616 	char fw_name[30];
617 	int err = 0, i;
618 	struct amdgpu_firmware_info *info = NULL;
619 	const struct common_firmware_header *header = NULL;
620 
621 	DRM_DEBUG("\n");
622 
623 	switch (adev->asic_type) {
624 	case CHIP_VEGA10:
625 		chip_name = "vega10";
626 		break;
627 	case CHIP_VEGA12:
628 		chip_name = "vega12";
629 		break;
630 	case CHIP_VEGA20:
631 		chip_name = "vega20";
632 		break;
633 	case CHIP_RAVEN:
634 		if (adev->apu_flags & AMD_APU_IS_RAVEN2)
635 			chip_name = "raven2";
636 		else if (adev->apu_flags & AMD_APU_IS_PICASSO)
637 			chip_name = "picasso";
638 		else
639 			chip_name = "raven";
640 		break;
641 	case CHIP_ARCTURUS:
642 		chip_name = "arcturus";
643 		break;
644 	case CHIP_RENOIR:
645 		if (adev->apu_flags & AMD_APU_IS_RENOIR)
646 			chip_name = "renoir";
647 		else
648 			chip_name = "green_sardine";
649 		break;
650 	case CHIP_ALDEBARAN:
651 		chip_name = "aldebaran";
652 		break;
653 	default:
654 		BUG();
655 	}
656 
657 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
658 
659 	err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev);
660 	if (err)
661 		goto out;
662 
663 	err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[0]);
664 	if (err)
665 		goto out;
666 
667 	for (i = 1; i < adev->sdma.num_instances; i++) {
668 		if (adev->asic_type == CHIP_ARCTURUS ||
669 		    adev->asic_type == CHIP_ALDEBARAN) {
670 			/* Acturus & Aldebaran will leverage the same FW memory
671 			   for every SDMA instance */
672 			memcpy((void *)&adev->sdma.instance[i],
673 			       (void *)&adev->sdma.instance[0],
674 			       sizeof(struct amdgpu_sdma_instance));
675 		}
676 		else {
677 			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i);
678 
679 			err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
680 			if (err)
681 				goto out;
682 
683 			err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[i]);
684 			if (err)
685 				goto out;
686 		}
687 	}
688 
689 	DRM_DEBUG("psp_load == '%s'\n",
690 		adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
691 
692 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
693 		for (i = 0; i < adev->sdma.num_instances; i++) {
694 			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
695 			info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
696 			info->fw = adev->sdma.instance[i].fw;
697 			header = (const struct common_firmware_header *)info->fw->data;
698 			adev->firmware.fw_size +=
699 				ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
700 		}
701 	}
702 
703 out:
704 	if (err) {
705 		DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name);
706 		sdma_v4_0_destroy_inst_ctx(adev);
707 	}
708 	return err;
709 }
710 
711 /**
712  * sdma_v4_0_ring_get_rptr - get the current read pointer
713  *
714  * @ring: amdgpu ring pointer
715  *
716  * Get the current rptr from the hardware (VEGA10+).
717  */
718 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring)
719 {
720 	u64 *rptr;
721 
722 	/* XXX check if swapping is necessary on BE */
723 	rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
724 
725 	DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
726 	return ((*rptr) >> 2);
727 }
728 
729 /**
730  * sdma_v4_0_ring_get_wptr - get the current write pointer
731  *
732  * @ring: amdgpu ring pointer
733  *
734  * Get the current wptr from the hardware (VEGA10+).
735  */
736 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring)
737 {
738 	struct amdgpu_device *adev = ring->adev;
739 	u64 wptr;
740 
741 	if (ring->use_doorbell) {
742 		/* XXX check if swapping is necessary on BE */
743 		wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
744 		DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
745 	} else {
746 		wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI);
747 		wptr = wptr << 32;
748 		wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR);
749 		DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n",
750 				ring->me, wptr);
751 	}
752 
753 	return wptr >> 2;
754 }
755 
756 /**
757  * sdma_v4_0_ring_set_wptr - commit the write pointer
758  *
759  * @ring: amdgpu ring pointer
760  *
761  * Write the wptr back to the hardware (VEGA10+).
762  */
763 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
764 {
765 	struct amdgpu_device *adev = ring->adev;
766 
767 	DRM_DEBUG("Setting write pointer\n");
768 	if (ring->use_doorbell) {
769 		u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
770 
771 		DRM_DEBUG("Using doorbell -- "
772 				"wptr_offs == 0x%08x "
773 				"lower_32_bits(ring->wptr) << 2 == 0x%08x "
774 				"upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
775 				ring->wptr_offs,
776 				lower_32_bits(ring->wptr << 2),
777 				upper_32_bits(ring->wptr << 2));
778 		/* XXX check if swapping is necessary on BE */
779 		WRITE_ONCE(*wb, (ring->wptr << 2));
780 		DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
781 				ring->doorbell_index, ring->wptr << 2);
782 		WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
783 	} else {
784 		DRM_DEBUG("Not using doorbell -- "
785 				"mmSDMA%i_GFX_RB_WPTR == 0x%08x "
786 				"mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
787 				ring->me,
788 				lower_32_bits(ring->wptr << 2),
789 				ring->me,
790 				upper_32_bits(ring->wptr << 2));
791 		WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR,
792 			    lower_32_bits(ring->wptr << 2));
793 		WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI,
794 			    upper_32_bits(ring->wptr << 2));
795 	}
796 }
797 
798 /**
799  * sdma_v4_0_page_ring_get_wptr - get the current write pointer
800  *
801  * @ring: amdgpu ring pointer
802  *
803  * Get the current wptr from the hardware (VEGA10+).
804  */
805 static uint64_t sdma_v4_0_page_ring_get_wptr(struct amdgpu_ring *ring)
806 {
807 	struct amdgpu_device *adev = ring->adev;
808 	u64 wptr;
809 
810 	if (ring->use_doorbell) {
811 		/* XXX check if swapping is necessary on BE */
812 		wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
813 	} else {
814 		wptr = RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI);
815 		wptr = wptr << 32;
816 		wptr |= RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR);
817 	}
818 
819 	return wptr >> 2;
820 }
821 
822 /**
823  * sdma_v4_0_page_ring_set_wptr - commit the write pointer
824  *
825  * @ring: amdgpu ring pointer
826  *
827  * Write the wptr back to the hardware (VEGA10+).
828  */
829 static void sdma_v4_0_page_ring_set_wptr(struct amdgpu_ring *ring)
830 {
831 	struct amdgpu_device *adev = ring->adev;
832 
833 	if (ring->use_doorbell) {
834 		u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
835 
836 		/* XXX check if swapping is necessary on BE */
837 		WRITE_ONCE(*wb, (ring->wptr << 2));
838 		WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
839 	} else {
840 		uint64_t wptr = ring->wptr << 2;
841 
842 		WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR,
843 			    lower_32_bits(wptr));
844 		WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI,
845 			    upper_32_bits(wptr));
846 	}
847 }
848 
849 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
850 {
851 	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
852 	int i;
853 
854 	for (i = 0; i < count; i++)
855 		if (sdma && sdma->burst_nop && (i == 0))
856 			amdgpu_ring_write(ring, ring->funcs->nop |
857 				SDMA_PKT_NOP_HEADER_COUNT(count - 1));
858 		else
859 			amdgpu_ring_write(ring, ring->funcs->nop);
860 }
861 
862 /**
863  * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine
864  *
865  * @ring: amdgpu ring pointer
866  * @job: job to retrieve vmid from
867  * @ib: IB object to schedule
868  * @flags: unused
869  *
870  * Schedule an IB in the DMA ring (VEGA10).
871  */
872 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring,
873 				   struct amdgpu_job *job,
874 				   struct amdgpu_ib *ib,
875 				   uint32_t flags)
876 {
877 	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
878 
879 	/* IB packet must end on a 8 DW boundary */
880 	sdma_v4_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
881 
882 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
883 			  SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
884 	/* base must be 32 byte aligned */
885 	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
886 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
887 	amdgpu_ring_write(ring, ib->length_dw);
888 	amdgpu_ring_write(ring, 0);
889 	amdgpu_ring_write(ring, 0);
890 
891 }
892 
893 static void sdma_v4_0_wait_reg_mem(struct amdgpu_ring *ring,
894 				   int mem_space, int hdp,
895 				   uint32_t addr0, uint32_t addr1,
896 				   uint32_t ref, uint32_t mask,
897 				   uint32_t inv)
898 {
899 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
900 			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) |
901 			  SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) |
902 			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
903 	if (mem_space) {
904 		/* memory */
905 		amdgpu_ring_write(ring, addr0);
906 		amdgpu_ring_write(ring, addr1);
907 	} else {
908 		/* registers */
909 		amdgpu_ring_write(ring, addr0 << 2);
910 		amdgpu_ring_write(ring, addr1 << 2);
911 	}
912 	amdgpu_ring_write(ring, ref); /* reference */
913 	amdgpu_ring_write(ring, mask); /* mask */
914 	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
915 			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */
916 }
917 
918 /**
919  * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
920  *
921  * @ring: amdgpu ring pointer
922  *
923  * Emit an hdp flush packet on the requested DMA ring.
924  */
925 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
926 {
927 	struct amdgpu_device *adev = ring->adev;
928 	u32 ref_and_mask = 0;
929 	const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
930 
931 	ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
932 
933 	sdma_v4_0_wait_reg_mem(ring, 0, 1,
934 			       adev->nbio.funcs->get_hdp_flush_done_offset(adev),
935 			       adev->nbio.funcs->get_hdp_flush_req_offset(adev),
936 			       ref_and_mask, ref_and_mask, 10);
937 }
938 
939 /**
940  * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring
941  *
942  * @ring: amdgpu ring pointer
943  * @addr: address
944  * @seq: sequence number
945  * @flags: fence related flags
946  *
947  * Add a DMA fence packet to the ring to write
948  * the fence seq number and DMA trap packet to generate
949  * an interrupt if needed (VEGA10).
950  */
951 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
952 				      unsigned flags)
953 {
954 	bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
955 	/* write the fence */
956 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
957 	/* zero in first two bits */
958 	BUG_ON(addr & 0x3);
959 	amdgpu_ring_write(ring, lower_32_bits(addr));
960 	amdgpu_ring_write(ring, upper_32_bits(addr));
961 	amdgpu_ring_write(ring, lower_32_bits(seq));
962 
963 	/* optionally write high bits as well */
964 	if (write64bit) {
965 		addr += 4;
966 		amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
967 		/* zero in first two bits */
968 		BUG_ON(addr & 0x3);
969 		amdgpu_ring_write(ring, lower_32_bits(addr));
970 		amdgpu_ring_write(ring, upper_32_bits(addr));
971 		amdgpu_ring_write(ring, upper_32_bits(seq));
972 	}
973 
974 	/* generate an interrupt */
975 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
976 	amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
977 }
978 
979 
980 /**
981  * sdma_v4_0_gfx_stop - stop the gfx async dma engines
982  *
983  * @adev: amdgpu_device pointer
984  *
985  * Stop the gfx async dma ring buffers (VEGA10).
986  */
987 static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev)
988 {
989 	struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES];
990 	u32 rb_cntl, ib_cntl;
991 	int i, unset = 0;
992 
993 	for (i = 0; i < adev->sdma.num_instances; i++) {
994 		sdma[i] = &adev->sdma.instance[i].ring;
995 
996 		if ((adev->mman.buffer_funcs_ring == sdma[i]) && unset != 1) {
997 			amdgpu_ttm_set_buffer_funcs_status(adev, false);
998 			unset = 1;
999 		}
1000 
1001 		rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL);
1002 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
1003 		WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
1004 		ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL);
1005 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
1006 		WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);
1007 	}
1008 }
1009 
1010 /**
1011  * sdma_v4_0_rlc_stop - stop the compute async dma engines
1012  *
1013  * @adev: amdgpu_device pointer
1014  *
1015  * Stop the compute async dma queues (VEGA10).
1016  */
1017 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev)
1018 {
1019 	/* XXX todo */
1020 }
1021 
1022 /**
1023  * sdma_v4_0_page_stop - stop the page async dma engines
1024  *
1025  * @adev: amdgpu_device pointer
1026  *
1027  * Stop the page async dma ring buffers (VEGA10).
1028  */
1029 static void sdma_v4_0_page_stop(struct amdgpu_device *adev)
1030 {
1031 	struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES];
1032 	u32 rb_cntl, ib_cntl;
1033 	int i;
1034 	bool unset = false;
1035 
1036 	for (i = 0; i < adev->sdma.num_instances; i++) {
1037 		sdma[i] = &adev->sdma.instance[i].page;
1038 
1039 		if ((adev->mman.buffer_funcs_ring == sdma[i]) &&
1040 			(!unset)) {
1041 			amdgpu_ttm_set_buffer_funcs_status(adev, false);
1042 			unset = true;
1043 		}
1044 
1045 		rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL);
1046 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL,
1047 					RB_ENABLE, 0);
1048 		WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
1049 		ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL);
1050 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL,
1051 					IB_ENABLE, 0);
1052 		WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl);
1053 	}
1054 }
1055 
1056 /**
1057  * sdma_v4_0_ctx_switch_enable - stop the async dma engines context switch
1058  *
1059  * @adev: amdgpu_device pointer
1060  * @enable: enable/disable the DMA MEs context switch.
1061  *
1062  * Halt or unhalt the async dma engines context switch (VEGA10).
1063  */
1064 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
1065 {
1066 	u32 f32_cntl, phase_quantum = 0;
1067 	int i;
1068 
1069 	if (amdgpu_sdma_phase_quantum) {
1070 		unsigned value = amdgpu_sdma_phase_quantum;
1071 		unsigned unit = 0;
1072 
1073 		while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
1074 				SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
1075 			value = (value + 1) >> 1;
1076 			unit++;
1077 		}
1078 		if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
1079 			    SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
1080 			value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
1081 				 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
1082 			unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
1083 				SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
1084 			WARN_ONCE(1,
1085 			"clamping sdma_phase_quantum to %uK clock cycles\n",
1086 				  value << unit);
1087 		}
1088 		phase_quantum =
1089 			value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
1090 			unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
1091 	}
1092 
1093 	for (i = 0; i < adev->sdma.num_instances; i++) {
1094 		f32_cntl = RREG32_SDMA(i, mmSDMA0_CNTL);
1095 		f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
1096 				AUTO_CTXSW_ENABLE, enable ? 1 : 0);
1097 		if (enable && amdgpu_sdma_phase_quantum) {
1098 			WREG32_SDMA(i, mmSDMA0_PHASE0_QUANTUM, phase_quantum);
1099 			WREG32_SDMA(i, mmSDMA0_PHASE1_QUANTUM, phase_quantum);
1100 			WREG32_SDMA(i, mmSDMA0_PHASE2_QUANTUM, phase_quantum);
1101 		}
1102 		WREG32_SDMA(i, mmSDMA0_CNTL, f32_cntl);
1103 
1104 		/*
1105 		 * Enable SDMA utilization. Its only supported on
1106 		 * Arcturus for the moment and firmware version 14
1107 		 * and above.
1108 		 */
1109 		if (adev->asic_type == CHIP_ARCTURUS &&
1110 		    adev->sdma.instance[i].fw_version >= 14)
1111 			WREG32_SDMA(i, mmSDMA0_PUB_DUMMY_REG2, enable);
1112 		/* Extend page fault timeout to avoid interrupt storm */
1113 		WREG32_SDMA(i, mmSDMA0_UTCL1_TIMEOUT, 0x00800080);
1114 	}
1115 
1116 }
1117 
1118 /**
1119  * sdma_v4_0_enable - stop the async dma engines
1120  *
1121  * @adev: amdgpu_device pointer
1122  * @enable: enable/disable the DMA MEs.
1123  *
1124  * Halt or unhalt the async dma engines (VEGA10).
1125  */
1126 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable)
1127 {
1128 	u32 f32_cntl;
1129 	int i;
1130 
1131 	if (!enable) {
1132 		sdma_v4_0_gfx_stop(adev);
1133 		sdma_v4_0_rlc_stop(adev);
1134 		if (adev->sdma.has_page_queue)
1135 			sdma_v4_0_page_stop(adev);
1136 	}
1137 
1138 	for (i = 0; i < adev->sdma.num_instances; i++) {
1139 		f32_cntl = RREG32_SDMA(i, mmSDMA0_F32_CNTL);
1140 		f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
1141 		WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl);
1142 	}
1143 }
1144 
1145 /*
1146  * sdma_v4_0_rb_cntl - get parameters for rb_cntl
1147  */
1148 static uint32_t sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl)
1149 {
1150 	/* Set ring buffer size in dwords */
1151 	uint32_t rb_bufsz = order_base_2(ring->ring_size / 4);
1152 
1153 	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
1154 #ifdef __BIG_ENDIAN
1155 	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
1156 	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
1157 				RPTR_WRITEBACK_SWAP_ENABLE, 1);
1158 #endif
1159 	return rb_cntl;
1160 }
1161 
1162 /**
1163  * sdma_v4_0_gfx_resume - setup and start the async dma engines
1164  *
1165  * @adev: amdgpu_device pointer
1166  * @i: instance to resume
1167  *
1168  * Set up the gfx DMA ring buffers and enable them (VEGA10).
1169  * Returns 0 for success, error for failure.
1170  */
1171 static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i)
1172 {
1173 	struct amdgpu_ring *ring = &adev->sdma.instance[i].ring;
1174 	u32 rb_cntl, ib_cntl, wptr_poll_cntl;
1175 	u32 wb_offset;
1176 	u32 doorbell;
1177 	u32 doorbell_offset;
1178 	u64 wptr_gpu_addr;
1179 
1180 	wb_offset = (ring->rptr_offs * 4);
1181 
1182 	rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL);
1183 	rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl);
1184 	WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
1185 
1186 	/* Initialize the ring buffer's read and write pointers */
1187 	WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR, 0);
1188 	WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_HI, 0);
1189 	WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR, 0);
1190 	WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_HI, 0);
1191 
1192 	/* set the wb address whether it's enabled or not */
1193 	WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI,
1194 	       upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
1195 	WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO,
1196 	       lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
1197 
1198 	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
1199 				RPTR_WRITEBACK_ENABLE, 1);
1200 
1201 	WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE, ring->gpu_addr >> 8);
1202 	WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE_HI, ring->gpu_addr >> 40);
1203 
1204 	ring->wptr = 0;
1205 
1206 	/* before programing wptr to a less value, need set minor_ptr_update first */
1207 	WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 1);
1208 
1209 	doorbell = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL);
1210 	doorbell_offset = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET);
1211 
1212 	doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE,
1213 				 ring->use_doorbell);
1214 	doorbell_offset = REG_SET_FIELD(doorbell_offset,
1215 					SDMA0_GFX_DOORBELL_OFFSET,
1216 					OFFSET, ring->doorbell_index);
1217 	WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL, doorbell);
1218 	WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET, doorbell_offset);
1219 
1220 	sdma_v4_0_ring_set_wptr(ring);
1221 
1222 	/* set minor_ptr_update to 0 after wptr programed */
1223 	WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 0);
1224 
1225 	/* setup the wptr shadow polling */
1226 	wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
1227 	WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO,
1228 		    lower_32_bits(wptr_gpu_addr));
1229 	WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI,
1230 		    upper_32_bits(wptr_gpu_addr));
1231 	wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL);
1232 	wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
1233 				       SDMA0_GFX_RB_WPTR_POLL_CNTL,
1234 				       F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
1235 	WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
1236 
1237 	/* enable DMA RB */
1238 	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
1239 	WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
1240 
1241 	ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL);
1242 	ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
1243 #ifdef __BIG_ENDIAN
1244 	ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
1245 #endif
1246 	/* enable DMA IBs */
1247 	WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);
1248 
1249 	ring->sched.ready = true;
1250 }
1251 
1252 /**
1253  * sdma_v4_0_page_resume - setup and start the async dma engines
1254  *
1255  * @adev: amdgpu_device pointer
1256  * @i: instance to resume
1257  *
1258  * Set up the page DMA ring buffers and enable them (VEGA10).
1259  * Returns 0 for success, error for failure.
1260  */
1261 static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i)
1262 {
1263 	struct amdgpu_ring *ring = &adev->sdma.instance[i].page;
1264 	u32 rb_cntl, ib_cntl, wptr_poll_cntl;
1265 	u32 wb_offset;
1266 	u32 doorbell;
1267 	u32 doorbell_offset;
1268 	u64 wptr_gpu_addr;
1269 
1270 	wb_offset = (ring->rptr_offs * 4);
1271 
1272 	rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL);
1273 	rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl);
1274 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
1275 
1276 	/* Initialize the ring buffer's read and write pointers */
1277 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR, 0);
1278 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_HI, 0);
1279 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR, 0);
1280 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_HI, 0);
1281 
1282 	/* set the wb address whether it's enabled or not */
1283 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_HI,
1284 	       upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
1285 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_LO,
1286 	       lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
1287 
1288 	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL,
1289 				RPTR_WRITEBACK_ENABLE, 1);
1290 
1291 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE, ring->gpu_addr >> 8);
1292 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE_HI, ring->gpu_addr >> 40);
1293 
1294 	ring->wptr = 0;
1295 
1296 	/* before programing wptr to a less value, need set minor_ptr_update first */
1297 	WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 1);
1298 
1299 	doorbell = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL);
1300 	doorbell_offset = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET);
1301 
1302 	doorbell = REG_SET_FIELD(doorbell, SDMA0_PAGE_DOORBELL, ENABLE,
1303 				 ring->use_doorbell);
1304 	doorbell_offset = REG_SET_FIELD(doorbell_offset,
1305 					SDMA0_PAGE_DOORBELL_OFFSET,
1306 					OFFSET, ring->doorbell_index);
1307 	WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL, doorbell);
1308 	WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET, doorbell_offset);
1309 
1310 	/* paging queue doorbell range is setup at sdma_v4_0_gfx_resume */
1311 	sdma_v4_0_page_ring_set_wptr(ring);
1312 
1313 	/* set minor_ptr_update to 0 after wptr programed */
1314 	WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 0);
1315 
1316 	/* setup the wptr shadow polling */
1317 	wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
1318 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO,
1319 		    lower_32_bits(wptr_gpu_addr));
1320 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI,
1321 		    upper_32_bits(wptr_gpu_addr));
1322 	wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL);
1323 	wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
1324 				       SDMA0_PAGE_RB_WPTR_POLL_CNTL,
1325 				       F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
1326 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
1327 
1328 	/* enable DMA RB */
1329 	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, RB_ENABLE, 1);
1330 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
1331 
1332 	ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL);
1333 	ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_ENABLE, 1);
1334 #ifdef __BIG_ENDIAN
1335 	ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1);
1336 #endif
1337 	/* enable DMA IBs */
1338 	WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl);
1339 
1340 	ring->sched.ready = true;
1341 }
1342 
1343 static void
1344 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable)
1345 {
1346 	uint32_t def, data;
1347 
1348 	if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) {
1349 		/* enable idle interrupt */
1350 		def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
1351 		data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
1352 
1353 		if (data != def)
1354 			WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
1355 	} else {
1356 		/* disable idle interrupt */
1357 		def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
1358 		data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
1359 		if (data != def)
1360 			WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
1361 	}
1362 }
1363 
1364 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev)
1365 {
1366 	uint32_t def, data;
1367 
1368 	/* Enable HW based PG. */
1369 	def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1370 	data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK;
1371 	if (data != def)
1372 		WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1373 
1374 	/* enable interrupt */
1375 	def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
1376 	data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
1377 	if (data != def)
1378 		WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
1379 
1380 	/* Configure hold time to filter in-valid power on/off request. Use default right now */
1381 	def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1382 	data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK;
1383 	data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK);
1384 	/* Configure switch time for hysteresis purpose. Use default right now */
1385 	data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK;
1386 	data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK);
1387 	if(data != def)
1388 		WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1389 }
1390 
1391 static void sdma_v4_0_init_pg(struct amdgpu_device *adev)
1392 {
1393 	if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA))
1394 		return;
1395 
1396 	switch (adev->asic_type) {
1397 	case CHIP_RAVEN:
1398 	case CHIP_RENOIR:
1399 		sdma_v4_1_init_power_gating(adev);
1400 		sdma_v4_1_update_power_gating(adev, true);
1401 		break;
1402 	default:
1403 		break;
1404 	}
1405 }
1406 
1407 /**
1408  * sdma_v4_0_rlc_resume - setup and start the async dma engines
1409  *
1410  * @adev: amdgpu_device pointer
1411  *
1412  * Set up the compute DMA queues and enable them (VEGA10).
1413  * Returns 0 for success, error for failure.
1414  */
1415 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev)
1416 {
1417 	sdma_v4_0_init_pg(adev);
1418 
1419 	return 0;
1420 }
1421 
1422 /**
1423  * sdma_v4_0_load_microcode - load the sDMA ME ucode
1424  *
1425  * @adev: amdgpu_device pointer
1426  *
1427  * Loads the sDMA0/1 ucode.
1428  * Returns 0 for success, -EINVAL if the ucode is not available.
1429  */
1430 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev)
1431 {
1432 	const struct sdma_firmware_header_v1_0 *hdr;
1433 	const __le32 *fw_data;
1434 	u32 fw_size;
1435 	int i, j;
1436 
1437 	/* halt the MEs */
1438 	sdma_v4_0_enable(adev, false);
1439 
1440 	for (i = 0; i < adev->sdma.num_instances; i++) {
1441 		if (!adev->sdma.instance[i].fw)
1442 			return -EINVAL;
1443 
1444 		hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
1445 		amdgpu_ucode_print_sdma_hdr(&hdr->header);
1446 		fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1447 
1448 		fw_data = (const __le32 *)
1449 			(adev->sdma.instance[i].fw->data +
1450 				le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1451 
1452 		WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 0);
1453 
1454 		for (j = 0; j < fw_size; j++)
1455 			WREG32_SDMA(i, mmSDMA0_UCODE_DATA,
1456 				    le32_to_cpup(fw_data++));
1457 
1458 		WREG32_SDMA(i, mmSDMA0_UCODE_ADDR,
1459 			    adev->sdma.instance[i].fw_version);
1460 	}
1461 
1462 	return 0;
1463 }
1464 
1465 /**
1466  * sdma_v4_0_start - setup and start the async dma engines
1467  *
1468  * @adev: amdgpu_device pointer
1469  *
1470  * Set up the DMA engines and enable them (VEGA10).
1471  * Returns 0 for success, error for failure.
1472  */
1473 static int sdma_v4_0_start(struct amdgpu_device *adev)
1474 {
1475 	struct amdgpu_ring *ring;
1476 	int i, r = 0;
1477 
1478 	if (amdgpu_sriov_vf(adev)) {
1479 		sdma_v4_0_ctx_switch_enable(adev, false);
1480 		sdma_v4_0_enable(adev, false);
1481 	} else {
1482 
1483 		if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1484 			r = sdma_v4_0_load_microcode(adev);
1485 			if (r)
1486 				return r;
1487 		}
1488 
1489 		/* unhalt the MEs */
1490 		sdma_v4_0_enable(adev, true);
1491 		/* enable sdma ring preemption */
1492 		sdma_v4_0_ctx_switch_enable(adev, true);
1493 	}
1494 
1495 	/* start the gfx rings and rlc compute queues */
1496 	for (i = 0; i < adev->sdma.num_instances; i++) {
1497 		uint32_t temp;
1498 
1499 		WREG32_SDMA(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL, 0);
1500 		sdma_v4_0_gfx_resume(adev, i);
1501 		if (adev->sdma.has_page_queue)
1502 			sdma_v4_0_page_resume(adev, i);
1503 
1504 		/* set utc l1 enable flag always to 1 */
1505 		temp = RREG32_SDMA(i, mmSDMA0_CNTL);
1506 		temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
1507 		WREG32_SDMA(i, mmSDMA0_CNTL, temp);
1508 
1509 		if (!amdgpu_sriov_vf(adev)) {
1510 			/* unhalt engine */
1511 			temp = RREG32_SDMA(i, mmSDMA0_F32_CNTL);
1512 			temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
1513 			WREG32_SDMA(i, mmSDMA0_F32_CNTL, temp);
1514 		}
1515 	}
1516 
1517 	if (amdgpu_sriov_vf(adev)) {
1518 		sdma_v4_0_ctx_switch_enable(adev, true);
1519 		sdma_v4_0_enable(adev, true);
1520 	} else {
1521 		r = sdma_v4_0_rlc_resume(adev);
1522 		if (r)
1523 			return r;
1524 	}
1525 
1526 	for (i = 0; i < adev->sdma.num_instances; i++) {
1527 		ring = &adev->sdma.instance[i].ring;
1528 
1529 		r = amdgpu_ring_test_helper(ring);
1530 		if (r)
1531 			return r;
1532 
1533 		if (adev->sdma.has_page_queue) {
1534 			struct amdgpu_ring *page = &adev->sdma.instance[i].page;
1535 
1536 			r = amdgpu_ring_test_helper(page);
1537 			if (r)
1538 				return r;
1539 
1540 			if (adev->mman.buffer_funcs_ring == page)
1541 				amdgpu_ttm_set_buffer_funcs_status(adev, true);
1542 		}
1543 
1544 		if (adev->mman.buffer_funcs_ring == ring)
1545 			amdgpu_ttm_set_buffer_funcs_status(adev, true);
1546 	}
1547 
1548 	return r;
1549 }
1550 
1551 /**
1552  * sdma_v4_0_ring_test_ring - simple async dma engine test
1553  *
1554  * @ring: amdgpu_ring structure holding ring information
1555  *
1556  * Test the DMA engine by writing using it to write an
1557  * value to memory. (VEGA10).
1558  * Returns 0 for success, error for failure.
1559  */
1560 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring)
1561 {
1562 	struct amdgpu_device *adev = ring->adev;
1563 	unsigned i;
1564 	unsigned index;
1565 	int r;
1566 	u32 tmp;
1567 	u64 gpu_addr;
1568 
1569 	r = amdgpu_device_wb_get(adev, &index);
1570 	if (r)
1571 		return r;
1572 
1573 	gpu_addr = adev->wb.gpu_addr + (index * 4);
1574 	tmp = 0xCAFEDEAD;
1575 	adev->wb.wb[index] = cpu_to_le32(tmp);
1576 
1577 	r = amdgpu_ring_alloc(ring, 5);
1578 	if (r)
1579 		goto error_free_wb;
1580 
1581 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1582 			  SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
1583 	amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
1584 	amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
1585 	amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
1586 	amdgpu_ring_write(ring, 0xDEADBEEF);
1587 	amdgpu_ring_commit(ring);
1588 
1589 	for (i = 0; i < adev->usec_timeout; i++) {
1590 		tmp = le32_to_cpu(adev->wb.wb[index]);
1591 		if (tmp == 0xDEADBEEF)
1592 			break;
1593 		udelay(1);
1594 	}
1595 
1596 	if (i >= adev->usec_timeout)
1597 		r = -ETIMEDOUT;
1598 
1599 error_free_wb:
1600 	amdgpu_device_wb_free(adev, index);
1601 	return r;
1602 }
1603 
1604 /**
1605  * sdma_v4_0_ring_test_ib - test an IB on the DMA engine
1606  *
1607  * @ring: amdgpu_ring structure holding ring information
1608  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
1609  *
1610  * Test a simple IB in the DMA ring (VEGA10).
1611  * Returns 0 on success, error on failure.
1612  */
1613 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1614 {
1615 	struct amdgpu_device *adev = ring->adev;
1616 	struct amdgpu_ib ib;
1617 	struct dma_fence *f = NULL;
1618 	unsigned index;
1619 	long r;
1620 	u32 tmp = 0;
1621 	u64 gpu_addr;
1622 
1623 	r = amdgpu_device_wb_get(adev, &index);
1624 	if (r)
1625 		return r;
1626 
1627 	gpu_addr = adev->wb.gpu_addr + (index * 4);
1628 	tmp = 0xCAFEDEAD;
1629 	adev->wb.wb[index] = cpu_to_le32(tmp);
1630 	memset(&ib, 0, sizeof(ib));
1631 	r = amdgpu_ib_get(adev, NULL, 256,
1632 					AMDGPU_IB_POOL_DIRECT, &ib);
1633 	if (r)
1634 		goto err0;
1635 
1636 	ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1637 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1638 	ib.ptr[1] = lower_32_bits(gpu_addr);
1639 	ib.ptr[2] = upper_32_bits(gpu_addr);
1640 	ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1641 	ib.ptr[4] = 0xDEADBEEF;
1642 	ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1643 	ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1644 	ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1645 	ib.length_dw = 8;
1646 
1647 	r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1648 	if (r)
1649 		goto err1;
1650 
1651 	r = dma_fence_wait_timeout(f, false, timeout);
1652 	if (r == 0) {
1653 		r = -ETIMEDOUT;
1654 		goto err1;
1655 	} else if (r < 0) {
1656 		goto err1;
1657 	}
1658 	tmp = le32_to_cpu(adev->wb.wb[index]);
1659 	if (tmp == 0xDEADBEEF)
1660 		r = 0;
1661 	else
1662 		r = -EINVAL;
1663 
1664 err1:
1665 	amdgpu_ib_free(adev, &ib, NULL);
1666 	dma_fence_put(f);
1667 err0:
1668 	amdgpu_device_wb_free(adev, index);
1669 	return r;
1670 }
1671 
1672 
1673 /**
1674  * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART
1675  *
1676  * @ib: indirect buffer to fill with commands
1677  * @pe: addr of the page entry
1678  * @src: src addr to copy from
1679  * @count: number of page entries to update
1680  *
1681  * Update PTEs by copying them from the GART using sDMA (VEGA10).
1682  */
1683 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib,
1684 				  uint64_t pe, uint64_t src,
1685 				  unsigned count)
1686 {
1687 	unsigned bytes = count * 8;
1688 
1689 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1690 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1691 	ib->ptr[ib->length_dw++] = bytes - 1;
1692 	ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1693 	ib->ptr[ib->length_dw++] = lower_32_bits(src);
1694 	ib->ptr[ib->length_dw++] = upper_32_bits(src);
1695 	ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1696 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1697 
1698 }
1699 
1700 /**
1701  * sdma_v4_0_vm_write_pte - update PTEs by writing them manually
1702  *
1703  * @ib: indirect buffer to fill with commands
1704  * @pe: addr of the page entry
1705  * @value: dst addr to write into pe
1706  * @count: number of page entries to update
1707  * @incr: increase next addr by incr bytes
1708  *
1709  * Update PTEs by writing them manually using sDMA (VEGA10).
1710  */
1711 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1712 				   uint64_t value, unsigned count,
1713 				   uint32_t incr)
1714 {
1715 	unsigned ndw = count * 2;
1716 
1717 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1718 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1719 	ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1720 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1721 	ib->ptr[ib->length_dw++] = ndw - 1;
1722 	for (; ndw > 0; ndw -= 2) {
1723 		ib->ptr[ib->length_dw++] = lower_32_bits(value);
1724 		ib->ptr[ib->length_dw++] = upper_32_bits(value);
1725 		value += incr;
1726 	}
1727 }
1728 
1729 /**
1730  * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA
1731  *
1732  * @ib: indirect buffer to fill with commands
1733  * @pe: addr of the page entry
1734  * @addr: dst addr to write into pe
1735  * @count: number of page entries to update
1736  * @incr: increase next addr by incr bytes
1737  * @flags: access flags
1738  *
1739  * Update the page tables using sDMA (VEGA10).
1740  */
1741 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1742 				     uint64_t pe,
1743 				     uint64_t addr, unsigned count,
1744 				     uint32_t incr, uint64_t flags)
1745 {
1746 	/* for physically contiguous pages (vram) */
1747 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1748 	ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1749 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1750 	ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1751 	ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1752 	ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1753 	ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1754 	ib->ptr[ib->length_dw++] = incr; /* increment size */
1755 	ib->ptr[ib->length_dw++] = 0;
1756 	ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1757 }
1758 
1759 /**
1760  * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw
1761  *
1762  * @ring: amdgpu_ring structure holding ring information
1763  * @ib: indirect buffer to fill with padding
1764  */
1765 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1766 {
1767 	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1768 	u32 pad_count;
1769 	int i;
1770 
1771 	pad_count = (-ib->length_dw) & 7;
1772 	for (i = 0; i < pad_count; i++)
1773 		if (sdma && sdma->burst_nop && (i == 0))
1774 			ib->ptr[ib->length_dw++] =
1775 				SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1776 				SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1777 		else
1778 			ib->ptr[ib->length_dw++] =
1779 				SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1780 }
1781 
1782 
1783 /**
1784  * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline
1785  *
1786  * @ring: amdgpu_ring pointer
1787  *
1788  * Make sure all previous operations are completed (CIK).
1789  */
1790 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1791 {
1792 	uint32_t seq = ring->fence_drv.sync_seq;
1793 	uint64_t addr = ring->fence_drv.gpu_addr;
1794 
1795 	/* wait for idle */
1796 	sdma_v4_0_wait_reg_mem(ring, 1, 0,
1797 			       addr & 0xfffffffc,
1798 			       upper_32_bits(addr) & 0xffffffff,
1799 			       seq, 0xffffffff, 4);
1800 }
1801 
1802 
1803 /**
1804  * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA
1805  *
1806  * @ring: amdgpu_ring pointer
1807  * @vmid: vmid number to use
1808  * @pd_addr: address
1809  *
1810  * Update the page table base and flush the VM TLB
1811  * using sDMA (VEGA10).
1812  */
1813 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1814 					 unsigned vmid, uint64_t pd_addr)
1815 {
1816 	amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1817 }
1818 
1819 static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring,
1820 				     uint32_t reg, uint32_t val)
1821 {
1822 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1823 			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1824 	amdgpu_ring_write(ring, reg);
1825 	amdgpu_ring_write(ring, val);
1826 }
1827 
1828 static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1829 					 uint32_t val, uint32_t mask)
1830 {
1831 	sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10);
1832 }
1833 
1834 static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev)
1835 {
1836 	uint fw_version = adev->sdma.instance[0].fw_version;
1837 
1838 	switch (adev->asic_type) {
1839 	case CHIP_VEGA10:
1840 		return fw_version >= 430;
1841 	case CHIP_VEGA12:
1842 		/*return fw_version >= 31;*/
1843 		return false;
1844 	case CHIP_VEGA20:
1845 		return fw_version >= 123;
1846 	default:
1847 		return false;
1848 	}
1849 }
1850 
1851 static int sdma_v4_0_early_init(void *handle)
1852 {
1853 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1854 	int r;
1855 
1856 	if (adev->flags & AMD_IS_APU)
1857 		adev->sdma.num_instances = 1;
1858 	else if (adev->asic_type == CHIP_ARCTURUS)
1859 		adev->sdma.num_instances = 8;
1860 	else if (adev->asic_type == CHIP_ALDEBARAN)
1861 		adev->sdma.num_instances = 5;
1862 	else
1863 		adev->sdma.num_instances = 2;
1864 
1865 	r = sdma_v4_0_init_microcode(adev);
1866 	if (r) {
1867 		DRM_ERROR("Failed to load sdma firmware!\n");
1868 		return r;
1869 	}
1870 
1871 	/* TODO: Page queue breaks driver reload under SRIOV */
1872 	if ((adev->asic_type == CHIP_VEGA10) && amdgpu_sriov_vf((adev)))
1873 		adev->sdma.has_page_queue = false;
1874 	else if (sdma_v4_0_fw_support_paging_queue(adev))
1875 		adev->sdma.has_page_queue = true;
1876 
1877 	sdma_v4_0_set_ring_funcs(adev);
1878 	sdma_v4_0_set_buffer_funcs(adev);
1879 	sdma_v4_0_set_vm_pte_funcs(adev);
1880 	sdma_v4_0_set_irq_funcs(adev);
1881 	sdma_v4_0_set_ras_funcs(adev);
1882 
1883 	return 0;
1884 }
1885 
1886 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
1887 		void *err_data,
1888 		struct amdgpu_iv_entry *entry);
1889 
1890 static int sdma_v4_0_late_init(void *handle)
1891 {
1892 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1893 	struct ras_ih_if ih_info = {
1894 		.cb = sdma_v4_0_process_ras_data_cb,
1895 	};
1896 
1897 	sdma_v4_0_setup_ulv(adev);
1898 
1899 	if (!amdgpu_persistent_edc_harvesting_supported(adev)) {
1900 		if (adev->sdma.funcs &&
1901 		    adev->sdma.funcs->reset_ras_error_count)
1902 			adev->sdma.funcs->reset_ras_error_count(adev);
1903 	}
1904 
1905 	if (adev->sdma.funcs && adev->sdma.funcs->ras_late_init)
1906 		return adev->sdma.funcs->ras_late_init(adev, &ih_info);
1907 	else
1908 		return 0;
1909 }
1910 
1911 static int sdma_v4_0_sw_init(void *handle)
1912 {
1913 	struct amdgpu_ring *ring;
1914 	int r, i;
1915 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1916 
1917 	/* SDMA trap event */
1918 	for (i = 0; i < adev->sdma.num_instances; i++) {
1919 		r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1920 				      SDMA0_4_0__SRCID__SDMA_TRAP,
1921 				      &adev->sdma.trap_irq);
1922 		if (r)
1923 			return r;
1924 	}
1925 
1926 	/* SDMA SRAM ECC event */
1927 	for (i = 0; i < adev->sdma.num_instances; i++) {
1928 		r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1929 				      SDMA0_4_0__SRCID__SDMA_SRAM_ECC,
1930 				      &adev->sdma.ecc_irq);
1931 		if (r)
1932 			return r;
1933 	}
1934 
1935 	/* SDMA VM_HOLE/DOORBELL_INV/POLL_TIMEOUT/SRBM_WRITE_PROTECTION event*/
1936 	for (i = 0; i < adev->sdma.num_instances; i++) {
1937 		r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1938 				      SDMA0_4_0__SRCID__SDMA_VM_HOLE,
1939 				      &adev->sdma.vm_hole_irq);
1940 		if (r)
1941 			return r;
1942 
1943 		r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1944 				      SDMA0_4_0__SRCID__SDMA_DOORBELL_INVALID,
1945 				      &adev->sdma.doorbell_invalid_irq);
1946 		if (r)
1947 			return r;
1948 
1949 		r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1950 				      SDMA0_4_0__SRCID__SDMA_POLL_TIMEOUT,
1951 				      &adev->sdma.pool_timeout_irq);
1952 		if (r)
1953 			return r;
1954 
1955 		r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1956 				      SDMA0_4_0__SRCID__SDMA_SRBMWRITE,
1957 				      &adev->sdma.srbm_write_irq);
1958 		if (r)
1959 			return r;
1960 	}
1961 
1962 	for (i = 0; i < adev->sdma.num_instances; i++) {
1963 		ring = &adev->sdma.instance[i].ring;
1964 		ring->ring_obj = NULL;
1965 		ring->use_doorbell = true;
1966 
1967 		DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1968 				ring->use_doorbell?"true":"false");
1969 
1970 		/* doorbell size is 2 dwords, get DWORD offset */
1971 		ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
1972 
1973 		sprintf(ring->name, "sdma%d", i);
1974 		r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1975 				     AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1976 				     AMDGPU_RING_PRIO_DEFAULT, NULL);
1977 		if (r)
1978 			return r;
1979 
1980 		if (adev->sdma.has_page_queue) {
1981 			ring = &adev->sdma.instance[i].page;
1982 			ring->ring_obj = NULL;
1983 			ring->use_doorbell = true;
1984 
1985 			/* paging queue use same doorbell index/routing as gfx queue
1986 			 * with 0x400 (4096 dwords) offset on second doorbell page
1987 			 */
1988 			ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
1989 			ring->doorbell_index += 0x400;
1990 
1991 			sprintf(ring->name, "page%d", i);
1992 			r = amdgpu_ring_init(adev, ring, 1024,
1993 					     &adev->sdma.trap_irq,
1994 					     AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1995 					     AMDGPU_RING_PRIO_DEFAULT, NULL);
1996 			if (r)
1997 				return r;
1998 		}
1999 	}
2000 
2001 	return r;
2002 }
2003 
2004 static int sdma_v4_0_sw_fini(void *handle)
2005 {
2006 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2007 	int i;
2008 
2009 	if (adev->sdma.funcs && adev->sdma.funcs->ras_fini)
2010 		adev->sdma.funcs->ras_fini(adev);
2011 
2012 	for (i = 0; i < adev->sdma.num_instances; i++) {
2013 		amdgpu_ring_fini(&adev->sdma.instance[i].ring);
2014 		if (adev->sdma.has_page_queue)
2015 			amdgpu_ring_fini(&adev->sdma.instance[i].page);
2016 	}
2017 
2018 	sdma_v4_0_destroy_inst_ctx(adev);
2019 
2020 	return 0;
2021 }
2022 
2023 static int sdma_v4_0_hw_init(void *handle)
2024 {
2025 	int r;
2026 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2027 
2028 	if (adev->flags & AMD_IS_APU)
2029 		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false);
2030 
2031 	if (!amdgpu_sriov_vf(adev))
2032 		sdma_v4_0_init_golden_registers(adev);
2033 
2034 	r = sdma_v4_0_start(adev);
2035 
2036 	return r;
2037 }
2038 
2039 static int sdma_v4_0_hw_fini(void *handle)
2040 {
2041 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2042 	int i;
2043 
2044 	if (amdgpu_sriov_vf(adev))
2045 		return 0;
2046 
2047 	for (i = 0; i < adev->sdma.num_instances; i++) {
2048 		amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
2049 			       AMDGPU_SDMA_IRQ_INSTANCE0 + i);
2050 	}
2051 
2052 	sdma_v4_0_ctx_switch_enable(adev, false);
2053 	sdma_v4_0_enable(adev, false);
2054 
2055 	if (adev->flags & AMD_IS_APU)
2056 		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true);
2057 
2058 	return 0;
2059 }
2060 
2061 static int sdma_v4_0_suspend(void *handle)
2062 {
2063 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2064 
2065 	return sdma_v4_0_hw_fini(adev);
2066 }
2067 
2068 static int sdma_v4_0_resume(void *handle)
2069 {
2070 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2071 
2072 	return sdma_v4_0_hw_init(adev);
2073 }
2074 
2075 static bool sdma_v4_0_is_idle(void *handle)
2076 {
2077 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2078 	u32 i;
2079 
2080 	for (i = 0; i < adev->sdma.num_instances; i++) {
2081 		u32 tmp = RREG32_SDMA(i, mmSDMA0_STATUS_REG);
2082 
2083 		if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
2084 			return false;
2085 	}
2086 
2087 	return true;
2088 }
2089 
2090 static int sdma_v4_0_wait_for_idle(void *handle)
2091 {
2092 	unsigned i, j;
2093 	u32 sdma[AMDGPU_MAX_SDMA_INSTANCES];
2094 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2095 
2096 	for (i = 0; i < adev->usec_timeout; i++) {
2097 		for (j = 0; j < adev->sdma.num_instances; j++) {
2098 			sdma[j] = RREG32_SDMA(j, mmSDMA0_STATUS_REG);
2099 			if (!(sdma[j] & SDMA0_STATUS_REG__IDLE_MASK))
2100 				break;
2101 		}
2102 		if (j == adev->sdma.num_instances)
2103 			return 0;
2104 		udelay(1);
2105 	}
2106 	return -ETIMEDOUT;
2107 }
2108 
2109 static int sdma_v4_0_soft_reset(void *handle)
2110 {
2111 	/* todo */
2112 
2113 	return 0;
2114 }
2115 
2116 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev,
2117 					struct amdgpu_irq_src *source,
2118 					unsigned type,
2119 					enum amdgpu_interrupt_state state)
2120 {
2121 	u32 sdma_cntl;
2122 
2123 	sdma_cntl = RREG32_SDMA(type, mmSDMA0_CNTL);
2124 	sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
2125 		       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
2126 	WREG32_SDMA(type, mmSDMA0_CNTL, sdma_cntl);
2127 
2128 	return 0;
2129 }
2130 
2131 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,
2132 				      struct amdgpu_irq_src *source,
2133 				      struct amdgpu_iv_entry *entry)
2134 {
2135 	uint32_t instance;
2136 
2137 	DRM_DEBUG("IH: SDMA trap\n");
2138 	instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2139 	switch (entry->ring_id) {
2140 	case 0:
2141 		amdgpu_fence_process(&adev->sdma.instance[instance].ring);
2142 		break;
2143 	case 1:
2144 		if (adev->asic_type == CHIP_VEGA20)
2145 			amdgpu_fence_process(&adev->sdma.instance[instance].page);
2146 		break;
2147 	case 2:
2148 		/* XXX compute */
2149 		break;
2150 	case 3:
2151 		if (adev->asic_type != CHIP_VEGA20)
2152 			amdgpu_fence_process(&adev->sdma.instance[instance].page);
2153 		break;
2154 	}
2155 	return 0;
2156 }
2157 
2158 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
2159 		void *err_data,
2160 		struct amdgpu_iv_entry *entry)
2161 {
2162 	int instance;
2163 
2164 	/* When “Full RAS” is enabled, the per-IP interrupt sources should
2165 	 * be disabled and the driver should only look for the aggregated
2166 	 * interrupt via sync flood
2167 	 */
2168 	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
2169 		goto out;
2170 
2171 	instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2172 	if (instance < 0)
2173 		goto out;
2174 
2175 	amdgpu_sdma_process_ras_data_cb(adev, err_data, entry);
2176 
2177 out:
2178 	return AMDGPU_RAS_SUCCESS;
2179 }
2180 
2181 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev,
2182 					      struct amdgpu_irq_src *source,
2183 					      struct amdgpu_iv_entry *entry)
2184 {
2185 	int instance;
2186 
2187 	DRM_ERROR("Illegal instruction in SDMA command stream\n");
2188 
2189 	instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2190 	if (instance < 0)
2191 		return 0;
2192 
2193 	switch (entry->ring_id) {
2194 	case 0:
2195 		drm_sched_fault(&adev->sdma.instance[instance].ring.sched);
2196 		break;
2197 	}
2198 	return 0;
2199 }
2200 
2201 static int sdma_v4_0_set_ecc_irq_state(struct amdgpu_device *adev,
2202 					struct amdgpu_irq_src *source,
2203 					unsigned type,
2204 					enum amdgpu_interrupt_state state)
2205 {
2206 	u32 sdma_edc_config;
2207 
2208 	sdma_edc_config = RREG32_SDMA(type, mmSDMA0_EDC_CONFIG);
2209 	sdma_edc_config = REG_SET_FIELD(sdma_edc_config, SDMA0_EDC_CONFIG, ECC_INT_ENABLE,
2210 		       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
2211 	WREG32_SDMA(type, mmSDMA0_EDC_CONFIG, sdma_edc_config);
2212 
2213 	return 0;
2214 }
2215 
2216 static int sdma_v4_0_print_iv_entry(struct amdgpu_device *adev,
2217 					      struct amdgpu_iv_entry *entry)
2218 {
2219 	int instance;
2220 	struct amdgpu_task_info task_info;
2221 	u64 addr;
2222 
2223 	instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2224 	if (instance < 0 || instance >= adev->sdma.num_instances) {
2225 		dev_err(adev->dev, "sdma instance invalid %d\n", instance);
2226 		return -EINVAL;
2227 	}
2228 
2229 	addr = (u64)entry->src_data[0] << 12;
2230 	addr |= ((u64)entry->src_data[1] & 0xf) << 44;
2231 
2232 	memset(&task_info, 0, sizeof(struct amdgpu_task_info));
2233 	amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
2234 
2235 	dev_dbg_ratelimited(adev->dev,
2236 		   "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u "
2237 		   "pasid:%u, for process %s pid %d thread %s pid %d\n",
2238 		   instance, addr, entry->src_id, entry->ring_id, entry->vmid,
2239 		   entry->pasid, task_info.process_name, task_info.tgid,
2240 		   task_info.task_name, task_info.pid);
2241 	return 0;
2242 }
2243 
2244 static int sdma_v4_0_process_vm_hole_irq(struct amdgpu_device *adev,
2245 					      struct amdgpu_irq_src *source,
2246 					      struct amdgpu_iv_entry *entry)
2247 {
2248 	dev_dbg_ratelimited(adev->dev, "MC or SEM address in VM hole\n");
2249 	sdma_v4_0_print_iv_entry(adev, entry);
2250 	return 0;
2251 }
2252 
2253 static int sdma_v4_0_process_doorbell_invalid_irq(struct amdgpu_device *adev,
2254 					      struct amdgpu_irq_src *source,
2255 					      struct amdgpu_iv_entry *entry)
2256 {
2257 	dev_dbg_ratelimited(adev->dev, "SDMA received a doorbell from BIF with byte_enable !=0xff\n");
2258 	sdma_v4_0_print_iv_entry(adev, entry);
2259 	return 0;
2260 }
2261 
2262 static int sdma_v4_0_process_pool_timeout_irq(struct amdgpu_device *adev,
2263 					      struct amdgpu_irq_src *source,
2264 					      struct amdgpu_iv_entry *entry)
2265 {
2266 	dev_dbg_ratelimited(adev->dev,
2267 		"Polling register/memory timeout executing POLL_REG/MEM with finite timer\n");
2268 	sdma_v4_0_print_iv_entry(adev, entry);
2269 	return 0;
2270 }
2271 
2272 static int sdma_v4_0_process_srbm_write_irq(struct amdgpu_device *adev,
2273 					      struct amdgpu_irq_src *source,
2274 					      struct amdgpu_iv_entry *entry)
2275 {
2276 	dev_dbg_ratelimited(adev->dev,
2277 		"SDMA gets an Register Write SRBM_WRITE command in non-privilege command buffer\n");
2278 	sdma_v4_0_print_iv_entry(adev, entry);
2279 	return 0;
2280 }
2281 
2282 static void sdma_v4_0_update_medium_grain_clock_gating(
2283 		struct amdgpu_device *adev,
2284 		bool enable)
2285 {
2286 	uint32_t data, def;
2287 	int i;
2288 
2289 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
2290 		for (i = 0; i < adev->sdma.num_instances; i++) {
2291 			def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL);
2292 			data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
2293 				  SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
2294 				  SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
2295 				  SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
2296 				  SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
2297 				  SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
2298 				  SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
2299 				  SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
2300 			if (def != data)
2301 				WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data);
2302 		}
2303 	} else {
2304 		for (i = 0; i < adev->sdma.num_instances; i++) {
2305 			def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL);
2306 			data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
2307 				 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
2308 				 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
2309 				 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
2310 				 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
2311 				 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
2312 				 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
2313 				 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
2314 			if (def != data)
2315 				WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data);
2316 		}
2317 	}
2318 }
2319 
2320 
2321 static void sdma_v4_0_update_medium_grain_light_sleep(
2322 		struct amdgpu_device *adev,
2323 		bool enable)
2324 {
2325 	uint32_t data, def;
2326 	int i;
2327 
2328 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
2329 		for (i = 0; i < adev->sdma.num_instances; i++) {
2330 			/* 1-not override: enable sdma mem light sleep */
2331 			def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL);
2332 			data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
2333 			if (def != data)
2334 				WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data);
2335 		}
2336 	} else {
2337 		for (i = 0; i < adev->sdma.num_instances; i++) {
2338 		/* 0-override:disable sdma mem light sleep */
2339 			def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL);
2340 			data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
2341 			if (def != data)
2342 				WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data);
2343 		}
2344 	}
2345 }
2346 
2347 static int sdma_v4_0_set_clockgating_state(void *handle,
2348 					  enum amd_clockgating_state state)
2349 {
2350 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2351 
2352 	if (amdgpu_sriov_vf(adev))
2353 		return 0;
2354 
2355 	sdma_v4_0_update_medium_grain_clock_gating(adev,
2356 			state == AMD_CG_STATE_GATE);
2357 	sdma_v4_0_update_medium_grain_light_sleep(adev,
2358 			state == AMD_CG_STATE_GATE);
2359 	return 0;
2360 }
2361 
2362 static int sdma_v4_0_set_powergating_state(void *handle,
2363 					  enum amd_powergating_state state)
2364 {
2365 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2366 
2367 	switch (adev->asic_type) {
2368 	case CHIP_RAVEN:
2369 	case CHIP_RENOIR:
2370 		sdma_v4_1_update_power_gating(adev,
2371 				state == AMD_PG_STATE_GATE);
2372 		break;
2373 	default:
2374 		break;
2375 	}
2376 
2377 	return 0;
2378 }
2379 
2380 static void sdma_v4_0_get_clockgating_state(void *handle, u32 *flags)
2381 {
2382 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2383 	int data;
2384 
2385 	if (amdgpu_sriov_vf(adev))
2386 		*flags = 0;
2387 
2388 	/* AMD_CG_SUPPORT_SDMA_MGCG */
2389 	data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
2390 	if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
2391 		*flags |= AMD_CG_SUPPORT_SDMA_MGCG;
2392 
2393 	/* AMD_CG_SUPPORT_SDMA_LS */
2394 	data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
2395 	if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
2396 		*flags |= AMD_CG_SUPPORT_SDMA_LS;
2397 }
2398 
2399 const struct amd_ip_funcs sdma_v4_0_ip_funcs = {
2400 	.name = "sdma_v4_0",
2401 	.early_init = sdma_v4_0_early_init,
2402 	.late_init = sdma_v4_0_late_init,
2403 	.sw_init = sdma_v4_0_sw_init,
2404 	.sw_fini = sdma_v4_0_sw_fini,
2405 	.hw_init = sdma_v4_0_hw_init,
2406 	.hw_fini = sdma_v4_0_hw_fini,
2407 	.suspend = sdma_v4_0_suspend,
2408 	.resume = sdma_v4_0_resume,
2409 	.is_idle = sdma_v4_0_is_idle,
2410 	.wait_for_idle = sdma_v4_0_wait_for_idle,
2411 	.soft_reset = sdma_v4_0_soft_reset,
2412 	.set_clockgating_state = sdma_v4_0_set_clockgating_state,
2413 	.set_powergating_state = sdma_v4_0_set_powergating_state,
2414 	.get_clockgating_state = sdma_v4_0_get_clockgating_state,
2415 };
2416 
2417 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {
2418 	.type = AMDGPU_RING_TYPE_SDMA,
2419 	.align_mask = 0xf,
2420 	.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2421 	.support_64bit_ptrs = true,
2422 	.vmhub = AMDGPU_MMHUB_0,
2423 	.get_rptr = sdma_v4_0_ring_get_rptr,
2424 	.get_wptr = sdma_v4_0_ring_get_wptr,
2425 	.set_wptr = sdma_v4_0_ring_set_wptr,
2426 	.emit_frame_size =
2427 		6 + /* sdma_v4_0_ring_emit_hdp_flush */
2428 		3 + /* hdp invalidate */
2429 		6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2430 		/* sdma_v4_0_ring_emit_vm_flush */
2431 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2432 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2433 		10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2434 	.emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2435 	.emit_ib = sdma_v4_0_ring_emit_ib,
2436 	.emit_fence = sdma_v4_0_ring_emit_fence,
2437 	.emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2438 	.emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2439 	.emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2440 	.test_ring = sdma_v4_0_ring_test_ring,
2441 	.test_ib = sdma_v4_0_ring_test_ib,
2442 	.insert_nop = sdma_v4_0_ring_insert_nop,
2443 	.pad_ib = sdma_v4_0_ring_pad_ib,
2444 	.emit_wreg = sdma_v4_0_ring_emit_wreg,
2445 	.emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2446 	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2447 };
2448 
2449 /*
2450  * On Arcturus, SDMA instance 5~7 has a different vmhub type(AMDGPU_MMHUB_1).
2451  * So create a individual constant ring_funcs for those instances.
2452  */
2453 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs_2nd_mmhub = {
2454 	.type = AMDGPU_RING_TYPE_SDMA,
2455 	.align_mask = 0xf,
2456 	.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2457 	.support_64bit_ptrs = true,
2458 	.vmhub = AMDGPU_MMHUB_1,
2459 	.get_rptr = sdma_v4_0_ring_get_rptr,
2460 	.get_wptr = sdma_v4_0_ring_get_wptr,
2461 	.set_wptr = sdma_v4_0_ring_set_wptr,
2462 	.emit_frame_size =
2463 		6 + /* sdma_v4_0_ring_emit_hdp_flush */
2464 		3 + /* hdp invalidate */
2465 		6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2466 		/* sdma_v4_0_ring_emit_vm_flush */
2467 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2468 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2469 		10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2470 	.emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2471 	.emit_ib = sdma_v4_0_ring_emit_ib,
2472 	.emit_fence = sdma_v4_0_ring_emit_fence,
2473 	.emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2474 	.emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2475 	.emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2476 	.test_ring = sdma_v4_0_ring_test_ring,
2477 	.test_ib = sdma_v4_0_ring_test_ib,
2478 	.insert_nop = sdma_v4_0_ring_insert_nop,
2479 	.pad_ib = sdma_v4_0_ring_pad_ib,
2480 	.emit_wreg = sdma_v4_0_ring_emit_wreg,
2481 	.emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2482 	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2483 };
2484 
2485 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = {
2486 	.type = AMDGPU_RING_TYPE_SDMA,
2487 	.align_mask = 0xf,
2488 	.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2489 	.support_64bit_ptrs = true,
2490 	.vmhub = AMDGPU_MMHUB_0,
2491 	.get_rptr = sdma_v4_0_ring_get_rptr,
2492 	.get_wptr = sdma_v4_0_page_ring_get_wptr,
2493 	.set_wptr = sdma_v4_0_page_ring_set_wptr,
2494 	.emit_frame_size =
2495 		6 + /* sdma_v4_0_ring_emit_hdp_flush */
2496 		3 + /* hdp invalidate */
2497 		6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2498 		/* sdma_v4_0_ring_emit_vm_flush */
2499 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2500 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2501 		10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2502 	.emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2503 	.emit_ib = sdma_v4_0_ring_emit_ib,
2504 	.emit_fence = sdma_v4_0_ring_emit_fence,
2505 	.emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2506 	.emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2507 	.emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2508 	.test_ring = sdma_v4_0_ring_test_ring,
2509 	.test_ib = sdma_v4_0_ring_test_ib,
2510 	.insert_nop = sdma_v4_0_ring_insert_nop,
2511 	.pad_ib = sdma_v4_0_ring_pad_ib,
2512 	.emit_wreg = sdma_v4_0_ring_emit_wreg,
2513 	.emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2514 	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2515 };
2516 
2517 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs_2nd_mmhub = {
2518 	.type = AMDGPU_RING_TYPE_SDMA,
2519 	.align_mask = 0xf,
2520 	.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2521 	.support_64bit_ptrs = true,
2522 	.vmhub = AMDGPU_MMHUB_1,
2523 	.get_rptr = sdma_v4_0_ring_get_rptr,
2524 	.get_wptr = sdma_v4_0_page_ring_get_wptr,
2525 	.set_wptr = sdma_v4_0_page_ring_set_wptr,
2526 	.emit_frame_size =
2527 		6 + /* sdma_v4_0_ring_emit_hdp_flush */
2528 		3 + /* hdp invalidate */
2529 		6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2530 		/* sdma_v4_0_ring_emit_vm_flush */
2531 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2532 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2533 		10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2534 	.emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2535 	.emit_ib = sdma_v4_0_ring_emit_ib,
2536 	.emit_fence = sdma_v4_0_ring_emit_fence,
2537 	.emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2538 	.emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2539 	.emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2540 	.test_ring = sdma_v4_0_ring_test_ring,
2541 	.test_ib = sdma_v4_0_ring_test_ib,
2542 	.insert_nop = sdma_v4_0_ring_insert_nop,
2543 	.pad_ib = sdma_v4_0_ring_pad_ib,
2544 	.emit_wreg = sdma_v4_0_ring_emit_wreg,
2545 	.emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2546 	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2547 };
2548 
2549 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
2550 {
2551 	int i;
2552 
2553 	for (i = 0; i < adev->sdma.num_instances; i++) {
2554 		if (adev->asic_type == CHIP_ARCTURUS && i >= 5)
2555 			adev->sdma.instance[i].ring.funcs =
2556 					&sdma_v4_0_ring_funcs_2nd_mmhub;
2557 		else
2558 			adev->sdma.instance[i].ring.funcs =
2559 					&sdma_v4_0_ring_funcs;
2560 		adev->sdma.instance[i].ring.me = i;
2561 		if (adev->sdma.has_page_queue) {
2562 			if (adev->asic_type == CHIP_ARCTURUS && i >= 5)
2563 				adev->sdma.instance[i].page.funcs =
2564 					&sdma_v4_0_page_ring_funcs_2nd_mmhub;
2565 			else
2566 				adev->sdma.instance[i].page.funcs =
2567 					&sdma_v4_0_page_ring_funcs;
2568 			adev->sdma.instance[i].page.me = i;
2569 		}
2570 	}
2571 }
2572 
2573 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = {
2574 	.set = sdma_v4_0_set_trap_irq_state,
2575 	.process = sdma_v4_0_process_trap_irq,
2576 };
2577 
2578 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = {
2579 	.process = sdma_v4_0_process_illegal_inst_irq,
2580 };
2581 
2582 static const struct amdgpu_irq_src_funcs sdma_v4_0_ecc_irq_funcs = {
2583 	.set = sdma_v4_0_set_ecc_irq_state,
2584 	.process = amdgpu_sdma_process_ecc_irq,
2585 };
2586 
2587 static const struct amdgpu_irq_src_funcs sdma_v4_0_vm_hole_irq_funcs = {
2588 	.process = sdma_v4_0_process_vm_hole_irq,
2589 };
2590 
2591 static const struct amdgpu_irq_src_funcs sdma_v4_0_doorbell_invalid_irq_funcs = {
2592 	.process = sdma_v4_0_process_doorbell_invalid_irq,
2593 };
2594 
2595 static const struct amdgpu_irq_src_funcs sdma_v4_0_pool_timeout_irq_funcs = {
2596 	.process = sdma_v4_0_process_pool_timeout_irq,
2597 };
2598 
2599 static const struct amdgpu_irq_src_funcs sdma_v4_0_srbm_write_irq_funcs = {
2600 	.process = sdma_v4_0_process_srbm_write_irq,
2601 };
2602 
2603 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev)
2604 {
2605 	adev->sdma.trap_irq.num_types = adev->sdma.num_instances;
2606 	adev->sdma.ecc_irq.num_types = adev->sdma.num_instances;
2607 	/*For Arcturus and Aldebaran, add another 4 irq handler*/
2608 	switch (adev->sdma.num_instances) {
2609 	case 5:
2610 	case 8:
2611 		adev->sdma.vm_hole_irq.num_types = adev->sdma.num_instances;
2612 		adev->sdma.doorbell_invalid_irq.num_types = adev->sdma.num_instances;
2613 		adev->sdma.pool_timeout_irq.num_types = adev->sdma.num_instances;
2614 		adev->sdma.srbm_write_irq.num_types = adev->sdma.num_instances;
2615 		break;
2616 	default:
2617 		break;
2618 	}
2619 	adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs;
2620 	adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs;
2621 	adev->sdma.ecc_irq.funcs = &sdma_v4_0_ecc_irq_funcs;
2622 	adev->sdma.vm_hole_irq.funcs = &sdma_v4_0_vm_hole_irq_funcs;
2623 	adev->sdma.doorbell_invalid_irq.funcs = &sdma_v4_0_doorbell_invalid_irq_funcs;
2624 	adev->sdma.pool_timeout_irq.funcs = &sdma_v4_0_pool_timeout_irq_funcs;
2625 	adev->sdma.srbm_write_irq.funcs = &sdma_v4_0_srbm_write_irq_funcs;
2626 }
2627 
2628 /**
2629  * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine
2630  *
2631  * @ib: indirect buffer to copy to
2632  * @src_offset: src GPU address
2633  * @dst_offset: dst GPU address
2634  * @byte_count: number of bytes to xfer
2635  * @tmz: if a secure copy should be used
2636  *
2637  * Copy GPU buffers using the DMA engine (VEGA10/12).
2638  * Used by the amdgpu ttm implementation to move pages if
2639  * registered as the asic copy callback.
2640  */
2641 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib,
2642 				       uint64_t src_offset,
2643 				       uint64_t dst_offset,
2644 				       uint32_t byte_count,
2645 				       bool tmz)
2646 {
2647 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
2648 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
2649 		SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
2650 	ib->ptr[ib->length_dw++] = byte_count - 1;
2651 	ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
2652 	ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
2653 	ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
2654 	ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
2655 	ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2656 }
2657 
2658 /**
2659  * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine
2660  *
2661  * @ib: indirect buffer to copy to
2662  * @src_data: value to write to buffer
2663  * @dst_offset: dst GPU address
2664  * @byte_count: number of bytes to xfer
2665  *
2666  * Fill GPU buffers using the DMA engine (VEGA10/12).
2667  */
2668 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib,
2669 				       uint32_t src_data,
2670 				       uint64_t dst_offset,
2671 				       uint32_t byte_count)
2672 {
2673 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
2674 	ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
2675 	ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2676 	ib->ptr[ib->length_dw++] = src_data;
2677 	ib->ptr[ib->length_dw++] = byte_count - 1;
2678 }
2679 
2680 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = {
2681 	.copy_max_bytes = 0x400000,
2682 	.copy_num_dw = 7,
2683 	.emit_copy_buffer = sdma_v4_0_emit_copy_buffer,
2684 
2685 	.fill_max_bytes = 0x400000,
2686 	.fill_num_dw = 5,
2687 	.emit_fill_buffer = sdma_v4_0_emit_fill_buffer,
2688 };
2689 
2690 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev)
2691 {
2692 	adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs;
2693 	if (adev->sdma.has_page_queue)
2694 		adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page;
2695 	else
2696 		adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
2697 }
2698 
2699 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = {
2700 	.copy_pte_num_dw = 7,
2701 	.copy_pte = sdma_v4_0_vm_copy_pte,
2702 
2703 	.write_pte = sdma_v4_0_vm_write_pte,
2704 	.set_pte_pde = sdma_v4_0_vm_set_pte_pde,
2705 };
2706 
2707 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev)
2708 {
2709 	struct drm_gpu_scheduler *sched;
2710 	unsigned i;
2711 
2712 	adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs;
2713 	for (i = 0; i < adev->sdma.num_instances; i++) {
2714 		if (adev->sdma.has_page_queue)
2715 			sched = &adev->sdma.instance[i].page.sched;
2716 		else
2717 			sched = &adev->sdma.instance[i].ring.sched;
2718 		adev->vm_manager.vm_pte_scheds[i] = sched;
2719 	}
2720 	adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
2721 }
2722 
2723 static void sdma_v4_0_get_ras_error_count(uint32_t value,
2724 					uint32_t instance,
2725 					uint32_t *sec_count)
2726 {
2727 	uint32_t i;
2728 	uint32_t sec_cnt;
2729 
2730 	/* double bits error (multiple bits) error detection is not supported */
2731 	for (i = 0; i < ARRAY_SIZE(sdma_v4_0_ras_fields); i++) {
2732 		/* the SDMA_EDC_COUNTER register in each sdma instance
2733 		 * shares the same sed shift_mask
2734 		 * */
2735 		sec_cnt = (value &
2736 			sdma_v4_0_ras_fields[i].sec_count_mask) >>
2737 			sdma_v4_0_ras_fields[i].sec_count_shift;
2738 		if (sec_cnt) {
2739 			DRM_INFO("Detected %s in SDMA%d, SED %d\n",
2740 				sdma_v4_0_ras_fields[i].name,
2741 				instance, sec_cnt);
2742 			*sec_count += sec_cnt;
2743 		}
2744 	}
2745 }
2746 
2747 static int sdma_v4_0_query_ras_error_count(struct amdgpu_device *adev,
2748 			uint32_t instance, void *ras_error_status)
2749 {
2750 	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
2751 	uint32_t sec_count = 0;
2752 	uint32_t reg_value = 0;
2753 
2754 	reg_value = RREG32_SDMA(instance, mmSDMA0_EDC_COUNTER);
2755 	/* double bit error is not supported */
2756 	if (reg_value)
2757 		sdma_v4_0_get_ras_error_count(reg_value,
2758 				instance, &sec_count);
2759 	/* err_data->ce_count should be initialized to 0
2760 	 * before calling into this function */
2761 	err_data->ce_count += sec_count;
2762 	/* double bit error is not supported
2763 	 * set ue count to 0 */
2764 	err_data->ue_count = 0;
2765 
2766 	return 0;
2767 };
2768 
2769 static void sdma_v4_0_reset_ras_error_count(struct amdgpu_device *adev)
2770 {
2771 	int i;
2772 
2773 	/* read back edc counter registers to clear the counters */
2774 	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
2775 		for (i = 0; i < adev->sdma.num_instances; i++)
2776 			RREG32_SDMA(i, mmSDMA0_EDC_COUNTER);
2777 	}
2778 }
2779 
2780 static const struct amdgpu_sdma_ras_funcs sdma_v4_0_ras_funcs = {
2781 	.ras_late_init = amdgpu_sdma_ras_late_init,
2782 	.ras_fini = amdgpu_sdma_ras_fini,
2783 	.query_ras_error_count = sdma_v4_0_query_ras_error_count,
2784 	.reset_ras_error_count = sdma_v4_0_reset_ras_error_count,
2785 };
2786 
2787 static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev)
2788 {
2789 	switch (adev->asic_type) {
2790 	case CHIP_VEGA20:
2791 	case CHIP_ARCTURUS:
2792 		adev->sdma.funcs = &sdma_v4_0_ras_funcs;
2793 		break;
2794 	case CHIP_ALDEBARAN:
2795 		adev->sdma.funcs = &sdma_v4_4_ras_funcs;
2796 		break;
2797 	default:
2798 		break;
2799 	}
2800 }
2801 
2802 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = {
2803 	.type = AMD_IP_BLOCK_TYPE_SDMA,
2804 	.major = 4,
2805 	.minor = 0,
2806 	.rev = 0,
2807 	.funcs = &sdma_v4_0_ip_funcs,
2808 };
2809