1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "sdma0/sdma0_4_2_offset.h" 34 #include "sdma0/sdma0_4_2_sh_mask.h" 35 #include "sdma1/sdma1_4_2_offset.h" 36 #include "sdma1/sdma1_4_2_sh_mask.h" 37 #include "sdma2/sdma2_4_2_2_offset.h" 38 #include "sdma2/sdma2_4_2_2_sh_mask.h" 39 #include "sdma3/sdma3_4_2_2_offset.h" 40 #include "sdma3/sdma3_4_2_2_sh_mask.h" 41 #include "sdma4/sdma4_4_2_2_offset.h" 42 #include "sdma4/sdma4_4_2_2_sh_mask.h" 43 #include "sdma5/sdma5_4_2_2_offset.h" 44 #include "sdma5/sdma5_4_2_2_sh_mask.h" 45 #include "sdma6/sdma6_4_2_2_offset.h" 46 #include "sdma6/sdma6_4_2_2_sh_mask.h" 47 #include "sdma7/sdma7_4_2_2_offset.h" 48 #include "sdma7/sdma7_4_2_2_sh_mask.h" 49 #include "sdma0/sdma0_4_1_default.h" 50 51 #include "soc15_common.h" 52 #include "soc15.h" 53 #include "vega10_sdma_pkt_open.h" 54 55 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h" 56 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h" 57 58 #include "amdgpu_ras.h" 59 #include "sdma_v4_4.h" 60 61 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin"); 62 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin"); 63 MODULE_FIRMWARE("amdgpu/vega12_sdma.bin"); 64 MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin"); 65 MODULE_FIRMWARE("amdgpu/vega20_sdma.bin"); 66 MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin"); 67 MODULE_FIRMWARE("amdgpu/raven_sdma.bin"); 68 MODULE_FIRMWARE("amdgpu/picasso_sdma.bin"); 69 MODULE_FIRMWARE("amdgpu/raven2_sdma.bin"); 70 MODULE_FIRMWARE("amdgpu/arcturus_sdma.bin"); 71 MODULE_FIRMWARE("amdgpu/renoir_sdma.bin"); 72 MODULE_FIRMWARE("amdgpu/green_sardine_sdma.bin"); 73 MODULE_FIRMWARE("amdgpu/aldebaran_sdma.bin"); 74 75 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L 76 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L 77 78 #define WREG32_SDMA(instance, offset, value) \ 79 WREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)), value) 80 #define RREG32_SDMA(instance, offset) \ 81 RREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset))) 82 83 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev); 84 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev); 85 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev); 86 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev); 87 static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev); 88 89 static const struct soc15_reg_golden golden_settings_sdma_4[] = { 90 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 91 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100), 92 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100), 93 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 94 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 95 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 96 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000), 97 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 98 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 99 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 100 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 101 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 102 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000), 103 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), 104 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100), 105 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 106 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 107 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 108 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000), 109 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 110 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 111 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 112 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 113 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0), 114 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xfc000000, 0x00000000) 115 }; 116 117 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = { 118 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 119 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 120 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 121 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 122 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 123 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 124 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 125 }; 126 127 static const struct soc15_reg_golden golden_settings_sdma_vg12[] = { 128 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), 129 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001), 130 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 131 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 132 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), 133 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001), 134 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 135 }; 136 137 static const struct soc15_reg_golden golden_settings_sdma_4_1[] = { 138 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 139 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 140 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100), 141 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 142 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051), 143 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100), 144 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 145 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100), 146 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 147 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003e0), 148 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000) 149 }; 150 151 static const struct soc15_reg_golden golden_settings_sdma0_4_2_init[] = { 152 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 153 }; 154 155 static const struct soc15_reg_golden golden_settings_sdma0_4_2[] = 156 { 157 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 158 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 159 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 160 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 161 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 162 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 163 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 164 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 165 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RD_BURST_CNTL, 0x0000000f, 0x00000003), 166 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 167 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 168 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 169 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 170 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 171 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 172 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 173 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 174 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 175 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 176 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 177 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 178 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 179 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 180 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 181 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 182 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 183 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 184 }; 185 186 static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = { 187 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 188 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), 189 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 190 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 191 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 192 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 193 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 194 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 195 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RD_BURST_CNTL, 0x0000000f, 0x00000003), 196 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 197 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 198 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 199 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 200 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 201 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 202 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 203 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 204 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 205 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 206 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 207 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 208 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 209 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 210 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 211 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 212 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0), 213 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 214 }; 215 216 static const struct soc15_reg_golden golden_settings_sdma_rv1[] = 217 { 218 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002), 219 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002) 220 }; 221 222 static const struct soc15_reg_golden golden_settings_sdma_rv2[] = 223 { 224 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00003001), 225 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003001) 226 }; 227 228 static const struct soc15_reg_golden golden_settings_sdma_arct[] = 229 { 230 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 231 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 232 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 233 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 234 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 235 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 236 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 237 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 238 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 239 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 240 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 241 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 242 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 243 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 244 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 245 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 246 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 247 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 248 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 249 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 250 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 251 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 252 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 253 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 254 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 255 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 256 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 257 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 258 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 259 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 260 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 261 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_UTCL1_TIMEOUT, 0xffffffff, 0x00010001) 262 }; 263 264 static const struct soc15_reg_golden golden_settings_sdma_aldebaran[] = { 265 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 266 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 267 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 268 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 269 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 270 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 271 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 272 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 273 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA2_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 274 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 275 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 276 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 277 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 278 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 279 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 280 }; 281 282 static const struct soc15_reg_golden golden_settings_sdma_4_3[] = { 283 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 284 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 285 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002), 286 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002), 287 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 288 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003fff07, 0x40000051), 289 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 290 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 291 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003e0), 292 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x03fbe1fe) 293 }; 294 295 static const struct soc15_ras_field_entry sdma_v4_0_ras_fields[] = { 296 { "SDMA_UCODE_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 297 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UCODE_BUF_SED), 298 0, 0, 299 }, 300 { "SDMA_RB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 301 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_RB_CMD_BUF_SED), 302 0, 0, 303 }, 304 { "SDMA_IB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 305 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_IB_CMD_BUF_SED), 306 0, 0, 307 }, 308 { "SDMA_UTCL1_RD_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 309 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UTCL1_RD_FIFO_SED), 310 0, 0, 311 }, 312 { "SDMA_UTCL1_RDBST_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 313 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UTCL1_RDBST_FIFO_SED), 314 0, 0, 315 }, 316 { "SDMA_DATA_LUT_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 317 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_DATA_LUT_FIFO_SED), 318 0, 0, 319 }, 320 { "SDMA_MBANK_DATA_BUF0_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 321 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF0_SED), 322 0, 0, 323 }, 324 { "SDMA_MBANK_DATA_BUF1_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 325 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF1_SED), 326 0, 0, 327 }, 328 { "SDMA_MBANK_DATA_BUF2_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 329 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF2_SED), 330 0, 0, 331 }, 332 { "SDMA_MBANK_DATA_BUF3_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 333 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF3_SED), 334 0, 0, 335 }, 336 { "SDMA_MBANK_DATA_BUF4_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 337 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF4_SED), 338 0, 0, 339 }, 340 { "SDMA_MBANK_DATA_BUF5_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 341 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF5_SED), 342 0, 0, 343 }, 344 { "SDMA_MBANK_DATA_BUF6_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 345 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF6_SED), 346 0, 0, 347 }, 348 { "SDMA_MBANK_DATA_BUF7_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 349 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF7_SED), 350 0, 0, 351 }, 352 { "SDMA_MBANK_DATA_BUF8_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 353 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF8_SED), 354 0, 0, 355 }, 356 { "SDMA_MBANK_DATA_BUF9_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 357 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF9_SED), 358 0, 0, 359 }, 360 { "SDMA_MBANK_DATA_BUF10_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 361 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF10_SED), 362 0, 0, 363 }, 364 { "SDMA_MBANK_DATA_BUF11_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 365 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF11_SED), 366 0, 0, 367 }, 368 { "SDMA_MBANK_DATA_BUF12_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 369 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF12_SED), 370 0, 0, 371 }, 372 { "SDMA_MBANK_DATA_BUF13_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 373 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF13_SED), 374 0, 0, 375 }, 376 { "SDMA_MBANK_DATA_BUF14_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 377 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF14_SED), 378 0, 0, 379 }, 380 { "SDMA_MBANK_DATA_BUF15_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 381 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF15_SED), 382 0, 0, 383 }, 384 { "SDMA_SPLIT_DAT_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 385 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_SPLIT_DAT_BUF_SED), 386 0, 0, 387 }, 388 { "SDMA_MC_WR_ADDR_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 389 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MC_WR_ADDR_FIFO_SED), 390 0, 0, 391 }, 392 }; 393 394 static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev, 395 u32 instance, u32 offset) 396 { 397 switch (instance) { 398 case 0: 399 return (adev->reg_offset[SDMA0_HWIP][0][0] + offset); 400 case 1: 401 return (adev->reg_offset[SDMA1_HWIP][0][0] + offset); 402 case 2: 403 return (adev->reg_offset[SDMA2_HWIP][0][1] + offset); 404 case 3: 405 return (adev->reg_offset[SDMA3_HWIP][0][1] + offset); 406 case 4: 407 return (adev->reg_offset[SDMA4_HWIP][0][1] + offset); 408 case 5: 409 return (adev->reg_offset[SDMA5_HWIP][0][1] + offset); 410 case 6: 411 return (adev->reg_offset[SDMA6_HWIP][0][1] + offset); 412 case 7: 413 return (adev->reg_offset[SDMA7_HWIP][0][1] + offset); 414 default: 415 break; 416 } 417 return 0; 418 } 419 420 static unsigned sdma_v4_0_seq_to_irq_id(int seq_num) 421 { 422 switch (seq_num) { 423 case 0: 424 return SOC15_IH_CLIENTID_SDMA0; 425 case 1: 426 return SOC15_IH_CLIENTID_SDMA1; 427 case 2: 428 return SOC15_IH_CLIENTID_SDMA2; 429 case 3: 430 return SOC15_IH_CLIENTID_SDMA3; 431 case 4: 432 return SOC15_IH_CLIENTID_SDMA4; 433 case 5: 434 return SOC15_IH_CLIENTID_SDMA5; 435 case 6: 436 return SOC15_IH_CLIENTID_SDMA6; 437 case 7: 438 return SOC15_IH_CLIENTID_SDMA7; 439 default: 440 break; 441 } 442 return -EINVAL; 443 } 444 445 static int sdma_v4_0_irq_id_to_seq(unsigned client_id) 446 { 447 switch (client_id) { 448 case SOC15_IH_CLIENTID_SDMA0: 449 return 0; 450 case SOC15_IH_CLIENTID_SDMA1: 451 return 1; 452 case SOC15_IH_CLIENTID_SDMA2: 453 return 2; 454 case SOC15_IH_CLIENTID_SDMA3: 455 return 3; 456 case SOC15_IH_CLIENTID_SDMA4: 457 return 4; 458 case SOC15_IH_CLIENTID_SDMA5: 459 return 5; 460 case SOC15_IH_CLIENTID_SDMA6: 461 return 6; 462 case SOC15_IH_CLIENTID_SDMA7: 463 return 7; 464 default: 465 break; 466 } 467 return -EINVAL; 468 } 469 470 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) 471 { 472 switch (adev->ip_versions[SDMA0_HWIP][0]) { 473 case IP_VERSION(4, 0, 0): 474 soc15_program_register_sequence(adev, 475 golden_settings_sdma_4, 476 ARRAY_SIZE(golden_settings_sdma_4)); 477 soc15_program_register_sequence(adev, 478 golden_settings_sdma_vg10, 479 ARRAY_SIZE(golden_settings_sdma_vg10)); 480 break; 481 case IP_VERSION(4, 0, 1): 482 soc15_program_register_sequence(adev, 483 golden_settings_sdma_4, 484 ARRAY_SIZE(golden_settings_sdma_4)); 485 soc15_program_register_sequence(adev, 486 golden_settings_sdma_vg12, 487 ARRAY_SIZE(golden_settings_sdma_vg12)); 488 break; 489 case IP_VERSION(4, 2, 0): 490 soc15_program_register_sequence(adev, 491 golden_settings_sdma0_4_2_init, 492 ARRAY_SIZE(golden_settings_sdma0_4_2_init)); 493 soc15_program_register_sequence(adev, 494 golden_settings_sdma0_4_2, 495 ARRAY_SIZE(golden_settings_sdma0_4_2)); 496 soc15_program_register_sequence(adev, 497 golden_settings_sdma1_4_2, 498 ARRAY_SIZE(golden_settings_sdma1_4_2)); 499 break; 500 case IP_VERSION(4, 2, 2): 501 soc15_program_register_sequence(adev, 502 golden_settings_sdma_arct, 503 ARRAY_SIZE(golden_settings_sdma_arct)); 504 break; 505 case IP_VERSION(4, 4, 0): 506 soc15_program_register_sequence(adev, 507 golden_settings_sdma_aldebaran, 508 ARRAY_SIZE(golden_settings_sdma_aldebaran)); 509 break; 510 case IP_VERSION(4, 1, 0): 511 case IP_VERSION(4, 1, 1): 512 soc15_program_register_sequence(adev, 513 golden_settings_sdma_4_1, 514 ARRAY_SIZE(golden_settings_sdma_4_1)); 515 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 516 soc15_program_register_sequence(adev, 517 golden_settings_sdma_rv2, 518 ARRAY_SIZE(golden_settings_sdma_rv2)); 519 else 520 soc15_program_register_sequence(adev, 521 golden_settings_sdma_rv1, 522 ARRAY_SIZE(golden_settings_sdma_rv1)); 523 break; 524 case IP_VERSION(4, 1, 2): 525 soc15_program_register_sequence(adev, 526 golden_settings_sdma_4_3, 527 ARRAY_SIZE(golden_settings_sdma_4_3)); 528 break; 529 default: 530 break; 531 } 532 } 533 534 static void sdma_v4_0_setup_ulv(struct amdgpu_device *adev) 535 { 536 int i; 537 538 /* 539 * The only chips with SDMAv4 and ULV are VG10 and VG20. 540 * Server SKUs take a different hysteresis setting from other SKUs. 541 */ 542 switch (adev->ip_versions[SDMA0_HWIP][0]) { 543 case IP_VERSION(4, 0, 0): 544 if (adev->pdev->device == 0x6860) 545 break; 546 return; 547 case IP_VERSION(4, 2, 0): 548 if (adev->pdev->device == 0x66a1) 549 break; 550 return; 551 default: 552 return; 553 } 554 555 for (i = 0; i < adev->sdma.num_instances; i++) { 556 uint32_t temp; 557 558 temp = RREG32_SDMA(i, mmSDMA0_ULV_CNTL); 559 temp = REG_SET_FIELD(temp, SDMA0_ULV_CNTL, HYSTERESIS, 0x0); 560 WREG32_SDMA(i, mmSDMA0_ULV_CNTL, temp); 561 } 562 } 563 564 /** 565 * sdma_v4_0_init_microcode - load ucode images from disk 566 * 567 * @adev: amdgpu_device pointer 568 * 569 * Use the firmware interface to load the ucode images into 570 * the driver (not loaded into hw). 571 * Returns 0 on success, error on failure. 572 */ 573 574 // emulation only, won't work on real chip 575 // vega10 real chip need to use PSP to load firmware 576 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev) 577 { 578 int ret, i; 579 580 for (i = 0; i < adev->sdma.num_instances; i++) { 581 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) || 582 adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 0)) { 583 /* Acturus & Aldebaran will leverage the same FW memory 584 for every SDMA instance */ 585 ret = amdgpu_sdma_init_microcode(adev, 0, true); 586 break; 587 } else { 588 ret = amdgpu_sdma_init_microcode(adev, i, false); 589 if (ret) 590 return ret; 591 } 592 } 593 594 return ret; 595 } 596 597 /** 598 * sdma_v4_0_ring_get_rptr - get the current read pointer 599 * 600 * @ring: amdgpu ring pointer 601 * 602 * Get the current rptr from the hardware (VEGA10+). 603 */ 604 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring) 605 { 606 u64 *rptr; 607 608 /* XXX check if swapping is necessary on BE */ 609 rptr = ((u64 *)ring->rptr_cpu_addr); 610 611 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 612 return ((*rptr) >> 2); 613 } 614 615 /** 616 * sdma_v4_0_ring_get_wptr - get the current write pointer 617 * 618 * @ring: amdgpu ring pointer 619 * 620 * Get the current wptr from the hardware (VEGA10+). 621 */ 622 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring) 623 { 624 struct amdgpu_device *adev = ring->adev; 625 u64 wptr; 626 627 if (ring->use_doorbell) { 628 /* XXX check if swapping is necessary on BE */ 629 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); 630 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 631 } else { 632 wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI); 633 wptr = wptr << 32; 634 wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR); 635 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", 636 ring->me, wptr); 637 } 638 639 return wptr >> 2; 640 } 641 642 /** 643 * sdma_v4_0_ring_set_wptr - commit the write pointer 644 * 645 * @ring: amdgpu ring pointer 646 * 647 * Write the wptr back to the hardware (VEGA10+). 648 */ 649 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring) 650 { 651 struct amdgpu_device *adev = ring->adev; 652 653 DRM_DEBUG("Setting write pointer\n"); 654 if (ring->use_doorbell) { 655 u64 *wb = (u64 *)ring->wptr_cpu_addr; 656 657 DRM_DEBUG("Using doorbell -- " 658 "wptr_offs == 0x%08x " 659 "lower_32_bits(ring->wptr << 2) == 0x%08x " 660 "upper_32_bits(ring->wptr << 2) == 0x%08x\n", 661 ring->wptr_offs, 662 lower_32_bits(ring->wptr << 2), 663 upper_32_bits(ring->wptr << 2)); 664 /* XXX check if swapping is necessary on BE */ 665 WRITE_ONCE(*wb, (ring->wptr << 2)); 666 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 667 ring->doorbell_index, ring->wptr << 2); 668 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 669 } else { 670 DRM_DEBUG("Not using doorbell -- " 671 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 672 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 673 ring->me, 674 lower_32_bits(ring->wptr << 2), 675 ring->me, 676 upper_32_bits(ring->wptr << 2)); 677 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR, 678 lower_32_bits(ring->wptr << 2)); 679 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI, 680 upper_32_bits(ring->wptr << 2)); 681 } 682 } 683 684 /** 685 * sdma_v4_0_page_ring_get_wptr - get the current write pointer 686 * 687 * @ring: amdgpu ring pointer 688 * 689 * Get the current wptr from the hardware (VEGA10+). 690 */ 691 static uint64_t sdma_v4_0_page_ring_get_wptr(struct amdgpu_ring *ring) 692 { 693 struct amdgpu_device *adev = ring->adev; 694 u64 wptr; 695 696 if (ring->use_doorbell) { 697 /* XXX check if swapping is necessary on BE */ 698 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); 699 } else { 700 wptr = RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI); 701 wptr = wptr << 32; 702 wptr |= RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR); 703 } 704 705 return wptr >> 2; 706 } 707 708 /** 709 * sdma_v4_0_page_ring_set_wptr - commit the write pointer 710 * 711 * @ring: amdgpu ring pointer 712 * 713 * Write the wptr back to the hardware (VEGA10+). 714 */ 715 static void sdma_v4_0_page_ring_set_wptr(struct amdgpu_ring *ring) 716 { 717 struct amdgpu_device *adev = ring->adev; 718 719 if (ring->use_doorbell) { 720 u64 *wb = (u64 *)ring->wptr_cpu_addr; 721 722 /* XXX check if swapping is necessary on BE */ 723 WRITE_ONCE(*wb, (ring->wptr << 2)); 724 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 725 } else { 726 uint64_t wptr = ring->wptr << 2; 727 728 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR, 729 lower_32_bits(wptr)); 730 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI, 731 upper_32_bits(wptr)); 732 } 733 } 734 735 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 736 { 737 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 738 int i; 739 740 for (i = 0; i < count; i++) 741 if (sdma && sdma->burst_nop && (i == 0)) 742 amdgpu_ring_write(ring, ring->funcs->nop | 743 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 744 else 745 amdgpu_ring_write(ring, ring->funcs->nop); 746 } 747 748 /** 749 * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine 750 * 751 * @ring: amdgpu ring pointer 752 * @job: job to retrieve vmid from 753 * @ib: IB object to schedule 754 * @flags: unused 755 * 756 * Schedule an IB in the DMA ring (VEGA10). 757 */ 758 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring, 759 struct amdgpu_job *job, 760 struct amdgpu_ib *ib, 761 uint32_t flags) 762 { 763 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 764 765 /* IB packet must end on a 8 DW boundary */ 766 sdma_v4_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 767 768 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 769 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 770 /* base must be 32 byte aligned */ 771 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 772 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 773 amdgpu_ring_write(ring, ib->length_dw); 774 amdgpu_ring_write(ring, 0); 775 amdgpu_ring_write(ring, 0); 776 777 } 778 779 static void sdma_v4_0_wait_reg_mem(struct amdgpu_ring *ring, 780 int mem_space, int hdp, 781 uint32_t addr0, uint32_t addr1, 782 uint32_t ref, uint32_t mask, 783 uint32_t inv) 784 { 785 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 786 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) | 787 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) | 788 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 789 if (mem_space) { 790 /* memory */ 791 amdgpu_ring_write(ring, addr0); 792 amdgpu_ring_write(ring, addr1); 793 } else { 794 /* registers */ 795 amdgpu_ring_write(ring, addr0 << 2); 796 amdgpu_ring_write(ring, addr1 << 2); 797 } 798 amdgpu_ring_write(ring, ref); /* reference */ 799 amdgpu_ring_write(ring, mask); /* mask */ 800 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 801 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */ 802 } 803 804 /** 805 * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 806 * 807 * @ring: amdgpu ring pointer 808 * 809 * Emit an hdp flush packet on the requested DMA ring. 810 */ 811 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 812 { 813 struct amdgpu_device *adev = ring->adev; 814 u32 ref_and_mask = 0; 815 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 816 817 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; 818 819 sdma_v4_0_wait_reg_mem(ring, 0, 1, 820 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 821 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 822 ref_and_mask, ref_and_mask, 10); 823 } 824 825 /** 826 * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring 827 * 828 * @ring: amdgpu ring pointer 829 * @addr: address 830 * @seq: sequence number 831 * @flags: fence related flags 832 * 833 * Add a DMA fence packet to the ring to write 834 * the fence seq number and DMA trap packet to generate 835 * an interrupt if needed (VEGA10). 836 */ 837 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 838 unsigned flags) 839 { 840 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 841 /* write the fence */ 842 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 843 /* zero in first two bits */ 844 BUG_ON(addr & 0x3); 845 amdgpu_ring_write(ring, lower_32_bits(addr)); 846 amdgpu_ring_write(ring, upper_32_bits(addr)); 847 amdgpu_ring_write(ring, lower_32_bits(seq)); 848 849 /* optionally write high bits as well */ 850 if (write64bit) { 851 addr += 4; 852 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 853 /* zero in first two bits */ 854 BUG_ON(addr & 0x3); 855 amdgpu_ring_write(ring, lower_32_bits(addr)); 856 amdgpu_ring_write(ring, upper_32_bits(addr)); 857 amdgpu_ring_write(ring, upper_32_bits(seq)); 858 } 859 860 /* generate an interrupt */ 861 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 862 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 863 } 864 865 866 /** 867 * sdma_v4_0_gfx_enable - enable the gfx async dma engines 868 * 869 * @adev: amdgpu_device pointer 870 * @enable: enable SDMA RB/IB 871 * control the gfx async dma ring buffers (VEGA10). 872 */ 873 static void sdma_v4_0_gfx_enable(struct amdgpu_device *adev, bool enable) 874 { 875 u32 rb_cntl, ib_cntl; 876 int i; 877 878 amdgpu_sdma_unset_buffer_funcs_helper(adev); 879 880 for (i = 0; i < adev->sdma.num_instances; i++) { 881 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL); 882 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, enable ? 1 : 0); 883 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 884 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL); 885 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, enable ? 1 : 0); 886 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl); 887 } 888 } 889 890 /** 891 * sdma_v4_0_rlc_stop - stop the compute async dma engines 892 * 893 * @adev: amdgpu_device pointer 894 * 895 * Stop the compute async dma queues (VEGA10). 896 */ 897 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev) 898 { 899 /* XXX todo */ 900 } 901 902 /** 903 * sdma_v4_0_page_stop - stop the page async dma engines 904 * 905 * @adev: amdgpu_device pointer 906 * 907 * Stop the page async dma ring buffers (VEGA10). 908 */ 909 static void sdma_v4_0_page_stop(struct amdgpu_device *adev) 910 { 911 u32 rb_cntl, ib_cntl; 912 int i; 913 914 amdgpu_sdma_unset_buffer_funcs_helper(adev); 915 916 for (i = 0; i < adev->sdma.num_instances; i++) { 917 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL); 918 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, 919 RB_ENABLE, 0); 920 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 921 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL); 922 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, 923 IB_ENABLE, 0); 924 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl); 925 } 926 } 927 928 /** 929 * sdma_v4_0_ctx_switch_enable - stop the async dma engines context switch 930 * 931 * @adev: amdgpu_device pointer 932 * @enable: enable/disable the DMA MEs context switch. 933 * 934 * Halt or unhalt the async dma engines context switch (VEGA10). 935 */ 936 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 937 { 938 u32 f32_cntl, phase_quantum = 0; 939 int i; 940 941 if (amdgpu_sdma_phase_quantum) { 942 unsigned value = amdgpu_sdma_phase_quantum; 943 unsigned unit = 0; 944 945 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 946 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 947 value = (value + 1) >> 1; 948 unit++; 949 } 950 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 951 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 952 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 953 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 954 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 955 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 956 WARN_ONCE(1, 957 "clamping sdma_phase_quantum to %uK clock cycles\n", 958 value << unit); 959 } 960 phase_quantum = 961 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 962 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 963 } 964 965 for (i = 0; i < adev->sdma.num_instances; i++) { 966 f32_cntl = RREG32_SDMA(i, mmSDMA0_CNTL); 967 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 968 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 969 if (enable && amdgpu_sdma_phase_quantum) { 970 WREG32_SDMA(i, mmSDMA0_PHASE0_QUANTUM, phase_quantum); 971 WREG32_SDMA(i, mmSDMA0_PHASE1_QUANTUM, phase_quantum); 972 WREG32_SDMA(i, mmSDMA0_PHASE2_QUANTUM, phase_quantum); 973 } 974 WREG32_SDMA(i, mmSDMA0_CNTL, f32_cntl); 975 976 /* 977 * Enable SDMA utilization. Its only supported on 978 * Arcturus for the moment and firmware version 14 979 * and above. 980 */ 981 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) && 982 adev->sdma.instance[i].fw_version >= 14) 983 WREG32_SDMA(i, mmSDMA0_PUB_DUMMY_REG2, enable); 984 /* Extend page fault timeout to avoid interrupt storm */ 985 WREG32_SDMA(i, mmSDMA0_UTCL1_TIMEOUT, 0x00800080); 986 } 987 988 } 989 990 /** 991 * sdma_v4_0_enable - stop the async dma engines 992 * 993 * @adev: amdgpu_device pointer 994 * @enable: enable/disable the DMA MEs. 995 * 996 * Halt or unhalt the async dma engines (VEGA10). 997 */ 998 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable) 999 { 1000 u32 f32_cntl; 1001 int i; 1002 1003 if (!enable) { 1004 sdma_v4_0_gfx_enable(adev, enable); 1005 sdma_v4_0_rlc_stop(adev); 1006 if (adev->sdma.has_page_queue) 1007 sdma_v4_0_page_stop(adev); 1008 } 1009 1010 for (i = 0; i < adev->sdma.num_instances; i++) { 1011 f32_cntl = RREG32_SDMA(i, mmSDMA0_F32_CNTL); 1012 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 1013 WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl); 1014 } 1015 } 1016 1017 /* 1018 * sdma_v4_0_rb_cntl - get parameters for rb_cntl 1019 */ 1020 static uint32_t sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl) 1021 { 1022 /* Set ring buffer size in dwords */ 1023 uint32_t rb_bufsz = order_base_2(ring->ring_size / 4); 1024 1025 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 1026 #ifdef __BIG_ENDIAN 1027 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 1028 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 1029 RPTR_WRITEBACK_SWAP_ENABLE, 1); 1030 #endif 1031 return rb_cntl; 1032 } 1033 1034 /** 1035 * sdma_v4_0_gfx_resume - setup and start the async dma engines 1036 * 1037 * @adev: amdgpu_device pointer 1038 * @i: instance to resume 1039 * 1040 * Set up the gfx DMA ring buffers and enable them (VEGA10). 1041 * Returns 0 for success, error for failure. 1042 */ 1043 static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i) 1044 { 1045 struct amdgpu_ring *ring = &adev->sdma.instance[i].ring; 1046 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 1047 u32 doorbell; 1048 u32 doorbell_offset; 1049 u64 wptr_gpu_addr; 1050 1051 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL); 1052 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl); 1053 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 1054 1055 /* Initialize the ring buffer's read and write pointers */ 1056 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR, 0); 1057 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_HI, 0); 1058 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR, 0); 1059 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_HI, 0); 1060 1061 /* set the wb address whether it's enabled or not */ 1062 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI, 1063 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); 1064 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 1065 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); 1066 1067 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 1068 RPTR_WRITEBACK_ENABLE, 1); 1069 1070 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE, ring->gpu_addr >> 8); 1071 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE_HI, ring->gpu_addr >> 40); 1072 1073 ring->wptr = 0; 1074 1075 /* before programing wptr to a less value, need set minor_ptr_update first */ 1076 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 1); 1077 1078 doorbell = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL); 1079 doorbell_offset = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET); 1080 1081 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1082 ring->use_doorbell); 1083 doorbell_offset = REG_SET_FIELD(doorbell_offset, 1084 SDMA0_GFX_DOORBELL_OFFSET, 1085 OFFSET, ring->doorbell_index); 1086 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL, doorbell); 1087 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET, doorbell_offset); 1088 1089 sdma_v4_0_ring_set_wptr(ring); 1090 1091 /* set minor_ptr_update to 0 after wptr programed */ 1092 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 0); 1093 1094 /* setup the wptr shadow polling */ 1095 wptr_gpu_addr = ring->wptr_gpu_addr; 1096 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO, 1097 lower_32_bits(wptr_gpu_addr)); 1098 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI, 1099 upper_32_bits(wptr_gpu_addr)); 1100 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL); 1101 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 1102 SDMA0_GFX_RB_WPTR_POLL_CNTL, 1103 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 1104 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 1105 1106 /* enable DMA RB */ 1107 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 1108 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 1109 1110 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL); 1111 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 1112 #ifdef __BIG_ENDIAN 1113 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 1114 #endif 1115 /* enable DMA IBs */ 1116 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl); 1117 1118 ring->sched.ready = true; 1119 } 1120 1121 /** 1122 * sdma_v4_0_page_resume - setup and start the async dma engines 1123 * 1124 * @adev: amdgpu_device pointer 1125 * @i: instance to resume 1126 * 1127 * Set up the page DMA ring buffers and enable them (VEGA10). 1128 * Returns 0 for success, error for failure. 1129 */ 1130 static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i) 1131 { 1132 struct amdgpu_ring *ring = &adev->sdma.instance[i].page; 1133 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 1134 u32 doorbell; 1135 u32 doorbell_offset; 1136 u64 wptr_gpu_addr; 1137 1138 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL); 1139 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl); 1140 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 1141 1142 /* Initialize the ring buffer's read and write pointers */ 1143 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR, 0); 1144 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_HI, 0); 1145 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR, 0); 1146 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_HI, 0); 1147 1148 /* set the wb address whether it's enabled or not */ 1149 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_HI, 1150 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); 1151 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 1152 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); 1153 1154 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, 1155 RPTR_WRITEBACK_ENABLE, 1); 1156 1157 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE, ring->gpu_addr >> 8); 1158 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE_HI, ring->gpu_addr >> 40); 1159 1160 ring->wptr = 0; 1161 1162 /* before programing wptr to a less value, need set minor_ptr_update first */ 1163 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 1); 1164 1165 doorbell = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL); 1166 doorbell_offset = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET); 1167 1168 doorbell = REG_SET_FIELD(doorbell, SDMA0_PAGE_DOORBELL, ENABLE, 1169 ring->use_doorbell); 1170 doorbell_offset = REG_SET_FIELD(doorbell_offset, 1171 SDMA0_PAGE_DOORBELL_OFFSET, 1172 OFFSET, ring->doorbell_index); 1173 WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL, doorbell); 1174 WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET, doorbell_offset); 1175 1176 /* paging queue doorbell range is setup at sdma_v4_0_gfx_resume */ 1177 sdma_v4_0_page_ring_set_wptr(ring); 1178 1179 /* set minor_ptr_update to 0 after wptr programed */ 1180 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 0); 1181 1182 /* setup the wptr shadow polling */ 1183 wptr_gpu_addr = ring->wptr_gpu_addr; 1184 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO, 1185 lower_32_bits(wptr_gpu_addr)); 1186 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI, 1187 upper_32_bits(wptr_gpu_addr)); 1188 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL); 1189 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 1190 SDMA0_PAGE_RB_WPTR_POLL_CNTL, 1191 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 1192 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 1193 1194 /* enable DMA RB */ 1195 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, RB_ENABLE, 1); 1196 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 1197 1198 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL); 1199 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_ENABLE, 1); 1200 #ifdef __BIG_ENDIAN 1201 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1); 1202 #endif 1203 /* enable DMA IBs */ 1204 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl); 1205 1206 ring->sched.ready = true; 1207 } 1208 1209 static void 1210 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable) 1211 { 1212 uint32_t def, data; 1213 1214 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) { 1215 /* enable idle interrupt */ 1216 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 1217 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 1218 1219 if (data != def) 1220 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 1221 } else { 1222 /* disable idle interrupt */ 1223 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 1224 data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 1225 if (data != def) 1226 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 1227 } 1228 } 1229 1230 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev) 1231 { 1232 uint32_t def, data; 1233 1234 /* Enable HW based PG. */ 1235 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1236 data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK; 1237 if (data != def) 1238 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1239 1240 /* enable interrupt */ 1241 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 1242 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 1243 if (data != def) 1244 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 1245 1246 /* Configure hold time to filter in-valid power on/off request. Use default right now */ 1247 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1248 data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK; 1249 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK); 1250 /* Configure switch time for hysteresis purpose. Use default right now */ 1251 data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK; 1252 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK); 1253 if(data != def) 1254 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1255 } 1256 1257 static void sdma_v4_0_init_pg(struct amdgpu_device *adev) 1258 { 1259 if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA)) 1260 return; 1261 1262 switch (adev->ip_versions[SDMA0_HWIP][0]) { 1263 case IP_VERSION(4, 1, 0): 1264 case IP_VERSION(4, 1, 1): 1265 case IP_VERSION(4, 1, 2): 1266 sdma_v4_1_init_power_gating(adev); 1267 sdma_v4_1_update_power_gating(adev, true); 1268 break; 1269 default: 1270 break; 1271 } 1272 } 1273 1274 /** 1275 * sdma_v4_0_rlc_resume - setup and start the async dma engines 1276 * 1277 * @adev: amdgpu_device pointer 1278 * 1279 * Set up the compute DMA queues and enable them (VEGA10). 1280 * Returns 0 for success, error for failure. 1281 */ 1282 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev) 1283 { 1284 sdma_v4_0_init_pg(adev); 1285 1286 return 0; 1287 } 1288 1289 /** 1290 * sdma_v4_0_load_microcode - load the sDMA ME ucode 1291 * 1292 * @adev: amdgpu_device pointer 1293 * 1294 * Loads the sDMA0/1 ucode. 1295 * Returns 0 for success, -EINVAL if the ucode is not available. 1296 */ 1297 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev) 1298 { 1299 const struct sdma_firmware_header_v1_0 *hdr; 1300 const __le32 *fw_data; 1301 u32 fw_size; 1302 int i, j; 1303 1304 /* halt the MEs */ 1305 sdma_v4_0_enable(adev, false); 1306 1307 for (i = 0; i < adev->sdma.num_instances; i++) { 1308 if (!adev->sdma.instance[i].fw) 1309 return -EINVAL; 1310 1311 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 1312 amdgpu_ucode_print_sdma_hdr(&hdr->header); 1313 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1314 1315 fw_data = (const __le32 *) 1316 (adev->sdma.instance[i].fw->data + 1317 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1318 1319 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 0); 1320 1321 for (j = 0; j < fw_size; j++) 1322 WREG32_SDMA(i, mmSDMA0_UCODE_DATA, 1323 le32_to_cpup(fw_data++)); 1324 1325 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 1326 adev->sdma.instance[i].fw_version); 1327 } 1328 1329 return 0; 1330 } 1331 1332 /** 1333 * sdma_v4_0_start - setup and start the async dma engines 1334 * 1335 * @adev: amdgpu_device pointer 1336 * 1337 * Set up the DMA engines and enable them (VEGA10). 1338 * Returns 0 for success, error for failure. 1339 */ 1340 static int sdma_v4_0_start(struct amdgpu_device *adev) 1341 { 1342 struct amdgpu_ring *ring; 1343 int i, r = 0; 1344 1345 if (amdgpu_sriov_vf(adev)) { 1346 sdma_v4_0_ctx_switch_enable(adev, false); 1347 sdma_v4_0_enable(adev, false); 1348 } else { 1349 1350 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1351 r = sdma_v4_0_load_microcode(adev); 1352 if (r) 1353 return r; 1354 } 1355 1356 /* unhalt the MEs */ 1357 sdma_v4_0_enable(adev, true); 1358 /* enable sdma ring preemption */ 1359 sdma_v4_0_ctx_switch_enable(adev, true); 1360 } 1361 1362 /* start the gfx rings and rlc compute queues */ 1363 for (i = 0; i < adev->sdma.num_instances; i++) { 1364 uint32_t temp; 1365 1366 WREG32_SDMA(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL, 0); 1367 sdma_v4_0_gfx_resume(adev, i); 1368 if (adev->sdma.has_page_queue) 1369 sdma_v4_0_page_resume(adev, i); 1370 1371 /* set utc l1 enable flag always to 1 */ 1372 temp = RREG32_SDMA(i, mmSDMA0_CNTL); 1373 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 1374 WREG32_SDMA(i, mmSDMA0_CNTL, temp); 1375 1376 if (!amdgpu_sriov_vf(adev)) { 1377 /* unhalt engine */ 1378 temp = RREG32_SDMA(i, mmSDMA0_F32_CNTL); 1379 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 1380 WREG32_SDMA(i, mmSDMA0_F32_CNTL, temp); 1381 } 1382 } 1383 1384 if (amdgpu_sriov_vf(adev)) { 1385 sdma_v4_0_ctx_switch_enable(adev, true); 1386 sdma_v4_0_enable(adev, true); 1387 } else { 1388 r = sdma_v4_0_rlc_resume(adev); 1389 if (r) 1390 return r; 1391 } 1392 1393 for (i = 0; i < adev->sdma.num_instances; i++) { 1394 ring = &adev->sdma.instance[i].ring; 1395 1396 r = amdgpu_ring_test_helper(ring); 1397 if (r) 1398 return r; 1399 1400 if (adev->sdma.has_page_queue) { 1401 struct amdgpu_ring *page = &adev->sdma.instance[i].page; 1402 1403 r = amdgpu_ring_test_helper(page); 1404 if (r) 1405 return r; 1406 1407 if (adev->mman.buffer_funcs_ring == page) 1408 amdgpu_ttm_set_buffer_funcs_status(adev, true); 1409 } 1410 1411 if (adev->mman.buffer_funcs_ring == ring) 1412 amdgpu_ttm_set_buffer_funcs_status(adev, true); 1413 } 1414 1415 return r; 1416 } 1417 1418 /** 1419 * sdma_v4_0_ring_test_ring - simple async dma engine test 1420 * 1421 * @ring: amdgpu_ring structure holding ring information 1422 * 1423 * Test the DMA engine by writing using it to write an 1424 * value to memory. (VEGA10). 1425 * Returns 0 for success, error for failure. 1426 */ 1427 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring) 1428 { 1429 struct amdgpu_device *adev = ring->adev; 1430 unsigned i; 1431 unsigned index; 1432 int r; 1433 u32 tmp; 1434 u64 gpu_addr; 1435 1436 r = amdgpu_device_wb_get(adev, &index); 1437 if (r) 1438 return r; 1439 1440 gpu_addr = adev->wb.gpu_addr + (index * 4); 1441 tmp = 0xCAFEDEAD; 1442 adev->wb.wb[index] = cpu_to_le32(tmp); 1443 1444 r = amdgpu_ring_alloc(ring, 5); 1445 if (r) 1446 goto error_free_wb; 1447 1448 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1449 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 1450 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 1451 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 1452 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 1453 amdgpu_ring_write(ring, 0xDEADBEEF); 1454 amdgpu_ring_commit(ring); 1455 1456 for (i = 0; i < adev->usec_timeout; i++) { 1457 tmp = le32_to_cpu(adev->wb.wb[index]); 1458 if (tmp == 0xDEADBEEF) 1459 break; 1460 udelay(1); 1461 } 1462 1463 if (i >= adev->usec_timeout) 1464 r = -ETIMEDOUT; 1465 1466 error_free_wb: 1467 amdgpu_device_wb_free(adev, index); 1468 return r; 1469 } 1470 1471 /** 1472 * sdma_v4_0_ring_test_ib - test an IB on the DMA engine 1473 * 1474 * @ring: amdgpu_ring structure holding ring information 1475 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 1476 * 1477 * Test a simple IB in the DMA ring (VEGA10). 1478 * Returns 0 on success, error on failure. 1479 */ 1480 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1481 { 1482 struct amdgpu_device *adev = ring->adev; 1483 struct amdgpu_ib ib; 1484 struct dma_fence *f = NULL; 1485 unsigned index; 1486 long r; 1487 u32 tmp = 0; 1488 u64 gpu_addr; 1489 1490 r = amdgpu_device_wb_get(adev, &index); 1491 if (r) 1492 return r; 1493 1494 gpu_addr = adev->wb.gpu_addr + (index * 4); 1495 tmp = 0xCAFEDEAD; 1496 adev->wb.wb[index] = cpu_to_le32(tmp); 1497 memset(&ib, 0, sizeof(ib)); 1498 r = amdgpu_ib_get(adev, NULL, 256, 1499 AMDGPU_IB_POOL_DIRECT, &ib); 1500 if (r) 1501 goto err0; 1502 1503 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1504 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1505 ib.ptr[1] = lower_32_bits(gpu_addr); 1506 ib.ptr[2] = upper_32_bits(gpu_addr); 1507 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1508 ib.ptr[4] = 0xDEADBEEF; 1509 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1510 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1511 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1512 ib.length_dw = 8; 1513 1514 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1515 if (r) 1516 goto err1; 1517 1518 r = dma_fence_wait_timeout(f, false, timeout); 1519 if (r == 0) { 1520 r = -ETIMEDOUT; 1521 goto err1; 1522 } else if (r < 0) { 1523 goto err1; 1524 } 1525 tmp = le32_to_cpu(adev->wb.wb[index]); 1526 if (tmp == 0xDEADBEEF) 1527 r = 0; 1528 else 1529 r = -EINVAL; 1530 1531 err1: 1532 amdgpu_ib_free(adev, &ib, NULL); 1533 dma_fence_put(f); 1534 err0: 1535 amdgpu_device_wb_free(adev, index); 1536 return r; 1537 } 1538 1539 1540 /** 1541 * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART 1542 * 1543 * @ib: indirect buffer to fill with commands 1544 * @pe: addr of the page entry 1545 * @src: src addr to copy from 1546 * @count: number of page entries to update 1547 * 1548 * Update PTEs by copying them from the GART using sDMA (VEGA10). 1549 */ 1550 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib, 1551 uint64_t pe, uint64_t src, 1552 unsigned count) 1553 { 1554 unsigned bytes = count * 8; 1555 1556 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1557 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1558 ib->ptr[ib->length_dw++] = bytes - 1; 1559 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1560 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1561 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1562 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1563 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1564 1565 } 1566 1567 /** 1568 * sdma_v4_0_vm_write_pte - update PTEs by writing them manually 1569 * 1570 * @ib: indirect buffer to fill with commands 1571 * @pe: addr of the page entry 1572 * @value: dst addr to write into pe 1573 * @count: number of page entries to update 1574 * @incr: increase next addr by incr bytes 1575 * 1576 * Update PTEs by writing them manually using sDMA (VEGA10). 1577 */ 1578 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1579 uint64_t value, unsigned count, 1580 uint32_t incr) 1581 { 1582 unsigned ndw = count * 2; 1583 1584 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1585 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1586 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1587 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1588 ib->ptr[ib->length_dw++] = ndw - 1; 1589 for (; ndw > 0; ndw -= 2) { 1590 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1591 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1592 value += incr; 1593 } 1594 } 1595 1596 /** 1597 * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA 1598 * 1599 * @ib: indirect buffer to fill with commands 1600 * @pe: addr of the page entry 1601 * @addr: dst addr to write into pe 1602 * @count: number of page entries to update 1603 * @incr: increase next addr by incr bytes 1604 * @flags: access flags 1605 * 1606 * Update the page tables using sDMA (VEGA10). 1607 */ 1608 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1609 uint64_t pe, 1610 uint64_t addr, unsigned count, 1611 uint32_t incr, uint64_t flags) 1612 { 1613 /* for physically contiguous pages (vram) */ 1614 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1615 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1616 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1617 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1618 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1619 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1620 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1621 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1622 ib->ptr[ib->length_dw++] = 0; 1623 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1624 } 1625 1626 /** 1627 * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw 1628 * 1629 * @ring: amdgpu_ring structure holding ring information 1630 * @ib: indirect buffer to fill with padding 1631 */ 1632 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1633 { 1634 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1635 u32 pad_count; 1636 int i; 1637 1638 pad_count = (-ib->length_dw) & 7; 1639 for (i = 0; i < pad_count; i++) 1640 if (sdma && sdma->burst_nop && (i == 0)) 1641 ib->ptr[ib->length_dw++] = 1642 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1643 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1644 else 1645 ib->ptr[ib->length_dw++] = 1646 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1647 } 1648 1649 1650 /** 1651 * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline 1652 * 1653 * @ring: amdgpu_ring pointer 1654 * 1655 * Make sure all previous operations are completed (CIK). 1656 */ 1657 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1658 { 1659 uint32_t seq = ring->fence_drv.sync_seq; 1660 uint64_t addr = ring->fence_drv.gpu_addr; 1661 1662 /* wait for idle */ 1663 sdma_v4_0_wait_reg_mem(ring, 1, 0, 1664 addr & 0xfffffffc, 1665 upper_32_bits(addr) & 0xffffffff, 1666 seq, 0xffffffff, 4); 1667 } 1668 1669 1670 /** 1671 * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA 1672 * 1673 * @ring: amdgpu_ring pointer 1674 * @vmid: vmid number to use 1675 * @pd_addr: address 1676 * 1677 * Update the page table base and flush the VM TLB 1678 * using sDMA (VEGA10). 1679 */ 1680 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1681 unsigned vmid, uint64_t pd_addr) 1682 { 1683 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1684 } 1685 1686 static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring, 1687 uint32_t reg, uint32_t val) 1688 { 1689 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1690 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1691 amdgpu_ring_write(ring, reg); 1692 amdgpu_ring_write(ring, val); 1693 } 1694 1695 static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1696 uint32_t val, uint32_t mask) 1697 { 1698 sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10); 1699 } 1700 1701 static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev) 1702 { 1703 uint fw_version = adev->sdma.instance[0].fw_version; 1704 1705 switch (adev->ip_versions[SDMA0_HWIP][0]) { 1706 case IP_VERSION(4, 0, 0): 1707 return fw_version >= 430; 1708 case IP_VERSION(4, 0, 1): 1709 /*return fw_version >= 31;*/ 1710 return false; 1711 case IP_VERSION(4, 2, 0): 1712 return fw_version >= 123; 1713 default: 1714 return false; 1715 } 1716 } 1717 1718 static int sdma_v4_0_early_init(void *handle) 1719 { 1720 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1721 int r; 1722 1723 r = sdma_v4_0_init_microcode(adev); 1724 if (r) { 1725 DRM_ERROR("Failed to load sdma firmware!\n"); 1726 return r; 1727 } 1728 1729 /* TODO: Page queue breaks driver reload under SRIOV */ 1730 if ((adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 0, 0)) && 1731 amdgpu_sriov_vf((adev))) 1732 adev->sdma.has_page_queue = false; 1733 else if (sdma_v4_0_fw_support_paging_queue(adev)) 1734 adev->sdma.has_page_queue = true; 1735 1736 sdma_v4_0_set_ring_funcs(adev); 1737 sdma_v4_0_set_buffer_funcs(adev); 1738 sdma_v4_0_set_vm_pte_funcs(adev); 1739 sdma_v4_0_set_irq_funcs(adev); 1740 sdma_v4_0_set_ras_funcs(adev); 1741 1742 return 0; 1743 } 1744 1745 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev, 1746 void *err_data, 1747 struct amdgpu_iv_entry *entry); 1748 1749 static int sdma_v4_0_late_init(void *handle) 1750 { 1751 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1752 1753 sdma_v4_0_setup_ulv(adev); 1754 1755 if (!amdgpu_persistent_edc_harvesting_supported(adev)) { 1756 if (adev->sdma.ras && adev->sdma.ras->ras_block.hw_ops && 1757 adev->sdma.ras->ras_block.hw_ops->reset_ras_error_count) 1758 adev->sdma.ras->ras_block.hw_ops->reset_ras_error_count(adev); 1759 } 1760 1761 return 0; 1762 } 1763 1764 static int sdma_v4_0_sw_init(void *handle) 1765 { 1766 struct amdgpu_ring *ring; 1767 int r, i; 1768 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1769 1770 /* SDMA trap event */ 1771 for (i = 0; i < adev->sdma.num_instances; i++) { 1772 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1773 SDMA0_4_0__SRCID__SDMA_TRAP, 1774 &adev->sdma.trap_irq); 1775 if (r) 1776 return r; 1777 } 1778 1779 /* SDMA SRAM ECC event */ 1780 for (i = 0; i < adev->sdma.num_instances; i++) { 1781 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1782 SDMA0_4_0__SRCID__SDMA_SRAM_ECC, 1783 &adev->sdma.ecc_irq); 1784 if (r) 1785 return r; 1786 } 1787 1788 /* SDMA VM_HOLE/DOORBELL_INV/POLL_TIMEOUT/SRBM_WRITE_PROTECTION event*/ 1789 for (i = 0; i < adev->sdma.num_instances; i++) { 1790 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1791 SDMA0_4_0__SRCID__SDMA_VM_HOLE, 1792 &adev->sdma.vm_hole_irq); 1793 if (r) 1794 return r; 1795 1796 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1797 SDMA0_4_0__SRCID__SDMA_DOORBELL_INVALID, 1798 &adev->sdma.doorbell_invalid_irq); 1799 if (r) 1800 return r; 1801 1802 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1803 SDMA0_4_0__SRCID__SDMA_POLL_TIMEOUT, 1804 &adev->sdma.pool_timeout_irq); 1805 if (r) 1806 return r; 1807 1808 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1809 SDMA0_4_0__SRCID__SDMA_SRBMWRITE, 1810 &adev->sdma.srbm_write_irq); 1811 if (r) 1812 return r; 1813 } 1814 1815 for (i = 0; i < adev->sdma.num_instances; i++) { 1816 ring = &adev->sdma.instance[i].ring; 1817 ring->ring_obj = NULL; 1818 ring->use_doorbell = true; 1819 1820 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1821 ring->use_doorbell?"true":"false"); 1822 1823 /* doorbell size is 2 dwords, get DWORD offset */ 1824 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1; 1825 1826 sprintf(ring->name, "sdma%d", i); 1827 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1828 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1829 AMDGPU_RING_PRIO_DEFAULT, NULL); 1830 if (r) 1831 return r; 1832 1833 if (adev->sdma.has_page_queue) { 1834 ring = &adev->sdma.instance[i].page; 1835 ring->ring_obj = NULL; 1836 ring->use_doorbell = true; 1837 1838 /* paging queue use same doorbell index/routing as gfx queue 1839 * with 0x400 (4096 dwords) offset on second doorbell page 1840 */ 1841 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1; 1842 ring->doorbell_index += 0x400; 1843 1844 sprintf(ring->name, "page%d", i); 1845 r = amdgpu_ring_init(adev, ring, 1024, 1846 &adev->sdma.trap_irq, 1847 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1848 AMDGPU_RING_PRIO_DEFAULT, NULL); 1849 if (r) 1850 return r; 1851 } 1852 } 1853 1854 return r; 1855 } 1856 1857 static int sdma_v4_0_sw_fini(void *handle) 1858 { 1859 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1860 int i; 1861 1862 for (i = 0; i < adev->sdma.num_instances; i++) { 1863 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1864 if (adev->sdma.has_page_queue) 1865 amdgpu_ring_fini(&adev->sdma.instance[i].page); 1866 } 1867 1868 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 0) || 1869 adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 0)) 1870 amdgpu_sdma_destroy_inst_ctx(adev, true); 1871 else 1872 amdgpu_sdma_destroy_inst_ctx(adev, false); 1873 1874 return 0; 1875 } 1876 1877 static int sdma_v4_0_hw_init(void *handle) 1878 { 1879 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1880 1881 if (adev->flags & AMD_IS_APU) 1882 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false); 1883 1884 if (!amdgpu_sriov_vf(adev)) 1885 sdma_v4_0_init_golden_registers(adev); 1886 1887 return sdma_v4_0_start(adev); 1888 } 1889 1890 static int sdma_v4_0_hw_fini(void *handle) 1891 { 1892 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1893 int i; 1894 1895 if (amdgpu_sriov_vf(adev)) { 1896 /* disable the scheduler for SDMA */ 1897 amdgpu_sdma_unset_buffer_funcs_helper(adev); 1898 return 0; 1899 } 1900 1901 for (i = 0; i < adev->sdma.num_instances; i++) { 1902 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, 1903 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 1904 } 1905 1906 sdma_v4_0_ctx_switch_enable(adev, false); 1907 sdma_v4_0_enable(adev, false); 1908 1909 if (adev->flags & AMD_IS_APU) 1910 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true); 1911 1912 return 0; 1913 } 1914 1915 static int sdma_v4_0_suspend(void *handle) 1916 { 1917 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1918 1919 /* SMU saves SDMA state for us */ 1920 if (adev->in_s0ix) { 1921 sdma_v4_0_gfx_enable(adev, false); 1922 return 0; 1923 } 1924 1925 return sdma_v4_0_hw_fini(adev); 1926 } 1927 1928 static int sdma_v4_0_resume(void *handle) 1929 { 1930 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1931 1932 /* SMU restores SDMA state for us */ 1933 if (adev->in_s0ix) { 1934 sdma_v4_0_enable(adev, true); 1935 sdma_v4_0_gfx_enable(adev, true); 1936 amdgpu_ttm_set_buffer_funcs_status(adev, true); 1937 return 0; 1938 } 1939 1940 return sdma_v4_0_hw_init(adev); 1941 } 1942 1943 static bool sdma_v4_0_is_idle(void *handle) 1944 { 1945 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1946 u32 i; 1947 1948 for (i = 0; i < adev->sdma.num_instances; i++) { 1949 u32 tmp = RREG32_SDMA(i, mmSDMA0_STATUS_REG); 1950 1951 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1952 return false; 1953 } 1954 1955 return true; 1956 } 1957 1958 static int sdma_v4_0_wait_for_idle(void *handle) 1959 { 1960 unsigned i, j; 1961 u32 sdma[AMDGPU_MAX_SDMA_INSTANCES]; 1962 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1963 1964 for (i = 0; i < adev->usec_timeout; i++) { 1965 for (j = 0; j < adev->sdma.num_instances; j++) { 1966 sdma[j] = RREG32_SDMA(j, mmSDMA0_STATUS_REG); 1967 if (!(sdma[j] & SDMA0_STATUS_REG__IDLE_MASK)) 1968 break; 1969 } 1970 if (j == adev->sdma.num_instances) 1971 return 0; 1972 udelay(1); 1973 } 1974 return -ETIMEDOUT; 1975 } 1976 1977 static int sdma_v4_0_soft_reset(void *handle) 1978 { 1979 /* todo */ 1980 1981 return 0; 1982 } 1983 1984 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev, 1985 struct amdgpu_irq_src *source, 1986 unsigned type, 1987 enum amdgpu_interrupt_state state) 1988 { 1989 u32 sdma_cntl; 1990 1991 sdma_cntl = RREG32_SDMA(type, mmSDMA0_CNTL); 1992 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1993 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1994 WREG32_SDMA(type, mmSDMA0_CNTL, sdma_cntl); 1995 1996 return 0; 1997 } 1998 1999 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev, 2000 struct amdgpu_irq_src *source, 2001 struct amdgpu_iv_entry *entry) 2002 { 2003 uint32_t instance; 2004 2005 DRM_DEBUG("IH: SDMA trap\n"); 2006 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 2007 switch (entry->ring_id) { 2008 case 0: 2009 amdgpu_fence_process(&adev->sdma.instance[instance].ring); 2010 break; 2011 case 1: 2012 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 0)) 2013 amdgpu_fence_process(&adev->sdma.instance[instance].page); 2014 break; 2015 case 2: 2016 /* XXX compute */ 2017 break; 2018 case 3: 2019 if (adev->ip_versions[SDMA0_HWIP][0] != IP_VERSION(4, 2, 0)) 2020 amdgpu_fence_process(&adev->sdma.instance[instance].page); 2021 break; 2022 } 2023 return 0; 2024 } 2025 2026 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev, 2027 void *err_data, 2028 struct amdgpu_iv_entry *entry) 2029 { 2030 int instance; 2031 2032 /* When “Full RAS” is enabled, the per-IP interrupt sources should 2033 * be disabled and the driver should only look for the aggregated 2034 * interrupt via sync flood 2035 */ 2036 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 2037 goto out; 2038 2039 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 2040 if (instance < 0) 2041 goto out; 2042 2043 amdgpu_sdma_process_ras_data_cb(adev, err_data, entry); 2044 2045 out: 2046 return AMDGPU_RAS_SUCCESS; 2047 } 2048 2049 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev, 2050 struct amdgpu_irq_src *source, 2051 struct amdgpu_iv_entry *entry) 2052 { 2053 int instance; 2054 2055 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 2056 2057 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 2058 if (instance < 0) 2059 return 0; 2060 2061 switch (entry->ring_id) { 2062 case 0: 2063 drm_sched_fault(&adev->sdma.instance[instance].ring.sched); 2064 break; 2065 } 2066 return 0; 2067 } 2068 2069 static int sdma_v4_0_set_ecc_irq_state(struct amdgpu_device *adev, 2070 struct amdgpu_irq_src *source, 2071 unsigned type, 2072 enum amdgpu_interrupt_state state) 2073 { 2074 u32 sdma_edc_config; 2075 2076 sdma_edc_config = RREG32_SDMA(type, mmSDMA0_EDC_CONFIG); 2077 sdma_edc_config = REG_SET_FIELD(sdma_edc_config, SDMA0_EDC_CONFIG, ECC_INT_ENABLE, 2078 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2079 WREG32_SDMA(type, mmSDMA0_EDC_CONFIG, sdma_edc_config); 2080 2081 return 0; 2082 } 2083 2084 static int sdma_v4_0_print_iv_entry(struct amdgpu_device *adev, 2085 struct amdgpu_iv_entry *entry) 2086 { 2087 int instance; 2088 struct amdgpu_task_info task_info; 2089 u64 addr; 2090 2091 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 2092 if (instance < 0 || instance >= adev->sdma.num_instances) { 2093 dev_err(adev->dev, "sdma instance invalid %d\n", instance); 2094 return -EINVAL; 2095 } 2096 2097 addr = (u64)entry->src_data[0] << 12; 2098 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 2099 2100 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 2101 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 2102 2103 dev_dbg_ratelimited(adev->dev, 2104 "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u " 2105 "pasid:%u, for process %s pid %d thread %s pid %d\n", 2106 instance, addr, entry->src_id, entry->ring_id, entry->vmid, 2107 entry->pasid, task_info.process_name, task_info.tgid, 2108 task_info.task_name, task_info.pid); 2109 return 0; 2110 } 2111 2112 static int sdma_v4_0_process_vm_hole_irq(struct amdgpu_device *adev, 2113 struct amdgpu_irq_src *source, 2114 struct amdgpu_iv_entry *entry) 2115 { 2116 dev_dbg_ratelimited(adev->dev, "MC or SEM address in VM hole\n"); 2117 sdma_v4_0_print_iv_entry(adev, entry); 2118 return 0; 2119 } 2120 2121 static int sdma_v4_0_process_doorbell_invalid_irq(struct amdgpu_device *adev, 2122 struct amdgpu_irq_src *source, 2123 struct amdgpu_iv_entry *entry) 2124 { 2125 dev_dbg_ratelimited(adev->dev, "SDMA received a doorbell from BIF with byte_enable !=0xff\n"); 2126 sdma_v4_0_print_iv_entry(adev, entry); 2127 return 0; 2128 } 2129 2130 static int sdma_v4_0_process_pool_timeout_irq(struct amdgpu_device *adev, 2131 struct amdgpu_irq_src *source, 2132 struct amdgpu_iv_entry *entry) 2133 { 2134 dev_dbg_ratelimited(adev->dev, 2135 "Polling register/memory timeout executing POLL_REG/MEM with finite timer\n"); 2136 sdma_v4_0_print_iv_entry(adev, entry); 2137 return 0; 2138 } 2139 2140 static int sdma_v4_0_process_srbm_write_irq(struct amdgpu_device *adev, 2141 struct amdgpu_irq_src *source, 2142 struct amdgpu_iv_entry *entry) 2143 { 2144 dev_dbg_ratelimited(adev->dev, 2145 "SDMA gets an Register Write SRBM_WRITE command in non-privilege command buffer\n"); 2146 sdma_v4_0_print_iv_entry(adev, entry); 2147 return 0; 2148 } 2149 2150 static void sdma_v4_0_update_medium_grain_clock_gating( 2151 struct amdgpu_device *adev, 2152 bool enable) 2153 { 2154 uint32_t data, def; 2155 int i; 2156 2157 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 2158 for (i = 0; i < adev->sdma.num_instances; i++) { 2159 def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL); 2160 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 2161 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 2162 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 2163 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 2164 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 2165 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 2166 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 2167 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 2168 if (def != data) 2169 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data); 2170 } 2171 } else { 2172 for (i = 0; i < adev->sdma.num_instances; i++) { 2173 def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL); 2174 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 2175 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 2176 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 2177 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 2178 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 2179 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 2180 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 2181 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 2182 if (def != data) 2183 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data); 2184 } 2185 } 2186 } 2187 2188 2189 static void sdma_v4_0_update_medium_grain_light_sleep( 2190 struct amdgpu_device *adev, 2191 bool enable) 2192 { 2193 uint32_t data, def; 2194 int i; 2195 2196 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 2197 for (i = 0; i < adev->sdma.num_instances; i++) { 2198 /* 1-not override: enable sdma mem light sleep */ 2199 def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL); 2200 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 2201 if (def != data) 2202 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data); 2203 } 2204 } else { 2205 for (i = 0; i < adev->sdma.num_instances; i++) { 2206 /* 0-override:disable sdma mem light sleep */ 2207 def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL); 2208 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 2209 if (def != data) 2210 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data); 2211 } 2212 } 2213 } 2214 2215 static int sdma_v4_0_set_clockgating_state(void *handle, 2216 enum amd_clockgating_state state) 2217 { 2218 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2219 2220 if (amdgpu_sriov_vf(adev)) 2221 return 0; 2222 2223 sdma_v4_0_update_medium_grain_clock_gating(adev, 2224 state == AMD_CG_STATE_GATE); 2225 sdma_v4_0_update_medium_grain_light_sleep(adev, 2226 state == AMD_CG_STATE_GATE); 2227 return 0; 2228 } 2229 2230 static int sdma_v4_0_set_powergating_state(void *handle, 2231 enum amd_powergating_state state) 2232 { 2233 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2234 2235 switch (adev->ip_versions[SDMA0_HWIP][0]) { 2236 case IP_VERSION(4, 1, 0): 2237 case IP_VERSION(4, 1, 1): 2238 case IP_VERSION(4, 1, 2): 2239 sdma_v4_1_update_power_gating(adev, 2240 state == AMD_PG_STATE_GATE); 2241 break; 2242 default: 2243 break; 2244 } 2245 2246 return 0; 2247 } 2248 2249 static void sdma_v4_0_get_clockgating_state(void *handle, u64 *flags) 2250 { 2251 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2252 int data; 2253 2254 if (amdgpu_sriov_vf(adev)) 2255 *flags = 0; 2256 2257 /* AMD_CG_SUPPORT_SDMA_MGCG */ 2258 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 2259 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK)) 2260 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 2261 2262 /* AMD_CG_SUPPORT_SDMA_LS */ 2263 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 2264 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 2265 *flags |= AMD_CG_SUPPORT_SDMA_LS; 2266 } 2267 2268 const struct amd_ip_funcs sdma_v4_0_ip_funcs = { 2269 .name = "sdma_v4_0", 2270 .early_init = sdma_v4_0_early_init, 2271 .late_init = sdma_v4_0_late_init, 2272 .sw_init = sdma_v4_0_sw_init, 2273 .sw_fini = sdma_v4_0_sw_fini, 2274 .hw_init = sdma_v4_0_hw_init, 2275 .hw_fini = sdma_v4_0_hw_fini, 2276 .suspend = sdma_v4_0_suspend, 2277 .resume = sdma_v4_0_resume, 2278 .is_idle = sdma_v4_0_is_idle, 2279 .wait_for_idle = sdma_v4_0_wait_for_idle, 2280 .soft_reset = sdma_v4_0_soft_reset, 2281 .set_clockgating_state = sdma_v4_0_set_clockgating_state, 2282 .set_powergating_state = sdma_v4_0_set_powergating_state, 2283 .get_clockgating_state = sdma_v4_0_get_clockgating_state, 2284 }; 2285 2286 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = { 2287 .type = AMDGPU_RING_TYPE_SDMA, 2288 .align_mask = 0xf, 2289 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2290 .support_64bit_ptrs = true, 2291 .secure_submission_supported = true, 2292 .vmhub = AMDGPU_MMHUB_0, 2293 .get_rptr = sdma_v4_0_ring_get_rptr, 2294 .get_wptr = sdma_v4_0_ring_get_wptr, 2295 .set_wptr = sdma_v4_0_ring_set_wptr, 2296 .emit_frame_size = 2297 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2298 3 + /* hdp invalidate */ 2299 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2300 /* sdma_v4_0_ring_emit_vm_flush */ 2301 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2302 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2303 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2304 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2305 .emit_ib = sdma_v4_0_ring_emit_ib, 2306 .emit_fence = sdma_v4_0_ring_emit_fence, 2307 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2308 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2309 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2310 .test_ring = sdma_v4_0_ring_test_ring, 2311 .test_ib = sdma_v4_0_ring_test_ib, 2312 .insert_nop = sdma_v4_0_ring_insert_nop, 2313 .pad_ib = sdma_v4_0_ring_pad_ib, 2314 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2315 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2316 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2317 }; 2318 2319 /* 2320 * On Arcturus, SDMA instance 5~7 has a different vmhub type(AMDGPU_MMHUB_1). 2321 * So create a individual constant ring_funcs for those instances. 2322 */ 2323 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs_2nd_mmhub = { 2324 .type = AMDGPU_RING_TYPE_SDMA, 2325 .align_mask = 0xf, 2326 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2327 .support_64bit_ptrs = true, 2328 .secure_submission_supported = true, 2329 .vmhub = AMDGPU_MMHUB_1, 2330 .get_rptr = sdma_v4_0_ring_get_rptr, 2331 .get_wptr = sdma_v4_0_ring_get_wptr, 2332 .set_wptr = sdma_v4_0_ring_set_wptr, 2333 .emit_frame_size = 2334 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2335 3 + /* hdp invalidate */ 2336 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2337 /* sdma_v4_0_ring_emit_vm_flush */ 2338 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2339 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2340 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2341 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2342 .emit_ib = sdma_v4_0_ring_emit_ib, 2343 .emit_fence = sdma_v4_0_ring_emit_fence, 2344 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2345 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2346 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2347 .test_ring = sdma_v4_0_ring_test_ring, 2348 .test_ib = sdma_v4_0_ring_test_ib, 2349 .insert_nop = sdma_v4_0_ring_insert_nop, 2350 .pad_ib = sdma_v4_0_ring_pad_ib, 2351 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2352 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2353 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2354 }; 2355 2356 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = { 2357 .type = AMDGPU_RING_TYPE_SDMA, 2358 .align_mask = 0xf, 2359 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2360 .support_64bit_ptrs = true, 2361 .secure_submission_supported = true, 2362 .vmhub = AMDGPU_MMHUB_0, 2363 .get_rptr = sdma_v4_0_ring_get_rptr, 2364 .get_wptr = sdma_v4_0_page_ring_get_wptr, 2365 .set_wptr = sdma_v4_0_page_ring_set_wptr, 2366 .emit_frame_size = 2367 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2368 3 + /* hdp invalidate */ 2369 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2370 /* sdma_v4_0_ring_emit_vm_flush */ 2371 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2372 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2373 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2374 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2375 .emit_ib = sdma_v4_0_ring_emit_ib, 2376 .emit_fence = sdma_v4_0_ring_emit_fence, 2377 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2378 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2379 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2380 .test_ring = sdma_v4_0_ring_test_ring, 2381 .test_ib = sdma_v4_0_ring_test_ib, 2382 .insert_nop = sdma_v4_0_ring_insert_nop, 2383 .pad_ib = sdma_v4_0_ring_pad_ib, 2384 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2385 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2386 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2387 }; 2388 2389 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs_2nd_mmhub = { 2390 .type = AMDGPU_RING_TYPE_SDMA, 2391 .align_mask = 0xf, 2392 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2393 .support_64bit_ptrs = true, 2394 .secure_submission_supported = true, 2395 .vmhub = AMDGPU_MMHUB_1, 2396 .get_rptr = sdma_v4_0_ring_get_rptr, 2397 .get_wptr = sdma_v4_0_page_ring_get_wptr, 2398 .set_wptr = sdma_v4_0_page_ring_set_wptr, 2399 .emit_frame_size = 2400 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2401 3 + /* hdp invalidate */ 2402 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2403 /* sdma_v4_0_ring_emit_vm_flush */ 2404 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2405 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2406 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2407 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2408 .emit_ib = sdma_v4_0_ring_emit_ib, 2409 .emit_fence = sdma_v4_0_ring_emit_fence, 2410 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2411 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2412 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2413 .test_ring = sdma_v4_0_ring_test_ring, 2414 .test_ib = sdma_v4_0_ring_test_ib, 2415 .insert_nop = sdma_v4_0_ring_insert_nop, 2416 .pad_ib = sdma_v4_0_ring_pad_ib, 2417 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2418 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2419 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2420 }; 2421 2422 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev) 2423 { 2424 int i; 2425 2426 for (i = 0; i < adev->sdma.num_instances; i++) { 2427 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) && i >= 5) 2428 adev->sdma.instance[i].ring.funcs = 2429 &sdma_v4_0_ring_funcs_2nd_mmhub; 2430 else 2431 adev->sdma.instance[i].ring.funcs = 2432 &sdma_v4_0_ring_funcs; 2433 adev->sdma.instance[i].ring.me = i; 2434 if (adev->sdma.has_page_queue) { 2435 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) && i >= 5) 2436 adev->sdma.instance[i].page.funcs = 2437 &sdma_v4_0_page_ring_funcs_2nd_mmhub; 2438 else 2439 adev->sdma.instance[i].page.funcs = 2440 &sdma_v4_0_page_ring_funcs; 2441 adev->sdma.instance[i].page.me = i; 2442 } 2443 } 2444 } 2445 2446 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = { 2447 .set = sdma_v4_0_set_trap_irq_state, 2448 .process = sdma_v4_0_process_trap_irq, 2449 }; 2450 2451 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = { 2452 .process = sdma_v4_0_process_illegal_inst_irq, 2453 }; 2454 2455 static const struct amdgpu_irq_src_funcs sdma_v4_0_ecc_irq_funcs = { 2456 .set = sdma_v4_0_set_ecc_irq_state, 2457 .process = amdgpu_sdma_process_ecc_irq, 2458 }; 2459 2460 static const struct amdgpu_irq_src_funcs sdma_v4_0_vm_hole_irq_funcs = { 2461 .process = sdma_v4_0_process_vm_hole_irq, 2462 }; 2463 2464 static const struct amdgpu_irq_src_funcs sdma_v4_0_doorbell_invalid_irq_funcs = { 2465 .process = sdma_v4_0_process_doorbell_invalid_irq, 2466 }; 2467 2468 static const struct amdgpu_irq_src_funcs sdma_v4_0_pool_timeout_irq_funcs = { 2469 .process = sdma_v4_0_process_pool_timeout_irq, 2470 }; 2471 2472 static const struct amdgpu_irq_src_funcs sdma_v4_0_srbm_write_irq_funcs = { 2473 .process = sdma_v4_0_process_srbm_write_irq, 2474 }; 2475 2476 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev) 2477 { 2478 adev->sdma.trap_irq.num_types = adev->sdma.num_instances; 2479 adev->sdma.ecc_irq.num_types = adev->sdma.num_instances; 2480 /*For Arcturus and Aldebaran, add another 4 irq handler*/ 2481 switch (adev->sdma.num_instances) { 2482 case 5: 2483 case 8: 2484 adev->sdma.vm_hole_irq.num_types = adev->sdma.num_instances; 2485 adev->sdma.doorbell_invalid_irq.num_types = adev->sdma.num_instances; 2486 adev->sdma.pool_timeout_irq.num_types = adev->sdma.num_instances; 2487 adev->sdma.srbm_write_irq.num_types = adev->sdma.num_instances; 2488 break; 2489 default: 2490 break; 2491 } 2492 adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs; 2493 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs; 2494 adev->sdma.ecc_irq.funcs = &sdma_v4_0_ecc_irq_funcs; 2495 adev->sdma.vm_hole_irq.funcs = &sdma_v4_0_vm_hole_irq_funcs; 2496 adev->sdma.doorbell_invalid_irq.funcs = &sdma_v4_0_doorbell_invalid_irq_funcs; 2497 adev->sdma.pool_timeout_irq.funcs = &sdma_v4_0_pool_timeout_irq_funcs; 2498 adev->sdma.srbm_write_irq.funcs = &sdma_v4_0_srbm_write_irq_funcs; 2499 } 2500 2501 /** 2502 * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine 2503 * 2504 * @ib: indirect buffer to copy to 2505 * @src_offset: src GPU address 2506 * @dst_offset: dst GPU address 2507 * @byte_count: number of bytes to xfer 2508 * @tmz: if a secure copy should be used 2509 * 2510 * Copy GPU buffers using the DMA engine (VEGA10/12). 2511 * Used by the amdgpu ttm implementation to move pages if 2512 * registered as the asic copy callback. 2513 */ 2514 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib, 2515 uint64_t src_offset, 2516 uint64_t dst_offset, 2517 uint32_t byte_count, 2518 bool tmz) 2519 { 2520 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 2521 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 2522 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0); 2523 ib->ptr[ib->length_dw++] = byte_count - 1; 2524 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 2525 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 2526 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 2527 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2528 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2529 } 2530 2531 /** 2532 * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine 2533 * 2534 * @ib: indirect buffer to copy to 2535 * @src_data: value to write to buffer 2536 * @dst_offset: dst GPU address 2537 * @byte_count: number of bytes to xfer 2538 * 2539 * Fill GPU buffers using the DMA engine (VEGA10/12). 2540 */ 2541 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib, 2542 uint32_t src_data, 2543 uint64_t dst_offset, 2544 uint32_t byte_count) 2545 { 2546 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 2547 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2548 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2549 ib->ptr[ib->length_dw++] = src_data; 2550 ib->ptr[ib->length_dw++] = byte_count - 1; 2551 } 2552 2553 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = { 2554 .copy_max_bytes = 0x400000, 2555 .copy_num_dw = 7, 2556 .emit_copy_buffer = sdma_v4_0_emit_copy_buffer, 2557 2558 .fill_max_bytes = 0x400000, 2559 .fill_num_dw = 5, 2560 .emit_fill_buffer = sdma_v4_0_emit_fill_buffer, 2561 }; 2562 2563 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev) 2564 { 2565 adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs; 2566 if (adev->sdma.has_page_queue) 2567 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page; 2568 else 2569 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 2570 } 2571 2572 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = { 2573 .copy_pte_num_dw = 7, 2574 .copy_pte = sdma_v4_0_vm_copy_pte, 2575 2576 .write_pte = sdma_v4_0_vm_write_pte, 2577 .set_pte_pde = sdma_v4_0_vm_set_pte_pde, 2578 }; 2579 2580 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev) 2581 { 2582 struct drm_gpu_scheduler *sched; 2583 unsigned i; 2584 2585 adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs; 2586 for (i = 0; i < adev->sdma.num_instances; i++) { 2587 if (adev->sdma.has_page_queue) 2588 sched = &adev->sdma.instance[i].page.sched; 2589 else 2590 sched = &adev->sdma.instance[i].ring.sched; 2591 adev->vm_manager.vm_pte_scheds[i] = sched; 2592 } 2593 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 2594 } 2595 2596 static void sdma_v4_0_get_ras_error_count(uint32_t value, 2597 uint32_t instance, 2598 uint32_t *sec_count) 2599 { 2600 uint32_t i; 2601 uint32_t sec_cnt; 2602 2603 /* double bits error (multiple bits) error detection is not supported */ 2604 for (i = 0; i < ARRAY_SIZE(sdma_v4_0_ras_fields); i++) { 2605 /* the SDMA_EDC_COUNTER register in each sdma instance 2606 * shares the same sed shift_mask 2607 * */ 2608 sec_cnt = (value & 2609 sdma_v4_0_ras_fields[i].sec_count_mask) >> 2610 sdma_v4_0_ras_fields[i].sec_count_shift; 2611 if (sec_cnt) { 2612 DRM_INFO("Detected %s in SDMA%d, SED %d\n", 2613 sdma_v4_0_ras_fields[i].name, 2614 instance, sec_cnt); 2615 *sec_count += sec_cnt; 2616 } 2617 } 2618 } 2619 2620 static int sdma_v4_0_query_ras_error_count_by_instance(struct amdgpu_device *adev, 2621 uint32_t instance, void *ras_error_status) 2622 { 2623 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 2624 uint32_t sec_count = 0; 2625 uint32_t reg_value = 0; 2626 2627 reg_value = RREG32_SDMA(instance, mmSDMA0_EDC_COUNTER); 2628 /* double bit error is not supported */ 2629 if (reg_value) 2630 sdma_v4_0_get_ras_error_count(reg_value, 2631 instance, &sec_count); 2632 /* err_data->ce_count should be initialized to 0 2633 * before calling into this function */ 2634 err_data->ce_count += sec_count; 2635 /* double bit error is not supported 2636 * set ue count to 0 */ 2637 err_data->ue_count = 0; 2638 2639 return 0; 2640 }; 2641 2642 static void sdma_v4_0_query_ras_error_count(struct amdgpu_device *adev, void *ras_error_status) 2643 { 2644 int i = 0; 2645 2646 for (i = 0; i < adev->sdma.num_instances; i++) { 2647 if (sdma_v4_0_query_ras_error_count_by_instance(adev, i, ras_error_status)) { 2648 dev_err(adev->dev, "Query ras error count failed in SDMA%d\n", i); 2649 return; 2650 } 2651 } 2652 } 2653 2654 static void sdma_v4_0_reset_ras_error_count(struct amdgpu_device *adev) 2655 { 2656 int i; 2657 2658 /* read back edc counter registers to clear the counters */ 2659 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 2660 for (i = 0; i < adev->sdma.num_instances; i++) 2661 RREG32_SDMA(i, mmSDMA0_EDC_COUNTER); 2662 } 2663 } 2664 2665 const struct amdgpu_ras_block_hw_ops sdma_v4_0_ras_hw_ops = { 2666 .query_ras_error_count = sdma_v4_0_query_ras_error_count, 2667 .reset_ras_error_count = sdma_v4_0_reset_ras_error_count, 2668 }; 2669 2670 static struct amdgpu_sdma_ras sdma_v4_0_ras = { 2671 .ras_block = { 2672 .hw_ops = &sdma_v4_0_ras_hw_ops, 2673 .ras_cb = sdma_v4_0_process_ras_data_cb, 2674 }, 2675 }; 2676 2677 static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev) 2678 { 2679 switch (adev->ip_versions[SDMA0_HWIP][0]) { 2680 case IP_VERSION(4, 2, 0): 2681 case IP_VERSION(4, 2, 2): 2682 adev->sdma.ras = &sdma_v4_0_ras; 2683 break; 2684 case IP_VERSION(4, 4, 0): 2685 adev->sdma.ras = &sdma_v4_4_ras; 2686 break; 2687 default: 2688 break; 2689 } 2690 2691 if (adev->sdma.ras) { 2692 amdgpu_ras_register_ras_block(adev, &adev->sdma.ras->ras_block); 2693 2694 strcpy(adev->sdma.ras->ras_block.ras_comm.name, "sdma"); 2695 adev->sdma.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__SDMA; 2696 adev->sdma.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; 2697 adev->sdma.ras_if = &adev->sdma.ras->ras_block.ras_comm; 2698 2699 /* If don't define special ras_late_init function, use default ras_late_init */ 2700 if (!adev->sdma.ras->ras_block.ras_late_init) 2701 adev->sdma.ras->ras_block.ras_late_init = amdgpu_sdma_ras_late_init; 2702 2703 /* If not defined special ras_cb function, use default ras_cb */ 2704 if (!adev->sdma.ras->ras_block.ras_cb) 2705 adev->sdma.ras->ras_block.ras_cb = amdgpu_sdma_process_ras_data_cb; 2706 } 2707 } 2708 2709 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = { 2710 .type = AMD_IP_BLOCK_TYPE_SDMA, 2711 .major = 4, 2712 .minor = 0, 2713 .rev = 0, 2714 .funcs = &sdma_v4_0_ip_funcs, 2715 }; 2716