1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "sdma0/sdma0_4_2_offset.h" 34 #include "sdma0/sdma0_4_2_sh_mask.h" 35 #include "sdma1/sdma1_4_2_offset.h" 36 #include "sdma1/sdma1_4_2_sh_mask.h" 37 #include "sdma2/sdma2_4_2_2_offset.h" 38 #include "sdma2/sdma2_4_2_2_sh_mask.h" 39 #include "sdma3/sdma3_4_2_2_offset.h" 40 #include "sdma3/sdma3_4_2_2_sh_mask.h" 41 #include "sdma4/sdma4_4_2_2_offset.h" 42 #include "sdma4/sdma4_4_2_2_sh_mask.h" 43 #include "sdma5/sdma5_4_2_2_offset.h" 44 #include "sdma5/sdma5_4_2_2_sh_mask.h" 45 #include "sdma6/sdma6_4_2_2_offset.h" 46 #include "sdma6/sdma6_4_2_2_sh_mask.h" 47 #include "sdma7/sdma7_4_2_2_offset.h" 48 #include "sdma7/sdma7_4_2_2_sh_mask.h" 49 #include "hdp/hdp_4_0_offset.h" 50 #include "sdma0/sdma0_4_1_default.h" 51 52 #include "soc15_common.h" 53 #include "soc15.h" 54 #include "vega10_sdma_pkt_open.h" 55 56 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h" 57 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h" 58 59 #include "amdgpu_ras.h" 60 61 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin"); 62 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin"); 63 MODULE_FIRMWARE("amdgpu/vega12_sdma.bin"); 64 MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin"); 65 MODULE_FIRMWARE("amdgpu/vega20_sdma.bin"); 66 MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin"); 67 MODULE_FIRMWARE("amdgpu/raven_sdma.bin"); 68 MODULE_FIRMWARE("amdgpu/picasso_sdma.bin"); 69 MODULE_FIRMWARE("amdgpu/raven2_sdma.bin"); 70 MODULE_FIRMWARE("amdgpu/arcturus_sdma.bin"); 71 MODULE_FIRMWARE("amdgpu/renoir_sdma.bin"); 72 73 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L 74 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L 75 76 #define WREG32_SDMA(instance, offset, value) \ 77 WREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)), value) 78 #define RREG32_SDMA(instance, offset) \ 79 RREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset))) 80 81 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev); 82 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev); 83 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev); 84 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev); 85 static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev); 86 87 static const struct soc15_reg_golden golden_settings_sdma_4[] = { 88 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 89 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100), 90 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100), 91 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 92 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 93 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 94 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000), 95 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 96 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 97 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 98 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 99 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 100 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000), 101 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), 102 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100), 103 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 104 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 105 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 106 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000), 107 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 108 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 109 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 110 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 111 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0), 112 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xfc000000, 0x00000000) 113 }; 114 115 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = { 116 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 117 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 118 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 119 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 120 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 121 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 122 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 123 }; 124 125 static const struct soc15_reg_golden golden_settings_sdma_vg12[] = { 126 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), 127 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001), 128 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 129 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 130 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), 131 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001), 132 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 133 }; 134 135 static const struct soc15_reg_golden golden_settings_sdma_4_1[] = { 136 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 137 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 138 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100), 139 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 140 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051), 141 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100), 142 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 143 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100), 144 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 145 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 146 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000) 147 }; 148 149 static const struct soc15_reg_golden golden_settings_sdma0_4_2_init[] = { 150 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 151 }; 152 153 static const struct soc15_reg_golden golden_settings_sdma0_4_2[] = 154 { 155 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 156 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 157 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 158 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 159 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 160 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 161 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 162 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 163 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RD_BURST_CNTL, 0x0000000f, 0x00000003), 164 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 165 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 166 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 167 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 168 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 169 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 170 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 171 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 172 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 173 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 174 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 175 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 176 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 177 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 178 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 179 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 180 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 181 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 182 }; 183 184 static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = { 185 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 186 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), 187 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 188 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 189 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 190 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 191 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 192 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 193 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RD_BURST_CNTL, 0x0000000f, 0x00000003), 194 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 195 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 196 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 197 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 198 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 199 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 200 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 201 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 202 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 203 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 204 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 205 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 206 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 207 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 208 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 209 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 210 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0), 211 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 212 }; 213 214 static const struct soc15_reg_golden golden_settings_sdma_rv1[] = 215 { 216 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002), 217 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002) 218 }; 219 220 static const struct soc15_reg_golden golden_settings_sdma_rv2[] = 221 { 222 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00003001), 223 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003001) 224 }; 225 226 static const struct soc15_reg_golden golden_settings_sdma_arct[] = 227 { 228 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 229 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 230 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 231 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 232 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 233 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 234 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 235 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 236 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 237 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 238 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 239 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 240 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 241 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 242 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 243 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 244 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 245 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 246 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 247 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 248 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 249 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 250 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 251 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 252 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 253 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 254 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 255 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 256 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 257 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 258 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 259 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_UTCL1_TIMEOUT, 0xffffffff, 0x00010001) 260 }; 261 262 static const struct soc15_reg_golden golden_settings_sdma_4_3[] = { 263 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 264 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 265 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002), 266 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002), 267 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 268 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003fff07, 0x40000051), 269 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 270 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 271 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 272 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x03fbe1fe) 273 }; 274 275 static const struct soc15_ras_field_entry sdma_v4_0_ras_fields[] = { 276 { "SDMA_UCODE_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 277 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UCODE_BUF_SED), 278 0, 0, 279 }, 280 { "SDMA_RB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 281 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_RB_CMD_BUF_SED), 282 0, 0, 283 }, 284 { "SDMA_IB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 285 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_IB_CMD_BUF_SED), 286 0, 0, 287 }, 288 { "SDMA_UTCL1_RD_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 289 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UTCL1_RD_FIFO_SED), 290 0, 0, 291 }, 292 { "SDMA_UTCL1_RDBST_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 293 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UTCL1_RDBST_FIFO_SED), 294 0, 0, 295 }, 296 { "SDMA_DATA_LUT_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 297 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_DATA_LUT_FIFO_SED), 298 0, 0, 299 }, 300 { "SDMA_MBANK_DATA_BUF0_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 301 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF0_SED), 302 0, 0, 303 }, 304 { "SDMA_MBANK_DATA_BUF1_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 305 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF1_SED), 306 0, 0, 307 }, 308 { "SDMA_MBANK_DATA_BUF2_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 309 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF2_SED), 310 0, 0, 311 }, 312 { "SDMA_MBANK_DATA_BUF3_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 313 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF3_SED), 314 0, 0, 315 }, 316 { "SDMA_MBANK_DATA_BUF4_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 317 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF4_SED), 318 0, 0, 319 }, 320 { "SDMA_MBANK_DATA_BUF5_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 321 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF5_SED), 322 0, 0, 323 }, 324 { "SDMA_MBANK_DATA_BUF6_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 325 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF6_SED), 326 0, 0, 327 }, 328 { "SDMA_MBANK_DATA_BUF7_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 329 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF7_SED), 330 0, 0, 331 }, 332 { "SDMA_MBANK_DATA_BUF8_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 333 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF8_SED), 334 0, 0, 335 }, 336 { "SDMA_MBANK_DATA_BUF9_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 337 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF9_SED), 338 0, 0, 339 }, 340 { "SDMA_MBANK_DATA_BUF10_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 341 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF10_SED), 342 0, 0, 343 }, 344 { "SDMA_MBANK_DATA_BUF11_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 345 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF11_SED), 346 0, 0, 347 }, 348 { "SDMA_MBANK_DATA_BUF12_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 349 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF12_SED), 350 0, 0, 351 }, 352 { "SDMA_MBANK_DATA_BUF13_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 353 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF13_SED), 354 0, 0, 355 }, 356 { "SDMA_MBANK_DATA_BUF14_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 357 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF14_SED), 358 0, 0, 359 }, 360 { "SDMA_MBANK_DATA_BUF15_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 361 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF15_SED), 362 0, 0, 363 }, 364 { "SDMA_SPLIT_DAT_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 365 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_SPLIT_DAT_BUF_SED), 366 0, 0, 367 }, 368 { "SDMA_MC_WR_ADDR_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 369 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MC_WR_ADDR_FIFO_SED), 370 0, 0, 371 }, 372 }; 373 374 static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev, 375 u32 instance, u32 offset) 376 { 377 switch (instance) { 378 case 0: 379 return (adev->reg_offset[SDMA0_HWIP][0][0] + offset); 380 case 1: 381 return (adev->reg_offset[SDMA1_HWIP][0][0] + offset); 382 case 2: 383 return (adev->reg_offset[SDMA2_HWIP][0][1] + offset); 384 case 3: 385 return (adev->reg_offset[SDMA3_HWIP][0][1] + offset); 386 case 4: 387 return (adev->reg_offset[SDMA4_HWIP][0][1] + offset); 388 case 5: 389 return (adev->reg_offset[SDMA5_HWIP][0][1] + offset); 390 case 6: 391 return (adev->reg_offset[SDMA6_HWIP][0][1] + offset); 392 case 7: 393 return (adev->reg_offset[SDMA7_HWIP][0][1] + offset); 394 default: 395 break; 396 } 397 return 0; 398 } 399 400 static unsigned sdma_v4_0_seq_to_irq_id(int seq_num) 401 { 402 switch (seq_num) { 403 case 0: 404 return SOC15_IH_CLIENTID_SDMA0; 405 case 1: 406 return SOC15_IH_CLIENTID_SDMA1; 407 case 2: 408 return SOC15_IH_CLIENTID_SDMA2; 409 case 3: 410 return SOC15_IH_CLIENTID_SDMA3; 411 case 4: 412 return SOC15_IH_CLIENTID_SDMA4; 413 case 5: 414 return SOC15_IH_CLIENTID_SDMA5; 415 case 6: 416 return SOC15_IH_CLIENTID_SDMA6; 417 case 7: 418 return SOC15_IH_CLIENTID_SDMA7; 419 default: 420 break; 421 } 422 return -EINVAL; 423 } 424 425 static int sdma_v4_0_irq_id_to_seq(unsigned client_id) 426 { 427 switch (client_id) { 428 case SOC15_IH_CLIENTID_SDMA0: 429 return 0; 430 case SOC15_IH_CLIENTID_SDMA1: 431 return 1; 432 case SOC15_IH_CLIENTID_SDMA2: 433 return 2; 434 case SOC15_IH_CLIENTID_SDMA3: 435 return 3; 436 case SOC15_IH_CLIENTID_SDMA4: 437 return 4; 438 case SOC15_IH_CLIENTID_SDMA5: 439 return 5; 440 case SOC15_IH_CLIENTID_SDMA6: 441 return 6; 442 case SOC15_IH_CLIENTID_SDMA7: 443 return 7; 444 default: 445 break; 446 } 447 return -EINVAL; 448 } 449 450 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) 451 { 452 switch (adev->asic_type) { 453 case CHIP_VEGA10: 454 soc15_program_register_sequence(adev, 455 golden_settings_sdma_4, 456 ARRAY_SIZE(golden_settings_sdma_4)); 457 soc15_program_register_sequence(adev, 458 golden_settings_sdma_vg10, 459 ARRAY_SIZE(golden_settings_sdma_vg10)); 460 break; 461 case CHIP_VEGA12: 462 soc15_program_register_sequence(adev, 463 golden_settings_sdma_4, 464 ARRAY_SIZE(golden_settings_sdma_4)); 465 soc15_program_register_sequence(adev, 466 golden_settings_sdma_vg12, 467 ARRAY_SIZE(golden_settings_sdma_vg12)); 468 break; 469 case CHIP_VEGA20: 470 soc15_program_register_sequence(adev, 471 golden_settings_sdma0_4_2_init, 472 ARRAY_SIZE(golden_settings_sdma0_4_2_init)); 473 soc15_program_register_sequence(adev, 474 golden_settings_sdma0_4_2, 475 ARRAY_SIZE(golden_settings_sdma0_4_2)); 476 soc15_program_register_sequence(adev, 477 golden_settings_sdma1_4_2, 478 ARRAY_SIZE(golden_settings_sdma1_4_2)); 479 break; 480 case CHIP_ARCTURUS: 481 soc15_program_register_sequence(adev, 482 golden_settings_sdma_arct, 483 ARRAY_SIZE(golden_settings_sdma_arct)); 484 break; 485 case CHIP_RAVEN: 486 soc15_program_register_sequence(adev, 487 golden_settings_sdma_4_1, 488 ARRAY_SIZE(golden_settings_sdma_4_1)); 489 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 490 soc15_program_register_sequence(adev, 491 golden_settings_sdma_rv2, 492 ARRAY_SIZE(golden_settings_sdma_rv2)); 493 else 494 soc15_program_register_sequence(adev, 495 golden_settings_sdma_rv1, 496 ARRAY_SIZE(golden_settings_sdma_rv1)); 497 break; 498 case CHIP_RENOIR: 499 soc15_program_register_sequence(adev, 500 golden_settings_sdma_4_3, 501 ARRAY_SIZE(golden_settings_sdma_4_3)); 502 break; 503 default: 504 break; 505 } 506 } 507 508 static void sdma_v4_0_setup_ulv(struct amdgpu_device *adev) 509 { 510 int i; 511 512 /* 513 * The only chips with SDMAv4 and ULV are VG10 and VG20. 514 * Server SKUs take a different hysteresis setting from other SKUs. 515 */ 516 switch (adev->asic_type) { 517 case CHIP_VEGA10: 518 if (adev->pdev->device == 0x6860) 519 break; 520 return; 521 case CHIP_VEGA20: 522 if (adev->pdev->device == 0x66a1) 523 break; 524 return; 525 default: 526 return; 527 } 528 529 for (i = 0; i < adev->sdma.num_instances; i++) { 530 uint32_t temp; 531 532 temp = RREG32_SDMA(i, mmSDMA0_ULV_CNTL); 533 temp = REG_SET_FIELD(temp, SDMA0_ULV_CNTL, HYSTERESIS, 0x0); 534 WREG32_SDMA(i, mmSDMA0_ULV_CNTL, temp); 535 } 536 } 537 538 static int sdma_v4_0_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst) 539 { 540 int err = 0; 541 const struct sdma_firmware_header_v1_0 *hdr; 542 543 err = amdgpu_ucode_validate(sdma_inst->fw); 544 if (err) 545 return err; 546 547 hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data; 548 sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version); 549 sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version); 550 551 if (sdma_inst->feature_version >= 20) 552 sdma_inst->burst_nop = true; 553 554 return 0; 555 } 556 557 static void sdma_v4_0_destroy_inst_ctx(struct amdgpu_device *adev) 558 { 559 int i; 560 561 for (i = 0; i < adev->sdma.num_instances; i++) { 562 release_firmware(adev->sdma.instance[i].fw); 563 adev->sdma.instance[i].fw = NULL; 564 565 /* arcturus shares the same FW memory across 566 all SDMA isntances */ 567 if (adev->asic_type == CHIP_ARCTURUS) 568 break; 569 } 570 571 memset((void*)adev->sdma.instance, 0, 572 sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES); 573 } 574 575 /** 576 * sdma_v4_0_init_microcode - load ucode images from disk 577 * 578 * @adev: amdgpu_device pointer 579 * 580 * Use the firmware interface to load the ucode images into 581 * the driver (not loaded into hw). 582 * Returns 0 on success, error on failure. 583 */ 584 585 // emulation only, won't work on real chip 586 // vega10 real chip need to use PSP to load firmware 587 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev) 588 { 589 const char *chip_name; 590 char fw_name[30]; 591 int err = 0, i; 592 struct amdgpu_firmware_info *info = NULL; 593 const struct common_firmware_header *header = NULL; 594 595 if (amdgpu_sriov_vf(adev)) 596 return 0; 597 598 DRM_DEBUG("\n"); 599 600 switch (adev->asic_type) { 601 case CHIP_VEGA10: 602 chip_name = "vega10"; 603 break; 604 case CHIP_VEGA12: 605 chip_name = "vega12"; 606 break; 607 case CHIP_VEGA20: 608 chip_name = "vega20"; 609 break; 610 case CHIP_RAVEN: 611 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 612 chip_name = "raven2"; 613 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 614 chip_name = "picasso"; 615 else 616 chip_name = "raven"; 617 break; 618 case CHIP_ARCTURUS: 619 chip_name = "arcturus"; 620 break; 621 case CHIP_RENOIR: 622 chip_name = "renoir"; 623 break; 624 default: 625 BUG(); 626 } 627 628 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 629 630 err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev); 631 if (err) 632 goto out; 633 634 err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[0]); 635 if (err) 636 goto out; 637 638 for (i = 1; i < adev->sdma.num_instances; i++) { 639 if (adev->asic_type == CHIP_ARCTURUS) { 640 /* Acturus will leverage the same FW memory 641 for every SDMA instance */ 642 memcpy((void*)&adev->sdma.instance[i], 643 (void*)&adev->sdma.instance[0], 644 sizeof(struct amdgpu_sdma_instance)); 645 } 646 else { 647 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i); 648 649 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 650 if (err) 651 goto out; 652 653 err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[i]); 654 if (err) 655 goto out; 656 } 657 } 658 659 DRM_DEBUG("psp_load == '%s'\n", 660 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); 661 662 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 663 for (i = 0; i < adev->sdma.num_instances; i++) { 664 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 665 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 666 info->fw = adev->sdma.instance[i].fw; 667 header = (const struct common_firmware_header *)info->fw->data; 668 adev->firmware.fw_size += 669 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 670 } 671 } 672 673 out: 674 if (err) { 675 DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name); 676 sdma_v4_0_destroy_inst_ctx(adev); 677 } 678 return err; 679 } 680 681 /** 682 * sdma_v4_0_ring_get_rptr - get the current read pointer 683 * 684 * @ring: amdgpu ring pointer 685 * 686 * Get the current rptr from the hardware (VEGA10+). 687 */ 688 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring) 689 { 690 u64 *rptr; 691 692 /* XXX check if swapping is necessary on BE */ 693 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]); 694 695 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 696 return ((*rptr) >> 2); 697 } 698 699 /** 700 * sdma_v4_0_ring_get_wptr - get the current write pointer 701 * 702 * @ring: amdgpu ring pointer 703 * 704 * Get the current wptr from the hardware (VEGA10+). 705 */ 706 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring) 707 { 708 struct amdgpu_device *adev = ring->adev; 709 u64 wptr; 710 711 if (ring->use_doorbell) { 712 /* XXX check if swapping is necessary on BE */ 713 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 714 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 715 } else { 716 wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI); 717 wptr = wptr << 32; 718 wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR); 719 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", 720 ring->me, wptr); 721 } 722 723 return wptr >> 2; 724 } 725 726 /** 727 * sdma_v4_0_page_ring_set_wptr - commit the write pointer 728 * 729 * @ring: amdgpu ring pointer 730 * 731 * Write the wptr back to the hardware (VEGA10+). 732 */ 733 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring) 734 { 735 struct amdgpu_device *adev = ring->adev; 736 737 DRM_DEBUG("Setting write pointer\n"); 738 if (ring->use_doorbell) { 739 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 740 741 DRM_DEBUG("Using doorbell -- " 742 "wptr_offs == 0x%08x " 743 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 744 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 745 ring->wptr_offs, 746 lower_32_bits(ring->wptr << 2), 747 upper_32_bits(ring->wptr << 2)); 748 /* XXX check if swapping is necessary on BE */ 749 WRITE_ONCE(*wb, (ring->wptr << 2)); 750 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 751 ring->doorbell_index, ring->wptr << 2); 752 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 753 } else { 754 DRM_DEBUG("Not using doorbell -- " 755 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 756 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 757 ring->me, 758 lower_32_bits(ring->wptr << 2), 759 ring->me, 760 upper_32_bits(ring->wptr << 2)); 761 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR, 762 lower_32_bits(ring->wptr << 2)); 763 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI, 764 upper_32_bits(ring->wptr << 2)); 765 } 766 } 767 768 /** 769 * sdma_v4_0_page_ring_get_wptr - get the current write pointer 770 * 771 * @ring: amdgpu ring pointer 772 * 773 * Get the current wptr from the hardware (VEGA10+). 774 */ 775 static uint64_t sdma_v4_0_page_ring_get_wptr(struct amdgpu_ring *ring) 776 { 777 struct amdgpu_device *adev = ring->adev; 778 u64 wptr; 779 780 if (ring->use_doorbell) { 781 /* XXX check if swapping is necessary on BE */ 782 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 783 } else { 784 wptr = RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI); 785 wptr = wptr << 32; 786 wptr |= RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR); 787 } 788 789 return wptr >> 2; 790 } 791 792 /** 793 * sdma_v4_0_ring_set_wptr - commit the write pointer 794 * 795 * @ring: amdgpu ring pointer 796 * 797 * Write the wptr back to the hardware (VEGA10+). 798 */ 799 static void sdma_v4_0_page_ring_set_wptr(struct amdgpu_ring *ring) 800 { 801 struct amdgpu_device *adev = ring->adev; 802 803 if (ring->use_doorbell) { 804 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 805 806 /* XXX check if swapping is necessary on BE */ 807 WRITE_ONCE(*wb, (ring->wptr << 2)); 808 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 809 } else { 810 uint64_t wptr = ring->wptr << 2; 811 812 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR, 813 lower_32_bits(wptr)); 814 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI, 815 upper_32_bits(wptr)); 816 } 817 } 818 819 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 820 { 821 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 822 int i; 823 824 for (i = 0; i < count; i++) 825 if (sdma && sdma->burst_nop && (i == 0)) 826 amdgpu_ring_write(ring, ring->funcs->nop | 827 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 828 else 829 amdgpu_ring_write(ring, ring->funcs->nop); 830 } 831 832 /** 833 * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine 834 * 835 * @ring: amdgpu ring pointer 836 * @ib: IB object to schedule 837 * 838 * Schedule an IB in the DMA ring (VEGA10). 839 */ 840 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring, 841 struct amdgpu_job *job, 842 struct amdgpu_ib *ib, 843 uint32_t flags) 844 { 845 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 846 847 /* IB packet must end on a 8 DW boundary */ 848 sdma_v4_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 849 850 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 851 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 852 /* base must be 32 byte aligned */ 853 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 854 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 855 amdgpu_ring_write(ring, ib->length_dw); 856 amdgpu_ring_write(ring, 0); 857 amdgpu_ring_write(ring, 0); 858 859 } 860 861 static void sdma_v4_0_wait_reg_mem(struct amdgpu_ring *ring, 862 int mem_space, int hdp, 863 uint32_t addr0, uint32_t addr1, 864 uint32_t ref, uint32_t mask, 865 uint32_t inv) 866 { 867 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 868 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) | 869 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) | 870 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 871 if (mem_space) { 872 /* memory */ 873 amdgpu_ring_write(ring, addr0); 874 amdgpu_ring_write(ring, addr1); 875 } else { 876 /* registers */ 877 amdgpu_ring_write(ring, addr0 << 2); 878 amdgpu_ring_write(ring, addr1 << 2); 879 } 880 amdgpu_ring_write(ring, ref); /* reference */ 881 amdgpu_ring_write(ring, mask); /* mask */ 882 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 883 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */ 884 } 885 886 /** 887 * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 888 * 889 * @ring: amdgpu ring pointer 890 * 891 * Emit an hdp flush packet on the requested DMA ring. 892 */ 893 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 894 { 895 struct amdgpu_device *adev = ring->adev; 896 u32 ref_and_mask = 0; 897 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 898 899 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; 900 901 sdma_v4_0_wait_reg_mem(ring, 0, 1, 902 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 903 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 904 ref_and_mask, ref_and_mask, 10); 905 } 906 907 /** 908 * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring 909 * 910 * @ring: amdgpu ring pointer 911 * @fence: amdgpu fence object 912 * 913 * Add a DMA fence packet to the ring to write 914 * the fence seq number and DMA trap packet to generate 915 * an interrupt if needed (VEGA10). 916 */ 917 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 918 unsigned flags) 919 { 920 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 921 /* write the fence */ 922 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 923 /* zero in first two bits */ 924 BUG_ON(addr & 0x3); 925 amdgpu_ring_write(ring, lower_32_bits(addr)); 926 amdgpu_ring_write(ring, upper_32_bits(addr)); 927 amdgpu_ring_write(ring, lower_32_bits(seq)); 928 929 /* optionally write high bits as well */ 930 if (write64bit) { 931 addr += 4; 932 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 933 /* zero in first two bits */ 934 BUG_ON(addr & 0x3); 935 amdgpu_ring_write(ring, lower_32_bits(addr)); 936 amdgpu_ring_write(ring, upper_32_bits(addr)); 937 amdgpu_ring_write(ring, upper_32_bits(seq)); 938 } 939 940 /* generate an interrupt */ 941 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 942 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 943 } 944 945 946 /** 947 * sdma_v4_0_gfx_stop - stop the gfx async dma engines 948 * 949 * @adev: amdgpu_device pointer 950 * 951 * Stop the gfx async dma ring buffers (VEGA10). 952 */ 953 static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev) 954 { 955 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; 956 u32 rb_cntl, ib_cntl; 957 int i, unset = 0; 958 959 for (i = 0; i < adev->sdma.num_instances; i++) { 960 sdma[i] = &adev->sdma.instance[i].ring; 961 962 if ((adev->mman.buffer_funcs_ring == sdma[i]) && unset != 1) { 963 amdgpu_ttm_set_buffer_funcs_status(adev, false); 964 unset = 1; 965 } 966 967 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL); 968 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 969 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 970 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL); 971 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 972 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl); 973 } 974 } 975 976 /** 977 * sdma_v4_0_rlc_stop - stop the compute async dma engines 978 * 979 * @adev: amdgpu_device pointer 980 * 981 * Stop the compute async dma queues (VEGA10). 982 */ 983 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev) 984 { 985 /* XXX todo */ 986 } 987 988 /** 989 * sdma_v4_0_page_stop - stop the page async dma engines 990 * 991 * @adev: amdgpu_device pointer 992 * 993 * Stop the page async dma ring buffers (VEGA10). 994 */ 995 static void sdma_v4_0_page_stop(struct amdgpu_device *adev) 996 { 997 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; 998 u32 rb_cntl, ib_cntl; 999 int i; 1000 bool unset = false; 1001 1002 for (i = 0; i < adev->sdma.num_instances; i++) { 1003 sdma[i] = &adev->sdma.instance[i].page; 1004 1005 if ((adev->mman.buffer_funcs_ring == sdma[i]) && 1006 (!unset)) { 1007 amdgpu_ttm_set_buffer_funcs_status(adev, false); 1008 unset = true; 1009 } 1010 1011 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL); 1012 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, 1013 RB_ENABLE, 0); 1014 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 1015 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL); 1016 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, 1017 IB_ENABLE, 0); 1018 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl); 1019 } 1020 } 1021 1022 /** 1023 * sdma_v4_0_ctx_switch_enable - stop the async dma engines context switch 1024 * 1025 * @adev: amdgpu_device pointer 1026 * @enable: enable/disable the DMA MEs context switch. 1027 * 1028 * Halt or unhalt the async dma engines context switch (VEGA10). 1029 */ 1030 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 1031 { 1032 u32 f32_cntl, phase_quantum = 0; 1033 int i; 1034 1035 if (amdgpu_sdma_phase_quantum) { 1036 unsigned value = amdgpu_sdma_phase_quantum; 1037 unsigned unit = 0; 1038 1039 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 1040 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 1041 value = (value + 1) >> 1; 1042 unit++; 1043 } 1044 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 1045 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 1046 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 1047 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 1048 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 1049 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 1050 WARN_ONCE(1, 1051 "clamping sdma_phase_quantum to %uK clock cycles\n", 1052 value << unit); 1053 } 1054 phase_quantum = 1055 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 1056 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 1057 } 1058 1059 for (i = 0; i < adev->sdma.num_instances; i++) { 1060 f32_cntl = RREG32_SDMA(i, mmSDMA0_CNTL); 1061 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 1062 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 1063 if (enable && amdgpu_sdma_phase_quantum) { 1064 WREG32_SDMA(i, mmSDMA0_PHASE0_QUANTUM, phase_quantum); 1065 WREG32_SDMA(i, mmSDMA0_PHASE1_QUANTUM, phase_quantum); 1066 WREG32_SDMA(i, mmSDMA0_PHASE2_QUANTUM, phase_quantum); 1067 } 1068 WREG32_SDMA(i, mmSDMA0_CNTL, f32_cntl); 1069 1070 /* 1071 * Enable SDMA utilization. Its only supported on 1072 * Arcturus for the moment and firmware version 14 1073 * and above. 1074 */ 1075 if (adev->asic_type == CHIP_ARCTURUS && 1076 adev->sdma.instance[i].fw_version >= 14) 1077 WREG32_SDMA(i, mmSDMA0_PUB_DUMMY_REG2, enable); 1078 } 1079 1080 } 1081 1082 /** 1083 * sdma_v4_0_enable - stop the async dma engines 1084 * 1085 * @adev: amdgpu_device pointer 1086 * @enable: enable/disable the DMA MEs. 1087 * 1088 * Halt or unhalt the async dma engines (VEGA10). 1089 */ 1090 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable) 1091 { 1092 u32 f32_cntl; 1093 int i; 1094 1095 if (!enable) { 1096 sdma_v4_0_gfx_stop(adev); 1097 sdma_v4_0_rlc_stop(adev); 1098 if (adev->sdma.has_page_queue) 1099 sdma_v4_0_page_stop(adev); 1100 } 1101 1102 for (i = 0; i < adev->sdma.num_instances; i++) { 1103 f32_cntl = RREG32_SDMA(i, mmSDMA0_F32_CNTL); 1104 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 1105 WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl); 1106 } 1107 } 1108 1109 /** 1110 * sdma_v4_0_rb_cntl - get parameters for rb_cntl 1111 */ 1112 static uint32_t sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl) 1113 { 1114 /* Set ring buffer size in dwords */ 1115 uint32_t rb_bufsz = order_base_2(ring->ring_size / 4); 1116 1117 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 1118 #ifdef __BIG_ENDIAN 1119 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 1120 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 1121 RPTR_WRITEBACK_SWAP_ENABLE, 1); 1122 #endif 1123 return rb_cntl; 1124 } 1125 1126 /** 1127 * sdma_v4_0_gfx_resume - setup and start the async dma engines 1128 * 1129 * @adev: amdgpu_device pointer 1130 * @i: instance to resume 1131 * 1132 * Set up the gfx DMA ring buffers and enable them (VEGA10). 1133 * Returns 0 for success, error for failure. 1134 */ 1135 static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i) 1136 { 1137 struct amdgpu_ring *ring = &adev->sdma.instance[i].ring; 1138 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 1139 u32 wb_offset; 1140 u32 doorbell; 1141 u32 doorbell_offset; 1142 u64 wptr_gpu_addr; 1143 1144 wb_offset = (ring->rptr_offs * 4); 1145 1146 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL); 1147 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl); 1148 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 1149 1150 /* Initialize the ring buffer's read and write pointers */ 1151 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR, 0); 1152 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_HI, 0); 1153 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR, 0); 1154 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_HI, 0); 1155 1156 /* set the wb address whether it's enabled or not */ 1157 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI, 1158 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 1159 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 1160 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 1161 1162 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 1163 RPTR_WRITEBACK_ENABLE, 1); 1164 1165 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE, ring->gpu_addr >> 8); 1166 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE_HI, ring->gpu_addr >> 40); 1167 1168 ring->wptr = 0; 1169 1170 /* before programing wptr to a less value, need set minor_ptr_update first */ 1171 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 1); 1172 1173 doorbell = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL); 1174 doorbell_offset = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET); 1175 1176 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1177 ring->use_doorbell); 1178 doorbell_offset = REG_SET_FIELD(doorbell_offset, 1179 SDMA0_GFX_DOORBELL_OFFSET, 1180 OFFSET, ring->doorbell_index); 1181 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL, doorbell); 1182 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET, doorbell_offset); 1183 1184 sdma_v4_0_ring_set_wptr(ring); 1185 1186 /* set minor_ptr_update to 0 after wptr programed */ 1187 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 0); 1188 1189 /* setup the wptr shadow polling */ 1190 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1191 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO, 1192 lower_32_bits(wptr_gpu_addr)); 1193 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI, 1194 upper_32_bits(wptr_gpu_addr)); 1195 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL); 1196 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 1197 SDMA0_GFX_RB_WPTR_POLL_CNTL, 1198 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 1199 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 1200 1201 /* enable DMA RB */ 1202 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 1203 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 1204 1205 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL); 1206 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 1207 #ifdef __BIG_ENDIAN 1208 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 1209 #endif 1210 /* enable DMA IBs */ 1211 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl); 1212 1213 ring->sched.ready = true; 1214 } 1215 1216 /** 1217 * sdma_v4_0_page_resume - setup and start the async dma engines 1218 * 1219 * @adev: amdgpu_device pointer 1220 * @i: instance to resume 1221 * 1222 * Set up the page DMA ring buffers and enable them (VEGA10). 1223 * Returns 0 for success, error for failure. 1224 */ 1225 static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i) 1226 { 1227 struct amdgpu_ring *ring = &adev->sdma.instance[i].page; 1228 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 1229 u32 wb_offset; 1230 u32 doorbell; 1231 u32 doorbell_offset; 1232 u64 wptr_gpu_addr; 1233 1234 wb_offset = (ring->rptr_offs * 4); 1235 1236 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL); 1237 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl); 1238 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 1239 1240 /* Initialize the ring buffer's read and write pointers */ 1241 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR, 0); 1242 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_HI, 0); 1243 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR, 0); 1244 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_HI, 0); 1245 1246 /* set the wb address whether it's enabled or not */ 1247 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_HI, 1248 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 1249 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 1250 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 1251 1252 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, 1253 RPTR_WRITEBACK_ENABLE, 1); 1254 1255 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE, ring->gpu_addr >> 8); 1256 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE_HI, ring->gpu_addr >> 40); 1257 1258 ring->wptr = 0; 1259 1260 /* before programing wptr to a less value, need set minor_ptr_update first */ 1261 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 1); 1262 1263 doorbell = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL); 1264 doorbell_offset = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET); 1265 1266 doorbell = REG_SET_FIELD(doorbell, SDMA0_PAGE_DOORBELL, ENABLE, 1267 ring->use_doorbell); 1268 doorbell_offset = REG_SET_FIELD(doorbell_offset, 1269 SDMA0_PAGE_DOORBELL_OFFSET, 1270 OFFSET, ring->doorbell_index); 1271 WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL, doorbell); 1272 WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET, doorbell_offset); 1273 1274 /* paging queue doorbell range is setup at sdma_v4_0_gfx_resume */ 1275 sdma_v4_0_page_ring_set_wptr(ring); 1276 1277 /* set minor_ptr_update to 0 after wptr programed */ 1278 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 0); 1279 1280 /* setup the wptr shadow polling */ 1281 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1282 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO, 1283 lower_32_bits(wptr_gpu_addr)); 1284 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI, 1285 upper_32_bits(wptr_gpu_addr)); 1286 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL); 1287 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 1288 SDMA0_PAGE_RB_WPTR_POLL_CNTL, 1289 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 1290 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 1291 1292 /* enable DMA RB */ 1293 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, RB_ENABLE, 1); 1294 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 1295 1296 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL); 1297 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_ENABLE, 1); 1298 #ifdef __BIG_ENDIAN 1299 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1); 1300 #endif 1301 /* enable DMA IBs */ 1302 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl); 1303 1304 ring->sched.ready = true; 1305 } 1306 1307 static void 1308 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable) 1309 { 1310 uint32_t def, data; 1311 1312 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) { 1313 /* enable idle interrupt */ 1314 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 1315 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 1316 1317 if (data != def) 1318 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 1319 } else { 1320 /* disable idle interrupt */ 1321 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 1322 data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 1323 if (data != def) 1324 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 1325 } 1326 } 1327 1328 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev) 1329 { 1330 uint32_t def, data; 1331 1332 /* Enable HW based PG. */ 1333 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1334 data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK; 1335 if (data != def) 1336 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1337 1338 /* enable interrupt */ 1339 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 1340 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 1341 if (data != def) 1342 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 1343 1344 /* Configure hold time to filter in-valid power on/off request. Use default right now */ 1345 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1346 data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK; 1347 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK); 1348 /* Configure switch time for hysteresis purpose. Use default right now */ 1349 data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK; 1350 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK); 1351 if(data != def) 1352 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1353 } 1354 1355 static void sdma_v4_0_init_pg(struct amdgpu_device *adev) 1356 { 1357 if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA)) 1358 return; 1359 1360 switch (adev->asic_type) { 1361 case CHIP_RAVEN: 1362 case CHIP_RENOIR: 1363 sdma_v4_1_init_power_gating(adev); 1364 sdma_v4_1_update_power_gating(adev, true); 1365 break; 1366 default: 1367 break; 1368 } 1369 } 1370 1371 /** 1372 * sdma_v4_0_rlc_resume - setup and start the async dma engines 1373 * 1374 * @adev: amdgpu_device pointer 1375 * 1376 * Set up the compute DMA queues and enable them (VEGA10). 1377 * Returns 0 for success, error for failure. 1378 */ 1379 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev) 1380 { 1381 sdma_v4_0_init_pg(adev); 1382 1383 return 0; 1384 } 1385 1386 /** 1387 * sdma_v4_0_load_microcode - load the sDMA ME ucode 1388 * 1389 * @adev: amdgpu_device pointer 1390 * 1391 * Loads the sDMA0/1 ucode. 1392 * Returns 0 for success, -EINVAL if the ucode is not available. 1393 */ 1394 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev) 1395 { 1396 const struct sdma_firmware_header_v1_0 *hdr; 1397 const __le32 *fw_data; 1398 u32 fw_size; 1399 int i, j; 1400 1401 /* halt the MEs */ 1402 sdma_v4_0_enable(adev, false); 1403 1404 for (i = 0; i < adev->sdma.num_instances; i++) { 1405 if (!adev->sdma.instance[i].fw) 1406 return -EINVAL; 1407 1408 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 1409 amdgpu_ucode_print_sdma_hdr(&hdr->header); 1410 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1411 1412 fw_data = (const __le32 *) 1413 (adev->sdma.instance[i].fw->data + 1414 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1415 1416 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 0); 1417 1418 for (j = 0; j < fw_size; j++) 1419 WREG32_SDMA(i, mmSDMA0_UCODE_DATA, 1420 le32_to_cpup(fw_data++)); 1421 1422 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 1423 adev->sdma.instance[i].fw_version); 1424 } 1425 1426 return 0; 1427 } 1428 1429 /** 1430 * sdma_v4_0_start - setup and start the async dma engines 1431 * 1432 * @adev: amdgpu_device pointer 1433 * 1434 * Set up the DMA engines and enable them (VEGA10). 1435 * Returns 0 for success, error for failure. 1436 */ 1437 static int sdma_v4_0_start(struct amdgpu_device *adev) 1438 { 1439 struct amdgpu_ring *ring; 1440 int i, r = 0; 1441 1442 if (amdgpu_sriov_vf(adev)) { 1443 sdma_v4_0_ctx_switch_enable(adev, false); 1444 sdma_v4_0_enable(adev, false); 1445 } else { 1446 1447 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1448 r = sdma_v4_0_load_microcode(adev); 1449 if (r) 1450 return r; 1451 } 1452 1453 /* unhalt the MEs */ 1454 sdma_v4_0_enable(adev, true); 1455 /* enable sdma ring preemption */ 1456 sdma_v4_0_ctx_switch_enable(adev, true); 1457 } 1458 1459 /* start the gfx rings and rlc compute queues */ 1460 for (i = 0; i < adev->sdma.num_instances; i++) { 1461 uint32_t temp; 1462 1463 WREG32_SDMA(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL, 0); 1464 sdma_v4_0_gfx_resume(adev, i); 1465 if (adev->sdma.has_page_queue) 1466 sdma_v4_0_page_resume(adev, i); 1467 1468 /* set utc l1 enable flag always to 1 */ 1469 temp = RREG32_SDMA(i, mmSDMA0_CNTL); 1470 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 1471 WREG32_SDMA(i, mmSDMA0_CNTL, temp); 1472 1473 if (!amdgpu_sriov_vf(adev)) { 1474 /* unhalt engine */ 1475 temp = RREG32_SDMA(i, mmSDMA0_F32_CNTL); 1476 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 1477 WREG32_SDMA(i, mmSDMA0_F32_CNTL, temp); 1478 } 1479 } 1480 1481 if (amdgpu_sriov_vf(adev)) { 1482 sdma_v4_0_ctx_switch_enable(adev, true); 1483 sdma_v4_0_enable(adev, true); 1484 } else { 1485 r = sdma_v4_0_rlc_resume(adev); 1486 if (r) 1487 return r; 1488 } 1489 1490 for (i = 0; i < adev->sdma.num_instances; i++) { 1491 ring = &adev->sdma.instance[i].ring; 1492 1493 r = amdgpu_ring_test_helper(ring); 1494 if (r) 1495 return r; 1496 1497 if (adev->sdma.has_page_queue) { 1498 struct amdgpu_ring *page = &adev->sdma.instance[i].page; 1499 1500 r = amdgpu_ring_test_helper(page); 1501 if (r) 1502 return r; 1503 1504 if (adev->mman.buffer_funcs_ring == page) 1505 amdgpu_ttm_set_buffer_funcs_status(adev, true); 1506 } 1507 1508 if (adev->mman.buffer_funcs_ring == ring) 1509 amdgpu_ttm_set_buffer_funcs_status(adev, true); 1510 } 1511 1512 return r; 1513 } 1514 1515 /** 1516 * sdma_v4_0_ring_test_ring - simple async dma engine test 1517 * 1518 * @ring: amdgpu_ring structure holding ring information 1519 * 1520 * Test the DMA engine by writing using it to write an 1521 * value to memory. (VEGA10). 1522 * Returns 0 for success, error for failure. 1523 */ 1524 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring) 1525 { 1526 struct amdgpu_device *adev = ring->adev; 1527 unsigned i; 1528 unsigned index; 1529 int r; 1530 u32 tmp; 1531 u64 gpu_addr; 1532 1533 r = amdgpu_device_wb_get(adev, &index); 1534 if (r) 1535 return r; 1536 1537 gpu_addr = adev->wb.gpu_addr + (index * 4); 1538 tmp = 0xCAFEDEAD; 1539 adev->wb.wb[index] = cpu_to_le32(tmp); 1540 1541 r = amdgpu_ring_alloc(ring, 5); 1542 if (r) 1543 goto error_free_wb; 1544 1545 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1546 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 1547 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 1548 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 1549 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 1550 amdgpu_ring_write(ring, 0xDEADBEEF); 1551 amdgpu_ring_commit(ring); 1552 1553 for (i = 0; i < adev->usec_timeout; i++) { 1554 tmp = le32_to_cpu(adev->wb.wb[index]); 1555 if (tmp == 0xDEADBEEF) 1556 break; 1557 udelay(1); 1558 } 1559 1560 if (i >= adev->usec_timeout) 1561 r = -ETIMEDOUT; 1562 1563 error_free_wb: 1564 amdgpu_device_wb_free(adev, index); 1565 return r; 1566 } 1567 1568 /** 1569 * sdma_v4_0_ring_test_ib - test an IB on the DMA engine 1570 * 1571 * @ring: amdgpu_ring structure holding ring information 1572 * 1573 * Test a simple IB in the DMA ring (VEGA10). 1574 * Returns 0 on success, error on failure. 1575 */ 1576 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1577 { 1578 struct amdgpu_device *adev = ring->adev; 1579 struct amdgpu_ib ib; 1580 struct dma_fence *f = NULL; 1581 unsigned index; 1582 long r; 1583 u32 tmp = 0; 1584 u64 gpu_addr; 1585 1586 r = amdgpu_device_wb_get(adev, &index); 1587 if (r) 1588 return r; 1589 1590 gpu_addr = adev->wb.gpu_addr + (index * 4); 1591 tmp = 0xCAFEDEAD; 1592 adev->wb.wb[index] = cpu_to_le32(tmp); 1593 memset(&ib, 0, sizeof(ib)); 1594 r = amdgpu_ib_get(adev, NULL, 256, 1595 AMDGPU_IB_POOL_DIRECT, &ib); 1596 if (r) 1597 goto err0; 1598 1599 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1600 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1601 ib.ptr[1] = lower_32_bits(gpu_addr); 1602 ib.ptr[2] = upper_32_bits(gpu_addr); 1603 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1604 ib.ptr[4] = 0xDEADBEEF; 1605 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1606 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1607 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1608 ib.length_dw = 8; 1609 1610 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1611 if (r) 1612 goto err1; 1613 1614 r = dma_fence_wait_timeout(f, false, timeout); 1615 if (r == 0) { 1616 r = -ETIMEDOUT; 1617 goto err1; 1618 } else if (r < 0) { 1619 goto err1; 1620 } 1621 tmp = le32_to_cpu(adev->wb.wb[index]); 1622 if (tmp == 0xDEADBEEF) 1623 r = 0; 1624 else 1625 r = -EINVAL; 1626 1627 err1: 1628 amdgpu_ib_free(adev, &ib, NULL); 1629 dma_fence_put(f); 1630 err0: 1631 amdgpu_device_wb_free(adev, index); 1632 return r; 1633 } 1634 1635 1636 /** 1637 * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART 1638 * 1639 * @ib: indirect buffer to fill with commands 1640 * @pe: addr of the page entry 1641 * @src: src addr to copy from 1642 * @count: number of page entries to update 1643 * 1644 * Update PTEs by copying them from the GART using sDMA (VEGA10). 1645 */ 1646 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib, 1647 uint64_t pe, uint64_t src, 1648 unsigned count) 1649 { 1650 unsigned bytes = count * 8; 1651 1652 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1653 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1654 ib->ptr[ib->length_dw++] = bytes - 1; 1655 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1656 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1657 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1658 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1659 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1660 1661 } 1662 1663 /** 1664 * sdma_v4_0_vm_write_pte - update PTEs by writing them manually 1665 * 1666 * @ib: indirect buffer to fill with commands 1667 * @pe: addr of the page entry 1668 * @addr: dst addr to write into pe 1669 * @count: number of page entries to update 1670 * @incr: increase next addr by incr bytes 1671 * @flags: access flags 1672 * 1673 * Update PTEs by writing them manually using sDMA (VEGA10). 1674 */ 1675 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1676 uint64_t value, unsigned count, 1677 uint32_t incr) 1678 { 1679 unsigned ndw = count * 2; 1680 1681 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1682 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1683 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1684 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1685 ib->ptr[ib->length_dw++] = ndw - 1; 1686 for (; ndw > 0; ndw -= 2) { 1687 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1688 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1689 value += incr; 1690 } 1691 } 1692 1693 /** 1694 * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA 1695 * 1696 * @ib: indirect buffer to fill with commands 1697 * @pe: addr of the page entry 1698 * @addr: dst addr to write into pe 1699 * @count: number of page entries to update 1700 * @incr: increase next addr by incr bytes 1701 * @flags: access flags 1702 * 1703 * Update the page tables using sDMA (VEGA10). 1704 */ 1705 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1706 uint64_t pe, 1707 uint64_t addr, unsigned count, 1708 uint32_t incr, uint64_t flags) 1709 { 1710 /* for physically contiguous pages (vram) */ 1711 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1712 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1713 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1714 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1715 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1716 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1717 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1718 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1719 ib->ptr[ib->length_dw++] = 0; 1720 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1721 } 1722 1723 /** 1724 * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw 1725 * 1726 * @ib: indirect buffer to fill with padding 1727 * 1728 */ 1729 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1730 { 1731 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1732 u32 pad_count; 1733 int i; 1734 1735 pad_count = (-ib->length_dw) & 7; 1736 for (i = 0; i < pad_count; i++) 1737 if (sdma && sdma->burst_nop && (i == 0)) 1738 ib->ptr[ib->length_dw++] = 1739 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1740 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1741 else 1742 ib->ptr[ib->length_dw++] = 1743 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1744 } 1745 1746 1747 /** 1748 * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline 1749 * 1750 * @ring: amdgpu_ring pointer 1751 * 1752 * Make sure all previous operations are completed (CIK). 1753 */ 1754 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1755 { 1756 uint32_t seq = ring->fence_drv.sync_seq; 1757 uint64_t addr = ring->fence_drv.gpu_addr; 1758 1759 /* wait for idle */ 1760 sdma_v4_0_wait_reg_mem(ring, 1, 0, 1761 addr & 0xfffffffc, 1762 upper_32_bits(addr) & 0xffffffff, 1763 seq, 0xffffffff, 4); 1764 } 1765 1766 1767 /** 1768 * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA 1769 * 1770 * @ring: amdgpu_ring pointer 1771 * @vm: amdgpu_vm pointer 1772 * 1773 * Update the page table base and flush the VM TLB 1774 * using sDMA (VEGA10). 1775 */ 1776 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1777 unsigned vmid, uint64_t pd_addr) 1778 { 1779 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1780 } 1781 1782 static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring, 1783 uint32_t reg, uint32_t val) 1784 { 1785 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1786 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1787 amdgpu_ring_write(ring, reg); 1788 amdgpu_ring_write(ring, val); 1789 } 1790 1791 static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1792 uint32_t val, uint32_t mask) 1793 { 1794 sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10); 1795 } 1796 1797 static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev) 1798 { 1799 uint fw_version = adev->sdma.instance[0].fw_version; 1800 1801 switch (adev->asic_type) { 1802 case CHIP_VEGA10: 1803 return fw_version >= 430; 1804 case CHIP_VEGA12: 1805 /*return fw_version >= 31;*/ 1806 return false; 1807 case CHIP_VEGA20: 1808 return fw_version >= 123; 1809 default: 1810 return false; 1811 } 1812 } 1813 1814 static int sdma_v4_0_early_init(void *handle) 1815 { 1816 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1817 int r; 1818 1819 if (adev->flags & AMD_IS_APU) 1820 adev->sdma.num_instances = 1; 1821 else if (adev->asic_type == CHIP_ARCTURUS) 1822 adev->sdma.num_instances = 8; 1823 else 1824 adev->sdma.num_instances = 2; 1825 1826 r = sdma_v4_0_init_microcode(adev); 1827 if (r) { 1828 DRM_ERROR("Failed to load sdma firmware!\n"); 1829 return r; 1830 } 1831 1832 /* TODO: Page queue breaks driver reload under SRIOV */ 1833 if ((adev->asic_type == CHIP_VEGA10) && amdgpu_sriov_vf((adev))) 1834 adev->sdma.has_page_queue = false; 1835 else if (sdma_v4_0_fw_support_paging_queue(adev)) 1836 adev->sdma.has_page_queue = true; 1837 1838 sdma_v4_0_set_ring_funcs(adev); 1839 sdma_v4_0_set_buffer_funcs(adev); 1840 sdma_v4_0_set_vm_pte_funcs(adev); 1841 sdma_v4_0_set_irq_funcs(adev); 1842 sdma_v4_0_set_ras_funcs(adev); 1843 1844 return 0; 1845 } 1846 1847 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev, 1848 void *err_data, 1849 struct amdgpu_iv_entry *entry); 1850 1851 static int sdma_v4_0_late_init(void *handle) 1852 { 1853 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1854 struct ras_ih_if ih_info = { 1855 .cb = sdma_v4_0_process_ras_data_cb, 1856 }; 1857 1858 sdma_v4_0_setup_ulv(adev); 1859 1860 if (adev->sdma.funcs && adev->sdma.funcs->reset_ras_error_count) 1861 adev->sdma.funcs->reset_ras_error_count(adev); 1862 1863 if (adev->sdma.funcs && adev->sdma.funcs->ras_late_init) 1864 return adev->sdma.funcs->ras_late_init(adev, &ih_info); 1865 else 1866 return 0; 1867 } 1868 1869 static int sdma_v4_0_sw_init(void *handle) 1870 { 1871 struct amdgpu_ring *ring; 1872 int r, i; 1873 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1874 1875 /* SDMA trap event */ 1876 for (i = 0; i < adev->sdma.num_instances; i++) { 1877 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1878 SDMA0_4_0__SRCID__SDMA_TRAP, 1879 &adev->sdma.trap_irq); 1880 if (r) 1881 return r; 1882 } 1883 1884 /* SDMA SRAM ECC event */ 1885 for (i = 0; i < adev->sdma.num_instances; i++) { 1886 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1887 SDMA0_4_0__SRCID__SDMA_SRAM_ECC, 1888 &adev->sdma.ecc_irq); 1889 if (r) 1890 return r; 1891 } 1892 1893 for (i = 0; i < adev->sdma.num_instances; i++) { 1894 ring = &adev->sdma.instance[i].ring; 1895 ring->ring_obj = NULL; 1896 ring->use_doorbell = true; 1897 1898 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1899 ring->use_doorbell?"true":"false"); 1900 1901 /* doorbell size is 2 dwords, get DWORD offset */ 1902 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1; 1903 1904 sprintf(ring->name, "sdma%d", i); 1905 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1906 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1907 AMDGPU_RING_PRIO_DEFAULT); 1908 if (r) 1909 return r; 1910 1911 if (adev->sdma.has_page_queue) { 1912 ring = &adev->sdma.instance[i].page; 1913 ring->ring_obj = NULL; 1914 ring->use_doorbell = true; 1915 1916 /* paging queue use same doorbell index/routing as gfx queue 1917 * with 0x400 (4096 dwords) offset on second doorbell page 1918 */ 1919 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1; 1920 ring->doorbell_index += 0x400; 1921 1922 sprintf(ring->name, "page%d", i); 1923 r = amdgpu_ring_init(adev, ring, 1024, 1924 &adev->sdma.trap_irq, 1925 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1926 AMDGPU_RING_PRIO_DEFAULT); 1927 if (r) 1928 return r; 1929 } 1930 } 1931 1932 return r; 1933 } 1934 1935 static int sdma_v4_0_sw_fini(void *handle) 1936 { 1937 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1938 int i; 1939 1940 if (adev->sdma.funcs && adev->sdma.funcs->ras_fini) 1941 adev->sdma.funcs->ras_fini(adev); 1942 1943 for (i = 0; i < adev->sdma.num_instances; i++) { 1944 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1945 if (adev->sdma.has_page_queue) 1946 amdgpu_ring_fini(&adev->sdma.instance[i].page); 1947 } 1948 1949 sdma_v4_0_destroy_inst_ctx(adev); 1950 1951 return 0; 1952 } 1953 1954 static int sdma_v4_0_hw_init(void *handle) 1955 { 1956 int r; 1957 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1958 1959 if (adev->flags & AMD_IS_APU) 1960 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false); 1961 1962 if (!amdgpu_sriov_vf(adev)) 1963 sdma_v4_0_init_golden_registers(adev); 1964 1965 r = sdma_v4_0_start(adev); 1966 1967 return r; 1968 } 1969 1970 static int sdma_v4_0_hw_fini(void *handle) 1971 { 1972 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1973 int i; 1974 1975 if (amdgpu_sriov_vf(adev)) 1976 return 0; 1977 1978 for (i = 0; i < adev->sdma.num_instances; i++) { 1979 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, 1980 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 1981 } 1982 1983 sdma_v4_0_ctx_switch_enable(adev, false); 1984 sdma_v4_0_enable(adev, false); 1985 1986 if (adev->flags & AMD_IS_APU) 1987 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true); 1988 1989 return 0; 1990 } 1991 1992 static int sdma_v4_0_suspend(void *handle) 1993 { 1994 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1995 1996 return sdma_v4_0_hw_fini(adev); 1997 } 1998 1999 static int sdma_v4_0_resume(void *handle) 2000 { 2001 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2002 2003 return sdma_v4_0_hw_init(adev); 2004 } 2005 2006 static bool sdma_v4_0_is_idle(void *handle) 2007 { 2008 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2009 u32 i; 2010 2011 for (i = 0; i < adev->sdma.num_instances; i++) { 2012 u32 tmp = RREG32_SDMA(i, mmSDMA0_STATUS_REG); 2013 2014 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 2015 return false; 2016 } 2017 2018 return true; 2019 } 2020 2021 static int sdma_v4_0_wait_for_idle(void *handle) 2022 { 2023 unsigned i, j; 2024 u32 sdma[AMDGPU_MAX_SDMA_INSTANCES]; 2025 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2026 2027 for (i = 0; i < adev->usec_timeout; i++) { 2028 for (j = 0; j < adev->sdma.num_instances; j++) { 2029 sdma[j] = RREG32_SDMA(j, mmSDMA0_STATUS_REG); 2030 if (!(sdma[j] & SDMA0_STATUS_REG__IDLE_MASK)) 2031 break; 2032 } 2033 if (j == adev->sdma.num_instances) 2034 return 0; 2035 udelay(1); 2036 } 2037 return -ETIMEDOUT; 2038 } 2039 2040 static int sdma_v4_0_soft_reset(void *handle) 2041 { 2042 /* todo */ 2043 2044 return 0; 2045 } 2046 2047 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev, 2048 struct amdgpu_irq_src *source, 2049 unsigned type, 2050 enum amdgpu_interrupt_state state) 2051 { 2052 u32 sdma_cntl; 2053 2054 sdma_cntl = RREG32_SDMA(type, mmSDMA0_CNTL); 2055 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 2056 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2057 WREG32_SDMA(type, mmSDMA0_CNTL, sdma_cntl); 2058 2059 return 0; 2060 } 2061 2062 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev, 2063 struct amdgpu_irq_src *source, 2064 struct amdgpu_iv_entry *entry) 2065 { 2066 uint32_t instance; 2067 2068 DRM_DEBUG("IH: SDMA trap\n"); 2069 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 2070 switch (entry->ring_id) { 2071 case 0: 2072 amdgpu_fence_process(&adev->sdma.instance[instance].ring); 2073 break; 2074 case 1: 2075 if (adev->asic_type == CHIP_VEGA20) 2076 amdgpu_fence_process(&adev->sdma.instance[instance].page); 2077 break; 2078 case 2: 2079 /* XXX compute */ 2080 break; 2081 case 3: 2082 if (adev->asic_type != CHIP_VEGA20) 2083 amdgpu_fence_process(&adev->sdma.instance[instance].page); 2084 break; 2085 } 2086 return 0; 2087 } 2088 2089 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev, 2090 void *err_data, 2091 struct amdgpu_iv_entry *entry) 2092 { 2093 int instance; 2094 2095 /* When “Full RAS” is enabled, the per-IP interrupt sources should 2096 * be disabled and the driver should only look for the aggregated 2097 * interrupt via sync flood 2098 */ 2099 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 2100 goto out; 2101 2102 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 2103 if (instance < 0) 2104 goto out; 2105 2106 amdgpu_sdma_process_ras_data_cb(adev, err_data, entry); 2107 2108 out: 2109 return AMDGPU_RAS_SUCCESS; 2110 } 2111 2112 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev, 2113 struct amdgpu_irq_src *source, 2114 struct amdgpu_iv_entry *entry) 2115 { 2116 int instance; 2117 2118 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 2119 2120 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 2121 if (instance < 0) 2122 return 0; 2123 2124 switch (entry->ring_id) { 2125 case 0: 2126 drm_sched_fault(&adev->sdma.instance[instance].ring.sched); 2127 break; 2128 } 2129 return 0; 2130 } 2131 2132 static int sdma_v4_0_set_ecc_irq_state(struct amdgpu_device *adev, 2133 struct amdgpu_irq_src *source, 2134 unsigned type, 2135 enum amdgpu_interrupt_state state) 2136 { 2137 u32 sdma_edc_config; 2138 2139 sdma_edc_config = RREG32_SDMA(type, mmSDMA0_EDC_CONFIG); 2140 sdma_edc_config = REG_SET_FIELD(sdma_edc_config, SDMA0_EDC_CONFIG, ECC_INT_ENABLE, 2141 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2142 WREG32_SDMA(type, mmSDMA0_EDC_CONFIG, sdma_edc_config); 2143 2144 return 0; 2145 } 2146 2147 static void sdma_v4_0_update_medium_grain_clock_gating( 2148 struct amdgpu_device *adev, 2149 bool enable) 2150 { 2151 uint32_t data, def; 2152 int i; 2153 2154 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 2155 for (i = 0; i < adev->sdma.num_instances; i++) { 2156 def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL); 2157 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 2158 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 2159 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 2160 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 2161 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 2162 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 2163 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 2164 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 2165 if (def != data) 2166 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data); 2167 } 2168 } else { 2169 for (i = 0; i < adev->sdma.num_instances; i++) { 2170 def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL); 2171 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 2172 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 2173 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 2174 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 2175 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 2176 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 2177 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 2178 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 2179 if (def != data) 2180 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data); 2181 } 2182 } 2183 } 2184 2185 2186 static void sdma_v4_0_update_medium_grain_light_sleep( 2187 struct amdgpu_device *adev, 2188 bool enable) 2189 { 2190 uint32_t data, def; 2191 int i; 2192 2193 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 2194 for (i = 0; i < adev->sdma.num_instances; i++) { 2195 /* 1-not override: enable sdma mem light sleep */ 2196 def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL); 2197 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 2198 if (def != data) 2199 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data); 2200 } 2201 } else { 2202 for (i = 0; i < adev->sdma.num_instances; i++) { 2203 /* 0-override:disable sdma mem light sleep */ 2204 def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL); 2205 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 2206 if (def != data) 2207 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data); 2208 } 2209 } 2210 } 2211 2212 static int sdma_v4_0_set_clockgating_state(void *handle, 2213 enum amd_clockgating_state state) 2214 { 2215 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2216 2217 if (amdgpu_sriov_vf(adev)) 2218 return 0; 2219 2220 switch (adev->asic_type) { 2221 case CHIP_VEGA10: 2222 case CHIP_VEGA12: 2223 case CHIP_VEGA20: 2224 case CHIP_RAVEN: 2225 case CHIP_ARCTURUS: 2226 case CHIP_RENOIR: 2227 sdma_v4_0_update_medium_grain_clock_gating(adev, 2228 state == AMD_CG_STATE_GATE); 2229 sdma_v4_0_update_medium_grain_light_sleep(adev, 2230 state == AMD_CG_STATE_GATE); 2231 break; 2232 default: 2233 break; 2234 } 2235 return 0; 2236 } 2237 2238 static int sdma_v4_0_set_powergating_state(void *handle, 2239 enum amd_powergating_state state) 2240 { 2241 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2242 2243 switch (adev->asic_type) { 2244 case CHIP_RAVEN: 2245 case CHIP_RENOIR: 2246 sdma_v4_1_update_power_gating(adev, 2247 state == AMD_PG_STATE_GATE ? true : false); 2248 break; 2249 default: 2250 break; 2251 } 2252 2253 return 0; 2254 } 2255 2256 static void sdma_v4_0_get_clockgating_state(void *handle, u32 *flags) 2257 { 2258 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2259 int data; 2260 2261 if (amdgpu_sriov_vf(adev)) 2262 *flags = 0; 2263 2264 /* AMD_CG_SUPPORT_SDMA_MGCG */ 2265 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 2266 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK)) 2267 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 2268 2269 /* AMD_CG_SUPPORT_SDMA_LS */ 2270 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 2271 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 2272 *flags |= AMD_CG_SUPPORT_SDMA_LS; 2273 } 2274 2275 const struct amd_ip_funcs sdma_v4_0_ip_funcs = { 2276 .name = "sdma_v4_0", 2277 .early_init = sdma_v4_0_early_init, 2278 .late_init = sdma_v4_0_late_init, 2279 .sw_init = sdma_v4_0_sw_init, 2280 .sw_fini = sdma_v4_0_sw_fini, 2281 .hw_init = sdma_v4_0_hw_init, 2282 .hw_fini = sdma_v4_0_hw_fini, 2283 .suspend = sdma_v4_0_suspend, 2284 .resume = sdma_v4_0_resume, 2285 .is_idle = sdma_v4_0_is_idle, 2286 .wait_for_idle = sdma_v4_0_wait_for_idle, 2287 .soft_reset = sdma_v4_0_soft_reset, 2288 .set_clockgating_state = sdma_v4_0_set_clockgating_state, 2289 .set_powergating_state = sdma_v4_0_set_powergating_state, 2290 .get_clockgating_state = sdma_v4_0_get_clockgating_state, 2291 }; 2292 2293 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = { 2294 .type = AMDGPU_RING_TYPE_SDMA, 2295 .align_mask = 0xf, 2296 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2297 .support_64bit_ptrs = true, 2298 .vmhub = AMDGPU_MMHUB_0, 2299 .get_rptr = sdma_v4_0_ring_get_rptr, 2300 .get_wptr = sdma_v4_0_ring_get_wptr, 2301 .set_wptr = sdma_v4_0_ring_set_wptr, 2302 .emit_frame_size = 2303 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2304 3 + /* hdp invalidate */ 2305 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2306 /* sdma_v4_0_ring_emit_vm_flush */ 2307 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2308 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2309 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2310 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2311 .emit_ib = sdma_v4_0_ring_emit_ib, 2312 .emit_fence = sdma_v4_0_ring_emit_fence, 2313 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2314 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2315 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2316 .test_ring = sdma_v4_0_ring_test_ring, 2317 .test_ib = sdma_v4_0_ring_test_ib, 2318 .insert_nop = sdma_v4_0_ring_insert_nop, 2319 .pad_ib = sdma_v4_0_ring_pad_ib, 2320 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2321 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2322 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2323 }; 2324 2325 /* 2326 * On Arcturus, SDMA instance 5~7 has a different vmhub type(AMDGPU_MMHUB_1). 2327 * So create a individual constant ring_funcs for those instances. 2328 */ 2329 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs_2nd_mmhub = { 2330 .type = AMDGPU_RING_TYPE_SDMA, 2331 .align_mask = 0xf, 2332 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2333 .support_64bit_ptrs = true, 2334 .vmhub = AMDGPU_MMHUB_1, 2335 .get_rptr = sdma_v4_0_ring_get_rptr, 2336 .get_wptr = sdma_v4_0_ring_get_wptr, 2337 .set_wptr = sdma_v4_0_ring_set_wptr, 2338 .emit_frame_size = 2339 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2340 3 + /* hdp invalidate */ 2341 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2342 /* sdma_v4_0_ring_emit_vm_flush */ 2343 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2344 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2345 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2346 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2347 .emit_ib = sdma_v4_0_ring_emit_ib, 2348 .emit_fence = sdma_v4_0_ring_emit_fence, 2349 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2350 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2351 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2352 .test_ring = sdma_v4_0_ring_test_ring, 2353 .test_ib = sdma_v4_0_ring_test_ib, 2354 .insert_nop = sdma_v4_0_ring_insert_nop, 2355 .pad_ib = sdma_v4_0_ring_pad_ib, 2356 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2357 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2358 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2359 }; 2360 2361 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = { 2362 .type = AMDGPU_RING_TYPE_SDMA, 2363 .align_mask = 0xf, 2364 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2365 .support_64bit_ptrs = true, 2366 .vmhub = AMDGPU_MMHUB_0, 2367 .get_rptr = sdma_v4_0_ring_get_rptr, 2368 .get_wptr = sdma_v4_0_page_ring_get_wptr, 2369 .set_wptr = sdma_v4_0_page_ring_set_wptr, 2370 .emit_frame_size = 2371 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2372 3 + /* hdp invalidate */ 2373 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2374 /* sdma_v4_0_ring_emit_vm_flush */ 2375 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2376 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2377 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2378 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2379 .emit_ib = sdma_v4_0_ring_emit_ib, 2380 .emit_fence = sdma_v4_0_ring_emit_fence, 2381 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2382 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2383 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2384 .test_ring = sdma_v4_0_ring_test_ring, 2385 .test_ib = sdma_v4_0_ring_test_ib, 2386 .insert_nop = sdma_v4_0_ring_insert_nop, 2387 .pad_ib = sdma_v4_0_ring_pad_ib, 2388 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2389 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2390 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2391 }; 2392 2393 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs_2nd_mmhub = { 2394 .type = AMDGPU_RING_TYPE_SDMA, 2395 .align_mask = 0xf, 2396 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2397 .support_64bit_ptrs = true, 2398 .vmhub = AMDGPU_MMHUB_1, 2399 .get_rptr = sdma_v4_0_ring_get_rptr, 2400 .get_wptr = sdma_v4_0_page_ring_get_wptr, 2401 .set_wptr = sdma_v4_0_page_ring_set_wptr, 2402 .emit_frame_size = 2403 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2404 3 + /* hdp invalidate */ 2405 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2406 /* sdma_v4_0_ring_emit_vm_flush */ 2407 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2408 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2409 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2410 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2411 .emit_ib = sdma_v4_0_ring_emit_ib, 2412 .emit_fence = sdma_v4_0_ring_emit_fence, 2413 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2414 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2415 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2416 .test_ring = sdma_v4_0_ring_test_ring, 2417 .test_ib = sdma_v4_0_ring_test_ib, 2418 .insert_nop = sdma_v4_0_ring_insert_nop, 2419 .pad_ib = sdma_v4_0_ring_pad_ib, 2420 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2421 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2422 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2423 }; 2424 2425 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev) 2426 { 2427 int i; 2428 2429 for (i = 0; i < adev->sdma.num_instances; i++) { 2430 if (adev->asic_type == CHIP_ARCTURUS && i >= 5) 2431 adev->sdma.instance[i].ring.funcs = 2432 &sdma_v4_0_ring_funcs_2nd_mmhub; 2433 else 2434 adev->sdma.instance[i].ring.funcs = 2435 &sdma_v4_0_ring_funcs; 2436 adev->sdma.instance[i].ring.me = i; 2437 if (adev->sdma.has_page_queue) { 2438 if (adev->asic_type == CHIP_ARCTURUS && i >= 5) 2439 adev->sdma.instance[i].page.funcs = 2440 &sdma_v4_0_page_ring_funcs_2nd_mmhub; 2441 else 2442 adev->sdma.instance[i].page.funcs = 2443 &sdma_v4_0_page_ring_funcs; 2444 adev->sdma.instance[i].page.me = i; 2445 } 2446 } 2447 } 2448 2449 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = { 2450 .set = sdma_v4_0_set_trap_irq_state, 2451 .process = sdma_v4_0_process_trap_irq, 2452 }; 2453 2454 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = { 2455 .process = sdma_v4_0_process_illegal_inst_irq, 2456 }; 2457 2458 static const struct amdgpu_irq_src_funcs sdma_v4_0_ecc_irq_funcs = { 2459 .set = sdma_v4_0_set_ecc_irq_state, 2460 .process = amdgpu_sdma_process_ecc_irq, 2461 }; 2462 2463 2464 2465 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev) 2466 { 2467 switch (adev->sdma.num_instances) { 2468 case 1: 2469 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1; 2470 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1; 2471 break; 2472 case 8: 2473 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 2474 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 2475 break; 2476 case 2: 2477 default: 2478 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2; 2479 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2; 2480 break; 2481 } 2482 adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs; 2483 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs; 2484 adev->sdma.ecc_irq.funcs = &sdma_v4_0_ecc_irq_funcs; 2485 } 2486 2487 /** 2488 * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine 2489 * 2490 * @ring: amdgpu_ring structure holding ring information 2491 * @src_offset: src GPU address 2492 * @dst_offset: dst GPU address 2493 * @byte_count: number of bytes to xfer 2494 * 2495 * Copy GPU buffers using the DMA engine (VEGA10/12). 2496 * Used by the amdgpu ttm implementation to move pages if 2497 * registered as the asic copy callback. 2498 */ 2499 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib, 2500 uint64_t src_offset, 2501 uint64_t dst_offset, 2502 uint32_t byte_count, 2503 bool tmz) 2504 { 2505 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 2506 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 2507 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0); 2508 ib->ptr[ib->length_dw++] = byte_count - 1; 2509 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 2510 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 2511 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 2512 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2513 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2514 } 2515 2516 /** 2517 * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine 2518 * 2519 * @ring: amdgpu_ring structure holding ring information 2520 * @src_data: value to write to buffer 2521 * @dst_offset: dst GPU address 2522 * @byte_count: number of bytes to xfer 2523 * 2524 * Fill GPU buffers using the DMA engine (VEGA10/12). 2525 */ 2526 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib, 2527 uint32_t src_data, 2528 uint64_t dst_offset, 2529 uint32_t byte_count) 2530 { 2531 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 2532 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2533 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2534 ib->ptr[ib->length_dw++] = src_data; 2535 ib->ptr[ib->length_dw++] = byte_count - 1; 2536 } 2537 2538 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = { 2539 .copy_max_bytes = 0x400000, 2540 .copy_num_dw = 7, 2541 .emit_copy_buffer = sdma_v4_0_emit_copy_buffer, 2542 2543 .fill_max_bytes = 0x400000, 2544 .fill_num_dw = 5, 2545 .emit_fill_buffer = sdma_v4_0_emit_fill_buffer, 2546 }; 2547 2548 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev) 2549 { 2550 adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs; 2551 if (adev->sdma.has_page_queue) 2552 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page; 2553 else 2554 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 2555 } 2556 2557 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = { 2558 .copy_pte_num_dw = 7, 2559 .copy_pte = sdma_v4_0_vm_copy_pte, 2560 2561 .write_pte = sdma_v4_0_vm_write_pte, 2562 .set_pte_pde = sdma_v4_0_vm_set_pte_pde, 2563 }; 2564 2565 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev) 2566 { 2567 struct drm_gpu_scheduler *sched; 2568 unsigned i; 2569 2570 adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs; 2571 for (i = 0; i < adev->sdma.num_instances; i++) { 2572 if (adev->sdma.has_page_queue) 2573 sched = &adev->sdma.instance[i].page.sched; 2574 else 2575 sched = &adev->sdma.instance[i].ring.sched; 2576 adev->vm_manager.vm_pte_scheds[i] = sched; 2577 } 2578 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 2579 } 2580 2581 static void sdma_v4_0_get_ras_error_count(uint32_t value, 2582 uint32_t instance, 2583 uint32_t *sec_count) 2584 { 2585 uint32_t i; 2586 uint32_t sec_cnt; 2587 2588 /* double bits error (multiple bits) error detection is not supported */ 2589 for (i = 0; i < ARRAY_SIZE(sdma_v4_0_ras_fields); i++) { 2590 /* the SDMA_EDC_COUNTER register in each sdma instance 2591 * shares the same sed shift_mask 2592 * */ 2593 sec_cnt = (value & 2594 sdma_v4_0_ras_fields[i].sec_count_mask) >> 2595 sdma_v4_0_ras_fields[i].sec_count_shift; 2596 if (sec_cnt) { 2597 DRM_INFO("Detected %s in SDMA%d, SED %d\n", 2598 sdma_v4_0_ras_fields[i].name, 2599 instance, sec_cnt); 2600 *sec_count += sec_cnt; 2601 } 2602 } 2603 } 2604 2605 static int sdma_v4_0_query_ras_error_count(struct amdgpu_device *adev, 2606 uint32_t instance, void *ras_error_status) 2607 { 2608 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 2609 uint32_t sec_count = 0; 2610 uint32_t reg_value = 0; 2611 2612 reg_value = RREG32_SDMA(instance, mmSDMA0_EDC_COUNTER); 2613 /* double bit error is not supported */ 2614 if (reg_value) 2615 sdma_v4_0_get_ras_error_count(reg_value, 2616 instance, &sec_count); 2617 /* err_data->ce_count should be initialized to 0 2618 * before calling into this function */ 2619 err_data->ce_count += sec_count; 2620 /* double bit error is not supported 2621 * set ue count to 0 */ 2622 err_data->ue_count = 0; 2623 2624 return 0; 2625 }; 2626 2627 static void sdma_v4_0_reset_ras_error_count(struct amdgpu_device *adev) 2628 { 2629 int i; 2630 2631 /* read back edc counter registers to clear the counters */ 2632 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 2633 for (i = 0; i < adev->sdma.num_instances; i++) 2634 RREG32_SDMA(i, mmSDMA0_EDC_COUNTER); 2635 } 2636 } 2637 2638 static const struct amdgpu_sdma_ras_funcs sdma_v4_0_ras_funcs = { 2639 .ras_late_init = amdgpu_sdma_ras_late_init, 2640 .ras_fini = amdgpu_sdma_ras_fini, 2641 .query_ras_error_count = sdma_v4_0_query_ras_error_count, 2642 .reset_ras_error_count = sdma_v4_0_reset_ras_error_count, 2643 }; 2644 2645 static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev) 2646 { 2647 switch (adev->asic_type) { 2648 case CHIP_VEGA20: 2649 case CHIP_ARCTURUS: 2650 adev->sdma.funcs = &sdma_v4_0_ras_funcs; 2651 break; 2652 default: 2653 break; 2654 } 2655 } 2656 2657 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = { 2658 .type = AMD_IP_BLOCK_TYPE_SDMA, 2659 .major = 4, 2660 .minor = 0, 2661 .rev = 0, 2662 .funcs = &sdma_v4_0_ip_funcs, 2663 }; 2664