1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "sdma0/sdma0_4_2_offset.h" 34 #include "sdma0/sdma0_4_2_sh_mask.h" 35 #include "sdma1/sdma1_4_2_offset.h" 36 #include "sdma1/sdma1_4_2_sh_mask.h" 37 #include "sdma2/sdma2_4_2_2_offset.h" 38 #include "sdma2/sdma2_4_2_2_sh_mask.h" 39 #include "sdma3/sdma3_4_2_2_offset.h" 40 #include "sdma3/sdma3_4_2_2_sh_mask.h" 41 #include "sdma4/sdma4_4_2_2_offset.h" 42 #include "sdma4/sdma4_4_2_2_sh_mask.h" 43 #include "sdma5/sdma5_4_2_2_offset.h" 44 #include "sdma5/sdma5_4_2_2_sh_mask.h" 45 #include "sdma6/sdma6_4_2_2_offset.h" 46 #include "sdma6/sdma6_4_2_2_sh_mask.h" 47 #include "sdma7/sdma7_4_2_2_offset.h" 48 #include "sdma7/sdma7_4_2_2_sh_mask.h" 49 #include "sdma0/sdma0_4_1_default.h" 50 51 #include "soc15_common.h" 52 #include "soc15.h" 53 #include "vega10_sdma_pkt_open.h" 54 55 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h" 56 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h" 57 58 #include "amdgpu_ras.h" 59 #include "sdma_v4_4.h" 60 61 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin"); 62 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin"); 63 MODULE_FIRMWARE("amdgpu/vega12_sdma.bin"); 64 MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin"); 65 MODULE_FIRMWARE("amdgpu/vega20_sdma.bin"); 66 MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin"); 67 MODULE_FIRMWARE("amdgpu/raven_sdma.bin"); 68 MODULE_FIRMWARE("amdgpu/picasso_sdma.bin"); 69 MODULE_FIRMWARE("amdgpu/raven2_sdma.bin"); 70 MODULE_FIRMWARE("amdgpu/arcturus_sdma.bin"); 71 MODULE_FIRMWARE("amdgpu/renoir_sdma.bin"); 72 MODULE_FIRMWARE("amdgpu/green_sardine_sdma.bin"); 73 MODULE_FIRMWARE("amdgpu/aldebaran_sdma.bin"); 74 75 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L 76 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L 77 78 #define WREG32_SDMA(instance, offset, value) \ 79 WREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)), value) 80 #define RREG32_SDMA(instance, offset) \ 81 RREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset))) 82 83 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev); 84 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev); 85 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev); 86 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev); 87 static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev); 88 89 static const struct soc15_reg_golden golden_settings_sdma_4[] = { 90 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 91 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100), 92 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100), 93 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 94 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 95 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 96 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000), 97 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 98 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 99 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 100 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 101 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 102 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000), 103 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), 104 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100), 105 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 106 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 107 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 108 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000), 109 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 110 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 111 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 112 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 113 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0), 114 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xfc000000, 0x00000000) 115 }; 116 117 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = { 118 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 119 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 120 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 121 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 122 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 123 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 124 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 125 }; 126 127 static const struct soc15_reg_golden golden_settings_sdma_vg12[] = { 128 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), 129 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001), 130 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 131 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 132 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), 133 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001), 134 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 135 }; 136 137 static const struct soc15_reg_golden golden_settings_sdma_4_1[] = { 138 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 139 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 140 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100), 141 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 142 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051), 143 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100), 144 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 145 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100), 146 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 147 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003e0), 148 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000) 149 }; 150 151 static const struct soc15_reg_golden golden_settings_sdma0_4_2_init[] = { 152 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 153 }; 154 155 static const struct soc15_reg_golden golden_settings_sdma0_4_2[] = 156 { 157 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 158 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 159 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 160 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 161 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 162 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 163 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 164 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 165 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RD_BURST_CNTL, 0x0000000f, 0x00000003), 166 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 167 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 168 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 169 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 170 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 171 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 172 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 173 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 174 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 175 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 176 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 177 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 178 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 179 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 180 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 181 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 182 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 183 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 184 }; 185 186 static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = { 187 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 188 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), 189 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 190 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 191 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 192 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 193 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 194 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 195 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RD_BURST_CNTL, 0x0000000f, 0x00000003), 196 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 197 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 198 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 199 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 200 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 201 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 202 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 203 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 204 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 205 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 206 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 207 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 208 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 209 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 210 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 211 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 212 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0), 213 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 214 }; 215 216 static const struct soc15_reg_golden golden_settings_sdma_rv1[] = 217 { 218 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002), 219 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002) 220 }; 221 222 static const struct soc15_reg_golden golden_settings_sdma_rv2[] = 223 { 224 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00003001), 225 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003001) 226 }; 227 228 static const struct soc15_reg_golden golden_settings_sdma_arct[] = 229 { 230 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 231 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 232 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 233 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 234 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 235 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 236 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 237 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 238 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 239 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 240 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 241 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 242 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 243 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 244 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 245 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 246 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 247 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 248 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 249 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 250 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 251 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 252 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 253 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 254 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 255 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 256 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 257 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 258 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 259 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 260 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 261 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_UTCL1_TIMEOUT, 0xffffffff, 0x00010001) 262 }; 263 264 static const struct soc15_reg_golden golden_settings_sdma_aldebaran[] = { 265 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 266 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 267 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 268 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 269 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 270 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 271 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 272 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 273 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA2_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 274 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 275 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 276 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 277 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 278 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 279 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 280 }; 281 282 static const struct soc15_reg_golden golden_settings_sdma_4_3[] = { 283 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 284 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 285 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002), 286 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002), 287 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 288 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003fff07, 0x40000051), 289 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 290 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 291 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003e0), 292 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x03fbe1fe) 293 }; 294 295 static const struct soc15_ras_field_entry sdma_v4_0_ras_fields[] = { 296 { "SDMA_UCODE_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 297 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UCODE_BUF_SED), 298 0, 0, 299 }, 300 { "SDMA_RB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 301 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_RB_CMD_BUF_SED), 302 0, 0, 303 }, 304 { "SDMA_IB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 305 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_IB_CMD_BUF_SED), 306 0, 0, 307 }, 308 { "SDMA_UTCL1_RD_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 309 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UTCL1_RD_FIFO_SED), 310 0, 0, 311 }, 312 { "SDMA_UTCL1_RDBST_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 313 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UTCL1_RDBST_FIFO_SED), 314 0, 0, 315 }, 316 { "SDMA_DATA_LUT_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 317 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_DATA_LUT_FIFO_SED), 318 0, 0, 319 }, 320 { "SDMA_MBANK_DATA_BUF0_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 321 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF0_SED), 322 0, 0, 323 }, 324 { "SDMA_MBANK_DATA_BUF1_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 325 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF1_SED), 326 0, 0, 327 }, 328 { "SDMA_MBANK_DATA_BUF2_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 329 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF2_SED), 330 0, 0, 331 }, 332 { "SDMA_MBANK_DATA_BUF3_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 333 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF3_SED), 334 0, 0, 335 }, 336 { "SDMA_MBANK_DATA_BUF4_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 337 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF4_SED), 338 0, 0, 339 }, 340 { "SDMA_MBANK_DATA_BUF5_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 341 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF5_SED), 342 0, 0, 343 }, 344 { "SDMA_MBANK_DATA_BUF6_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 345 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF6_SED), 346 0, 0, 347 }, 348 { "SDMA_MBANK_DATA_BUF7_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 349 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF7_SED), 350 0, 0, 351 }, 352 { "SDMA_MBANK_DATA_BUF8_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 353 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF8_SED), 354 0, 0, 355 }, 356 { "SDMA_MBANK_DATA_BUF9_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 357 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF9_SED), 358 0, 0, 359 }, 360 { "SDMA_MBANK_DATA_BUF10_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 361 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF10_SED), 362 0, 0, 363 }, 364 { "SDMA_MBANK_DATA_BUF11_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 365 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF11_SED), 366 0, 0, 367 }, 368 { "SDMA_MBANK_DATA_BUF12_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 369 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF12_SED), 370 0, 0, 371 }, 372 { "SDMA_MBANK_DATA_BUF13_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 373 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF13_SED), 374 0, 0, 375 }, 376 { "SDMA_MBANK_DATA_BUF14_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 377 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF14_SED), 378 0, 0, 379 }, 380 { "SDMA_MBANK_DATA_BUF15_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 381 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF15_SED), 382 0, 0, 383 }, 384 { "SDMA_SPLIT_DAT_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 385 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_SPLIT_DAT_BUF_SED), 386 0, 0, 387 }, 388 { "SDMA_MC_WR_ADDR_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 389 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MC_WR_ADDR_FIFO_SED), 390 0, 0, 391 }, 392 }; 393 394 static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev, 395 u32 instance, u32 offset) 396 { 397 switch (instance) { 398 case 0: 399 return (adev->reg_offset[SDMA0_HWIP][0][0] + offset); 400 case 1: 401 return (adev->reg_offset[SDMA1_HWIP][0][0] + offset); 402 case 2: 403 return (adev->reg_offset[SDMA2_HWIP][0][1] + offset); 404 case 3: 405 return (adev->reg_offset[SDMA3_HWIP][0][1] + offset); 406 case 4: 407 return (adev->reg_offset[SDMA4_HWIP][0][1] + offset); 408 case 5: 409 return (adev->reg_offset[SDMA5_HWIP][0][1] + offset); 410 case 6: 411 return (adev->reg_offset[SDMA6_HWIP][0][1] + offset); 412 case 7: 413 return (adev->reg_offset[SDMA7_HWIP][0][1] + offset); 414 default: 415 break; 416 } 417 return 0; 418 } 419 420 static unsigned sdma_v4_0_seq_to_irq_id(int seq_num) 421 { 422 switch (seq_num) { 423 case 0: 424 return SOC15_IH_CLIENTID_SDMA0; 425 case 1: 426 return SOC15_IH_CLIENTID_SDMA1; 427 case 2: 428 return SOC15_IH_CLIENTID_SDMA2; 429 case 3: 430 return SOC15_IH_CLIENTID_SDMA3; 431 case 4: 432 return SOC15_IH_CLIENTID_SDMA4; 433 case 5: 434 return SOC15_IH_CLIENTID_SDMA5; 435 case 6: 436 return SOC15_IH_CLIENTID_SDMA6; 437 case 7: 438 return SOC15_IH_CLIENTID_SDMA7; 439 default: 440 break; 441 } 442 return -EINVAL; 443 } 444 445 static int sdma_v4_0_irq_id_to_seq(unsigned client_id) 446 { 447 switch (client_id) { 448 case SOC15_IH_CLIENTID_SDMA0: 449 return 0; 450 case SOC15_IH_CLIENTID_SDMA1: 451 return 1; 452 case SOC15_IH_CLIENTID_SDMA2: 453 return 2; 454 case SOC15_IH_CLIENTID_SDMA3: 455 return 3; 456 case SOC15_IH_CLIENTID_SDMA4: 457 return 4; 458 case SOC15_IH_CLIENTID_SDMA5: 459 return 5; 460 case SOC15_IH_CLIENTID_SDMA6: 461 return 6; 462 case SOC15_IH_CLIENTID_SDMA7: 463 return 7; 464 default: 465 break; 466 } 467 return -EINVAL; 468 } 469 470 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) 471 { 472 switch (adev->ip_versions[SDMA0_HWIP][0]) { 473 case IP_VERSION(4, 0, 0): 474 soc15_program_register_sequence(adev, 475 golden_settings_sdma_4, 476 ARRAY_SIZE(golden_settings_sdma_4)); 477 soc15_program_register_sequence(adev, 478 golden_settings_sdma_vg10, 479 ARRAY_SIZE(golden_settings_sdma_vg10)); 480 break; 481 case IP_VERSION(4, 0, 1): 482 soc15_program_register_sequence(adev, 483 golden_settings_sdma_4, 484 ARRAY_SIZE(golden_settings_sdma_4)); 485 soc15_program_register_sequence(adev, 486 golden_settings_sdma_vg12, 487 ARRAY_SIZE(golden_settings_sdma_vg12)); 488 break; 489 case IP_VERSION(4, 2, 0): 490 soc15_program_register_sequence(adev, 491 golden_settings_sdma0_4_2_init, 492 ARRAY_SIZE(golden_settings_sdma0_4_2_init)); 493 soc15_program_register_sequence(adev, 494 golden_settings_sdma0_4_2, 495 ARRAY_SIZE(golden_settings_sdma0_4_2)); 496 soc15_program_register_sequence(adev, 497 golden_settings_sdma1_4_2, 498 ARRAY_SIZE(golden_settings_sdma1_4_2)); 499 break; 500 case IP_VERSION(4, 2, 2): 501 soc15_program_register_sequence(adev, 502 golden_settings_sdma_arct, 503 ARRAY_SIZE(golden_settings_sdma_arct)); 504 break; 505 case IP_VERSION(4, 4, 0): 506 soc15_program_register_sequence(adev, 507 golden_settings_sdma_aldebaran, 508 ARRAY_SIZE(golden_settings_sdma_aldebaran)); 509 break; 510 case IP_VERSION(4, 1, 0): 511 case IP_VERSION(4, 1, 1): 512 soc15_program_register_sequence(adev, 513 golden_settings_sdma_4_1, 514 ARRAY_SIZE(golden_settings_sdma_4_1)); 515 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 516 soc15_program_register_sequence(adev, 517 golden_settings_sdma_rv2, 518 ARRAY_SIZE(golden_settings_sdma_rv2)); 519 else 520 soc15_program_register_sequence(adev, 521 golden_settings_sdma_rv1, 522 ARRAY_SIZE(golden_settings_sdma_rv1)); 523 break; 524 case IP_VERSION(4, 1, 2): 525 soc15_program_register_sequence(adev, 526 golden_settings_sdma_4_3, 527 ARRAY_SIZE(golden_settings_sdma_4_3)); 528 break; 529 default: 530 break; 531 } 532 } 533 534 static void sdma_v4_0_setup_ulv(struct amdgpu_device *adev) 535 { 536 int i; 537 538 /* 539 * The only chips with SDMAv4 and ULV are VG10 and VG20. 540 * Server SKUs take a different hysteresis setting from other SKUs. 541 */ 542 switch (adev->ip_versions[SDMA0_HWIP][0]) { 543 case IP_VERSION(4, 0, 0): 544 if (adev->pdev->device == 0x6860) 545 break; 546 return; 547 case IP_VERSION(4, 2, 0): 548 if (adev->pdev->device == 0x66a1) 549 break; 550 return; 551 default: 552 return; 553 } 554 555 for (i = 0; i < adev->sdma.num_instances; i++) { 556 uint32_t temp; 557 558 temp = RREG32_SDMA(i, mmSDMA0_ULV_CNTL); 559 temp = REG_SET_FIELD(temp, SDMA0_ULV_CNTL, HYSTERESIS, 0x0); 560 WREG32_SDMA(i, mmSDMA0_ULV_CNTL, temp); 561 } 562 } 563 564 static int sdma_v4_0_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst) 565 { 566 int err = 0; 567 const struct sdma_firmware_header_v1_0 *hdr; 568 569 err = amdgpu_ucode_validate(sdma_inst->fw); 570 if (err) 571 return err; 572 573 hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data; 574 sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version); 575 sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version); 576 577 if (sdma_inst->feature_version >= 20) 578 sdma_inst->burst_nop = true; 579 580 return 0; 581 } 582 583 static void sdma_v4_0_destroy_inst_ctx(struct amdgpu_device *adev) 584 { 585 int i; 586 587 for (i = 0; i < adev->sdma.num_instances; i++) { 588 release_firmware(adev->sdma.instance[i].fw); 589 adev->sdma.instance[i].fw = NULL; 590 591 /* arcturus shares the same FW memory across 592 all SDMA isntances */ 593 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) || 594 adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 0)) 595 break; 596 } 597 598 memset((void *)adev->sdma.instance, 0, 599 sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES); 600 } 601 602 /** 603 * sdma_v4_0_init_microcode - load ucode images from disk 604 * 605 * @adev: amdgpu_device pointer 606 * 607 * Use the firmware interface to load the ucode images into 608 * the driver (not loaded into hw). 609 * Returns 0 on success, error on failure. 610 */ 611 612 // emulation only, won't work on real chip 613 // vega10 real chip need to use PSP to load firmware 614 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev) 615 { 616 const char *chip_name; 617 char fw_name[30]; 618 int err = 0, i; 619 struct amdgpu_firmware_info *info = NULL; 620 const struct common_firmware_header *header = NULL; 621 622 DRM_DEBUG("\n"); 623 624 switch (adev->ip_versions[SDMA0_HWIP][0]) { 625 case IP_VERSION(4, 0, 0): 626 chip_name = "vega10"; 627 break; 628 case IP_VERSION(4, 0, 1): 629 chip_name = "vega12"; 630 break; 631 case IP_VERSION(4, 2, 0): 632 chip_name = "vega20"; 633 break; 634 case IP_VERSION(4, 1, 0): 635 case IP_VERSION(4, 1, 1): 636 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 637 chip_name = "raven2"; 638 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 639 chip_name = "picasso"; 640 else 641 chip_name = "raven"; 642 break; 643 case IP_VERSION(4, 2, 2): 644 chip_name = "arcturus"; 645 break; 646 case IP_VERSION(4, 1, 2): 647 if (adev->apu_flags & AMD_APU_IS_RENOIR) 648 chip_name = "renoir"; 649 else 650 chip_name = "green_sardine"; 651 break; 652 case IP_VERSION(4, 4, 0): 653 chip_name = "aldebaran"; 654 break; 655 default: 656 BUG(); 657 } 658 659 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 660 661 err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev); 662 if (err) 663 goto out; 664 665 err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[0]); 666 if (err) 667 goto out; 668 669 for (i = 1; i < adev->sdma.num_instances; i++) { 670 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) || 671 adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 0)) { 672 /* Acturus & Aldebaran will leverage the same FW memory 673 for every SDMA instance */ 674 memcpy((void *)&adev->sdma.instance[i], 675 (void *)&adev->sdma.instance[0], 676 sizeof(struct amdgpu_sdma_instance)); 677 } 678 else { 679 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i); 680 681 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 682 if (err) 683 goto out; 684 685 err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[i]); 686 if (err) 687 goto out; 688 } 689 } 690 691 DRM_DEBUG("psp_load == '%s'\n", 692 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); 693 694 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 695 for (i = 0; i < adev->sdma.num_instances; i++) { 696 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 697 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 698 info->fw = adev->sdma.instance[i].fw; 699 header = (const struct common_firmware_header *)info->fw->data; 700 adev->firmware.fw_size += 701 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 702 } 703 } 704 705 out: 706 if (err) { 707 DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name); 708 sdma_v4_0_destroy_inst_ctx(adev); 709 } 710 return err; 711 } 712 713 /** 714 * sdma_v4_0_ring_get_rptr - get the current read pointer 715 * 716 * @ring: amdgpu ring pointer 717 * 718 * Get the current rptr from the hardware (VEGA10+). 719 */ 720 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring) 721 { 722 u64 *rptr; 723 724 /* XXX check if swapping is necessary on BE */ 725 rptr = ((u64 *)ring->rptr_cpu_addr); 726 727 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 728 return ((*rptr) >> 2); 729 } 730 731 /** 732 * sdma_v4_0_ring_get_wptr - get the current write pointer 733 * 734 * @ring: amdgpu ring pointer 735 * 736 * Get the current wptr from the hardware (VEGA10+). 737 */ 738 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring) 739 { 740 struct amdgpu_device *adev = ring->adev; 741 u64 wptr; 742 743 if (ring->use_doorbell) { 744 /* XXX check if swapping is necessary on BE */ 745 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); 746 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 747 } else { 748 wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI); 749 wptr = wptr << 32; 750 wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR); 751 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", 752 ring->me, wptr); 753 } 754 755 return wptr >> 2; 756 } 757 758 /** 759 * sdma_v4_0_ring_set_wptr - commit the write pointer 760 * 761 * @ring: amdgpu ring pointer 762 * 763 * Write the wptr back to the hardware (VEGA10+). 764 */ 765 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring) 766 { 767 struct amdgpu_device *adev = ring->adev; 768 769 DRM_DEBUG("Setting write pointer\n"); 770 if (ring->use_doorbell) { 771 u64 *wb = (u64 *)ring->wptr_cpu_addr; 772 773 DRM_DEBUG("Using doorbell -- " 774 "wptr_offs == 0x%08x " 775 "lower_32_bits(ring->wptr << 2) == 0x%08x " 776 "upper_32_bits(ring->wptr << 2) == 0x%08x\n", 777 ring->wptr_offs, 778 lower_32_bits(ring->wptr << 2), 779 upper_32_bits(ring->wptr << 2)); 780 /* XXX check if swapping is necessary on BE */ 781 WRITE_ONCE(*wb, (ring->wptr << 2)); 782 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 783 ring->doorbell_index, ring->wptr << 2); 784 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 785 } else { 786 DRM_DEBUG("Not using doorbell -- " 787 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 788 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 789 ring->me, 790 lower_32_bits(ring->wptr << 2), 791 ring->me, 792 upper_32_bits(ring->wptr << 2)); 793 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR, 794 lower_32_bits(ring->wptr << 2)); 795 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI, 796 upper_32_bits(ring->wptr << 2)); 797 } 798 } 799 800 /** 801 * sdma_v4_0_page_ring_get_wptr - get the current write pointer 802 * 803 * @ring: amdgpu ring pointer 804 * 805 * Get the current wptr from the hardware (VEGA10+). 806 */ 807 static uint64_t sdma_v4_0_page_ring_get_wptr(struct amdgpu_ring *ring) 808 { 809 struct amdgpu_device *adev = ring->adev; 810 u64 wptr; 811 812 if (ring->use_doorbell) { 813 /* XXX check if swapping is necessary on BE */ 814 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); 815 } else { 816 wptr = RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI); 817 wptr = wptr << 32; 818 wptr |= RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR); 819 } 820 821 return wptr >> 2; 822 } 823 824 /** 825 * sdma_v4_0_page_ring_set_wptr - commit the write pointer 826 * 827 * @ring: amdgpu ring pointer 828 * 829 * Write the wptr back to the hardware (VEGA10+). 830 */ 831 static void sdma_v4_0_page_ring_set_wptr(struct amdgpu_ring *ring) 832 { 833 struct amdgpu_device *adev = ring->adev; 834 835 if (ring->use_doorbell) { 836 u64 *wb = (u64 *)ring->wptr_cpu_addr; 837 838 /* XXX check if swapping is necessary on BE */ 839 WRITE_ONCE(*wb, (ring->wptr << 2)); 840 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 841 } else { 842 uint64_t wptr = ring->wptr << 2; 843 844 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR, 845 lower_32_bits(wptr)); 846 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI, 847 upper_32_bits(wptr)); 848 } 849 } 850 851 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 852 { 853 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 854 int i; 855 856 for (i = 0; i < count; i++) 857 if (sdma && sdma->burst_nop && (i == 0)) 858 amdgpu_ring_write(ring, ring->funcs->nop | 859 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 860 else 861 amdgpu_ring_write(ring, ring->funcs->nop); 862 } 863 864 /** 865 * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine 866 * 867 * @ring: amdgpu ring pointer 868 * @job: job to retrieve vmid from 869 * @ib: IB object to schedule 870 * @flags: unused 871 * 872 * Schedule an IB in the DMA ring (VEGA10). 873 */ 874 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring, 875 struct amdgpu_job *job, 876 struct amdgpu_ib *ib, 877 uint32_t flags) 878 { 879 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 880 881 /* IB packet must end on a 8 DW boundary */ 882 sdma_v4_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 883 884 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 885 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 886 /* base must be 32 byte aligned */ 887 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 888 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 889 amdgpu_ring_write(ring, ib->length_dw); 890 amdgpu_ring_write(ring, 0); 891 amdgpu_ring_write(ring, 0); 892 893 } 894 895 static void sdma_v4_0_wait_reg_mem(struct amdgpu_ring *ring, 896 int mem_space, int hdp, 897 uint32_t addr0, uint32_t addr1, 898 uint32_t ref, uint32_t mask, 899 uint32_t inv) 900 { 901 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 902 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) | 903 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) | 904 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 905 if (mem_space) { 906 /* memory */ 907 amdgpu_ring_write(ring, addr0); 908 amdgpu_ring_write(ring, addr1); 909 } else { 910 /* registers */ 911 amdgpu_ring_write(ring, addr0 << 2); 912 amdgpu_ring_write(ring, addr1 << 2); 913 } 914 amdgpu_ring_write(ring, ref); /* reference */ 915 amdgpu_ring_write(ring, mask); /* mask */ 916 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 917 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */ 918 } 919 920 /** 921 * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 922 * 923 * @ring: amdgpu ring pointer 924 * 925 * Emit an hdp flush packet on the requested DMA ring. 926 */ 927 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 928 { 929 struct amdgpu_device *adev = ring->adev; 930 u32 ref_and_mask = 0; 931 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 932 933 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; 934 935 sdma_v4_0_wait_reg_mem(ring, 0, 1, 936 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 937 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 938 ref_and_mask, ref_and_mask, 10); 939 } 940 941 /** 942 * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring 943 * 944 * @ring: amdgpu ring pointer 945 * @addr: address 946 * @seq: sequence number 947 * @flags: fence related flags 948 * 949 * Add a DMA fence packet to the ring to write 950 * the fence seq number and DMA trap packet to generate 951 * an interrupt if needed (VEGA10). 952 */ 953 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 954 unsigned flags) 955 { 956 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 957 /* write the fence */ 958 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 959 /* zero in first two bits */ 960 BUG_ON(addr & 0x3); 961 amdgpu_ring_write(ring, lower_32_bits(addr)); 962 amdgpu_ring_write(ring, upper_32_bits(addr)); 963 amdgpu_ring_write(ring, lower_32_bits(seq)); 964 965 /* optionally write high bits as well */ 966 if (write64bit) { 967 addr += 4; 968 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 969 /* zero in first two bits */ 970 BUG_ON(addr & 0x3); 971 amdgpu_ring_write(ring, lower_32_bits(addr)); 972 amdgpu_ring_write(ring, upper_32_bits(addr)); 973 amdgpu_ring_write(ring, upper_32_bits(seq)); 974 } 975 976 /* generate an interrupt */ 977 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 978 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 979 } 980 981 982 /** 983 * sdma_v4_0_gfx_stop - stop the gfx async dma engines 984 * 985 * @adev: amdgpu_device pointer 986 * 987 * Stop the gfx async dma ring buffers (VEGA10). 988 */ 989 static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev) 990 { 991 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; 992 u32 rb_cntl, ib_cntl; 993 int i, unset = 0; 994 995 for (i = 0; i < adev->sdma.num_instances; i++) { 996 sdma[i] = &adev->sdma.instance[i].ring; 997 998 if ((adev->mman.buffer_funcs_ring == sdma[i]) && unset != 1) { 999 amdgpu_ttm_set_buffer_funcs_status(adev, false); 1000 unset = 1; 1001 } 1002 1003 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL); 1004 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 1005 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 1006 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL); 1007 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 1008 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl); 1009 } 1010 } 1011 1012 /** 1013 * sdma_v4_0_rlc_stop - stop the compute async dma engines 1014 * 1015 * @adev: amdgpu_device pointer 1016 * 1017 * Stop the compute async dma queues (VEGA10). 1018 */ 1019 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev) 1020 { 1021 /* XXX todo */ 1022 } 1023 1024 /** 1025 * sdma_v4_0_page_stop - stop the page async dma engines 1026 * 1027 * @adev: amdgpu_device pointer 1028 * 1029 * Stop the page async dma ring buffers (VEGA10). 1030 */ 1031 static void sdma_v4_0_page_stop(struct amdgpu_device *adev) 1032 { 1033 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; 1034 u32 rb_cntl, ib_cntl; 1035 int i; 1036 bool unset = false; 1037 1038 for (i = 0; i < adev->sdma.num_instances; i++) { 1039 sdma[i] = &adev->sdma.instance[i].page; 1040 1041 if ((adev->mman.buffer_funcs_ring == sdma[i]) && 1042 (!unset)) { 1043 amdgpu_ttm_set_buffer_funcs_status(adev, false); 1044 unset = true; 1045 } 1046 1047 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL); 1048 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, 1049 RB_ENABLE, 0); 1050 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 1051 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL); 1052 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, 1053 IB_ENABLE, 0); 1054 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl); 1055 } 1056 } 1057 1058 /** 1059 * sdma_v4_0_ctx_switch_enable - stop the async dma engines context switch 1060 * 1061 * @adev: amdgpu_device pointer 1062 * @enable: enable/disable the DMA MEs context switch. 1063 * 1064 * Halt or unhalt the async dma engines context switch (VEGA10). 1065 */ 1066 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 1067 { 1068 u32 f32_cntl, phase_quantum = 0; 1069 int i; 1070 1071 if (amdgpu_sdma_phase_quantum) { 1072 unsigned value = amdgpu_sdma_phase_quantum; 1073 unsigned unit = 0; 1074 1075 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 1076 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 1077 value = (value + 1) >> 1; 1078 unit++; 1079 } 1080 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 1081 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 1082 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 1083 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 1084 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 1085 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 1086 WARN_ONCE(1, 1087 "clamping sdma_phase_quantum to %uK clock cycles\n", 1088 value << unit); 1089 } 1090 phase_quantum = 1091 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 1092 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 1093 } 1094 1095 for (i = 0; i < adev->sdma.num_instances; i++) { 1096 f32_cntl = RREG32_SDMA(i, mmSDMA0_CNTL); 1097 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 1098 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 1099 if (enable && amdgpu_sdma_phase_quantum) { 1100 WREG32_SDMA(i, mmSDMA0_PHASE0_QUANTUM, phase_quantum); 1101 WREG32_SDMA(i, mmSDMA0_PHASE1_QUANTUM, phase_quantum); 1102 WREG32_SDMA(i, mmSDMA0_PHASE2_QUANTUM, phase_quantum); 1103 } 1104 WREG32_SDMA(i, mmSDMA0_CNTL, f32_cntl); 1105 1106 /* 1107 * Enable SDMA utilization. Its only supported on 1108 * Arcturus for the moment and firmware version 14 1109 * and above. 1110 */ 1111 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) && 1112 adev->sdma.instance[i].fw_version >= 14) 1113 WREG32_SDMA(i, mmSDMA0_PUB_DUMMY_REG2, enable); 1114 /* Extend page fault timeout to avoid interrupt storm */ 1115 WREG32_SDMA(i, mmSDMA0_UTCL1_TIMEOUT, 0x00800080); 1116 } 1117 1118 } 1119 1120 /** 1121 * sdma_v4_0_enable - stop the async dma engines 1122 * 1123 * @adev: amdgpu_device pointer 1124 * @enable: enable/disable the DMA MEs. 1125 * 1126 * Halt or unhalt the async dma engines (VEGA10). 1127 */ 1128 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable) 1129 { 1130 u32 f32_cntl; 1131 int i; 1132 1133 if (!enable) { 1134 sdma_v4_0_gfx_stop(adev); 1135 sdma_v4_0_rlc_stop(adev); 1136 if (adev->sdma.has_page_queue) 1137 sdma_v4_0_page_stop(adev); 1138 } 1139 1140 for (i = 0; i < adev->sdma.num_instances; i++) { 1141 f32_cntl = RREG32_SDMA(i, mmSDMA0_F32_CNTL); 1142 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 1143 WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl); 1144 } 1145 } 1146 1147 /* 1148 * sdma_v4_0_rb_cntl - get parameters for rb_cntl 1149 */ 1150 static uint32_t sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl) 1151 { 1152 /* Set ring buffer size in dwords */ 1153 uint32_t rb_bufsz = order_base_2(ring->ring_size / 4); 1154 1155 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 1156 #ifdef __BIG_ENDIAN 1157 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 1158 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 1159 RPTR_WRITEBACK_SWAP_ENABLE, 1); 1160 #endif 1161 return rb_cntl; 1162 } 1163 1164 /** 1165 * sdma_v4_0_gfx_resume - setup and start the async dma engines 1166 * 1167 * @adev: amdgpu_device pointer 1168 * @i: instance to resume 1169 * 1170 * Set up the gfx DMA ring buffers and enable them (VEGA10). 1171 * Returns 0 for success, error for failure. 1172 */ 1173 static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i) 1174 { 1175 struct amdgpu_ring *ring = &adev->sdma.instance[i].ring; 1176 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 1177 u32 doorbell; 1178 u32 doorbell_offset; 1179 u64 wptr_gpu_addr; 1180 1181 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL); 1182 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl); 1183 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 1184 1185 /* Initialize the ring buffer's read and write pointers */ 1186 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR, 0); 1187 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_HI, 0); 1188 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR, 0); 1189 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_HI, 0); 1190 1191 /* set the wb address whether it's enabled or not */ 1192 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI, 1193 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); 1194 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 1195 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); 1196 1197 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 1198 RPTR_WRITEBACK_ENABLE, 1); 1199 1200 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE, ring->gpu_addr >> 8); 1201 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE_HI, ring->gpu_addr >> 40); 1202 1203 ring->wptr = 0; 1204 1205 /* before programing wptr to a less value, need set minor_ptr_update first */ 1206 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 1); 1207 1208 doorbell = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL); 1209 doorbell_offset = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET); 1210 1211 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1212 ring->use_doorbell); 1213 doorbell_offset = REG_SET_FIELD(doorbell_offset, 1214 SDMA0_GFX_DOORBELL_OFFSET, 1215 OFFSET, ring->doorbell_index); 1216 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL, doorbell); 1217 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET, doorbell_offset); 1218 1219 sdma_v4_0_ring_set_wptr(ring); 1220 1221 /* set minor_ptr_update to 0 after wptr programed */ 1222 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 0); 1223 1224 /* setup the wptr shadow polling */ 1225 wptr_gpu_addr = ring->wptr_gpu_addr; 1226 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO, 1227 lower_32_bits(wptr_gpu_addr)); 1228 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI, 1229 upper_32_bits(wptr_gpu_addr)); 1230 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL); 1231 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 1232 SDMA0_GFX_RB_WPTR_POLL_CNTL, 1233 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 1234 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 1235 1236 /* enable DMA RB */ 1237 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 1238 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 1239 1240 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL); 1241 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 1242 #ifdef __BIG_ENDIAN 1243 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 1244 #endif 1245 /* enable DMA IBs */ 1246 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl); 1247 1248 ring->sched.ready = true; 1249 } 1250 1251 /** 1252 * sdma_v4_0_page_resume - setup and start the async dma engines 1253 * 1254 * @adev: amdgpu_device pointer 1255 * @i: instance to resume 1256 * 1257 * Set up the page DMA ring buffers and enable them (VEGA10). 1258 * Returns 0 for success, error for failure. 1259 */ 1260 static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i) 1261 { 1262 struct amdgpu_ring *ring = &adev->sdma.instance[i].page; 1263 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 1264 u32 doorbell; 1265 u32 doorbell_offset; 1266 u64 wptr_gpu_addr; 1267 1268 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL); 1269 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl); 1270 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 1271 1272 /* Initialize the ring buffer's read and write pointers */ 1273 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR, 0); 1274 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_HI, 0); 1275 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR, 0); 1276 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_HI, 0); 1277 1278 /* set the wb address whether it's enabled or not */ 1279 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_HI, 1280 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); 1281 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 1282 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); 1283 1284 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, 1285 RPTR_WRITEBACK_ENABLE, 1); 1286 1287 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE, ring->gpu_addr >> 8); 1288 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE_HI, ring->gpu_addr >> 40); 1289 1290 ring->wptr = 0; 1291 1292 /* before programing wptr to a less value, need set minor_ptr_update first */ 1293 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 1); 1294 1295 doorbell = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL); 1296 doorbell_offset = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET); 1297 1298 doorbell = REG_SET_FIELD(doorbell, SDMA0_PAGE_DOORBELL, ENABLE, 1299 ring->use_doorbell); 1300 doorbell_offset = REG_SET_FIELD(doorbell_offset, 1301 SDMA0_PAGE_DOORBELL_OFFSET, 1302 OFFSET, ring->doorbell_index); 1303 WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL, doorbell); 1304 WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET, doorbell_offset); 1305 1306 /* paging queue doorbell range is setup at sdma_v4_0_gfx_resume */ 1307 sdma_v4_0_page_ring_set_wptr(ring); 1308 1309 /* set minor_ptr_update to 0 after wptr programed */ 1310 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 0); 1311 1312 /* setup the wptr shadow polling */ 1313 wptr_gpu_addr = ring->wptr_gpu_addr; 1314 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO, 1315 lower_32_bits(wptr_gpu_addr)); 1316 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI, 1317 upper_32_bits(wptr_gpu_addr)); 1318 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL); 1319 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 1320 SDMA0_PAGE_RB_WPTR_POLL_CNTL, 1321 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 1322 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 1323 1324 /* enable DMA RB */ 1325 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, RB_ENABLE, 1); 1326 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 1327 1328 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL); 1329 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_ENABLE, 1); 1330 #ifdef __BIG_ENDIAN 1331 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1); 1332 #endif 1333 /* enable DMA IBs */ 1334 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl); 1335 1336 ring->sched.ready = true; 1337 } 1338 1339 static void 1340 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable) 1341 { 1342 uint32_t def, data; 1343 1344 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) { 1345 /* enable idle interrupt */ 1346 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 1347 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 1348 1349 if (data != def) 1350 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 1351 } else { 1352 /* disable idle interrupt */ 1353 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 1354 data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 1355 if (data != def) 1356 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 1357 } 1358 } 1359 1360 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev) 1361 { 1362 uint32_t def, data; 1363 1364 /* Enable HW based PG. */ 1365 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1366 data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK; 1367 if (data != def) 1368 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1369 1370 /* enable interrupt */ 1371 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 1372 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 1373 if (data != def) 1374 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 1375 1376 /* Configure hold time to filter in-valid power on/off request. Use default right now */ 1377 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1378 data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK; 1379 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK); 1380 /* Configure switch time for hysteresis purpose. Use default right now */ 1381 data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK; 1382 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK); 1383 if(data != def) 1384 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1385 } 1386 1387 static void sdma_v4_0_init_pg(struct amdgpu_device *adev) 1388 { 1389 if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA)) 1390 return; 1391 1392 switch (adev->ip_versions[SDMA0_HWIP][0]) { 1393 case IP_VERSION(4, 1, 0): 1394 case IP_VERSION(4, 1, 1): 1395 case IP_VERSION(4, 1, 2): 1396 sdma_v4_1_init_power_gating(adev); 1397 sdma_v4_1_update_power_gating(adev, true); 1398 break; 1399 default: 1400 break; 1401 } 1402 } 1403 1404 /** 1405 * sdma_v4_0_rlc_resume - setup and start the async dma engines 1406 * 1407 * @adev: amdgpu_device pointer 1408 * 1409 * Set up the compute DMA queues and enable them (VEGA10). 1410 * Returns 0 for success, error for failure. 1411 */ 1412 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev) 1413 { 1414 sdma_v4_0_init_pg(adev); 1415 1416 return 0; 1417 } 1418 1419 /** 1420 * sdma_v4_0_load_microcode - load the sDMA ME ucode 1421 * 1422 * @adev: amdgpu_device pointer 1423 * 1424 * Loads the sDMA0/1 ucode. 1425 * Returns 0 for success, -EINVAL if the ucode is not available. 1426 */ 1427 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev) 1428 { 1429 const struct sdma_firmware_header_v1_0 *hdr; 1430 const __le32 *fw_data; 1431 u32 fw_size; 1432 int i, j; 1433 1434 /* halt the MEs */ 1435 sdma_v4_0_enable(adev, false); 1436 1437 for (i = 0; i < adev->sdma.num_instances; i++) { 1438 if (!adev->sdma.instance[i].fw) 1439 return -EINVAL; 1440 1441 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 1442 amdgpu_ucode_print_sdma_hdr(&hdr->header); 1443 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1444 1445 fw_data = (const __le32 *) 1446 (adev->sdma.instance[i].fw->data + 1447 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1448 1449 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 0); 1450 1451 for (j = 0; j < fw_size; j++) 1452 WREG32_SDMA(i, mmSDMA0_UCODE_DATA, 1453 le32_to_cpup(fw_data++)); 1454 1455 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 1456 adev->sdma.instance[i].fw_version); 1457 } 1458 1459 return 0; 1460 } 1461 1462 /** 1463 * sdma_v4_0_start - setup and start the async dma engines 1464 * 1465 * @adev: amdgpu_device pointer 1466 * 1467 * Set up the DMA engines and enable them (VEGA10). 1468 * Returns 0 for success, error for failure. 1469 */ 1470 static int sdma_v4_0_start(struct amdgpu_device *adev) 1471 { 1472 struct amdgpu_ring *ring; 1473 int i, r = 0; 1474 1475 if (amdgpu_sriov_vf(adev)) { 1476 sdma_v4_0_ctx_switch_enable(adev, false); 1477 sdma_v4_0_enable(adev, false); 1478 } else { 1479 1480 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1481 r = sdma_v4_0_load_microcode(adev); 1482 if (r) 1483 return r; 1484 } 1485 1486 /* unhalt the MEs */ 1487 sdma_v4_0_enable(adev, true); 1488 /* enable sdma ring preemption */ 1489 sdma_v4_0_ctx_switch_enable(adev, true); 1490 } 1491 1492 /* start the gfx rings and rlc compute queues */ 1493 for (i = 0; i < adev->sdma.num_instances; i++) { 1494 uint32_t temp; 1495 1496 WREG32_SDMA(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL, 0); 1497 sdma_v4_0_gfx_resume(adev, i); 1498 if (adev->sdma.has_page_queue) 1499 sdma_v4_0_page_resume(adev, i); 1500 1501 /* set utc l1 enable flag always to 1 */ 1502 temp = RREG32_SDMA(i, mmSDMA0_CNTL); 1503 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 1504 WREG32_SDMA(i, mmSDMA0_CNTL, temp); 1505 1506 if (!amdgpu_sriov_vf(adev)) { 1507 /* unhalt engine */ 1508 temp = RREG32_SDMA(i, mmSDMA0_F32_CNTL); 1509 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 1510 WREG32_SDMA(i, mmSDMA0_F32_CNTL, temp); 1511 } 1512 } 1513 1514 if (amdgpu_sriov_vf(adev)) { 1515 sdma_v4_0_ctx_switch_enable(adev, true); 1516 sdma_v4_0_enable(adev, true); 1517 } else { 1518 r = sdma_v4_0_rlc_resume(adev); 1519 if (r) 1520 return r; 1521 } 1522 1523 for (i = 0; i < adev->sdma.num_instances; i++) { 1524 ring = &adev->sdma.instance[i].ring; 1525 1526 r = amdgpu_ring_test_helper(ring); 1527 if (r) 1528 return r; 1529 1530 if (adev->sdma.has_page_queue) { 1531 struct amdgpu_ring *page = &adev->sdma.instance[i].page; 1532 1533 r = amdgpu_ring_test_helper(page); 1534 if (r) 1535 return r; 1536 1537 if (adev->mman.buffer_funcs_ring == page) 1538 amdgpu_ttm_set_buffer_funcs_status(adev, true); 1539 } 1540 1541 if (adev->mman.buffer_funcs_ring == ring) 1542 amdgpu_ttm_set_buffer_funcs_status(adev, true); 1543 } 1544 1545 return r; 1546 } 1547 1548 /** 1549 * sdma_v4_0_ring_test_ring - simple async dma engine test 1550 * 1551 * @ring: amdgpu_ring structure holding ring information 1552 * 1553 * Test the DMA engine by writing using it to write an 1554 * value to memory. (VEGA10). 1555 * Returns 0 for success, error for failure. 1556 */ 1557 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring) 1558 { 1559 struct amdgpu_device *adev = ring->adev; 1560 unsigned i; 1561 unsigned index; 1562 int r; 1563 u32 tmp; 1564 u64 gpu_addr; 1565 1566 r = amdgpu_device_wb_get(adev, &index); 1567 if (r) 1568 return r; 1569 1570 gpu_addr = adev->wb.gpu_addr + (index * 4); 1571 tmp = 0xCAFEDEAD; 1572 adev->wb.wb[index] = cpu_to_le32(tmp); 1573 1574 r = amdgpu_ring_alloc(ring, 5); 1575 if (r) 1576 goto error_free_wb; 1577 1578 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1579 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 1580 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 1581 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 1582 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 1583 amdgpu_ring_write(ring, 0xDEADBEEF); 1584 amdgpu_ring_commit(ring); 1585 1586 for (i = 0; i < adev->usec_timeout; i++) { 1587 tmp = le32_to_cpu(adev->wb.wb[index]); 1588 if (tmp == 0xDEADBEEF) 1589 break; 1590 udelay(1); 1591 } 1592 1593 if (i >= adev->usec_timeout) 1594 r = -ETIMEDOUT; 1595 1596 error_free_wb: 1597 amdgpu_device_wb_free(adev, index); 1598 return r; 1599 } 1600 1601 /** 1602 * sdma_v4_0_ring_test_ib - test an IB on the DMA engine 1603 * 1604 * @ring: amdgpu_ring structure holding ring information 1605 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 1606 * 1607 * Test a simple IB in the DMA ring (VEGA10). 1608 * Returns 0 on success, error on failure. 1609 */ 1610 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1611 { 1612 struct amdgpu_device *adev = ring->adev; 1613 struct amdgpu_ib ib; 1614 struct dma_fence *f = NULL; 1615 unsigned index; 1616 long r; 1617 u32 tmp = 0; 1618 u64 gpu_addr; 1619 1620 r = amdgpu_device_wb_get(adev, &index); 1621 if (r) 1622 return r; 1623 1624 gpu_addr = adev->wb.gpu_addr + (index * 4); 1625 tmp = 0xCAFEDEAD; 1626 adev->wb.wb[index] = cpu_to_le32(tmp); 1627 memset(&ib, 0, sizeof(ib)); 1628 r = amdgpu_ib_get(adev, NULL, 256, 1629 AMDGPU_IB_POOL_DIRECT, &ib); 1630 if (r) 1631 goto err0; 1632 1633 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1634 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1635 ib.ptr[1] = lower_32_bits(gpu_addr); 1636 ib.ptr[2] = upper_32_bits(gpu_addr); 1637 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1638 ib.ptr[4] = 0xDEADBEEF; 1639 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1640 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1641 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1642 ib.length_dw = 8; 1643 1644 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1645 if (r) 1646 goto err1; 1647 1648 r = dma_fence_wait_timeout(f, false, timeout); 1649 if (r == 0) { 1650 r = -ETIMEDOUT; 1651 goto err1; 1652 } else if (r < 0) { 1653 goto err1; 1654 } 1655 tmp = le32_to_cpu(adev->wb.wb[index]); 1656 if (tmp == 0xDEADBEEF) 1657 r = 0; 1658 else 1659 r = -EINVAL; 1660 1661 err1: 1662 amdgpu_ib_free(adev, &ib, NULL); 1663 dma_fence_put(f); 1664 err0: 1665 amdgpu_device_wb_free(adev, index); 1666 return r; 1667 } 1668 1669 1670 /** 1671 * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART 1672 * 1673 * @ib: indirect buffer to fill with commands 1674 * @pe: addr of the page entry 1675 * @src: src addr to copy from 1676 * @count: number of page entries to update 1677 * 1678 * Update PTEs by copying them from the GART using sDMA (VEGA10). 1679 */ 1680 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib, 1681 uint64_t pe, uint64_t src, 1682 unsigned count) 1683 { 1684 unsigned bytes = count * 8; 1685 1686 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1687 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1688 ib->ptr[ib->length_dw++] = bytes - 1; 1689 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1690 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1691 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1692 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1693 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1694 1695 } 1696 1697 /** 1698 * sdma_v4_0_vm_write_pte - update PTEs by writing them manually 1699 * 1700 * @ib: indirect buffer to fill with commands 1701 * @pe: addr of the page entry 1702 * @value: dst addr to write into pe 1703 * @count: number of page entries to update 1704 * @incr: increase next addr by incr bytes 1705 * 1706 * Update PTEs by writing them manually using sDMA (VEGA10). 1707 */ 1708 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1709 uint64_t value, unsigned count, 1710 uint32_t incr) 1711 { 1712 unsigned ndw = count * 2; 1713 1714 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1715 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1716 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1717 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1718 ib->ptr[ib->length_dw++] = ndw - 1; 1719 for (; ndw > 0; ndw -= 2) { 1720 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1721 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1722 value += incr; 1723 } 1724 } 1725 1726 /** 1727 * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA 1728 * 1729 * @ib: indirect buffer to fill with commands 1730 * @pe: addr of the page entry 1731 * @addr: dst addr to write into pe 1732 * @count: number of page entries to update 1733 * @incr: increase next addr by incr bytes 1734 * @flags: access flags 1735 * 1736 * Update the page tables using sDMA (VEGA10). 1737 */ 1738 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1739 uint64_t pe, 1740 uint64_t addr, unsigned count, 1741 uint32_t incr, uint64_t flags) 1742 { 1743 /* for physically contiguous pages (vram) */ 1744 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1745 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1746 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1747 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1748 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1749 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1750 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1751 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1752 ib->ptr[ib->length_dw++] = 0; 1753 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1754 } 1755 1756 /** 1757 * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw 1758 * 1759 * @ring: amdgpu_ring structure holding ring information 1760 * @ib: indirect buffer to fill with padding 1761 */ 1762 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1763 { 1764 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1765 u32 pad_count; 1766 int i; 1767 1768 pad_count = (-ib->length_dw) & 7; 1769 for (i = 0; i < pad_count; i++) 1770 if (sdma && sdma->burst_nop && (i == 0)) 1771 ib->ptr[ib->length_dw++] = 1772 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1773 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1774 else 1775 ib->ptr[ib->length_dw++] = 1776 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1777 } 1778 1779 1780 /** 1781 * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline 1782 * 1783 * @ring: amdgpu_ring pointer 1784 * 1785 * Make sure all previous operations are completed (CIK). 1786 */ 1787 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1788 { 1789 uint32_t seq = ring->fence_drv.sync_seq; 1790 uint64_t addr = ring->fence_drv.gpu_addr; 1791 1792 /* wait for idle */ 1793 sdma_v4_0_wait_reg_mem(ring, 1, 0, 1794 addr & 0xfffffffc, 1795 upper_32_bits(addr) & 0xffffffff, 1796 seq, 0xffffffff, 4); 1797 } 1798 1799 1800 /** 1801 * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA 1802 * 1803 * @ring: amdgpu_ring pointer 1804 * @vmid: vmid number to use 1805 * @pd_addr: address 1806 * 1807 * Update the page table base and flush the VM TLB 1808 * using sDMA (VEGA10). 1809 */ 1810 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1811 unsigned vmid, uint64_t pd_addr) 1812 { 1813 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1814 } 1815 1816 static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring, 1817 uint32_t reg, uint32_t val) 1818 { 1819 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1820 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1821 amdgpu_ring_write(ring, reg); 1822 amdgpu_ring_write(ring, val); 1823 } 1824 1825 static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1826 uint32_t val, uint32_t mask) 1827 { 1828 sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10); 1829 } 1830 1831 static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev) 1832 { 1833 uint fw_version = adev->sdma.instance[0].fw_version; 1834 1835 switch (adev->ip_versions[SDMA0_HWIP][0]) { 1836 case IP_VERSION(4, 0, 0): 1837 return fw_version >= 430; 1838 case IP_VERSION(4, 0, 1): 1839 /*return fw_version >= 31;*/ 1840 return false; 1841 case IP_VERSION(4, 2, 0): 1842 return fw_version >= 123; 1843 default: 1844 return false; 1845 } 1846 } 1847 1848 static int sdma_v4_0_early_init(void *handle) 1849 { 1850 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1851 int r; 1852 1853 r = sdma_v4_0_init_microcode(adev); 1854 if (r) { 1855 DRM_ERROR("Failed to load sdma firmware!\n"); 1856 return r; 1857 } 1858 1859 /* TODO: Page queue breaks driver reload under SRIOV */ 1860 if ((adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 0, 0)) && 1861 amdgpu_sriov_vf((adev))) 1862 adev->sdma.has_page_queue = false; 1863 else if (sdma_v4_0_fw_support_paging_queue(adev)) 1864 adev->sdma.has_page_queue = true; 1865 1866 sdma_v4_0_set_ring_funcs(adev); 1867 sdma_v4_0_set_buffer_funcs(adev); 1868 sdma_v4_0_set_vm_pte_funcs(adev); 1869 sdma_v4_0_set_irq_funcs(adev); 1870 sdma_v4_0_set_ras_funcs(adev); 1871 1872 return 0; 1873 } 1874 1875 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev, 1876 void *err_data, 1877 struct amdgpu_iv_entry *entry); 1878 1879 static int sdma_v4_0_late_init(void *handle) 1880 { 1881 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1882 1883 sdma_v4_0_setup_ulv(adev); 1884 1885 if (!amdgpu_persistent_edc_harvesting_supported(adev)) { 1886 if (adev->sdma.ras && adev->sdma.ras->ras_block.hw_ops && 1887 adev->sdma.ras->ras_block.hw_ops->reset_ras_error_count) 1888 adev->sdma.ras->ras_block.hw_ops->reset_ras_error_count(adev); 1889 } 1890 1891 return 0; 1892 } 1893 1894 static int sdma_v4_0_sw_init(void *handle) 1895 { 1896 struct amdgpu_ring *ring; 1897 int r, i; 1898 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1899 1900 /* SDMA trap event */ 1901 for (i = 0; i < adev->sdma.num_instances; i++) { 1902 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1903 SDMA0_4_0__SRCID__SDMA_TRAP, 1904 &adev->sdma.trap_irq); 1905 if (r) 1906 return r; 1907 } 1908 1909 /* SDMA SRAM ECC event */ 1910 for (i = 0; i < adev->sdma.num_instances; i++) { 1911 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1912 SDMA0_4_0__SRCID__SDMA_SRAM_ECC, 1913 &adev->sdma.ecc_irq); 1914 if (r) 1915 return r; 1916 } 1917 1918 /* SDMA VM_HOLE/DOORBELL_INV/POLL_TIMEOUT/SRBM_WRITE_PROTECTION event*/ 1919 for (i = 0; i < adev->sdma.num_instances; i++) { 1920 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1921 SDMA0_4_0__SRCID__SDMA_VM_HOLE, 1922 &adev->sdma.vm_hole_irq); 1923 if (r) 1924 return r; 1925 1926 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1927 SDMA0_4_0__SRCID__SDMA_DOORBELL_INVALID, 1928 &adev->sdma.doorbell_invalid_irq); 1929 if (r) 1930 return r; 1931 1932 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1933 SDMA0_4_0__SRCID__SDMA_POLL_TIMEOUT, 1934 &adev->sdma.pool_timeout_irq); 1935 if (r) 1936 return r; 1937 1938 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1939 SDMA0_4_0__SRCID__SDMA_SRBMWRITE, 1940 &adev->sdma.srbm_write_irq); 1941 if (r) 1942 return r; 1943 } 1944 1945 for (i = 0; i < adev->sdma.num_instances; i++) { 1946 ring = &adev->sdma.instance[i].ring; 1947 ring->ring_obj = NULL; 1948 ring->use_doorbell = true; 1949 1950 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1951 ring->use_doorbell?"true":"false"); 1952 1953 /* doorbell size is 2 dwords, get DWORD offset */ 1954 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1; 1955 1956 sprintf(ring->name, "sdma%d", i); 1957 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1958 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1959 AMDGPU_RING_PRIO_DEFAULT, NULL); 1960 if (r) 1961 return r; 1962 1963 if (adev->sdma.has_page_queue) { 1964 ring = &adev->sdma.instance[i].page; 1965 ring->ring_obj = NULL; 1966 ring->use_doorbell = true; 1967 1968 /* paging queue use same doorbell index/routing as gfx queue 1969 * with 0x400 (4096 dwords) offset on second doorbell page 1970 */ 1971 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1; 1972 ring->doorbell_index += 0x400; 1973 1974 sprintf(ring->name, "page%d", i); 1975 r = amdgpu_ring_init(adev, ring, 1024, 1976 &adev->sdma.trap_irq, 1977 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1978 AMDGPU_RING_PRIO_DEFAULT, NULL); 1979 if (r) 1980 return r; 1981 } 1982 } 1983 1984 return r; 1985 } 1986 1987 static int sdma_v4_0_sw_fini(void *handle) 1988 { 1989 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1990 int i; 1991 1992 for (i = 0; i < adev->sdma.num_instances; i++) { 1993 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1994 if (adev->sdma.has_page_queue) 1995 amdgpu_ring_fini(&adev->sdma.instance[i].page); 1996 } 1997 1998 sdma_v4_0_destroy_inst_ctx(adev); 1999 2000 return 0; 2001 } 2002 2003 static int sdma_v4_0_hw_init(void *handle) 2004 { 2005 int r; 2006 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2007 2008 if (adev->flags & AMD_IS_APU) 2009 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false); 2010 2011 if (!amdgpu_sriov_vf(adev)) 2012 sdma_v4_0_init_golden_registers(adev); 2013 2014 r = sdma_v4_0_start(adev); 2015 2016 return r; 2017 } 2018 2019 static int sdma_v4_0_hw_fini(void *handle) 2020 { 2021 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2022 int i; 2023 2024 if (amdgpu_sriov_vf(adev)) 2025 return 0; 2026 2027 for (i = 0; i < adev->sdma.num_instances; i++) { 2028 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, 2029 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 2030 } 2031 2032 sdma_v4_0_ctx_switch_enable(adev, false); 2033 sdma_v4_0_enable(adev, false); 2034 2035 if (adev->flags & AMD_IS_APU) 2036 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true); 2037 2038 return 0; 2039 } 2040 2041 static int sdma_v4_0_suspend(void *handle) 2042 { 2043 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2044 2045 /* SMU saves SDMA state for us */ 2046 if (adev->in_s0ix) 2047 return 0; 2048 2049 return sdma_v4_0_hw_fini(adev); 2050 } 2051 2052 static int sdma_v4_0_resume(void *handle) 2053 { 2054 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2055 2056 /* SMU restores SDMA state for us */ 2057 if (adev->in_s0ix) 2058 return 0; 2059 2060 return sdma_v4_0_hw_init(adev); 2061 } 2062 2063 static bool sdma_v4_0_is_idle(void *handle) 2064 { 2065 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2066 u32 i; 2067 2068 for (i = 0; i < adev->sdma.num_instances; i++) { 2069 u32 tmp = RREG32_SDMA(i, mmSDMA0_STATUS_REG); 2070 2071 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 2072 return false; 2073 } 2074 2075 return true; 2076 } 2077 2078 static int sdma_v4_0_wait_for_idle(void *handle) 2079 { 2080 unsigned i, j; 2081 u32 sdma[AMDGPU_MAX_SDMA_INSTANCES]; 2082 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2083 2084 for (i = 0; i < adev->usec_timeout; i++) { 2085 for (j = 0; j < adev->sdma.num_instances; j++) { 2086 sdma[j] = RREG32_SDMA(j, mmSDMA0_STATUS_REG); 2087 if (!(sdma[j] & SDMA0_STATUS_REG__IDLE_MASK)) 2088 break; 2089 } 2090 if (j == adev->sdma.num_instances) 2091 return 0; 2092 udelay(1); 2093 } 2094 return -ETIMEDOUT; 2095 } 2096 2097 static int sdma_v4_0_soft_reset(void *handle) 2098 { 2099 /* todo */ 2100 2101 return 0; 2102 } 2103 2104 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev, 2105 struct amdgpu_irq_src *source, 2106 unsigned type, 2107 enum amdgpu_interrupt_state state) 2108 { 2109 u32 sdma_cntl; 2110 2111 sdma_cntl = RREG32_SDMA(type, mmSDMA0_CNTL); 2112 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 2113 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2114 WREG32_SDMA(type, mmSDMA0_CNTL, sdma_cntl); 2115 2116 return 0; 2117 } 2118 2119 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev, 2120 struct amdgpu_irq_src *source, 2121 struct amdgpu_iv_entry *entry) 2122 { 2123 uint32_t instance; 2124 2125 DRM_DEBUG("IH: SDMA trap\n"); 2126 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 2127 switch (entry->ring_id) { 2128 case 0: 2129 amdgpu_fence_process(&adev->sdma.instance[instance].ring); 2130 break; 2131 case 1: 2132 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 0)) 2133 amdgpu_fence_process(&adev->sdma.instance[instance].page); 2134 break; 2135 case 2: 2136 /* XXX compute */ 2137 break; 2138 case 3: 2139 if (adev->ip_versions[SDMA0_HWIP][0] != IP_VERSION(4, 2, 0)) 2140 amdgpu_fence_process(&adev->sdma.instance[instance].page); 2141 break; 2142 } 2143 return 0; 2144 } 2145 2146 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev, 2147 void *err_data, 2148 struct amdgpu_iv_entry *entry) 2149 { 2150 int instance; 2151 2152 /* When “Full RAS” is enabled, the per-IP interrupt sources should 2153 * be disabled and the driver should only look for the aggregated 2154 * interrupt via sync flood 2155 */ 2156 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 2157 goto out; 2158 2159 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 2160 if (instance < 0) 2161 goto out; 2162 2163 amdgpu_sdma_process_ras_data_cb(adev, err_data, entry); 2164 2165 out: 2166 return AMDGPU_RAS_SUCCESS; 2167 } 2168 2169 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev, 2170 struct amdgpu_irq_src *source, 2171 struct amdgpu_iv_entry *entry) 2172 { 2173 int instance; 2174 2175 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 2176 2177 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 2178 if (instance < 0) 2179 return 0; 2180 2181 switch (entry->ring_id) { 2182 case 0: 2183 drm_sched_fault(&adev->sdma.instance[instance].ring.sched); 2184 break; 2185 } 2186 return 0; 2187 } 2188 2189 static int sdma_v4_0_set_ecc_irq_state(struct amdgpu_device *adev, 2190 struct amdgpu_irq_src *source, 2191 unsigned type, 2192 enum amdgpu_interrupt_state state) 2193 { 2194 u32 sdma_edc_config; 2195 2196 sdma_edc_config = RREG32_SDMA(type, mmSDMA0_EDC_CONFIG); 2197 sdma_edc_config = REG_SET_FIELD(sdma_edc_config, SDMA0_EDC_CONFIG, ECC_INT_ENABLE, 2198 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2199 WREG32_SDMA(type, mmSDMA0_EDC_CONFIG, sdma_edc_config); 2200 2201 return 0; 2202 } 2203 2204 static int sdma_v4_0_print_iv_entry(struct amdgpu_device *adev, 2205 struct amdgpu_iv_entry *entry) 2206 { 2207 int instance; 2208 struct amdgpu_task_info task_info; 2209 u64 addr; 2210 2211 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 2212 if (instance < 0 || instance >= adev->sdma.num_instances) { 2213 dev_err(adev->dev, "sdma instance invalid %d\n", instance); 2214 return -EINVAL; 2215 } 2216 2217 addr = (u64)entry->src_data[0] << 12; 2218 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 2219 2220 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 2221 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 2222 2223 dev_dbg_ratelimited(adev->dev, 2224 "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u " 2225 "pasid:%u, for process %s pid %d thread %s pid %d\n", 2226 instance, addr, entry->src_id, entry->ring_id, entry->vmid, 2227 entry->pasid, task_info.process_name, task_info.tgid, 2228 task_info.task_name, task_info.pid); 2229 return 0; 2230 } 2231 2232 static int sdma_v4_0_process_vm_hole_irq(struct amdgpu_device *adev, 2233 struct amdgpu_irq_src *source, 2234 struct amdgpu_iv_entry *entry) 2235 { 2236 dev_dbg_ratelimited(adev->dev, "MC or SEM address in VM hole\n"); 2237 sdma_v4_0_print_iv_entry(adev, entry); 2238 return 0; 2239 } 2240 2241 static int sdma_v4_0_process_doorbell_invalid_irq(struct amdgpu_device *adev, 2242 struct amdgpu_irq_src *source, 2243 struct amdgpu_iv_entry *entry) 2244 { 2245 dev_dbg_ratelimited(adev->dev, "SDMA received a doorbell from BIF with byte_enable !=0xff\n"); 2246 sdma_v4_0_print_iv_entry(adev, entry); 2247 return 0; 2248 } 2249 2250 static int sdma_v4_0_process_pool_timeout_irq(struct amdgpu_device *adev, 2251 struct amdgpu_irq_src *source, 2252 struct amdgpu_iv_entry *entry) 2253 { 2254 dev_dbg_ratelimited(adev->dev, 2255 "Polling register/memory timeout executing POLL_REG/MEM with finite timer\n"); 2256 sdma_v4_0_print_iv_entry(adev, entry); 2257 return 0; 2258 } 2259 2260 static int sdma_v4_0_process_srbm_write_irq(struct amdgpu_device *adev, 2261 struct amdgpu_irq_src *source, 2262 struct amdgpu_iv_entry *entry) 2263 { 2264 dev_dbg_ratelimited(adev->dev, 2265 "SDMA gets an Register Write SRBM_WRITE command in non-privilege command buffer\n"); 2266 sdma_v4_0_print_iv_entry(adev, entry); 2267 return 0; 2268 } 2269 2270 static void sdma_v4_0_update_medium_grain_clock_gating( 2271 struct amdgpu_device *adev, 2272 bool enable) 2273 { 2274 uint32_t data, def; 2275 int i; 2276 2277 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 2278 for (i = 0; i < adev->sdma.num_instances; i++) { 2279 def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL); 2280 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 2281 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 2282 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 2283 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 2284 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 2285 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 2286 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 2287 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 2288 if (def != data) 2289 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data); 2290 } 2291 } else { 2292 for (i = 0; i < adev->sdma.num_instances; i++) { 2293 def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL); 2294 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 2295 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 2296 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 2297 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 2298 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 2299 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 2300 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 2301 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 2302 if (def != data) 2303 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data); 2304 } 2305 } 2306 } 2307 2308 2309 static void sdma_v4_0_update_medium_grain_light_sleep( 2310 struct amdgpu_device *adev, 2311 bool enable) 2312 { 2313 uint32_t data, def; 2314 int i; 2315 2316 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 2317 for (i = 0; i < adev->sdma.num_instances; i++) { 2318 /* 1-not override: enable sdma mem light sleep */ 2319 def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL); 2320 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 2321 if (def != data) 2322 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data); 2323 } 2324 } else { 2325 for (i = 0; i < adev->sdma.num_instances; i++) { 2326 /* 0-override:disable sdma mem light sleep */ 2327 def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL); 2328 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 2329 if (def != data) 2330 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data); 2331 } 2332 } 2333 } 2334 2335 static int sdma_v4_0_set_clockgating_state(void *handle, 2336 enum amd_clockgating_state state) 2337 { 2338 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2339 2340 if (amdgpu_sriov_vf(adev)) 2341 return 0; 2342 2343 sdma_v4_0_update_medium_grain_clock_gating(adev, 2344 state == AMD_CG_STATE_GATE); 2345 sdma_v4_0_update_medium_grain_light_sleep(adev, 2346 state == AMD_CG_STATE_GATE); 2347 return 0; 2348 } 2349 2350 static int sdma_v4_0_set_powergating_state(void *handle, 2351 enum amd_powergating_state state) 2352 { 2353 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2354 2355 switch (adev->ip_versions[SDMA0_HWIP][0]) { 2356 case IP_VERSION(4, 1, 0): 2357 case IP_VERSION(4, 1, 1): 2358 case IP_VERSION(4, 1, 2): 2359 sdma_v4_1_update_power_gating(adev, 2360 state == AMD_PG_STATE_GATE); 2361 break; 2362 default: 2363 break; 2364 } 2365 2366 return 0; 2367 } 2368 2369 static void sdma_v4_0_get_clockgating_state(void *handle, u64 *flags) 2370 { 2371 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2372 int data; 2373 2374 if (amdgpu_sriov_vf(adev)) 2375 *flags = 0; 2376 2377 /* AMD_CG_SUPPORT_SDMA_MGCG */ 2378 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 2379 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK)) 2380 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 2381 2382 /* AMD_CG_SUPPORT_SDMA_LS */ 2383 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 2384 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 2385 *flags |= AMD_CG_SUPPORT_SDMA_LS; 2386 } 2387 2388 const struct amd_ip_funcs sdma_v4_0_ip_funcs = { 2389 .name = "sdma_v4_0", 2390 .early_init = sdma_v4_0_early_init, 2391 .late_init = sdma_v4_0_late_init, 2392 .sw_init = sdma_v4_0_sw_init, 2393 .sw_fini = sdma_v4_0_sw_fini, 2394 .hw_init = sdma_v4_0_hw_init, 2395 .hw_fini = sdma_v4_0_hw_fini, 2396 .suspend = sdma_v4_0_suspend, 2397 .resume = sdma_v4_0_resume, 2398 .is_idle = sdma_v4_0_is_idle, 2399 .wait_for_idle = sdma_v4_0_wait_for_idle, 2400 .soft_reset = sdma_v4_0_soft_reset, 2401 .set_clockgating_state = sdma_v4_0_set_clockgating_state, 2402 .set_powergating_state = sdma_v4_0_set_powergating_state, 2403 .get_clockgating_state = sdma_v4_0_get_clockgating_state, 2404 }; 2405 2406 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = { 2407 .type = AMDGPU_RING_TYPE_SDMA, 2408 .align_mask = 0xf, 2409 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2410 .support_64bit_ptrs = true, 2411 .secure_submission_supported = true, 2412 .vmhub = AMDGPU_MMHUB_0, 2413 .get_rptr = sdma_v4_0_ring_get_rptr, 2414 .get_wptr = sdma_v4_0_ring_get_wptr, 2415 .set_wptr = sdma_v4_0_ring_set_wptr, 2416 .emit_frame_size = 2417 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2418 3 + /* hdp invalidate */ 2419 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2420 /* sdma_v4_0_ring_emit_vm_flush */ 2421 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2422 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2423 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2424 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2425 .emit_ib = sdma_v4_0_ring_emit_ib, 2426 .emit_fence = sdma_v4_0_ring_emit_fence, 2427 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2428 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2429 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2430 .test_ring = sdma_v4_0_ring_test_ring, 2431 .test_ib = sdma_v4_0_ring_test_ib, 2432 .insert_nop = sdma_v4_0_ring_insert_nop, 2433 .pad_ib = sdma_v4_0_ring_pad_ib, 2434 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2435 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2436 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2437 }; 2438 2439 /* 2440 * On Arcturus, SDMA instance 5~7 has a different vmhub type(AMDGPU_MMHUB_1). 2441 * So create a individual constant ring_funcs for those instances. 2442 */ 2443 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs_2nd_mmhub = { 2444 .type = AMDGPU_RING_TYPE_SDMA, 2445 .align_mask = 0xf, 2446 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2447 .support_64bit_ptrs = true, 2448 .secure_submission_supported = true, 2449 .vmhub = AMDGPU_MMHUB_1, 2450 .get_rptr = sdma_v4_0_ring_get_rptr, 2451 .get_wptr = sdma_v4_0_ring_get_wptr, 2452 .set_wptr = sdma_v4_0_ring_set_wptr, 2453 .emit_frame_size = 2454 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2455 3 + /* hdp invalidate */ 2456 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2457 /* sdma_v4_0_ring_emit_vm_flush */ 2458 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2459 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2460 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2461 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2462 .emit_ib = sdma_v4_0_ring_emit_ib, 2463 .emit_fence = sdma_v4_0_ring_emit_fence, 2464 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2465 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2466 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2467 .test_ring = sdma_v4_0_ring_test_ring, 2468 .test_ib = sdma_v4_0_ring_test_ib, 2469 .insert_nop = sdma_v4_0_ring_insert_nop, 2470 .pad_ib = sdma_v4_0_ring_pad_ib, 2471 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2472 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2473 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2474 }; 2475 2476 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = { 2477 .type = AMDGPU_RING_TYPE_SDMA, 2478 .align_mask = 0xf, 2479 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2480 .support_64bit_ptrs = true, 2481 .secure_submission_supported = true, 2482 .vmhub = AMDGPU_MMHUB_0, 2483 .get_rptr = sdma_v4_0_ring_get_rptr, 2484 .get_wptr = sdma_v4_0_page_ring_get_wptr, 2485 .set_wptr = sdma_v4_0_page_ring_set_wptr, 2486 .emit_frame_size = 2487 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2488 3 + /* hdp invalidate */ 2489 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2490 /* sdma_v4_0_ring_emit_vm_flush */ 2491 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2492 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2493 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2494 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2495 .emit_ib = sdma_v4_0_ring_emit_ib, 2496 .emit_fence = sdma_v4_0_ring_emit_fence, 2497 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2498 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2499 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2500 .test_ring = sdma_v4_0_ring_test_ring, 2501 .test_ib = sdma_v4_0_ring_test_ib, 2502 .insert_nop = sdma_v4_0_ring_insert_nop, 2503 .pad_ib = sdma_v4_0_ring_pad_ib, 2504 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2505 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2506 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2507 }; 2508 2509 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs_2nd_mmhub = { 2510 .type = AMDGPU_RING_TYPE_SDMA, 2511 .align_mask = 0xf, 2512 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2513 .support_64bit_ptrs = true, 2514 .secure_submission_supported = true, 2515 .vmhub = AMDGPU_MMHUB_1, 2516 .get_rptr = sdma_v4_0_ring_get_rptr, 2517 .get_wptr = sdma_v4_0_page_ring_get_wptr, 2518 .set_wptr = sdma_v4_0_page_ring_set_wptr, 2519 .emit_frame_size = 2520 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2521 3 + /* hdp invalidate */ 2522 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2523 /* sdma_v4_0_ring_emit_vm_flush */ 2524 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2525 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2526 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2527 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2528 .emit_ib = sdma_v4_0_ring_emit_ib, 2529 .emit_fence = sdma_v4_0_ring_emit_fence, 2530 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2531 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2532 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2533 .test_ring = sdma_v4_0_ring_test_ring, 2534 .test_ib = sdma_v4_0_ring_test_ib, 2535 .insert_nop = sdma_v4_0_ring_insert_nop, 2536 .pad_ib = sdma_v4_0_ring_pad_ib, 2537 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2538 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2539 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2540 }; 2541 2542 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev) 2543 { 2544 int i; 2545 2546 for (i = 0; i < adev->sdma.num_instances; i++) { 2547 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) && i >= 5) 2548 adev->sdma.instance[i].ring.funcs = 2549 &sdma_v4_0_ring_funcs_2nd_mmhub; 2550 else 2551 adev->sdma.instance[i].ring.funcs = 2552 &sdma_v4_0_ring_funcs; 2553 adev->sdma.instance[i].ring.me = i; 2554 if (adev->sdma.has_page_queue) { 2555 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) && i >= 5) 2556 adev->sdma.instance[i].page.funcs = 2557 &sdma_v4_0_page_ring_funcs_2nd_mmhub; 2558 else 2559 adev->sdma.instance[i].page.funcs = 2560 &sdma_v4_0_page_ring_funcs; 2561 adev->sdma.instance[i].page.me = i; 2562 } 2563 } 2564 } 2565 2566 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = { 2567 .set = sdma_v4_0_set_trap_irq_state, 2568 .process = sdma_v4_0_process_trap_irq, 2569 }; 2570 2571 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = { 2572 .process = sdma_v4_0_process_illegal_inst_irq, 2573 }; 2574 2575 static const struct amdgpu_irq_src_funcs sdma_v4_0_ecc_irq_funcs = { 2576 .set = sdma_v4_0_set_ecc_irq_state, 2577 .process = amdgpu_sdma_process_ecc_irq, 2578 }; 2579 2580 static const struct amdgpu_irq_src_funcs sdma_v4_0_vm_hole_irq_funcs = { 2581 .process = sdma_v4_0_process_vm_hole_irq, 2582 }; 2583 2584 static const struct amdgpu_irq_src_funcs sdma_v4_0_doorbell_invalid_irq_funcs = { 2585 .process = sdma_v4_0_process_doorbell_invalid_irq, 2586 }; 2587 2588 static const struct amdgpu_irq_src_funcs sdma_v4_0_pool_timeout_irq_funcs = { 2589 .process = sdma_v4_0_process_pool_timeout_irq, 2590 }; 2591 2592 static const struct amdgpu_irq_src_funcs sdma_v4_0_srbm_write_irq_funcs = { 2593 .process = sdma_v4_0_process_srbm_write_irq, 2594 }; 2595 2596 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev) 2597 { 2598 adev->sdma.trap_irq.num_types = adev->sdma.num_instances; 2599 adev->sdma.ecc_irq.num_types = adev->sdma.num_instances; 2600 /*For Arcturus and Aldebaran, add another 4 irq handler*/ 2601 switch (adev->sdma.num_instances) { 2602 case 5: 2603 case 8: 2604 adev->sdma.vm_hole_irq.num_types = adev->sdma.num_instances; 2605 adev->sdma.doorbell_invalid_irq.num_types = adev->sdma.num_instances; 2606 adev->sdma.pool_timeout_irq.num_types = adev->sdma.num_instances; 2607 adev->sdma.srbm_write_irq.num_types = adev->sdma.num_instances; 2608 break; 2609 default: 2610 break; 2611 } 2612 adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs; 2613 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs; 2614 adev->sdma.ecc_irq.funcs = &sdma_v4_0_ecc_irq_funcs; 2615 adev->sdma.vm_hole_irq.funcs = &sdma_v4_0_vm_hole_irq_funcs; 2616 adev->sdma.doorbell_invalid_irq.funcs = &sdma_v4_0_doorbell_invalid_irq_funcs; 2617 adev->sdma.pool_timeout_irq.funcs = &sdma_v4_0_pool_timeout_irq_funcs; 2618 adev->sdma.srbm_write_irq.funcs = &sdma_v4_0_srbm_write_irq_funcs; 2619 } 2620 2621 /** 2622 * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine 2623 * 2624 * @ib: indirect buffer to copy to 2625 * @src_offset: src GPU address 2626 * @dst_offset: dst GPU address 2627 * @byte_count: number of bytes to xfer 2628 * @tmz: if a secure copy should be used 2629 * 2630 * Copy GPU buffers using the DMA engine (VEGA10/12). 2631 * Used by the amdgpu ttm implementation to move pages if 2632 * registered as the asic copy callback. 2633 */ 2634 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib, 2635 uint64_t src_offset, 2636 uint64_t dst_offset, 2637 uint32_t byte_count, 2638 bool tmz) 2639 { 2640 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 2641 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 2642 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0); 2643 ib->ptr[ib->length_dw++] = byte_count - 1; 2644 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 2645 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 2646 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 2647 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2648 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2649 } 2650 2651 /** 2652 * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine 2653 * 2654 * @ib: indirect buffer to copy to 2655 * @src_data: value to write to buffer 2656 * @dst_offset: dst GPU address 2657 * @byte_count: number of bytes to xfer 2658 * 2659 * Fill GPU buffers using the DMA engine (VEGA10/12). 2660 */ 2661 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib, 2662 uint32_t src_data, 2663 uint64_t dst_offset, 2664 uint32_t byte_count) 2665 { 2666 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 2667 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2668 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2669 ib->ptr[ib->length_dw++] = src_data; 2670 ib->ptr[ib->length_dw++] = byte_count - 1; 2671 } 2672 2673 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = { 2674 .copy_max_bytes = 0x400000, 2675 .copy_num_dw = 7, 2676 .emit_copy_buffer = sdma_v4_0_emit_copy_buffer, 2677 2678 .fill_max_bytes = 0x400000, 2679 .fill_num_dw = 5, 2680 .emit_fill_buffer = sdma_v4_0_emit_fill_buffer, 2681 }; 2682 2683 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev) 2684 { 2685 adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs; 2686 if (adev->sdma.has_page_queue) 2687 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page; 2688 else 2689 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 2690 } 2691 2692 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = { 2693 .copy_pte_num_dw = 7, 2694 .copy_pte = sdma_v4_0_vm_copy_pte, 2695 2696 .write_pte = sdma_v4_0_vm_write_pte, 2697 .set_pte_pde = sdma_v4_0_vm_set_pte_pde, 2698 }; 2699 2700 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev) 2701 { 2702 struct drm_gpu_scheduler *sched; 2703 unsigned i; 2704 2705 adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs; 2706 for (i = 0; i < adev->sdma.num_instances; i++) { 2707 if (adev->sdma.has_page_queue) 2708 sched = &adev->sdma.instance[i].page.sched; 2709 else 2710 sched = &adev->sdma.instance[i].ring.sched; 2711 adev->vm_manager.vm_pte_scheds[i] = sched; 2712 } 2713 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 2714 } 2715 2716 static void sdma_v4_0_get_ras_error_count(uint32_t value, 2717 uint32_t instance, 2718 uint32_t *sec_count) 2719 { 2720 uint32_t i; 2721 uint32_t sec_cnt; 2722 2723 /* double bits error (multiple bits) error detection is not supported */ 2724 for (i = 0; i < ARRAY_SIZE(sdma_v4_0_ras_fields); i++) { 2725 /* the SDMA_EDC_COUNTER register in each sdma instance 2726 * shares the same sed shift_mask 2727 * */ 2728 sec_cnt = (value & 2729 sdma_v4_0_ras_fields[i].sec_count_mask) >> 2730 sdma_v4_0_ras_fields[i].sec_count_shift; 2731 if (sec_cnt) { 2732 DRM_INFO("Detected %s in SDMA%d, SED %d\n", 2733 sdma_v4_0_ras_fields[i].name, 2734 instance, sec_cnt); 2735 *sec_count += sec_cnt; 2736 } 2737 } 2738 } 2739 2740 static int sdma_v4_0_query_ras_error_count_by_instance(struct amdgpu_device *adev, 2741 uint32_t instance, void *ras_error_status) 2742 { 2743 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 2744 uint32_t sec_count = 0; 2745 uint32_t reg_value = 0; 2746 2747 reg_value = RREG32_SDMA(instance, mmSDMA0_EDC_COUNTER); 2748 /* double bit error is not supported */ 2749 if (reg_value) 2750 sdma_v4_0_get_ras_error_count(reg_value, 2751 instance, &sec_count); 2752 /* err_data->ce_count should be initialized to 0 2753 * before calling into this function */ 2754 err_data->ce_count += sec_count; 2755 /* double bit error is not supported 2756 * set ue count to 0 */ 2757 err_data->ue_count = 0; 2758 2759 return 0; 2760 }; 2761 2762 static void sdma_v4_0_query_ras_error_count(struct amdgpu_device *adev, void *ras_error_status) 2763 { 2764 int i = 0; 2765 2766 for (i = 0; i < adev->sdma.num_instances; i++) { 2767 if (sdma_v4_0_query_ras_error_count_by_instance(adev, i, ras_error_status)) { 2768 dev_err(adev->dev, "Query ras error count failed in SDMA%d\n", i); 2769 return; 2770 } 2771 } 2772 } 2773 2774 static void sdma_v4_0_reset_ras_error_count(struct amdgpu_device *adev) 2775 { 2776 int i; 2777 2778 /* read back edc counter registers to clear the counters */ 2779 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 2780 for (i = 0; i < adev->sdma.num_instances; i++) 2781 RREG32_SDMA(i, mmSDMA0_EDC_COUNTER); 2782 } 2783 } 2784 2785 const struct amdgpu_ras_block_hw_ops sdma_v4_0_ras_hw_ops = { 2786 .query_ras_error_count = sdma_v4_0_query_ras_error_count, 2787 .reset_ras_error_count = sdma_v4_0_reset_ras_error_count, 2788 }; 2789 2790 static struct amdgpu_sdma_ras sdma_v4_0_ras = { 2791 .ras_block = { 2792 .hw_ops = &sdma_v4_0_ras_hw_ops, 2793 .ras_cb = sdma_v4_0_process_ras_data_cb, 2794 }, 2795 }; 2796 2797 static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev) 2798 { 2799 switch (adev->ip_versions[SDMA0_HWIP][0]) { 2800 case IP_VERSION(4, 2, 0): 2801 case IP_VERSION(4, 2, 2): 2802 adev->sdma.ras = &sdma_v4_0_ras; 2803 break; 2804 case IP_VERSION(4, 4, 0): 2805 adev->sdma.ras = &sdma_v4_4_ras; 2806 break; 2807 default: 2808 break; 2809 } 2810 2811 if (adev->sdma.ras) { 2812 amdgpu_ras_register_ras_block(adev, &adev->sdma.ras->ras_block); 2813 2814 strcpy(adev->sdma.ras->ras_block.ras_comm.name, "sdma"); 2815 adev->sdma.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__SDMA; 2816 adev->sdma.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; 2817 adev->sdma.ras_if = &adev->sdma.ras->ras_block.ras_comm; 2818 2819 /* If don't define special ras_late_init function, use default ras_late_init */ 2820 if (!adev->sdma.ras->ras_block.ras_late_init) 2821 adev->sdma.ras->ras_block.ras_late_init = amdgpu_sdma_ras_late_init; 2822 2823 /* If not defined special ras_cb function, use default ras_cb */ 2824 if (!adev->sdma.ras->ras_block.ras_cb) 2825 adev->sdma.ras->ras_block.ras_cb = amdgpu_sdma_process_ras_data_cb; 2826 } 2827 } 2828 2829 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = { 2830 .type = AMD_IP_BLOCK_TYPE_SDMA, 2831 .major = 4, 2832 .minor = 0, 2833 .rev = 0, 2834 .funcs = &sdma_v4_0_ip_funcs, 2835 }; 2836