1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "sdma0/sdma0_4_2_offset.h" 34 #include "sdma0/sdma0_4_2_sh_mask.h" 35 #include "sdma1/sdma1_4_2_offset.h" 36 #include "sdma1/sdma1_4_2_sh_mask.h" 37 #include "sdma2/sdma2_4_2_2_offset.h" 38 #include "sdma2/sdma2_4_2_2_sh_mask.h" 39 #include "sdma3/sdma3_4_2_2_offset.h" 40 #include "sdma3/sdma3_4_2_2_sh_mask.h" 41 #include "sdma4/sdma4_4_2_2_offset.h" 42 #include "sdma4/sdma4_4_2_2_sh_mask.h" 43 #include "sdma5/sdma5_4_2_2_offset.h" 44 #include "sdma5/sdma5_4_2_2_sh_mask.h" 45 #include "sdma6/sdma6_4_2_2_offset.h" 46 #include "sdma6/sdma6_4_2_2_sh_mask.h" 47 #include "sdma7/sdma7_4_2_2_offset.h" 48 #include "sdma7/sdma7_4_2_2_sh_mask.h" 49 #include "hdp/hdp_4_0_offset.h" 50 #include "sdma0/sdma0_4_1_default.h" 51 52 #include "soc15_common.h" 53 #include "soc15.h" 54 #include "vega10_sdma_pkt_open.h" 55 56 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h" 57 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h" 58 59 #include "amdgpu_ras.h" 60 61 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin"); 62 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin"); 63 MODULE_FIRMWARE("amdgpu/vega12_sdma.bin"); 64 MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin"); 65 MODULE_FIRMWARE("amdgpu/vega20_sdma.bin"); 66 MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin"); 67 MODULE_FIRMWARE("amdgpu/raven_sdma.bin"); 68 MODULE_FIRMWARE("amdgpu/picasso_sdma.bin"); 69 MODULE_FIRMWARE("amdgpu/raven2_sdma.bin"); 70 MODULE_FIRMWARE("amdgpu/arcturus_sdma.bin"); 71 MODULE_FIRMWARE("amdgpu/renoir_sdma.bin"); 72 73 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L 74 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L 75 76 #define WREG32_SDMA(instance, offset, value) \ 77 WREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)), value) 78 #define RREG32_SDMA(instance, offset) \ 79 RREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset))) 80 81 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev); 82 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev); 83 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev); 84 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev); 85 static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev); 86 87 static const struct soc15_reg_golden golden_settings_sdma_4[] = { 88 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 89 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100), 90 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100), 91 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 92 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 93 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 94 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000), 95 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 96 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 97 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 98 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 99 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 100 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000), 101 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), 102 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100), 103 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 104 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 105 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 106 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000), 107 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 108 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 109 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 110 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 111 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0), 112 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xfc000000, 0x00000000) 113 }; 114 115 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = { 116 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 117 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 118 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 119 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 120 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 121 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 122 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 123 }; 124 125 static const struct soc15_reg_golden golden_settings_sdma_vg12[] = { 126 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), 127 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001), 128 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 129 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 130 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), 131 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001), 132 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 133 }; 134 135 static const struct soc15_reg_golden golden_settings_sdma_4_1[] = { 136 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 137 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 138 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100), 139 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 140 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051), 141 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100), 142 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 143 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100), 144 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 145 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 146 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000) 147 }; 148 149 static const struct soc15_reg_golden golden_settings_sdma0_4_2_init[] = { 150 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 151 }; 152 153 static const struct soc15_reg_golden golden_settings_sdma0_4_2[] = 154 { 155 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 156 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 157 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 158 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 159 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 160 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 161 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 162 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 163 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RD_BURST_CNTL, 0x0000000f, 0x00000003), 164 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 165 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 166 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 167 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 168 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 169 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 170 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 171 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 172 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 173 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 174 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 175 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 176 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 177 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 178 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 179 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 180 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 181 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 182 }; 183 184 static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = { 185 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 186 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), 187 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 188 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 189 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 190 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 191 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 192 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 193 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RD_BURST_CNTL, 0x0000000f, 0x00000003), 194 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 195 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 196 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 197 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 198 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 199 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 200 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 201 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 202 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 203 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 204 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 205 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 206 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 207 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 208 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 209 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 210 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0), 211 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 212 }; 213 214 static const struct soc15_reg_golden golden_settings_sdma_rv1[] = 215 { 216 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002), 217 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002) 218 }; 219 220 static const struct soc15_reg_golden golden_settings_sdma_rv2[] = 221 { 222 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00003001), 223 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003001) 224 }; 225 226 static const struct soc15_reg_golden golden_settings_sdma_arct[] = 227 { 228 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 229 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 230 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 231 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 232 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 233 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 234 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 235 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 236 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 237 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 238 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 239 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 240 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 241 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 242 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 243 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 244 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 245 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 246 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 247 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 248 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 249 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 250 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 251 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 252 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 253 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 254 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 255 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 256 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 257 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 258 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 259 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_UTCL1_TIMEOUT, 0xffffffff, 0x00010001) 260 }; 261 262 static const struct soc15_reg_golden golden_settings_sdma_4_3[] = { 263 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 264 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 265 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002), 266 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002), 267 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 268 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003fff07, 0x40000051), 269 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 270 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 271 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 272 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x03fbe1fe) 273 }; 274 275 static const struct soc15_ras_field_entry sdma_v4_0_ras_fields[] = { 276 { "SDMA_UCODE_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 277 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UCODE_BUF_SED), 278 0, 0, 279 }, 280 { "SDMA_RB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 281 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_RB_CMD_BUF_SED), 282 0, 0, 283 }, 284 { "SDMA_IB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 285 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_IB_CMD_BUF_SED), 286 0, 0, 287 }, 288 { "SDMA_UTCL1_RD_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 289 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UTCL1_RD_FIFO_SED), 290 0, 0, 291 }, 292 { "SDMA_UTCL1_RDBST_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 293 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UTCL1_RDBST_FIFO_SED), 294 0, 0, 295 }, 296 { "SDMA_DATA_LUT_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 297 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_DATA_LUT_FIFO_SED), 298 0, 0, 299 }, 300 { "SDMA_MBANK_DATA_BUF0_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 301 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF0_SED), 302 0, 0, 303 }, 304 { "SDMA_MBANK_DATA_BUF1_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 305 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF1_SED), 306 0, 0, 307 }, 308 { "SDMA_MBANK_DATA_BUF2_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 309 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF2_SED), 310 0, 0, 311 }, 312 { "SDMA_MBANK_DATA_BUF3_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 313 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF3_SED), 314 0, 0, 315 }, 316 { "SDMA_MBANK_DATA_BUF4_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 317 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF4_SED), 318 0, 0, 319 }, 320 { "SDMA_MBANK_DATA_BUF5_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 321 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF5_SED), 322 0, 0, 323 }, 324 { "SDMA_MBANK_DATA_BUF6_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 325 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF6_SED), 326 0, 0, 327 }, 328 { "SDMA_MBANK_DATA_BUF7_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 329 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF7_SED), 330 0, 0, 331 }, 332 { "SDMA_MBANK_DATA_BUF8_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 333 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF8_SED), 334 0, 0, 335 }, 336 { "SDMA_MBANK_DATA_BUF9_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 337 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF9_SED), 338 0, 0, 339 }, 340 { "SDMA_MBANK_DATA_BUF10_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 341 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF10_SED), 342 0, 0, 343 }, 344 { "SDMA_MBANK_DATA_BUF11_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 345 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF11_SED), 346 0, 0, 347 }, 348 { "SDMA_MBANK_DATA_BUF12_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 349 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF12_SED), 350 0, 0, 351 }, 352 { "SDMA_MBANK_DATA_BUF13_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 353 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF13_SED), 354 0, 0, 355 }, 356 { "SDMA_MBANK_DATA_BUF14_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 357 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF14_SED), 358 0, 0, 359 }, 360 { "SDMA_MBANK_DATA_BUF15_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 361 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF15_SED), 362 0, 0, 363 }, 364 { "SDMA_SPLIT_DAT_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 365 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_SPLIT_DAT_BUF_SED), 366 0, 0, 367 }, 368 { "SDMA_MC_WR_ADDR_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 369 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MC_WR_ADDR_FIFO_SED), 370 0, 0, 371 }, 372 }; 373 374 static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev, 375 u32 instance, u32 offset) 376 { 377 switch (instance) { 378 case 0: 379 return (adev->reg_offset[SDMA0_HWIP][0][0] + offset); 380 case 1: 381 return (adev->reg_offset[SDMA1_HWIP][0][0] + offset); 382 case 2: 383 return (adev->reg_offset[SDMA2_HWIP][0][1] + offset); 384 case 3: 385 return (adev->reg_offset[SDMA3_HWIP][0][1] + offset); 386 case 4: 387 return (adev->reg_offset[SDMA4_HWIP][0][1] + offset); 388 case 5: 389 return (adev->reg_offset[SDMA5_HWIP][0][1] + offset); 390 case 6: 391 return (adev->reg_offset[SDMA6_HWIP][0][1] + offset); 392 case 7: 393 return (adev->reg_offset[SDMA7_HWIP][0][1] + offset); 394 default: 395 break; 396 } 397 return 0; 398 } 399 400 static unsigned sdma_v4_0_seq_to_irq_id(int seq_num) 401 { 402 switch (seq_num) { 403 case 0: 404 return SOC15_IH_CLIENTID_SDMA0; 405 case 1: 406 return SOC15_IH_CLIENTID_SDMA1; 407 case 2: 408 return SOC15_IH_CLIENTID_SDMA2; 409 case 3: 410 return SOC15_IH_CLIENTID_SDMA3; 411 case 4: 412 return SOC15_IH_CLIENTID_SDMA4; 413 case 5: 414 return SOC15_IH_CLIENTID_SDMA5; 415 case 6: 416 return SOC15_IH_CLIENTID_SDMA6; 417 case 7: 418 return SOC15_IH_CLIENTID_SDMA7; 419 default: 420 break; 421 } 422 return -EINVAL; 423 } 424 425 static int sdma_v4_0_irq_id_to_seq(unsigned client_id) 426 { 427 switch (client_id) { 428 case SOC15_IH_CLIENTID_SDMA0: 429 return 0; 430 case SOC15_IH_CLIENTID_SDMA1: 431 return 1; 432 case SOC15_IH_CLIENTID_SDMA2: 433 return 2; 434 case SOC15_IH_CLIENTID_SDMA3: 435 return 3; 436 case SOC15_IH_CLIENTID_SDMA4: 437 return 4; 438 case SOC15_IH_CLIENTID_SDMA5: 439 return 5; 440 case SOC15_IH_CLIENTID_SDMA6: 441 return 6; 442 case SOC15_IH_CLIENTID_SDMA7: 443 return 7; 444 default: 445 break; 446 } 447 return -EINVAL; 448 } 449 450 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) 451 { 452 switch (adev->asic_type) { 453 case CHIP_VEGA10: 454 soc15_program_register_sequence(adev, 455 golden_settings_sdma_4, 456 ARRAY_SIZE(golden_settings_sdma_4)); 457 soc15_program_register_sequence(adev, 458 golden_settings_sdma_vg10, 459 ARRAY_SIZE(golden_settings_sdma_vg10)); 460 break; 461 case CHIP_VEGA12: 462 soc15_program_register_sequence(adev, 463 golden_settings_sdma_4, 464 ARRAY_SIZE(golden_settings_sdma_4)); 465 soc15_program_register_sequence(adev, 466 golden_settings_sdma_vg12, 467 ARRAY_SIZE(golden_settings_sdma_vg12)); 468 break; 469 case CHIP_VEGA20: 470 soc15_program_register_sequence(adev, 471 golden_settings_sdma0_4_2_init, 472 ARRAY_SIZE(golden_settings_sdma0_4_2_init)); 473 soc15_program_register_sequence(adev, 474 golden_settings_sdma0_4_2, 475 ARRAY_SIZE(golden_settings_sdma0_4_2)); 476 soc15_program_register_sequence(adev, 477 golden_settings_sdma1_4_2, 478 ARRAY_SIZE(golden_settings_sdma1_4_2)); 479 break; 480 case CHIP_ARCTURUS: 481 soc15_program_register_sequence(adev, 482 golden_settings_sdma_arct, 483 ARRAY_SIZE(golden_settings_sdma_arct)); 484 break; 485 case CHIP_RAVEN: 486 soc15_program_register_sequence(adev, 487 golden_settings_sdma_4_1, 488 ARRAY_SIZE(golden_settings_sdma_4_1)); 489 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 490 soc15_program_register_sequence(adev, 491 golden_settings_sdma_rv2, 492 ARRAY_SIZE(golden_settings_sdma_rv2)); 493 else 494 soc15_program_register_sequence(adev, 495 golden_settings_sdma_rv1, 496 ARRAY_SIZE(golden_settings_sdma_rv1)); 497 break; 498 case CHIP_RENOIR: 499 soc15_program_register_sequence(adev, 500 golden_settings_sdma_4_3, 501 ARRAY_SIZE(golden_settings_sdma_4_3)); 502 break; 503 default: 504 break; 505 } 506 } 507 508 static void sdma_v4_0_setup_ulv(struct amdgpu_device *adev) 509 { 510 int i; 511 512 /* 513 * The only chips with SDMAv4 and ULV are VG10 and VG20. 514 * Server SKUs take a different hysteresis setting from other SKUs. 515 */ 516 switch (adev->asic_type) { 517 case CHIP_VEGA10: 518 if (adev->pdev->device == 0x6860) 519 break; 520 return; 521 case CHIP_VEGA20: 522 if (adev->pdev->device == 0x66a1) 523 break; 524 return; 525 default: 526 return; 527 } 528 529 for (i = 0; i < adev->sdma.num_instances; i++) { 530 uint32_t temp; 531 532 temp = RREG32_SDMA(i, mmSDMA0_ULV_CNTL); 533 temp = REG_SET_FIELD(temp, SDMA0_ULV_CNTL, HYSTERESIS, 0x0); 534 WREG32_SDMA(i, mmSDMA0_ULV_CNTL, temp); 535 } 536 } 537 538 static int sdma_v4_0_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst) 539 { 540 int err = 0; 541 const struct sdma_firmware_header_v1_0 *hdr; 542 543 err = amdgpu_ucode_validate(sdma_inst->fw); 544 if (err) 545 return err; 546 547 hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data; 548 sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version); 549 sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version); 550 551 if (sdma_inst->feature_version >= 20) 552 sdma_inst->burst_nop = true; 553 554 return 0; 555 } 556 557 static void sdma_v4_0_destroy_inst_ctx(struct amdgpu_device *adev) 558 { 559 int i; 560 561 for (i = 0; i < adev->sdma.num_instances; i++) { 562 release_firmware(adev->sdma.instance[i].fw); 563 adev->sdma.instance[i].fw = NULL; 564 565 /* arcturus shares the same FW memory across 566 all SDMA isntances */ 567 if (adev->asic_type == CHIP_ARCTURUS) 568 break; 569 } 570 571 memset((void*)adev->sdma.instance, 0, 572 sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES); 573 } 574 575 /** 576 * sdma_v4_0_init_microcode - load ucode images from disk 577 * 578 * @adev: amdgpu_device pointer 579 * 580 * Use the firmware interface to load the ucode images into 581 * the driver (not loaded into hw). 582 * Returns 0 on success, error on failure. 583 */ 584 585 // emulation only, won't work on real chip 586 // vega10 real chip need to use PSP to load firmware 587 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev) 588 { 589 const char *chip_name; 590 char fw_name[30]; 591 int err = 0, i; 592 struct amdgpu_firmware_info *info = NULL; 593 const struct common_firmware_header *header = NULL; 594 595 DRM_DEBUG("\n"); 596 597 switch (adev->asic_type) { 598 case CHIP_VEGA10: 599 chip_name = "vega10"; 600 break; 601 case CHIP_VEGA12: 602 chip_name = "vega12"; 603 break; 604 case CHIP_VEGA20: 605 chip_name = "vega20"; 606 break; 607 case CHIP_RAVEN: 608 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 609 chip_name = "raven2"; 610 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 611 chip_name = "picasso"; 612 else 613 chip_name = "raven"; 614 break; 615 case CHIP_ARCTURUS: 616 chip_name = "arcturus"; 617 break; 618 case CHIP_RENOIR: 619 chip_name = "renoir"; 620 break; 621 default: 622 BUG(); 623 } 624 625 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 626 627 err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev); 628 if (err) 629 goto out; 630 631 err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[0]); 632 if (err) 633 goto out; 634 635 for (i = 1; i < adev->sdma.num_instances; i++) { 636 if (adev->asic_type == CHIP_ARCTURUS) { 637 /* Acturus will leverage the same FW memory 638 for every SDMA instance */ 639 memcpy((void*)&adev->sdma.instance[i], 640 (void*)&adev->sdma.instance[0], 641 sizeof(struct amdgpu_sdma_instance)); 642 } 643 else { 644 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i); 645 646 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 647 if (err) 648 goto out; 649 650 err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[i]); 651 if (err) 652 goto out; 653 } 654 } 655 656 DRM_DEBUG("psp_load == '%s'\n", 657 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); 658 659 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 660 for (i = 0; i < adev->sdma.num_instances; i++) { 661 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 662 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 663 info->fw = adev->sdma.instance[i].fw; 664 header = (const struct common_firmware_header *)info->fw->data; 665 adev->firmware.fw_size += 666 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 667 } 668 } 669 670 out: 671 if (err) { 672 DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name); 673 sdma_v4_0_destroy_inst_ctx(adev); 674 } 675 return err; 676 } 677 678 /** 679 * sdma_v4_0_ring_get_rptr - get the current read pointer 680 * 681 * @ring: amdgpu ring pointer 682 * 683 * Get the current rptr from the hardware (VEGA10+). 684 */ 685 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring) 686 { 687 u64 *rptr; 688 689 /* XXX check if swapping is necessary on BE */ 690 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]); 691 692 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 693 return ((*rptr) >> 2); 694 } 695 696 /** 697 * sdma_v4_0_ring_get_wptr - get the current write pointer 698 * 699 * @ring: amdgpu ring pointer 700 * 701 * Get the current wptr from the hardware (VEGA10+). 702 */ 703 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring) 704 { 705 struct amdgpu_device *adev = ring->adev; 706 u64 wptr; 707 708 if (ring->use_doorbell) { 709 /* XXX check if swapping is necessary on BE */ 710 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 711 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 712 } else { 713 wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI); 714 wptr = wptr << 32; 715 wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR); 716 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", 717 ring->me, wptr); 718 } 719 720 return wptr >> 2; 721 } 722 723 /** 724 * sdma_v4_0_page_ring_set_wptr - commit the write pointer 725 * 726 * @ring: amdgpu ring pointer 727 * 728 * Write the wptr back to the hardware (VEGA10+). 729 */ 730 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring) 731 { 732 struct amdgpu_device *adev = ring->adev; 733 734 DRM_DEBUG("Setting write pointer\n"); 735 if (ring->use_doorbell) { 736 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 737 738 DRM_DEBUG("Using doorbell -- " 739 "wptr_offs == 0x%08x " 740 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 741 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 742 ring->wptr_offs, 743 lower_32_bits(ring->wptr << 2), 744 upper_32_bits(ring->wptr << 2)); 745 /* XXX check if swapping is necessary on BE */ 746 WRITE_ONCE(*wb, (ring->wptr << 2)); 747 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 748 ring->doorbell_index, ring->wptr << 2); 749 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 750 } else { 751 DRM_DEBUG("Not using doorbell -- " 752 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 753 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 754 ring->me, 755 lower_32_bits(ring->wptr << 2), 756 ring->me, 757 upper_32_bits(ring->wptr << 2)); 758 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR, 759 lower_32_bits(ring->wptr << 2)); 760 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI, 761 upper_32_bits(ring->wptr << 2)); 762 } 763 } 764 765 /** 766 * sdma_v4_0_page_ring_get_wptr - get the current write pointer 767 * 768 * @ring: amdgpu ring pointer 769 * 770 * Get the current wptr from the hardware (VEGA10+). 771 */ 772 static uint64_t sdma_v4_0_page_ring_get_wptr(struct amdgpu_ring *ring) 773 { 774 struct amdgpu_device *adev = ring->adev; 775 u64 wptr; 776 777 if (ring->use_doorbell) { 778 /* XXX check if swapping is necessary on BE */ 779 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 780 } else { 781 wptr = RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI); 782 wptr = wptr << 32; 783 wptr |= RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR); 784 } 785 786 return wptr >> 2; 787 } 788 789 /** 790 * sdma_v4_0_ring_set_wptr - commit the write pointer 791 * 792 * @ring: amdgpu ring pointer 793 * 794 * Write the wptr back to the hardware (VEGA10+). 795 */ 796 static void sdma_v4_0_page_ring_set_wptr(struct amdgpu_ring *ring) 797 { 798 struct amdgpu_device *adev = ring->adev; 799 800 if (ring->use_doorbell) { 801 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 802 803 /* XXX check if swapping is necessary on BE */ 804 WRITE_ONCE(*wb, (ring->wptr << 2)); 805 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 806 } else { 807 uint64_t wptr = ring->wptr << 2; 808 809 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR, 810 lower_32_bits(wptr)); 811 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI, 812 upper_32_bits(wptr)); 813 } 814 } 815 816 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 817 { 818 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 819 int i; 820 821 for (i = 0; i < count; i++) 822 if (sdma && sdma->burst_nop && (i == 0)) 823 amdgpu_ring_write(ring, ring->funcs->nop | 824 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 825 else 826 amdgpu_ring_write(ring, ring->funcs->nop); 827 } 828 829 /** 830 * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine 831 * 832 * @ring: amdgpu ring pointer 833 * @ib: IB object to schedule 834 * 835 * Schedule an IB in the DMA ring (VEGA10). 836 */ 837 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring, 838 struct amdgpu_job *job, 839 struct amdgpu_ib *ib, 840 uint32_t flags) 841 { 842 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 843 844 /* IB packet must end on a 8 DW boundary */ 845 sdma_v4_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 846 847 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 848 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 849 /* base must be 32 byte aligned */ 850 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 851 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 852 amdgpu_ring_write(ring, ib->length_dw); 853 amdgpu_ring_write(ring, 0); 854 amdgpu_ring_write(ring, 0); 855 856 } 857 858 static void sdma_v4_0_wait_reg_mem(struct amdgpu_ring *ring, 859 int mem_space, int hdp, 860 uint32_t addr0, uint32_t addr1, 861 uint32_t ref, uint32_t mask, 862 uint32_t inv) 863 { 864 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 865 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) | 866 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) | 867 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 868 if (mem_space) { 869 /* memory */ 870 amdgpu_ring_write(ring, addr0); 871 amdgpu_ring_write(ring, addr1); 872 } else { 873 /* registers */ 874 amdgpu_ring_write(ring, addr0 << 2); 875 amdgpu_ring_write(ring, addr1 << 2); 876 } 877 amdgpu_ring_write(ring, ref); /* reference */ 878 amdgpu_ring_write(ring, mask); /* mask */ 879 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 880 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */ 881 } 882 883 /** 884 * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 885 * 886 * @ring: amdgpu ring pointer 887 * 888 * Emit an hdp flush packet on the requested DMA ring. 889 */ 890 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 891 { 892 struct amdgpu_device *adev = ring->adev; 893 u32 ref_and_mask = 0; 894 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 895 896 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; 897 898 sdma_v4_0_wait_reg_mem(ring, 0, 1, 899 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 900 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 901 ref_and_mask, ref_and_mask, 10); 902 } 903 904 /** 905 * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring 906 * 907 * @ring: amdgpu ring pointer 908 * @fence: amdgpu fence object 909 * 910 * Add a DMA fence packet to the ring to write 911 * the fence seq number and DMA trap packet to generate 912 * an interrupt if needed (VEGA10). 913 */ 914 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 915 unsigned flags) 916 { 917 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 918 /* write the fence */ 919 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 920 /* zero in first two bits */ 921 BUG_ON(addr & 0x3); 922 amdgpu_ring_write(ring, lower_32_bits(addr)); 923 amdgpu_ring_write(ring, upper_32_bits(addr)); 924 amdgpu_ring_write(ring, lower_32_bits(seq)); 925 926 /* optionally write high bits as well */ 927 if (write64bit) { 928 addr += 4; 929 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 930 /* zero in first two bits */ 931 BUG_ON(addr & 0x3); 932 amdgpu_ring_write(ring, lower_32_bits(addr)); 933 amdgpu_ring_write(ring, upper_32_bits(addr)); 934 amdgpu_ring_write(ring, upper_32_bits(seq)); 935 } 936 937 /* generate an interrupt */ 938 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 939 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 940 } 941 942 943 /** 944 * sdma_v4_0_gfx_stop - stop the gfx async dma engines 945 * 946 * @adev: amdgpu_device pointer 947 * 948 * Stop the gfx async dma ring buffers (VEGA10). 949 */ 950 static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev) 951 { 952 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; 953 u32 rb_cntl, ib_cntl; 954 int i, unset = 0; 955 956 for (i = 0; i < adev->sdma.num_instances; i++) { 957 sdma[i] = &adev->sdma.instance[i].ring; 958 959 if ((adev->mman.buffer_funcs_ring == sdma[i]) && unset != 1) { 960 amdgpu_ttm_set_buffer_funcs_status(adev, false); 961 unset = 1; 962 } 963 964 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL); 965 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 966 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 967 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL); 968 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 969 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl); 970 } 971 } 972 973 /** 974 * sdma_v4_0_rlc_stop - stop the compute async dma engines 975 * 976 * @adev: amdgpu_device pointer 977 * 978 * Stop the compute async dma queues (VEGA10). 979 */ 980 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev) 981 { 982 /* XXX todo */ 983 } 984 985 /** 986 * sdma_v4_0_page_stop - stop the page async dma engines 987 * 988 * @adev: amdgpu_device pointer 989 * 990 * Stop the page async dma ring buffers (VEGA10). 991 */ 992 static void sdma_v4_0_page_stop(struct amdgpu_device *adev) 993 { 994 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; 995 u32 rb_cntl, ib_cntl; 996 int i; 997 bool unset = false; 998 999 for (i = 0; i < adev->sdma.num_instances; i++) { 1000 sdma[i] = &adev->sdma.instance[i].page; 1001 1002 if ((adev->mman.buffer_funcs_ring == sdma[i]) && 1003 (unset == false)) { 1004 amdgpu_ttm_set_buffer_funcs_status(adev, false); 1005 unset = true; 1006 } 1007 1008 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL); 1009 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, 1010 RB_ENABLE, 0); 1011 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 1012 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL); 1013 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, 1014 IB_ENABLE, 0); 1015 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl); 1016 } 1017 } 1018 1019 /** 1020 * sdma_v4_0_ctx_switch_enable - stop the async dma engines context switch 1021 * 1022 * @adev: amdgpu_device pointer 1023 * @enable: enable/disable the DMA MEs context switch. 1024 * 1025 * Halt or unhalt the async dma engines context switch (VEGA10). 1026 */ 1027 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 1028 { 1029 u32 f32_cntl, phase_quantum = 0; 1030 int i; 1031 1032 if (amdgpu_sdma_phase_quantum) { 1033 unsigned value = amdgpu_sdma_phase_quantum; 1034 unsigned unit = 0; 1035 1036 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 1037 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 1038 value = (value + 1) >> 1; 1039 unit++; 1040 } 1041 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 1042 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 1043 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 1044 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 1045 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 1046 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 1047 WARN_ONCE(1, 1048 "clamping sdma_phase_quantum to %uK clock cycles\n", 1049 value << unit); 1050 } 1051 phase_quantum = 1052 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 1053 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 1054 } 1055 1056 for (i = 0; i < adev->sdma.num_instances; i++) { 1057 f32_cntl = RREG32_SDMA(i, mmSDMA0_CNTL); 1058 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 1059 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 1060 if (enable && amdgpu_sdma_phase_quantum) { 1061 WREG32_SDMA(i, mmSDMA0_PHASE0_QUANTUM, phase_quantum); 1062 WREG32_SDMA(i, mmSDMA0_PHASE1_QUANTUM, phase_quantum); 1063 WREG32_SDMA(i, mmSDMA0_PHASE2_QUANTUM, phase_quantum); 1064 } 1065 WREG32_SDMA(i, mmSDMA0_CNTL, f32_cntl); 1066 1067 /* 1068 * Enable SDMA utilization. Its only supported on 1069 * Arcturus for the moment and firmware version 14 1070 * and above. 1071 */ 1072 if (adev->asic_type == CHIP_ARCTURUS && 1073 adev->sdma.instance[i].fw_version >= 14) 1074 WREG32_SDMA(i, mmSDMA0_PUB_DUMMY_REG2, enable); 1075 } 1076 1077 } 1078 1079 /** 1080 * sdma_v4_0_enable - stop the async dma engines 1081 * 1082 * @adev: amdgpu_device pointer 1083 * @enable: enable/disable the DMA MEs. 1084 * 1085 * Halt or unhalt the async dma engines (VEGA10). 1086 */ 1087 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable) 1088 { 1089 u32 f32_cntl; 1090 int i; 1091 1092 if (enable == false) { 1093 sdma_v4_0_gfx_stop(adev); 1094 sdma_v4_0_rlc_stop(adev); 1095 if (adev->sdma.has_page_queue) 1096 sdma_v4_0_page_stop(adev); 1097 } 1098 1099 for (i = 0; i < adev->sdma.num_instances; i++) { 1100 f32_cntl = RREG32_SDMA(i, mmSDMA0_F32_CNTL); 1101 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 1102 WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl); 1103 } 1104 } 1105 1106 /** 1107 * sdma_v4_0_rb_cntl - get parameters for rb_cntl 1108 */ 1109 static uint32_t sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl) 1110 { 1111 /* Set ring buffer size in dwords */ 1112 uint32_t rb_bufsz = order_base_2(ring->ring_size / 4); 1113 1114 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 1115 #ifdef __BIG_ENDIAN 1116 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 1117 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 1118 RPTR_WRITEBACK_SWAP_ENABLE, 1); 1119 #endif 1120 return rb_cntl; 1121 } 1122 1123 /** 1124 * sdma_v4_0_gfx_resume - setup and start the async dma engines 1125 * 1126 * @adev: amdgpu_device pointer 1127 * @i: instance to resume 1128 * 1129 * Set up the gfx DMA ring buffers and enable them (VEGA10). 1130 * Returns 0 for success, error for failure. 1131 */ 1132 static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i) 1133 { 1134 struct amdgpu_ring *ring = &adev->sdma.instance[i].ring; 1135 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 1136 u32 wb_offset; 1137 u32 doorbell; 1138 u32 doorbell_offset; 1139 u64 wptr_gpu_addr; 1140 1141 wb_offset = (ring->rptr_offs * 4); 1142 1143 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL); 1144 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl); 1145 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 1146 1147 /* Initialize the ring buffer's read and write pointers */ 1148 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR, 0); 1149 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_HI, 0); 1150 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR, 0); 1151 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_HI, 0); 1152 1153 /* set the wb address whether it's enabled or not */ 1154 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI, 1155 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 1156 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 1157 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 1158 1159 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 1160 RPTR_WRITEBACK_ENABLE, 1); 1161 1162 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE, ring->gpu_addr >> 8); 1163 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE_HI, ring->gpu_addr >> 40); 1164 1165 ring->wptr = 0; 1166 1167 /* before programing wptr to a less value, need set minor_ptr_update first */ 1168 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 1); 1169 1170 doorbell = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL); 1171 doorbell_offset = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET); 1172 1173 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1174 ring->use_doorbell); 1175 doorbell_offset = REG_SET_FIELD(doorbell_offset, 1176 SDMA0_GFX_DOORBELL_OFFSET, 1177 OFFSET, ring->doorbell_index); 1178 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL, doorbell); 1179 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET, doorbell_offset); 1180 1181 sdma_v4_0_ring_set_wptr(ring); 1182 1183 /* set minor_ptr_update to 0 after wptr programed */ 1184 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 0); 1185 1186 /* setup the wptr shadow polling */ 1187 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1188 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO, 1189 lower_32_bits(wptr_gpu_addr)); 1190 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI, 1191 upper_32_bits(wptr_gpu_addr)); 1192 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL); 1193 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 1194 SDMA0_GFX_RB_WPTR_POLL_CNTL, 1195 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 1196 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 1197 1198 /* enable DMA RB */ 1199 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 1200 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 1201 1202 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL); 1203 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 1204 #ifdef __BIG_ENDIAN 1205 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 1206 #endif 1207 /* enable DMA IBs */ 1208 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl); 1209 1210 ring->sched.ready = true; 1211 } 1212 1213 /** 1214 * sdma_v4_0_page_resume - setup and start the async dma engines 1215 * 1216 * @adev: amdgpu_device pointer 1217 * @i: instance to resume 1218 * 1219 * Set up the page DMA ring buffers and enable them (VEGA10). 1220 * Returns 0 for success, error for failure. 1221 */ 1222 static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i) 1223 { 1224 struct amdgpu_ring *ring = &adev->sdma.instance[i].page; 1225 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 1226 u32 wb_offset; 1227 u32 doorbell; 1228 u32 doorbell_offset; 1229 u64 wptr_gpu_addr; 1230 1231 wb_offset = (ring->rptr_offs * 4); 1232 1233 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL); 1234 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl); 1235 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 1236 1237 /* Initialize the ring buffer's read and write pointers */ 1238 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR, 0); 1239 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_HI, 0); 1240 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR, 0); 1241 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_HI, 0); 1242 1243 /* set the wb address whether it's enabled or not */ 1244 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_HI, 1245 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 1246 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 1247 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 1248 1249 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, 1250 RPTR_WRITEBACK_ENABLE, 1); 1251 1252 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE, ring->gpu_addr >> 8); 1253 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE_HI, ring->gpu_addr >> 40); 1254 1255 ring->wptr = 0; 1256 1257 /* before programing wptr to a less value, need set minor_ptr_update first */ 1258 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 1); 1259 1260 doorbell = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL); 1261 doorbell_offset = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET); 1262 1263 doorbell = REG_SET_FIELD(doorbell, SDMA0_PAGE_DOORBELL, ENABLE, 1264 ring->use_doorbell); 1265 doorbell_offset = REG_SET_FIELD(doorbell_offset, 1266 SDMA0_PAGE_DOORBELL_OFFSET, 1267 OFFSET, ring->doorbell_index); 1268 WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL, doorbell); 1269 WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET, doorbell_offset); 1270 1271 /* paging queue doorbell range is setup at sdma_v4_0_gfx_resume */ 1272 sdma_v4_0_page_ring_set_wptr(ring); 1273 1274 /* set minor_ptr_update to 0 after wptr programed */ 1275 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 0); 1276 1277 /* setup the wptr shadow polling */ 1278 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1279 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO, 1280 lower_32_bits(wptr_gpu_addr)); 1281 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI, 1282 upper_32_bits(wptr_gpu_addr)); 1283 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL); 1284 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 1285 SDMA0_PAGE_RB_WPTR_POLL_CNTL, 1286 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 1287 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 1288 1289 /* enable DMA RB */ 1290 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, RB_ENABLE, 1); 1291 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 1292 1293 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL); 1294 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_ENABLE, 1); 1295 #ifdef __BIG_ENDIAN 1296 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1); 1297 #endif 1298 /* enable DMA IBs */ 1299 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl); 1300 1301 ring->sched.ready = true; 1302 } 1303 1304 static void 1305 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable) 1306 { 1307 uint32_t def, data; 1308 1309 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) { 1310 /* enable idle interrupt */ 1311 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 1312 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 1313 1314 if (data != def) 1315 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 1316 } else { 1317 /* disable idle interrupt */ 1318 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 1319 data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 1320 if (data != def) 1321 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 1322 } 1323 } 1324 1325 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev) 1326 { 1327 uint32_t def, data; 1328 1329 /* Enable HW based PG. */ 1330 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1331 data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK; 1332 if (data != def) 1333 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1334 1335 /* enable interrupt */ 1336 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 1337 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 1338 if (data != def) 1339 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 1340 1341 /* Configure hold time to filter in-valid power on/off request. Use default right now */ 1342 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1343 data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK; 1344 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK); 1345 /* Configure switch time for hysteresis purpose. Use default right now */ 1346 data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK; 1347 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK); 1348 if(data != def) 1349 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1350 } 1351 1352 static void sdma_v4_0_init_pg(struct amdgpu_device *adev) 1353 { 1354 if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA)) 1355 return; 1356 1357 switch (adev->asic_type) { 1358 case CHIP_RAVEN: 1359 case CHIP_RENOIR: 1360 sdma_v4_1_init_power_gating(adev); 1361 sdma_v4_1_update_power_gating(adev, true); 1362 break; 1363 default: 1364 break; 1365 } 1366 } 1367 1368 /** 1369 * sdma_v4_0_rlc_resume - setup and start the async dma engines 1370 * 1371 * @adev: amdgpu_device pointer 1372 * 1373 * Set up the compute DMA queues and enable them (VEGA10). 1374 * Returns 0 for success, error for failure. 1375 */ 1376 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev) 1377 { 1378 sdma_v4_0_init_pg(adev); 1379 1380 return 0; 1381 } 1382 1383 /** 1384 * sdma_v4_0_load_microcode - load the sDMA ME ucode 1385 * 1386 * @adev: amdgpu_device pointer 1387 * 1388 * Loads the sDMA0/1 ucode. 1389 * Returns 0 for success, -EINVAL if the ucode is not available. 1390 */ 1391 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev) 1392 { 1393 const struct sdma_firmware_header_v1_0 *hdr; 1394 const __le32 *fw_data; 1395 u32 fw_size; 1396 int i, j; 1397 1398 /* halt the MEs */ 1399 sdma_v4_0_enable(adev, false); 1400 1401 for (i = 0; i < adev->sdma.num_instances; i++) { 1402 if (!adev->sdma.instance[i].fw) 1403 return -EINVAL; 1404 1405 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 1406 amdgpu_ucode_print_sdma_hdr(&hdr->header); 1407 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1408 1409 fw_data = (const __le32 *) 1410 (adev->sdma.instance[i].fw->data + 1411 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1412 1413 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 0); 1414 1415 for (j = 0; j < fw_size; j++) 1416 WREG32_SDMA(i, mmSDMA0_UCODE_DATA, 1417 le32_to_cpup(fw_data++)); 1418 1419 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 1420 adev->sdma.instance[i].fw_version); 1421 } 1422 1423 return 0; 1424 } 1425 1426 /** 1427 * sdma_v4_0_start - setup and start the async dma engines 1428 * 1429 * @adev: amdgpu_device pointer 1430 * 1431 * Set up the DMA engines and enable them (VEGA10). 1432 * Returns 0 for success, error for failure. 1433 */ 1434 static int sdma_v4_0_start(struct amdgpu_device *adev) 1435 { 1436 struct amdgpu_ring *ring; 1437 int i, r = 0; 1438 1439 if (amdgpu_sriov_vf(adev)) { 1440 sdma_v4_0_ctx_switch_enable(adev, false); 1441 sdma_v4_0_enable(adev, false); 1442 } else { 1443 1444 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1445 r = sdma_v4_0_load_microcode(adev); 1446 if (r) 1447 return r; 1448 } 1449 1450 /* unhalt the MEs */ 1451 sdma_v4_0_enable(adev, true); 1452 /* enable sdma ring preemption */ 1453 sdma_v4_0_ctx_switch_enable(adev, true); 1454 } 1455 1456 /* start the gfx rings and rlc compute queues */ 1457 for (i = 0; i < adev->sdma.num_instances; i++) { 1458 uint32_t temp; 1459 1460 WREG32_SDMA(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL, 0); 1461 sdma_v4_0_gfx_resume(adev, i); 1462 if (adev->sdma.has_page_queue) 1463 sdma_v4_0_page_resume(adev, i); 1464 1465 /* set utc l1 enable flag always to 1 */ 1466 temp = RREG32_SDMA(i, mmSDMA0_CNTL); 1467 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 1468 WREG32_SDMA(i, mmSDMA0_CNTL, temp); 1469 1470 if (!amdgpu_sriov_vf(adev)) { 1471 /* unhalt engine */ 1472 temp = RREG32_SDMA(i, mmSDMA0_F32_CNTL); 1473 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 1474 WREG32_SDMA(i, mmSDMA0_F32_CNTL, temp); 1475 } 1476 } 1477 1478 if (amdgpu_sriov_vf(adev)) { 1479 sdma_v4_0_ctx_switch_enable(adev, true); 1480 sdma_v4_0_enable(adev, true); 1481 } else { 1482 r = sdma_v4_0_rlc_resume(adev); 1483 if (r) 1484 return r; 1485 } 1486 1487 for (i = 0; i < adev->sdma.num_instances; i++) { 1488 ring = &adev->sdma.instance[i].ring; 1489 1490 r = amdgpu_ring_test_helper(ring); 1491 if (r) 1492 return r; 1493 1494 if (adev->sdma.has_page_queue) { 1495 struct amdgpu_ring *page = &adev->sdma.instance[i].page; 1496 1497 r = amdgpu_ring_test_helper(page); 1498 if (r) 1499 return r; 1500 1501 if (adev->mman.buffer_funcs_ring == page) 1502 amdgpu_ttm_set_buffer_funcs_status(adev, true); 1503 } 1504 1505 if (adev->mman.buffer_funcs_ring == ring) 1506 amdgpu_ttm_set_buffer_funcs_status(adev, true); 1507 } 1508 1509 return r; 1510 } 1511 1512 /** 1513 * sdma_v4_0_ring_test_ring - simple async dma engine test 1514 * 1515 * @ring: amdgpu_ring structure holding ring information 1516 * 1517 * Test the DMA engine by writing using it to write an 1518 * value to memory. (VEGA10). 1519 * Returns 0 for success, error for failure. 1520 */ 1521 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring) 1522 { 1523 struct amdgpu_device *adev = ring->adev; 1524 unsigned i; 1525 unsigned index; 1526 int r; 1527 u32 tmp; 1528 u64 gpu_addr; 1529 1530 r = amdgpu_device_wb_get(adev, &index); 1531 if (r) 1532 return r; 1533 1534 gpu_addr = adev->wb.gpu_addr + (index * 4); 1535 tmp = 0xCAFEDEAD; 1536 adev->wb.wb[index] = cpu_to_le32(tmp); 1537 1538 r = amdgpu_ring_alloc(ring, 5); 1539 if (r) 1540 goto error_free_wb; 1541 1542 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1543 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 1544 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 1545 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 1546 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 1547 amdgpu_ring_write(ring, 0xDEADBEEF); 1548 amdgpu_ring_commit(ring); 1549 1550 for (i = 0; i < adev->usec_timeout; i++) { 1551 tmp = le32_to_cpu(adev->wb.wb[index]); 1552 if (tmp == 0xDEADBEEF) 1553 break; 1554 udelay(1); 1555 } 1556 1557 if (i >= adev->usec_timeout) 1558 r = -ETIMEDOUT; 1559 1560 error_free_wb: 1561 amdgpu_device_wb_free(adev, index); 1562 return r; 1563 } 1564 1565 /** 1566 * sdma_v4_0_ring_test_ib - test an IB on the DMA engine 1567 * 1568 * @ring: amdgpu_ring structure holding ring information 1569 * 1570 * Test a simple IB in the DMA ring (VEGA10). 1571 * Returns 0 on success, error on failure. 1572 */ 1573 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1574 { 1575 struct amdgpu_device *adev = ring->adev; 1576 struct amdgpu_ib ib; 1577 struct dma_fence *f = NULL; 1578 unsigned index; 1579 long r; 1580 u32 tmp = 0; 1581 u64 gpu_addr; 1582 1583 r = amdgpu_device_wb_get(adev, &index); 1584 if (r) 1585 return r; 1586 1587 gpu_addr = adev->wb.gpu_addr + (index * 4); 1588 tmp = 0xCAFEDEAD; 1589 adev->wb.wb[index] = cpu_to_le32(tmp); 1590 memset(&ib, 0, sizeof(ib)); 1591 r = amdgpu_ib_get(adev, NULL, 256, 1592 AMDGPU_IB_POOL_DIRECT, &ib); 1593 if (r) 1594 goto err0; 1595 1596 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1597 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1598 ib.ptr[1] = lower_32_bits(gpu_addr); 1599 ib.ptr[2] = upper_32_bits(gpu_addr); 1600 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1601 ib.ptr[4] = 0xDEADBEEF; 1602 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1603 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1604 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1605 ib.length_dw = 8; 1606 1607 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1608 if (r) 1609 goto err1; 1610 1611 r = dma_fence_wait_timeout(f, false, timeout); 1612 if (r == 0) { 1613 r = -ETIMEDOUT; 1614 goto err1; 1615 } else if (r < 0) { 1616 goto err1; 1617 } 1618 tmp = le32_to_cpu(adev->wb.wb[index]); 1619 if (tmp == 0xDEADBEEF) 1620 r = 0; 1621 else 1622 r = -EINVAL; 1623 1624 err1: 1625 amdgpu_ib_free(adev, &ib, NULL); 1626 dma_fence_put(f); 1627 err0: 1628 amdgpu_device_wb_free(adev, index); 1629 return r; 1630 } 1631 1632 1633 /** 1634 * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART 1635 * 1636 * @ib: indirect buffer to fill with commands 1637 * @pe: addr of the page entry 1638 * @src: src addr to copy from 1639 * @count: number of page entries to update 1640 * 1641 * Update PTEs by copying them from the GART using sDMA (VEGA10). 1642 */ 1643 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib, 1644 uint64_t pe, uint64_t src, 1645 unsigned count) 1646 { 1647 unsigned bytes = count * 8; 1648 1649 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1650 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1651 ib->ptr[ib->length_dw++] = bytes - 1; 1652 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1653 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1654 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1655 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1656 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1657 1658 } 1659 1660 /** 1661 * sdma_v4_0_vm_write_pte - update PTEs by writing them manually 1662 * 1663 * @ib: indirect buffer to fill with commands 1664 * @pe: addr of the page entry 1665 * @addr: dst addr to write into pe 1666 * @count: number of page entries to update 1667 * @incr: increase next addr by incr bytes 1668 * @flags: access flags 1669 * 1670 * Update PTEs by writing them manually using sDMA (VEGA10). 1671 */ 1672 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1673 uint64_t value, unsigned count, 1674 uint32_t incr) 1675 { 1676 unsigned ndw = count * 2; 1677 1678 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1679 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1680 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1681 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1682 ib->ptr[ib->length_dw++] = ndw - 1; 1683 for (; ndw > 0; ndw -= 2) { 1684 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1685 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1686 value += incr; 1687 } 1688 } 1689 1690 /** 1691 * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA 1692 * 1693 * @ib: indirect buffer to fill with commands 1694 * @pe: addr of the page entry 1695 * @addr: dst addr to write into pe 1696 * @count: number of page entries to update 1697 * @incr: increase next addr by incr bytes 1698 * @flags: access flags 1699 * 1700 * Update the page tables using sDMA (VEGA10). 1701 */ 1702 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1703 uint64_t pe, 1704 uint64_t addr, unsigned count, 1705 uint32_t incr, uint64_t flags) 1706 { 1707 /* for physically contiguous pages (vram) */ 1708 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1709 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1710 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1711 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1712 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1713 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1714 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1715 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1716 ib->ptr[ib->length_dw++] = 0; 1717 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1718 } 1719 1720 /** 1721 * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw 1722 * 1723 * @ib: indirect buffer to fill with padding 1724 * 1725 */ 1726 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1727 { 1728 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1729 u32 pad_count; 1730 int i; 1731 1732 pad_count = (-ib->length_dw) & 7; 1733 for (i = 0; i < pad_count; i++) 1734 if (sdma && sdma->burst_nop && (i == 0)) 1735 ib->ptr[ib->length_dw++] = 1736 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1737 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1738 else 1739 ib->ptr[ib->length_dw++] = 1740 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1741 } 1742 1743 1744 /** 1745 * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline 1746 * 1747 * @ring: amdgpu_ring pointer 1748 * 1749 * Make sure all previous operations are completed (CIK). 1750 */ 1751 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1752 { 1753 uint32_t seq = ring->fence_drv.sync_seq; 1754 uint64_t addr = ring->fence_drv.gpu_addr; 1755 1756 /* wait for idle */ 1757 sdma_v4_0_wait_reg_mem(ring, 1, 0, 1758 addr & 0xfffffffc, 1759 upper_32_bits(addr) & 0xffffffff, 1760 seq, 0xffffffff, 4); 1761 } 1762 1763 1764 /** 1765 * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA 1766 * 1767 * @ring: amdgpu_ring pointer 1768 * @vm: amdgpu_vm pointer 1769 * 1770 * Update the page table base and flush the VM TLB 1771 * using sDMA (VEGA10). 1772 */ 1773 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1774 unsigned vmid, uint64_t pd_addr) 1775 { 1776 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1777 } 1778 1779 static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring, 1780 uint32_t reg, uint32_t val) 1781 { 1782 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1783 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1784 amdgpu_ring_write(ring, reg); 1785 amdgpu_ring_write(ring, val); 1786 } 1787 1788 static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1789 uint32_t val, uint32_t mask) 1790 { 1791 sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10); 1792 } 1793 1794 static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev) 1795 { 1796 uint fw_version = adev->sdma.instance[0].fw_version; 1797 1798 switch (adev->asic_type) { 1799 case CHIP_VEGA10: 1800 return fw_version >= 430; 1801 case CHIP_VEGA12: 1802 /*return fw_version >= 31;*/ 1803 return false; 1804 case CHIP_VEGA20: 1805 return fw_version >= 123; 1806 default: 1807 return false; 1808 } 1809 } 1810 1811 static int sdma_v4_0_early_init(void *handle) 1812 { 1813 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1814 int r; 1815 1816 if (adev->flags & AMD_IS_APU) 1817 adev->sdma.num_instances = 1; 1818 else if (adev->asic_type == CHIP_ARCTURUS) 1819 adev->sdma.num_instances = 8; 1820 else 1821 adev->sdma.num_instances = 2; 1822 1823 r = sdma_v4_0_init_microcode(adev); 1824 if (r) { 1825 DRM_ERROR("Failed to load sdma firmware!\n"); 1826 return r; 1827 } 1828 1829 /* TODO: Page queue breaks driver reload under SRIOV */ 1830 if ((adev->asic_type == CHIP_VEGA10) && amdgpu_sriov_vf((adev))) 1831 adev->sdma.has_page_queue = false; 1832 else if (sdma_v4_0_fw_support_paging_queue(adev)) 1833 adev->sdma.has_page_queue = true; 1834 1835 sdma_v4_0_set_ring_funcs(adev); 1836 sdma_v4_0_set_buffer_funcs(adev); 1837 sdma_v4_0_set_vm_pte_funcs(adev); 1838 sdma_v4_0_set_irq_funcs(adev); 1839 sdma_v4_0_set_ras_funcs(adev); 1840 1841 return 0; 1842 } 1843 1844 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev, 1845 void *err_data, 1846 struct amdgpu_iv_entry *entry); 1847 1848 static int sdma_v4_0_late_init(void *handle) 1849 { 1850 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1851 struct ras_ih_if ih_info = { 1852 .cb = sdma_v4_0_process_ras_data_cb, 1853 }; 1854 1855 sdma_v4_0_setup_ulv(adev); 1856 1857 if (adev->sdma.funcs && adev->sdma.funcs->reset_ras_error_count) 1858 adev->sdma.funcs->reset_ras_error_count(adev); 1859 1860 if (adev->sdma.funcs && adev->sdma.funcs->ras_late_init) 1861 return adev->sdma.funcs->ras_late_init(adev, &ih_info); 1862 else 1863 return 0; 1864 } 1865 1866 static int sdma_v4_0_sw_init(void *handle) 1867 { 1868 struct amdgpu_ring *ring; 1869 int r, i; 1870 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1871 1872 /* SDMA trap event */ 1873 for (i = 0; i < adev->sdma.num_instances; i++) { 1874 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1875 SDMA0_4_0__SRCID__SDMA_TRAP, 1876 &adev->sdma.trap_irq); 1877 if (r) 1878 return r; 1879 } 1880 1881 /* SDMA SRAM ECC event */ 1882 for (i = 0; i < adev->sdma.num_instances; i++) { 1883 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1884 SDMA0_4_0__SRCID__SDMA_SRAM_ECC, 1885 &adev->sdma.ecc_irq); 1886 if (r) 1887 return r; 1888 } 1889 1890 for (i = 0; i < adev->sdma.num_instances; i++) { 1891 ring = &adev->sdma.instance[i].ring; 1892 ring->ring_obj = NULL; 1893 ring->use_doorbell = true; 1894 1895 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1896 ring->use_doorbell?"true":"false"); 1897 1898 /* doorbell size is 2 dwords, get DWORD offset */ 1899 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1; 1900 1901 sprintf(ring->name, "sdma%d", i); 1902 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1903 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1904 AMDGPU_RING_PRIO_DEFAULT); 1905 if (r) 1906 return r; 1907 1908 if (adev->sdma.has_page_queue) { 1909 ring = &adev->sdma.instance[i].page; 1910 ring->ring_obj = NULL; 1911 ring->use_doorbell = true; 1912 1913 /* paging queue use same doorbell index/routing as gfx queue 1914 * with 0x400 (4096 dwords) offset on second doorbell page 1915 */ 1916 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1; 1917 ring->doorbell_index += 0x400; 1918 1919 sprintf(ring->name, "page%d", i); 1920 r = amdgpu_ring_init(adev, ring, 1024, 1921 &adev->sdma.trap_irq, 1922 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1923 AMDGPU_RING_PRIO_DEFAULT); 1924 if (r) 1925 return r; 1926 } 1927 } 1928 1929 return r; 1930 } 1931 1932 static int sdma_v4_0_sw_fini(void *handle) 1933 { 1934 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1935 int i; 1936 1937 if (adev->sdma.funcs && adev->sdma.funcs->ras_fini) 1938 adev->sdma.funcs->ras_fini(adev); 1939 1940 for (i = 0; i < adev->sdma.num_instances; i++) { 1941 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1942 if (adev->sdma.has_page_queue) 1943 amdgpu_ring_fini(&adev->sdma.instance[i].page); 1944 } 1945 1946 sdma_v4_0_destroy_inst_ctx(adev); 1947 1948 return 0; 1949 } 1950 1951 static int sdma_v4_0_hw_init(void *handle) 1952 { 1953 int r; 1954 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1955 1956 if (adev->flags & AMD_IS_APU) 1957 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false); 1958 1959 if (!amdgpu_sriov_vf(adev)) 1960 sdma_v4_0_init_golden_registers(adev); 1961 1962 r = sdma_v4_0_start(adev); 1963 1964 return r; 1965 } 1966 1967 static int sdma_v4_0_hw_fini(void *handle) 1968 { 1969 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1970 int i; 1971 1972 if (amdgpu_sriov_vf(adev)) 1973 return 0; 1974 1975 for (i = 0; i < adev->sdma.num_instances; i++) { 1976 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, 1977 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 1978 } 1979 1980 sdma_v4_0_ctx_switch_enable(adev, false); 1981 sdma_v4_0_enable(adev, false); 1982 1983 if (adev->flags & AMD_IS_APU) 1984 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true); 1985 1986 return 0; 1987 } 1988 1989 static int sdma_v4_0_suspend(void *handle) 1990 { 1991 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1992 1993 return sdma_v4_0_hw_fini(adev); 1994 } 1995 1996 static int sdma_v4_0_resume(void *handle) 1997 { 1998 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1999 2000 return sdma_v4_0_hw_init(adev); 2001 } 2002 2003 static bool sdma_v4_0_is_idle(void *handle) 2004 { 2005 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2006 u32 i; 2007 2008 for (i = 0; i < adev->sdma.num_instances; i++) { 2009 u32 tmp = RREG32_SDMA(i, mmSDMA0_STATUS_REG); 2010 2011 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 2012 return false; 2013 } 2014 2015 return true; 2016 } 2017 2018 static int sdma_v4_0_wait_for_idle(void *handle) 2019 { 2020 unsigned i, j; 2021 u32 sdma[AMDGPU_MAX_SDMA_INSTANCES]; 2022 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2023 2024 for (i = 0; i < adev->usec_timeout; i++) { 2025 for (j = 0; j < adev->sdma.num_instances; j++) { 2026 sdma[j] = RREG32_SDMA(j, mmSDMA0_STATUS_REG); 2027 if (!(sdma[j] & SDMA0_STATUS_REG__IDLE_MASK)) 2028 break; 2029 } 2030 if (j == adev->sdma.num_instances) 2031 return 0; 2032 udelay(1); 2033 } 2034 return -ETIMEDOUT; 2035 } 2036 2037 static int sdma_v4_0_soft_reset(void *handle) 2038 { 2039 /* todo */ 2040 2041 return 0; 2042 } 2043 2044 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev, 2045 struct amdgpu_irq_src *source, 2046 unsigned type, 2047 enum amdgpu_interrupt_state state) 2048 { 2049 u32 sdma_cntl; 2050 2051 sdma_cntl = RREG32_SDMA(type, mmSDMA0_CNTL); 2052 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 2053 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2054 WREG32_SDMA(type, mmSDMA0_CNTL, sdma_cntl); 2055 2056 return 0; 2057 } 2058 2059 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev, 2060 struct amdgpu_irq_src *source, 2061 struct amdgpu_iv_entry *entry) 2062 { 2063 uint32_t instance; 2064 2065 DRM_DEBUG("IH: SDMA trap\n"); 2066 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 2067 switch (entry->ring_id) { 2068 case 0: 2069 amdgpu_fence_process(&adev->sdma.instance[instance].ring); 2070 break; 2071 case 1: 2072 if (adev->asic_type == CHIP_VEGA20) 2073 amdgpu_fence_process(&adev->sdma.instance[instance].page); 2074 break; 2075 case 2: 2076 /* XXX compute */ 2077 break; 2078 case 3: 2079 if (adev->asic_type != CHIP_VEGA20) 2080 amdgpu_fence_process(&adev->sdma.instance[instance].page); 2081 break; 2082 } 2083 return 0; 2084 } 2085 2086 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev, 2087 void *err_data, 2088 struct amdgpu_iv_entry *entry) 2089 { 2090 int instance; 2091 2092 /* When “Full RAS” is enabled, the per-IP interrupt sources should 2093 * be disabled and the driver should only look for the aggregated 2094 * interrupt via sync flood 2095 */ 2096 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 2097 goto out; 2098 2099 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 2100 if (instance < 0) 2101 goto out; 2102 2103 amdgpu_sdma_process_ras_data_cb(adev, err_data, entry); 2104 2105 out: 2106 return AMDGPU_RAS_SUCCESS; 2107 } 2108 2109 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev, 2110 struct amdgpu_irq_src *source, 2111 struct amdgpu_iv_entry *entry) 2112 { 2113 int instance; 2114 2115 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 2116 2117 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 2118 if (instance < 0) 2119 return 0; 2120 2121 switch (entry->ring_id) { 2122 case 0: 2123 drm_sched_fault(&adev->sdma.instance[instance].ring.sched); 2124 break; 2125 } 2126 return 0; 2127 } 2128 2129 static int sdma_v4_0_set_ecc_irq_state(struct amdgpu_device *adev, 2130 struct amdgpu_irq_src *source, 2131 unsigned type, 2132 enum amdgpu_interrupt_state state) 2133 { 2134 u32 sdma_edc_config; 2135 2136 sdma_edc_config = RREG32_SDMA(type, mmSDMA0_EDC_CONFIG); 2137 sdma_edc_config = REG_SET_FIELD(sdma_edc_config, SDMA0_EDC_CONFIG, ECC_INT_ENABLE, 2138 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2139 WREG32_SDMA(type, mmSDMA0_EDC_CONFIG, sdma_edc_config); 2140 2141 return 0; 2142 } 2143 2144 static void sdma_v4_0_update_medium_grain_clock_gating( 2145 struct amdgpu_device *adev, 2146 bool enable) 2147 { 2148 uint32_t data, def; 2149 int i; 2150 2151 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 2152 for (i = 0; i < adev->sdma.num_instances; i++) { 2153 def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL); 2154 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 2155 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 2156 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 2157 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 2158 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 2159 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 2160 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 2161 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 2162 if (def != data) 2163 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data); 2164 } 2165 } else { 2166 for (i = 0; i < adev->sdma.num_instances; i++) { 2167 def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL); 2168 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 2169 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 2170 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 2171 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 2172 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 2173 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 2174 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 2175 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 2176 if (def != data) 2177 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data); 2178 } 2179 } 2180 } 2181 2182 2183 static void sdma_v4_0_update_medium_grain_light_sleep( 2184 struct amdgpu_device *adev, 2185 bool enable) 2186 { 2187 uint32_t data, def; 2188 int i; 2189 2190 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 2191 for (i = 0; i < adev->sdma.num_instances; i++) { 2192 /* 1-not override: enable sdma mem light sleep */ 2193 def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL); 2194 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 2195 if (def != data) 2196 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data); 2197 } 2198 } else { 2199 for (i = 0; i < adev->sdma.num_instances; i++) { 2200 /* 0-override:disable sdma mem light sleep */ 2201 def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL); 2202 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 2203 if (def != data) 2204 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data); 2205 } 2206 } 2207 } 2208 2209 static int sdma_v4_0_set_clockgating_state(void *handle, 2210 enum amd_clockgating_state state) 2211 { 2212 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2213 2214 if (amdgpu_sriov_vf(adev)) 2215 return 0; 2216 2217 switch (adev->asic_type) { 2218 case CHIP_VEGA10: 2219 case CHIP_VEGA12: 2220 case CHIP_VEGA20: 2221 case CHIP_RAVEN: 2222 case CHIP_ARCTURUS: 2223 case CHIP_RENOIR: 2224 sdma_v4_0_update_medium_grain_clock_gating(adev, 2225 state == AMD_CG_STATE_GATE); 2226 sdma_v4_0_update_medium_grain_light_sleep(adev, 2227 state == AMD_CG_STATE_GATE); 2228 break; 2229 default: 2230 break; 2231 } 2232 return 0; 2233 } 2234 2235 static int sdma_v4_0_set_powergating_state(void *handle, 2236 enum amd_powergating_state state) 2237 { 2238 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2239 2240 switch (adev->asic_type) { 2241 case CHIP_RAVEN: 2242 case CHIP_RENOIR: 2243 sdma_v4_1_update_power_gating(adev, 2244 state == AMD_PG_STATE_GATE ? true : false); 2245 break; 2246 default: 2247 break; 2248 } 2249 2250 return 0; 2251 } 2252 2253 static void sdma_v4_0_get_clockgating_state(void *handle, u32 *flags) 2254 { 2255 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2256 int data; 2257 2258 if (amdgpu_sriov_vf(adev)) 2259 *flags = 0; 2260 2261 /* AMD_CG_SUPPORT_SDMA_MGCG */ 2262 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 2263 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK)) 2264 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 2265 2266 /* AMD_CG_SUPPORT_SDMA_LS */ 2267 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 2268 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 2269 *flags |= AMD_CG_SUPPORT_SDMA_LS; 2270 } 2271 2272 const struct amd_ip_funcs sdma_v4_0_ip_funcs = { 2273 .name = "sdma_v4_0", 2274 .early_init = sdma_v4_0_early_init, 2275 .late_init = sdma_v4_0_late_init, 2276 .sw_init = sdma_v4_0_sw_init, 2277 .sw_fini = sdma_v4_0_sw_fini, 2278 .hw_init = sdma_v4_0_hw_init, 2279 .hw_fini = sdma_v4_0_hw_fini, 2280 .suspend = sdma_v4_0_suspend, 2281 .resume = sdma_v4_0_resume, 2282 .is_idle = sdma_v4_0_is_idle, 2283 .wait_for_idle = sdma_v4_0_wait_for_idle, 2284 .soft_reset = sdma_v4_0_soft_reset, 2285 .set_clockgating_state = sdma_v4_0_set_clockgating_state, 2286 .set_powergating_state = sdma_v4_0_set_powergating_state, 2287 .get_clockgating_state = sdma_v4_0_get_clockgating_state, 2288 }; 2289 2290 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = { 2291 .type = AMDGPU_RING_TYPE_SDMA, 2292 .align_mask = 0xf, 2293 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2294 .support_64bit_ptrs = true, 2295 .vmhub = AMDGPU_MMHUB_0, 2296 .get_rptr = sdma_v4_0_ring_get_rptr, 2297 .get_wptr = sdma_v4_0_ring_get_wptr, 2298 .set_wptr = sdma_v4_0_ring_set_wptr, 2299 .emit_frame_size = 2300 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2301 3 + /* hdp invalidate */ 2302 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2303 /* sdma_v4_0_ring_emit_vm_flush */ 2304 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2305 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2306 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2307 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2308 .emit_ib = sdma_v4_0_ring_emit_ib, 2309 .emit_fence = sdma_v4_0_ring_emit_fence, 2310 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2311 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2312 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2313 .test_ring = sdma_v4_0_ring_test_ring, 2314 .test_ib = sdma_v4_0_ring_test_ib, 2315 .insert_nop = sdma_v4_0_ring_insert_nop, 2316 .pad_ib = sdma_v4_0_ring_pad_ib, 2317 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2318 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2319 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2320 }; 2321 2322 /* 2323 * On Arcturus, SDMA instance 5~7 has a different vmhub type(AMDGPU_MMHUB_1). 2324 * So create a individual constant ring_funcs for those instances. 2325 */ 2326 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs_2nd_mmhub = { 2327 .type = AMDGPU_RING_TYPE_SDMA, 2328 .align_mask = 0xf, 2329 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2330 .support_64bit_ptrs = true, 2331 .vmhub = AMDGPU_MMHUB_1, 2332 .get_rptr = sdma_v4_0_ring_get_rptr, 2333 .get_wptr = sdma_v4_0_ring_get_wptr, 2334 .set_wptr = sdma_v4_0_ring_set_wptr, 2335 .emit_frame_size = 2336 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2337 3 + /* hdp invalidate */ 2338 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2339 /* sdma_v4_0_ring_emit_vm_flush */ 2340 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2341 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2342 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2343 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2344 .emit_ib = sdma_v4_0_ring_emit_ib, 2345 .emit_fence = sdma_v4_0_ring_emit_fence, 2346 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2347 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2348 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2349 .test_ring = sdma_v4_0_ring_test_ring, 2350 .test_ib = sdma_v4_0_ring_test_ib, 2351 .insert_nop = sdma_v4_0_ring_insert_nop, 2352 .pad_ib = sdma_v4_0_ring_pad_ib, 2353 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2354 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2355 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2356 }; 2357 2358 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = { 2359 .type = AMDGPU_RING_TYPE_SDMA, 2360 .align_mask = 0xf, 2361 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2362 .support_64bit_ptrs = true, 2363 .vmhub = AMDGPU_MMHUB_0, 2364 .get_rptr = sdma_v4_0_ring_get_rptr, 2365 .get_wptr = sdma_v4_0_page_ring_get_wptr, 2366 .set_wptr = sdma_v4_0_page_ring_set_wptr, 2367 .emit_frame_size = 2368 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2369 3 + /* hdp invalidate */ 2370 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2371 /* sdma_v4_0_ring_emit_vm_flush */ 2372 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2373 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2374 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2375 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2376 .emit_ib = sdma_v4_0_ring_emit_ib, 2377 .emit_fence = sdma_v4_0_ring_emit_fence, 2378 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2379 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2380 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2381 .test_ring = sdma_v4_0_ring_test_ring, 2382 .test_ib = sdma_v4_0_ring_test_ib, 2383 .insert_nop = sdma_v4_0_ring_insert_nop, 2384 .pad_ib = sdma_v4_0_ring_pad_ib, 2385 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2386 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2387 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2388 }; 2389 2390 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs_2nd_mmhub = { 2391 .type = AMDGPU_RING_TYPE_SDMA, 2392 .align_mask = 0xf, 2393 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2394 .support_64bit_ptrs = true, 2395 .vmhub = AMDGPU_MMHUB_1, 2396 .get_rptr = sdma_v4_0_ring_get_rptr, 2397 .get_wptr = sdma_v4_0_page_ring_get_wptr, 2398 .set_wptr = sdma_v4_0_page_ring_set_wptr, 2399 .emit_frame_size = 2400 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2401 3 + /* hdp invalidate */ 2402 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2403 /* sdma_v4_0_ring_emit_vm_flush */ 2404 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2405 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2406 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2407 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2408 .emit_ib = sdma_v4_0_ring_emit_ib, 2409 .emit_fence = sdma_v4_0_ring_emit_fence, 2410 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2411 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2412 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2413 .test_ring = sdma_v4_0_ring_test_ring, 2414 .test_ib = sdma_v4_0_ring_test_ib, 2415 .insert_nop = sdma_v4_0_ring_insert_nop, 2416 .pad_ib = sdma_v4_0_ring_pad_ib, 2417 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2418 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2419 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2420 }; 2421 2422 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev) 2423 { 2424 int i; 2425 2426 for (i = 0; i < adev->sdma.num_instances; i++) { 2427 if (adev->asic_type == CHIP_ARCTURUS && i >= 5) 2428 adev->sdma.instance[i].ring.funcs = 2429 &sdma_v4_0_ring_funcs_2nd_mmhub; 2430 else 2431 adev->sdma.instance[i].ring.funcs = 2432 &sdma_v4_0_ring_funcs; 2433 adev->sdma.instance[i].ring.me = i; 2434 if (adev->sdma.has_page_queue) { 2435 if (adev->asic_type == CHIP_ARCTURUS && i >= 5) 2436 adev->sdma.instance[i].page.funcs = 2437 &sdma_v4_0_page_ring_funcs_2nd_mmhub; 2438 else 2439 adev->sdma.instance[i].page.funcs = 2440 &sdma_v4_0_page_ring_funcs; 2441 adev->sdma.instance[i].page.me = i; 2442 } 2443 } 2444 } 2445 2446 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = { 2447 .set = sdma_v4_0_set_trap_irq_state, 2448 .process = sdma_v4_0_process_trap_irq, 2449 }; 2450 2451 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = { 2452 .process = sdma_v4_0_process_illegal_inst_irq, 2453 }; 2454 2455 static const struct amdgpu_irq_src_funcs sdma_v4_0_ecc_irq_funcs = { 2456 .set = sdma_v4_0_set_ecc_irq_state, 2457 .process = amdgpu_sdma_process_ecc_irq, 2458 }; 2459 2460 2461 2462 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev) 2463 { 2464 switch (adev->sdma.num_instances) { 2465 case 1: 2466 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1; 2467 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1; 2468 break; 2469 case 8: 2470 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 2471 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 2472 break; 2473 case 2: 2474 default: 2475 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2; 2476 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2; 2477 break; 2478 } 2479 adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs; 2480 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs; 2481 adev->sdma.ecc_irq.funcs = &sdma_v4_0_ecc_irq_funcs; 2482 } 2483 2484 /** 2485 * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine 2486 * 2487 * @ring: amdgpu_ring structure holding ring information 2488 * @src_offset: src GPU address 2489 * @dst_offset: dst GPU address 2490 * @byte_count: number of bytes to xfer 2491 * 2492 * Copy GPU buffers using the DMA engine (VEGA10/12). 2493 * Used by the amdgpu ttm implementation to move pages if 2494 * registered as the asic copy callback. 2495 */ 2496 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib, 2497 uint64_t src_offset, 2498 uint64_t dst_offset, 2499 uint32_t byte_count, 2500 bool tmz) 2501 { 2502 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 2503 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 2504 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0); 2505 ib->ptr[ib->length_dw++] = byte_count - 1; 2506 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 2507 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 2508 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 2509 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2510 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2511 } 2512 2513 /** 2514 * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine 2515 * 2516 * @ring: amdgpu_ring structure holding ring information 2517 * @src_data: value to write to buffer 2518 * @dst_offset: dst GPU address 2519 * @byte_count: number of bytes to xfer 2520 * 2521 * Fill GPU buffers using the DMA engine (VEGA10/12). 2522 */ 2523 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib, 2524 uint32_t src_data, 2525 uint64_t dst_offset, 2526 uint32_t byte_count) 2527 { 2528 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 2529 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2530 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2531 ib->ptr[ib->length_dw++] = src_data; 2532 ib->ptr[ib->length_dw++] = byte_count - 1; 2533 } 2534 2535 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = { 2536 .copy_max_bytes = 0x400000, 2537 .copy_num_dw = 7, 2538 .emit_copy_buffer = sdma_v4_0_emit_copy_buffer, 2539 2540 .fill_max_bytes = 0x400000, 2541 .fill_num_dw = 5, 2542 .emit_fill_buffer = sdma_v4_0_emit_fill_buffer, 2543 }; 2544 2545 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev) 2546 { 2547 adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs; 2548 if (adev->sdma.has_page_queue) 2549 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page; 2550 else 2551 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 2552 } 2553 2554 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = { 2555 .copy_pte_num_dw = 7, 2556 .copy_pte = sdma_v4_0_vm_copy_pte, 2557 2558 .write_pte = sdma_v4_0_vm_write_pte, 2559 .set_pte_pde = sdma_v4_0_vm_set_pte_pde, 2560 }; 2561 2562 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev) 2563 { 2564 struct drm_gpu_scheduler *sched; 2565 unsigned i; 2566 2567 adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs; 2568 for (i = 0; i < adev->sdma.num_instances; i++) { 2569 if (adev->sdma.has_page_queue) 2570 sched = &adev->sdma.instance[i].page.sched; 2571 else 2572 sched = &adev->sdma.instance[i].ring.sched; 2573 adev->vm_manager.vm_pte_scheds[i] = sched; 2574 } 2575 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 2576 } 2577 2578 static void sdma_v4_0_get_ras_error_count(uint32_t value, 2579 uint32_t instance, 2580 uint32_t *sec_count) 2581 { 2582 uint32_t i; 2583 uint32_t sec_cnt; 2584 2585 /* double bits error (multiple bits) error detection is not supported */ 2586 for (i = 0; i < ARRAY_SIZE(sdma_v4_0_ras_fields); i++) { 2587 /* the SDMA_EDC_COUNTER register in each sdma instance 2588 * shares the same sed shift_mask 2589 * */ 2590 sec_cnt = (value & 2591 sdma_v4_0_ras_fields[i].sec_count_mask) >> 2592 sdma_v4_0_ras_fields[i].sec_count_shift; 2593 if (sec_cnt) { 2594 DRM_INFO("Detected %s in SDMA%d, SED %d\n", 2595 sdma_v4_0_ras_fields[i].name, 2596 instance, sec_cnt); 2597 *sec_count += sec_cnt; 2598 } 2599 } 2600 } 2601 2602 static int sdma_v4_0_query_ras_error_count(struct amdgpu_device *adev, 2603 uint32_t instance, void *ras_error_status) 2604 { 2605 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 2606 uint32_t sec_count = 0; 2607 uint32_t reg_value = 0; 2608 2609 reg_value = RREG32_SDMA(instance, mmSDMA0_EDC_COUNTER); 2610 /* double bit error is not supported */ 2611 if (reg_value) 2612 sdma_v4_0_get_ras_error_count(reg_value, 2613 instance, &sec_count); 2614 /* err_data->ce_count should be initialized to 0 2615 * before calling into this function */ 2616 err_data->ce_count += sec_count; 2617 /* double bit error is not supported 2618 * set ue count to 0 */ 2619 err_data->ue_count = 0; 2620 2621 return 0; 2622 }; 2623 2624 static void sdma_v4_0_reset_ras_error_count(struct amdgpu_device *adev) 2625 { 2626 int i; 2627 2628 /* read back edc counter registers to clear the counters */ 2629 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 2630 for (i = 0; i < adev->sdma.num_instances; i++) 2631 RREG32_SDMA(i, mmSDMA0_EDC_COUNTER); 2632 } 2633 } 2634 2635 static const struct amdgpu_sdma_ras_funcs sdma_v4_0_ras_funcs = { 2636 .ras_late_init = amdgpu_sdma_ras_late_init, 2637 .ras_fini = amdgpu_sdma_ras_fini, 2638 .query_ras_error_count = sdma_v4_0_query_ras_error_count, 2639 .reset_ras_error_count = sdma_v4_0_reset_ras_error_count, 2640 }; 2641 2642 static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev) 2643 { 2644 switch (adev->asic_type) { 2645 case CHIP_VEGA20: 2646 case CHIP_ARCTURUS: 2647 adev->sdma.funcs = &sdma_v4_0_ras_funcs; 2648 break; 2649 default: 2650 break; 2651 } 2652 } 2653 2654 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = { 2655 .type = AMD_IP_BLOCK_TYPE_SDMA, 2656 .major = 4, 2657 .minor = 0, 2658 .rev = 0, 2659 .funcs = &sdma_v4_0_ip_funcs, 2660 }; 2661