1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_ucode.h" 28 #include "amdgpu_trace.h" 29 30 #include "sdma0/sdma0_4_2_offset.h" 31 #include "sdma0/sdma0_4_2_sh_mask.h" 32 #include "sdma1/sdma1_4_2_offset.h" 33 #include "sdma1/sdma1_4_2_sh_mask.h" 34 #include "hdp/hdp_4_0_offset.h" 35 #include "sdma0/sdma0_4_1_default.h" 36 37 #include "soc15_common.h" 38 #include "soc15.h" 39 #include "vega10_sdma_pkt_open.h" 40 41 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h" 42 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h" 43 44 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin"); 45 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin"); 46 MODULE_FIRMWARE("amdgpu/vega12_sdma.bin"); 47 MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin"); 48 MODULE_FIRMWARE("amdgpu/vega20_sdma.bin"); 49 MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin"); 50 MODULE_FIRMWARE("amdgpu/raven_sdma.bin"); 51 MODULE_FIRMWARE("amdgpu/picasso_sdma.bin"); 52 MODULE_FIRMWARE("amdgpu/raven2_sdma.bin"); 53 54 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L 55 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L 56 57 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev); 58 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev); 59 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev); 60 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev); 61 62 static const struct soc15_reg_golden golden_settings_sdma_4[] = { 63 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 64 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100), 65 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100), 66 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 67 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 68 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 69 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000), 70 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 71 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 72 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 73 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 74 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 75 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000), 76 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 77 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), 78 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100), 79 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 80 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 81 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 82 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000), 83 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 84 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 85 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 86 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 87 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0), 88 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xfc000000, 0x00000000) 89 }; 90 91 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = { 92 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 93 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 94 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 95 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002) 96 }; 97 98 static const struct soc15_reg_golden golden_settings_sdma_vg12[] = { 99 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), 100 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001), 101 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), 102 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001) 103 }; 104 105 static const struct soc15_reg_golden golden_settings_sdma_4_1[] = { 106 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 107 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 108 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100), 109 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 110 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051), 111 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100), 112 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 113 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100), 114 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 115 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 116 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000) 117 }; 118 119 static const struct soc15_reg_golden golden_settings_sdma0_4_2_init[] = { 120 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 121 }; 122 123 static const struct soc15_reg_golden golden_settings_sdma0_4_2[] = 124 { 125 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 126 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 127 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 128 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 129 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 130 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 131 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 132 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 133 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RD_BURST_CNTL, 0x0000000f, 0x00000003), 134 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 135 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 136 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 137 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 138 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 139 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 140 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 141 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 142 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 143 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 144 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 145 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 146 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 147 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 148 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 149 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 150 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 151 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xFE000000, 0x00000000), 152 }; 153 154 static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = { 155 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 156 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), 157 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 158 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 159 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 160 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 161 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 162 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 163 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RD_BURST_CNTL, 0x0000000f, 0x00000003), 164 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 165 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 166 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 167 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 168 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 169 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 170 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 171 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 172 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 173 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 174 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 175 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 176 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 177 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 178 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 179 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 180 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0), 181 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xFE000000, 0x00000000), 182 }; 183 184 static const struct soc15_reg_golden golden_settings_sdma_rv1[] = 185 { 186 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002), 187 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002) 188 }; 189 190 static const struct soc15_reg_golden golden_settings_sdma_rv2[] = 191 { 192 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00003001), 193 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003001) 194 }; 195 196 static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev, 197 u32 instance, u32 offset) 198 { 199 return ( 0 == instance ? (adev->reg_offset[SDMA0_HWIP][0][0] + offset) : 200 (adev->reg_offset[SDMA1_HWIP][0][0] + offset)); 201 } 202 203 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) 204 { 205 switch (adev->asic_type) { 206 case CHIP_VEGA10: 207 soc15_program_register_sequence(adev, 208 golden_settings_sdma_4, 209 ARRAY_SIZE(golden_settings_sdma_4)); 210 soc15_program_register_sequence(adev, 211 golden_settings_sdma_vg10, 212 ARRAY_SIZE(golden_settings_sdma_vg10)); 213 break; 214 case CHIP_VEGA12: 215 soc15_program_register_sequence(adev, 216 golden_settings_sdma_4, 217 ARRAY_SIZE(golden_settings_sdma_4)); 218 soc15_program_register_sequence(adev, 219 golden_settings_sdma_vg12, 220 ARRAY_SIZE(golden_settings_sdma_vg12)); 221 break; 222 case CHIP_VEGA20: 223 soc15_program_register_sequence(adev, 224 golden_settings_sdma0_4_2_init, 225 ARRAY_SIZE(golden_settings_sdma0_4_2_init)); 226 soc15_program_register_sequence(adev, 227 golden_settings_sdma0_4_2, 228 ARRAY_SIZE(golden_settings_sdma0_4_2)); 229 soc15_program_register_sequence(adev, 230 golden_settings_sdma1_4_2, 231 ARRAY_SIZE(golden_settings_sdma1_4_2)); 232 break; 233 case CHIP_RAVEN: 234 soc15_program_register_sequence(adev, 235 golden_settings_sdma_4_1, 236 ARRAY_SIZE(golden_settings_sdma_4_1)); 237 if (adev->rev_id >= 8) 238 soc15_program_register_sequence(adev, 239 golden_settings_sdma_rv2, 240 ARRAY_SIZE(golden_settings_sdma_rv2)); 241 else 242 soc15_program_register_sequence(adev, 243 golden_settings_sdma_rv1, 244 ARRAY_SIZE(golden_settings_sdma_rv1)); 245 break; 246 default: 247 break; 248 } 249 } 250 251 /** 252 * sdma_v4_0_init_microcode - load ucode images from disk 253 * 254 * @adev: amdgpu_device pointer 255 * 256 * Use the firmware interface to load the ucode images into 257 * the driver (not loaded into hw). 258 * Returns 0 on success, error on failure. 259 */ 260 261 // emulation only, won't work on real chip 262 // vega10 real chip need to use PSP to load firmware 263 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev) 264 { 265 const char *chip_name; 266 char fw_name[30]; 267 int err = 0, i; 268 struct amdgpu_firmware_info *info = NULL; 269 const struct common_firmware_header *header = NULL; 270 const struct sdma_firmware_header_v1_0 *hdr; 271 272 DRM_DEBUG("\n"); 273 274 switch (adev->asic_type) { 275 case CHIP_VEGA10: 276 chip_name = "vega10"; 277 break; 278 case CHIP_VEGA12: 279 chip_name = "vega12"; 280 break; 281 case CHIP_VEGA20: 282 chip_name = "vega20"; 283 break; 284 case CHIP_RAVEN: 285 if (adev->rev_id >= 8) 286 chip_name = "raven2"; 287 else if (adev->pdev->device == 0x15d8) 288 chip_name = "picasso"; 289 else 290 chip_name = "raven"; 291 break; 292 default: 293 BUG(); 294 } 295 296 for (i = 0; i < adev->sdma.num_instances; i++) { 297 if (i == 0) 298 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 299 else 300 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); 301 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 302 if (err) 303 goto out; 304 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); 305 if (err) 306 goto out; 307 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 308 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 309 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 310 if (adev->sdma.instance[i].feature_version >= 20) 311 adev->sdma.instance[i].burst_nop = true; 312 DRM_DEBUG("psp_load == '%s'\n", 313 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); 314 315 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 316 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 317 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 318 info->fw = adev->sdma.instance[i].fw; 319 header = (const struct common_firmware_header *)info->fw->data; 320 adev->firmware.fw_size += 321 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 322 } 323 } 324 out: 325 if (err) { 326 DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name); 327 for (i = 0; i < adev->sdma.num_instances; i++) { 328 release_firmware(adev->sdma.instance[i].fw); 329 adev->sdma.instance[i].fw = NULL; 330 } 331 } 332 return err; 333 } 334 335 /** 336 * sdma_v4_0_ring_get_rptr - get the current read pointer 337 * 338 * @ring: amdgpu ring pointer 339 * 340 * Get the current rptr from the hardware (VEGA10+). 341 */ 342 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring) 343 { 344 u64 *rptr; 345 346 /* XXX check if swapping is necessary on BE */ 347 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]); 348 349 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 350 return ((*rptr) >> 2); 351 } 352 353 /** 354 * sdma_v4_0_ring_get_wptr - get the current write pointer 355 * 356 * @ring: amdgpu ring pointer 357 * 358 * Get the current wptr from the hardware (VEGA10+). 359 */ 360 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring) 361 { 362 struct amdgpu_device *adev = ring->adev; 363 u64 wptr; 364 365 if (ring->use_doorbell) { 366 /* XXX check if swapping is necessary on BE */ 367 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 368 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 369 } else { 370 u32 lowbit, highbit; 371 372 lowbit = RREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)) >> 2; 373 highbit = RREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2; 374 375 DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n", 376 ring->me, highbit, lowbit); 377 wptr = highbit; 378 wptr = wptr << 32; 379 wptr |= lowbit; 380 } 381 382 return wptr >> 2; 383 } 384 385 /** 386 * sdma_v4_0_ring_set_wptr - commit the write pointer 387 * 388 * @ring: amdgpu ring pointer 389 * 390 * Write the wptr back to the hardware (VEGA10+). 391 */ 392 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring) 393 { 394 struct amdgpu_device *adev = ring->adev; 395 396 DRM_DEBUG("Setting write pointer\n"); 397 if (ring->use_doorbell) { 398 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 399 400 DRM_DEBUG("Using doorbell -- " 401 "wptr_offs == 0x%08x " 402 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 403 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 404 ring->wptr_offs, 405 lower_32_bits(ring->wptr << 2), 406 upper_32_bits(ring->wptr << 2)); 407 /* XXX check if swapping is necessary on BE */ 408 WRITE_ONCE(*wb, (ring->wptr << 2)); 409 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 410 ring->doorbell_index, ring->wptr << 2); 411 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 412 } else { 413 DRM_DEBUG("Not using doorbell -- " 414 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 415 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 416 ring->me, 417 lower_32_bits(ring->wptr << 2), 418 ring->me, 419 upper_32_bits(ring->wptr << 2)); 420 WREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2)); 421 WREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2)); 422 } 423 } 424 425 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 426 { 427 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); 428 int i; 429 430 for (i = 0; i < count; i++) 431 if (sdma && sdma->burst_nop && (i == 0)) 432 amdgpu_ring_write(ring, ring->funcs->nop | 433 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 434 else 435 amdgpu_ring_write(ring, ring->funcs->nop); 436 } 437 438 /** 439 * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine 440 * 441 * @ring: amdgpu ring pointer 442 * @ib: IB object to schedule 443 * 444 * Schedule an IB in the DMA ring (VEGA10). 445 */ 446 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring, 447 struct amdgpu_ib *ib, 448 unsigned vmid, bool ctx_switch) 449 { 450 /* IB packet must end on a 8 DW boundary */ 451 sdma_v4_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8); 452 453 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 454 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 455 /* base must be 32 byte aligned */ 456 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 457 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 458 amdgpu_ring_write(ring, ib->length_dw); 459 amdgpu_ring_write(ring, 0); 460 amdgpu_ring_write(ring, 0); 461 462 } 463 464 static void sdma_v4_0_wait_reg_mem(struct amdgpu_ring *ring, 465 int mem_space, int hdp, 466 uint32_t addr0, uint32_t addr1, 467 uint32_t ref, uint32_t mask, 468 uint32_t inv) 469 { 470 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 471 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) | 472 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) | 473 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 474 if (mem_space) { 475 /* memory */ 476 amdgpu_ring_write(ring, addr0); 477 amdgpu_ring_write(ring, addr1); 478 } else { 479 /* registers */ 480 amdgpu_ring_write(ring, addr0 << 2); 481 amdgpu_ring_write(ring, addr1 << 2); 482 } 483 amdgpu_ring_write(ring, ref); /* reference */ 484 amdgpu_ring_write(ring, mask); /* mask */ 485 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 486 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */ 487 } 488 489 /** 490 * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 491 * 492 * @ring: amdgpu ring pointer 493 * 494 * Emit an hdp flush packet on the requested DMA ring. 495 */ 496 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 497 { 498 struct amdgpu_device *adev = ring->adev; 499 u32 ref_and_mask = 0; 500 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg; 501 502 if (ring->me == 0) 503 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0; 504 else 505 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1; 506 507 sdma_v4_0_wait_reg_mem(ring, 0, 1, 508 adev->nbio_funcs->get_hdp_flush_done_offset(adev), 509 adev->nbio_funcs->get_hdp_flush_req_offset(adev), 510 ref_and_mask, ref_and_mask, 10); 511 } 512 513 /** 514 * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring 515 * 516 * @ring: amdgpu ring pointer 517 * @fence: amdgpu fence object 518 * 519 * Add a DMA fence packet to the ring to write 520 * the fence seq number and DMA trap packet to generate 521 * an interrupt if needed (VEGA10). 522 */ 523 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 524 unsigned flags) 525 { 526 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 527 /* write the fence */ 528 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 529 /* zero in first two bits */ 530 BUG_ON(addr & 0x3); 531 amdgpu_ring_write(ring, lower_32_bits(addr)); 532 amdgpu_ring_write(ring, upper_32_bits(addr)); 533 amdgpu_ring_write(ring, lower_32_bits(seq)); 534 535 /* optionally write high bits as well */ 536 if (write64bit) { 537 addr += 4; 538 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 539 /* zero in first two bits */ 540 BUG_ON(addr & 0x3); 541 amdgpu_ring_write(ring, lower_32_bits(addr)); 542 amdgpu_ring_write(ring, upper_32_bits(addr)); 543 amdgpu_ring_write(ring, upper_32_bits(seq)); 544 } 545 546 /* generate an interrupt */ 547 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 548 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 549 } 550 551 552 /** 553 * sdma_v4_0_gfx_stop - stop the gfx async dma engines 554 * 555 * @adev: amdgpu_device pointer 556 * 557 * Stop the gfx async dma ring buffers (VEGA10). 558 */ 559 static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev) 560 { 561 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 562 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 563 u32 rb_cntl, ib_cntl; 564 int i; 565 566 if ((adev->mman.buffer_funcs_ring == sdma0) || 567 (adev->mman.buffer_funcs_ring == sdma1)) 568 amdgpu_ttm_set_buffer_funcs_status(adev, false); 569 570 for (i = 0; i < adev->sdma.num_instances; i++) { 571 rb_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 572 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 573 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 574 ib_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 575 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 576 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 577 } 578 579 sdma0->ready = false; 580 sdma1->ready = false; 581 } 582 583 /** 584 * sdma_v4_0_rlc_stop - stop the compute async dma engines 585 * 586 * @adev: amdgpu_device pointer 587 * 588 * Stop the compute async dma queues (VEGA10). 589 */ 590 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev) 591 { 592 /* XXX todo */ 593 } 594 595 /** 596 * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch 597 * 598 * @adev: amdgpu_device pointer 599 * @enable: enable/disable the DMA MEs context switch. 600 * 601 * Halt or unhalt the async dma engines context switch (VEGA10). 602 */ 603 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 604 { 605 u32 f32_cntl, phase_quantum = 0; 606 int i; 607 608 if (amdgpu_sdma_phase_quantum) { 609 unsigned value = amdgpu_sdma_phase_quantum; 610 unsigned unit = 0; 611 612 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 613 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 614 value = (value + 1) >> 1; 615 unit++; 616 } 617 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 618 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 619 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 620 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 621 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 622 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 623 WARN_ONCE(1, 624 "clamping sdma_phase_quantum to %uK clock cycles\n", 625 value << unit); 626 } 627 phase_quantum = 628 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 629 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 630 } 631 632 for (i = 0; i < adev->sdma.num_instances; i++) { 633 f32_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); 634 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 635 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 636 if (enable && amdgpu_sdma_phase_quantum) { 637 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), 638 phase_quantum); 639 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), 640 phase_quantum); 641 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), 642 phase_quantum); 643 } 644 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); 645 } 646 647 } 648 649 /** 650 * sdma_v4_0_enable - stop the async dma engines 651 * 652 * @adev: amdgpu_device pointer 653 * @enable: enable/disable the DMA MEs. 654 * 655 * Halt or unhalt the async dma engines (VEGA10). 656 */ 657 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable) 658 { 659 u32 f32_cntl; 660 int i; 661 662 if (enable == false) { 663 sdma_v4_0_gfx_stop(adev); 664 sdma_v4_0_rlc_stop(adev); 665 } 666 667 for (i = 0; i < adev->sdma.num_instances; i++) { 668 f32_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 669 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 670 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); 671 } 672 } 673 674 /** 675 * sdma_v4_0_gfx_resume - setup and start the async dma engines 676 * 677 * @adev: amdgpu_device pointer 678 * 679 * Set up the gfx DMA ring buffers and enable them (VEGA10). 680 * Returns 0 for success, error for failure. 681 */ 682 static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev) 683 { 684 struct amdgpu_ring *ring; 685 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 686 u32 rb_bufsz; 687 u32 wb_offset; 688 u32 doorbell; 689 u32 doorbell_offset; 690 u32 temp; 691 u64 wptr_gpu_addr; 692 int i, r; 693 694 for (i = 0; i < adev->sdma.num_instances; i++) { 695 ring = &adev->sdma.instance[i].ring; 696 wb_offset = (ring->rptr_offs * 4); 697 698 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); 699 700 /* Set ring buffer size in dwords */ 701 rb_bufsz = order_base_2(ring->ring_size / 4); 702 rb_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 703 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 704 #ifdef __BIG_ENDIAN 705 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 706 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 707 RPTR_WRITEBACK_SWAP_ENABLE, 1); 708 #endif 709 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 710 711 /* Initialize the ring buffer's read and write pointers */ 712 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); 713 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); 714 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); 715 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); 716 717 /* set the wb address whether it's enabled or not */ 718 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), 719 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 720 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), 721 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 722 723 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 724 725 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8); 726 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40); 727 728 ring->wptr = 0; 729 730 /* before programing wptr to a less value, need set minor_ptr_update first */ 731 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); 732 733 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 734 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2); 735 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); 736 } 737 738 doorbell = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); 739 doorbell_offset = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET)); 740 741 if (ring->use_doorbell) { 742 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 743 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET, 744 OFFSET, ring->doorbell_index); 745 } else { 746 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 747 } 748 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell); 749 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset); 750 adev->nbio_funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 751 ring->doorbell_index); 752 753 if (amdgpu_sriov_vf(adev)) 754 sdma_v4_0_ring_set_wptr(ring); 755 756 /* set minor_ptr_update to 0 after wptr programed */ 757 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); 758 759 /* set utc l1 enable flag always to 1 */ 760 temp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); 761 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 762 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); 763 764 if (!amdgpu_sriov_vf(adev)) { 765 /* unhalt engine */ 766 temp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 767 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 768 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); 769 } 770 771 /* setup the wptr shadow polling */ 772 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 773 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), 774 lower_32_bits(wptr_gpu_addr)); 775 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), 776 upper_32_bits(wptr_gpu_addr)); 777 wptr_poll_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); 778 if (amdgpu_sriov_vf(adev)) 779 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 1); 780 else 781 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 0); 782 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), wptr_poll_cntl); 783 784 /* enable DMA RB */ 785 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 786 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 787 788 ib_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 789 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 790 #ifdef __BIG_ENDIAN 791 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 792 #endif 793 /* enable DMA IBs */ 794 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 795 796 ring->ready = true; 797 798 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ 799 sdma_v4_0_ctx_switch_enable(adev, true); 800 sdma_v4_0_enable(adev, true); 801 } 802 803 r = amdgpu_ring_test_ring(ring); 804 if (r) { 805 ring->ready = false; 806 return r; 807 } 808 809 if (adev->mman.buffer_funcs_ring == ring) 810 amdgpu_ttm_set_buffer_funcs_status(adev, true); 811 812 } 813 814 return 0; 815 } 816 817 static void 818 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable) 819 { 820 uint32_t def, data; 821 822 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) { 823 /* enable idle interrupt */ 824 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 825 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 826 827 if (data != def) 828 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 829 } else { 830 /* disable idle interrupt */ 831 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 832 data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 833 if (data != def) 834 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 835 } 836 } 837 838 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev) 839 { 840 uint32_t def, data; 841 842 /* Enable HW based PG. */ 843 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 844 data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK; 845 if (data != def) 846 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 847 848 /* enable interrupt */ 849 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 850 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 851 if (data != def) 852 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 853 854 /* Configure hold time to filter in-valid power on/off request. Use default right now */ 855 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 856 data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK; 857 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK); 858 /* Configure switch time for hysteresis purpose. Use default right now */ 859 data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK; 860 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK); 861 if(data != def) 862 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 863 } 864 865 static void sdma_v4_0_init_pg(struct amdgpu_device *adev) 866 { 867 if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA)) 868 return; 869 870 switch (adev->asic_type) { 871 case CHIP_RAVEN: 872 sdma_v4_1_init_power_gating(adev); 873 sdma_v4_1_update_power_gating(adev, true); 874 break; 875 default: 876 break; 877 } 878 } 879 880 /** 881 * sdma_v4_0_rlc_resume - setup and start the async dma engines 882 * 883 * @adev: amdgpu_device pointer 884 * 885 * Set up the compute DMA queues and enable them (VEGA10). 886 * Returns 0 for success, error for failure. 887 */ 888 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev) 889 { 890 sdma_v4_0_init_pg(adev); 891 892 return 0; 893 } 894 895 /** 896 * sdma_v4_0_load_microcode - load the sDMA ME ucode 897 * 898 * @adev: amdgpu_device pointer 899 * 900 * Loads the sDMA0/1 ucode. 901 * Returns 0 for success, -EINVAL if the ucode is not available. 902 */ 903 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev) 904 { 905 const struct sdma_firmware_header_v1_0 *hdr; 906 const __le32 *fw_data; 907 u32 fw_size; 908 int i, j; 909 910 /* halt the MEs */ 911 sdma_v4_0_enable(adev, false); 912 913 for (i = 0; i < adev->sdma.num_instances; i++) { 914 if (!adev->sdma.instance[i].fw) 915 return -EINVAL; 916 917 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 918 amdgpu_ucode_print_sdma_hdr(&hdr->header); 919 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 920 921 fw_data = (const __le32 *) 922 (adev->sdma.instance[i].fw->data + 923 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 924 925 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0); 926 927 for (j = 0; j < fw_size; j++) 928 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 929 930 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version); 931 } 932 933 return 0; 934 } 935 936 /** 937 * sdma_v4_0_start - setup and start the async dma engines 938 * 939 * @adev: amdgpu_device pointer 940 * 941 * Set up the DMA engines and enable them (VEGA10). 942 * Returns 0 for success, error for failure. 943 */ 944 static int sdma_v4_0_start(struct amdgpu_device *adev) 945 { 946 int r = 0; 947 948 if (amdgpu_sriov_vf(adev)) { 949 sdma_v4_0_ctx_switch_enable(adev, false); 950 sdma_v4_0_enable(adev, false); 951 952 /* set RB registers */ 953 r = sdma_v4_0_gfx_resume(adev); 954 return r; 955 } 956 957 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 958 r = sdma_v4_0_load_microcode(adev); 959 if (r) 960 return r; 961 } 962 963 /* unhalt the MEs */ 964 sdma_v4_0_enable(adev, true); 965 /* enable sdma ring preemption */ 966 sdma_v4_0_ctx_switch_enable(adev, true); 967 968 /* start the gfx rings and rlc compute queues */ 969 r = sdma_v4_0_gfx_resume(adev); 970 if (r) 971 return r; 972 r = sdma_v4_0_rlc_resume(adev); 973 974 return r; 975 } 976 977 /** 978 * sdma_v4_0_ring_test_ring - simple async dma engine test 979 * 980 * @ring: amdgpu_ring structure holding ring information 981 * 982 * Test the DMA engine by writing using it to write an 983 * value to memory. (VEGA10). 984 * Returns 0 for success, error for failure. 985 */ 986 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring) 987 { 988 struct amdgpu_device *adev = ring->adev; 989 unsigned i; 990 unsigned index; 991 int r; 992 u32 tmp; 993 u64 gpu_addr; 994 995 r = amdgpu_device_wb_get(adev, &index); 996 if (r) { 997 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 998 return r; 999 } 1000 1001 gpu_addr = adev->wb.gpu_addr + (index * 4); 1002 tmp = 0xCAFEDEAD; 1003 adev->wb.wb[index] = cpu_to_le32(tmp); 1004 1005 r = amdgpu_ring_alloc(ring, 5); 1006 if (r) { 1007 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 1008 amdgpu_device_wb_free(adev, index); 1009 return r; 1010 } 1011 1012 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1013 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 1014 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 1015 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 1016 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 1017 amdgpu_ring_write(ring, 0xDEADBEEF); 1018 amdgpu_ring_commit(ring); 1019 1020 for (i = 0; i < adev->usec_timeout; i++) { 1021 tmp = le32_to_cpu(adev->wb.wb[index]); 1022 if (tmp == 0xDEADBEEF) 1023 break; 1024 DRM_UDELAY(1); 1025 } 1026 1027 if (i < adev->usec_timeout) { 1028 DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); 1029 } else { 1030 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 1031 ring->idx, tmp); 1032 r = -EINVAL; 1033 } 1034 amdgpu_device_wb_free(adev, index); 1035 1036 return r; 1037 } 1038 1039 /** 1040 * sdma_v4_0_ring_test_ib - test an IB on the DMA engine 1041 * 1042 * @ring: amdgpu_ring structure holding ring information 1043 * 1044 * Test a simple IB in the DMA ring (VEGA10). 1045 * Returns 0 on success, error on failure. 1046 */ 1047 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1048 { 1049 struct amdgpu_device *adev = ring->adev; 1050 struct amdgpu_ib ib; 1051 struct dma_fence *f = NULL; 1052 unsigned index; 1053 long r; 1054 u32 tmp = 0; 1055 u64 gpu_addr; 1056 1057 r = amdgpu_device_wb_get(adev, &index); 1058 if (r) { 1059 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 1060 return r; 1061 } 1062 1063 gpu_addr = adev->wb.gpu_addr + (index * 4); 1064 tmp = 0xCAFEDEAD; 1065 adev->wb.wb[index] = cpu_to_le32(tmp); 1066 memset(&ib, 0, sizeof(ib)); 1067 r = amdgpu_ib_get(adev, NULL, 256, &ib); 1068 if (r) { 1069 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 1070 goto err0; 1071 } 1072 1073 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1074 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1075 ib.ptr[1] = lower_32_bits(gpu_addr); 1076 ib.ptr[2] = upper_32_bits(gpu_addr); 1077 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1078 ib.ptr[4] = 0xDEADBEEF; 1079 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1080 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1081 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1082 ib.length_dw = 8; 1083 1084 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1085 if (r) 1086 goto err1; 1087 1088 r = dma_fence_wait_timeout(f, false, timeout); 1089 if (r == 0) { 1090 DRM_ERROR("amdgpu: IB test timed out\n"); 1091 r = -ETIMEDOUT; 1092 goto err1; 1093 } else if (r < 0) { 1094 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 1095 goto err1; 1096 } 1097 tmp = le32_to_cpu(adev->wb.wb[index]); 1098 if (tmp == 0xDEADBEEF) { 1099 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); 1100 r = 0; 1101 } else { 1102 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); 1103 r = -EINVAL; 1104 } 1105 err1: 1106 amdgpu_ib_free(adev, &ib, NULL); 1107 dma_fence_put(f); 1108 err0: 1109 amdgpu_device_wb_free(adev, index); 1110 return r; 1111 } 1112 1113 1114 /** 1115 * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART 1116 * 1117 * @ib: indirect buffer to fill with commands 1118 * @pe: addr of the page entry 1119 * @src: src addr to copy from 1120 * @count: number of page entries to update 1121 * 1122 * Update PTEs by copying them from the GART using sDMA (VEGA10). 1123 */ 1124 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib, 1125 uint64_t pe, uint64_t src, 1126 unsigned count) 1127 { 1128 unsigned bytes = count * 8; 1129 1130 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1131 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1132 ib->ptr[ib->length_dw++] = bytes - 1; 1133 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1134 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1135 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1136 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1137 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1138 1139 } 1140 1141 /** 1142 * sdma_v4_0_vm_write_pte - update PTEs by writing them manually 1143 * 1144 * @ib: indirect buffer to fill with commands 1145 * @pe: addr of the page entry 1146 * @addr: dst addr to write into pe 1147 * @count: number of page entries to update 1148 * @incr: increase next addr by incr bytes 1149 * @flags: access flags 1150 * 1151 * Update PTEs by writing them manually using sDMA (VEGA10). 1152 */ 1153 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1154 uint64_t value, unsigned count, 1155 uint32_t incr) 1156 { 1157 unsigned ndw = count * 2; 1158 1159 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1160 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1161 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1162 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1163 ib->ptr[ib->length_dw++] = ndw - 1; 1164 for (; ndw > 0; ndw -= 2) { 1165 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1166 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1167 value += incr; 1168 } 1169 } 1170 1171 /** 1172 * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA 1173 * 1174 * @ib: indirect buffer to fill with commands 1175 * @pe: addr of the page entry 1176 * @addr: dst addr to write into pe 1177 * @count: number of page entries to update 1178 * @incr: increase next addr by incr bytes 1179 * @flags: access flags 1180 * 1181 * Update the page tables using sDMA (VEGA10). 1182 */ 1183 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1184 uint64_t pe, 1185 uint64_t addr, unsigned count, 1186 uint32_t incr, uint64_t flags) 1187 { 1188 /* for physically contiguous pages (vram) */ 1189 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1190 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1191 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1192 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1193 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1194 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1195 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1196 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1197 ib->ptr[ib->length_dw++] = 0; 1198 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1199 } 1200 1201 /** 1202 * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw 1203 * 1204 * @ib: indirect buffer to fill with padding 1205 * 1206 */ 1207 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1208 { 1209 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); 1210 u32 pad_count; 1211 int i; 1212 1213 pad_count = (8 - (ib->length_dw & 0x7)) % 8; 1214 for (i = 0; i < pad_count; i++) 1215 if (sdma && sdma->burst_nop && (i == 0)) 1216 ib->ptr[ib->length_dw++] = 1217 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1218 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1219 else 1220 ib->ptr[ib->length_dw++] = 1221 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1222 } 1223 1224 1225 /** 1226 * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline 1227 * 1228 * @ring: amdgpu_ring pointer 1229 * 1230 * Make sure all previous operations are completed (CIK). 1231 */ 1232 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1233 { 1234 uint32_t seq = ring->fence_drv.sync_seq; 1235 uint64_t addr = ring->fence_drv.gpu_addr; 1236 1237 /* wait for idle */ 1238 sdma_v4_0_wait_reg_mem(ring, 1, 0, 1239 addr & 0xfffffffc, 1240 upper_32_bits(addr) & 0xffffffff, 1241 seq, 0xffffffff, 4); 1242 } 1243 1244 1245 /** 1246 * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA 1247 * 1248 * @ring: amdgpu_ring pointer 1249 * @vm: amdgpu_vm pointer 1250 * 1251 * Update the page table base and flush the VM TLB 1252 * using sDMA (VEGA10). 1253 */ 1254 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1255 unsigned vmid, uint64_t pd_addr) 1256 { 1257 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1258 } 1259 1260 static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring, 1261 uint32_t reg, uint32_t val) 1262 { 1263 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1264 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1265 amdgpu_ring_write(ring, reg); 1266 amdgpu_ring_write(ring, val); 1267 } 1268 1269 static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1270 uint32_t val, uint32_t mask) 1271 { 1272 sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10); 1273 } 1274 1275 static int sdma_v4_0_early_init(void *handle) 1276 { 1277 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1278 1279 if (adev->asic_type == CHIP_RAVEN) 1280 adev->sdma.num_instances = 1; 1281 else 1282 adev->sdma.num_instances = 2; 1283 1284 sdma_v4_0_set_ring_funcs(adev); 1285 sdma_v4_0_set_buffer_funcs(adev); 1286 sdma_v4_0_set_vm_pte_funcs(adev); 1287 sdma_v4_0_set_irq_funcs(adev); 1288 1289 return 0; 1290 } 1291 1292 1293 static int sdma_v4_0_sw_init(void *handle) 1294 { 1295 struct amdgpu_ring *ring; 1296 int r, i; 1297 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1298 1299 /* SDMA trap event */ 1300 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0, SDMA0_4_0__SRCID__SDMA_TRAP, 1301 &adev->sdma.trap_irq); 1302 if (r) 1303 return r; 1304 1305 /* SDMA trap event */ 1306 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1, SDMA1_4_0__SRCID__SDMA_TRAP, 1307 &adev->sdma.trap_irq); 1308 if (r) 1309 return r; 1310 1311 r = sdma_v4_0_init_microcode(adev); 1312 if (r) { 1313 DRM_ERROR("Failed to load sdma firmware!\n"); 1314 return r; 1315 } 1316 1317 for (i = 0; i < adev->sdma.num_instances; i++) { 1318 ring = &adev->sdma.instance[i].ring; 1319 ring->ring_obj = NULL; 1320 ring->use_doorbell = true; 1321 1322 DRM_INFO("use_doorbell being set to: [%s]\n", 1323 ring->use_doorbell?"true":"false"); 1324 1325 if (adev->asic_type == CHIP_VEGA10) 1326 ring->doorbell_index = (i == 0) ? 1327 (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 << 1) //get DWORD offset 1328 : (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 << 1); // get DWORD offset 1329 else 1330 ring->doorbell_index = (i == 0) ? 1331 (AMDGPU_DOORBELL64_sDMA_ENGINE0 << 1) //get DWORD offset 1332 : (AMDGPU_DOORBELL64_sDMA_ENGINE1 << 1); // get DWORD offset 1333 1334 1335 sprintf(ring->name, "sdma%d", i); 1336 r = amdgpu_ring_init(adev, ring, 1024, 1337 &adev->sdma.trap_irq, 1338 (i == 0) ? 1339 AMDGPU_SDMA_IRQ_TRAP0 : 1340 AMDGPU_SDMA_IRQ_TRAP1); 1341 if (r) 1342 return r; 1343 } 1344 1345 return r; 1346 } 1347 1348 static int sdma_v4_0_sw_fini(void *handle) 1349 { 1350 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1351 int i; 1352 1353 for (i = 0; i < adev->sdma.num_instances; i++) 1354 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1355 1356 for (i = 0; i < adev->sdma.num_instances; i++) { 1357 release_firmware(adev->sdma.instance[i].fw); 1358 adev->sdma.instance[i].fw = NULL; 1359 } 1360 1361 return 0; 1362 } 1363 1364 static int sdma_v4_0_hw_init(void *handle) 1365 { 1366 int r; 1367 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1368 1369 if (adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs->set_powergating_by_smu) 1370 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false); 1371 1372 sdma_v4_0_init_golden_registers(adev); 1373 1374 r = sdma_v4_0_start(adev); 1375 1376 return r; 1377 } 1378 1379 static int sdma_v4_0_hw_fini(void *handle) 1380 { 1381 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1382 1383 if (amdgpu_sriov_vf(adev)) 1384 return 0; 1385 1386 sdma_v4_0_ctx_switch_enable(adev, false); 1387 sdma_v4_0_enable(adev, false); 1388 1389 if (adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs->set_powergating_by_smu) 1390 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true); 1391 1392 return 0; 1393 } 1394 1395 static int sdma_v4_0_suspend(void *handle) 1396 { 1397 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1398 1399 return sdma_v4_0_hw_fini(adev); 1400 } 1401 1402 static int sdma_v4_0_resume(void *handle) 1403 { 1404 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1405 1406 return sdma_v4_0_hw_init(adev); 1407 } 1408 1409 static bool sdma_v4_0_is_idle(void *handle) 1410 { 1411 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1412 u32 i; 1413 1414 for (i = 0; i < adev->sdma.num_instances; i++) { 1415 u32 tmp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG)); 1416 1417 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1418 return false; 1419 } 1420 1421 return true; 1422 } 1423 1424 static int sdma_v4_0_wait_for_idle(void *handle) 1425 { 1426 unsigned i; 1427 u32 sdma0, sdma1; 1428 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1429 1430 for (i = 0; i < adev->usec_timeout; i++) { 1431 sdma0 = RREG32(sdma_v4_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG)); 1432 sdma1 = RREG32(sdma_v4_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG)); 1433 1434 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK) 1435 return 0; 1436 udelay(1); 1437 } 1438 return -ETIMEDOUT; 1439 } 1440 1441 static int sdma_v4_0_soft_reset(void *handle) 1442 { 1443 /* todo */ 1444 1445 return 0; 1446 } 1447 1448 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev, 1449 struct amdgpu_irq_src *source, 1450 unsigned type, 1451 enum amdgpu_interrupt_state state) 1452 { 1453 u32 sdma_cntl; 1454 1455 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_TRAP0) ? 1456 sdma_v4_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) : 1457 sdma_v4_0_get_reg_offset(adev, 1, mmSDMA0_CNTL); 1458 1459 sdma_cntl = RREG32(reg_offset); 1460 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1461 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1462 WREG32(reg_offset, sdma_cntl); 1463 1464 return 0; 1465 } 1466 1467 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev, 1468 struct amdgpu_irq_src *source, 1469 struct amdgpu_iv_entry *entry) 1470 { 1471 DRM_DEBUG("IH: SDMA trap\n"); 1472 switch (entry->client_id) { 1473 case SOC15_IH_CLIENTID_SDMA0: 1474 switch (entry->ring_id) { 1475 case 0: 1476 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1477 break; 1478 case 1: 1479 /* XXX compute */ 1480 break; 1481 case 2: 1482 /* XXX compute */ 1483 break; 1484 case 3: 1485 /* XXX page queue*/ 1486 break; 1487 } 1488 break; 1489 case SOC15_IH_CLIENTID_SDMA1: 1490 switch (entry->ring_id) { 1491 case 0: 1492 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1493 break; 1494 case 1: 1495 /* XXX compute */ 1496 break; 1497 case 2: 1498 /* XXX compute */ 1499 break; 1500 case 3: 1501 /* XXX page queue*/ 1502 break; 1503 } 1504 break; 1505 } 1506 return 0; 1507 } 1508 1509 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1510 struct amdgpu_irq_src *source, 1511 struct amdgpu_iv_entry *entry) 1512 { 1513 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1514 schedule_work(&adev->reset_work); 1515 return 0; 1516 } 1517 1518 1519 static void sdma_v4_0_update_medium_grain_clock_gating( 1520 struct amdgpu_device *adev, 1521 bool enable) 1522 { 1523 uint32_t data, def; 1524 1525 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1526 /* enable sdma0 clock gating */ 1527 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 1528 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1529 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1530 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1531 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1532 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1533 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1534 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1535 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1536 if (def != data) 1537 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data); 1538 1539 if (adev->sdma.num_instances > 1) { 1540 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL)); 1541 data &= ~(SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1542 SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1543 SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1544 SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1545 SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1546 SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1547 SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1548 SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1549 if (def != data) 1550 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data); 1551 } 1552 } else { 1553 /* disable sdma0 clock gating */ 1554 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 1555 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1556 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1557 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1558 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1559 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1560 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1561 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1562 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1563 1564 if (def != data) 1565 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data); 1566 1567 if (adev->sdma.num_instances > 1) { 1568 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL)); 1569 data |= (SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1570 SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1571 SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1572 SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1573 SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1574 SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1575 SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1576 SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1577 if (def != data) 1578 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data); 1579 } 1580 } 1581 } 1582 1583 1584 static void sdma_v4_0_update_medium_grain_light_sleep( 1585 struct amdgpu_device *adev, 1586 bool enable) 1587 { 1588 uint32_t data, def; 1589 1590 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1591 /* 1-not override: enable sdma0 mem light sleep */ 1592 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1593 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1594 if (def != data) 1595 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1596 1597 /* 1-not override: enable sdma1 mem light sleep */ 1598 if (adev->sdma.num_instances > 1) { 1599 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL)); 1600 data |= SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1601 if (def != data) 1602 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data); 1603 } 1604 } else { 1605 /* 0-override:disable sdma0 mem light sleep */ 1606 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1607 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1608 if (def != data) 1609 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1610 1611 /* 0-override:disable sdma1 mem light sleep */ 1612 if (adev->sdma.num_instances > 1) { 1613 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL)); 1614 data &= ~SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1615 if (def != data) 1616 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data); 1617 } 1618 } 1619 } 1620 1621 static int sdma_v4_0_set_clockgating_state(void *handle, 1622 enum amd_clockgating_state state) 1623 { 1624 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1625 1626 if (amdgpu_sriov_vf(adev)) 1627 return 0; 1628 1629 switch (adev->asic_type) { 1630 case CHIP_VEGA10: 1631 case CHIP_VEGA12: 1632 case CHIP_VEGA20: 1633 case CHIP_RAVEN: 1634 sdma_v4_0_update_medium_grain_clock_gating(adev, 1635 state == AMD_CG_STATE_GATE ? true : false); 1636 sdma_v4_0_update_medium_grain_light_sleep(adev, 1637 state == AMD_CG_STATE_GATE ? true : false); 1638 break; 1639 default: 1640 break; 1641 } 1642 return 0; 1643 } 1644 1645 static int sdma_v4_0_set_powergating_state(void *handle, 1646 enum amd_powergating_state state) 1647 { 1648 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1649 1650 switch (adev->asic_type) { 1651 case CHIP_RAVEN: 1652 sdma_v4_1_update_power_gating(adev, 1653 state == AMD_PG_STATE_GATE ? true : false); 1654 break; 1655 default: 1656 break; 1657 } 1658 1659 return 0; 1660 } 1661 1662 static void sdma_v4_0_get_clockgating_state(void *handle, u32 *flags) 1663 { 1664 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1665 int data; 1666 1667 if (amdgpu_sriov_vf(adev)) 1668 *flags = 0; 1669 1670 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1671 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 1672 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK)) 1673 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1674 1675 /* AMD_CG_SUPPORT_SDMA_LS */ 1676 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1677 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1678 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1679 } 1680 1681 const struct amd_ip_funcs sdma_v4_0_ip_funcs = { 1682 .name = "sdma_v4_0", 1683 .early_init = sdma_v4_0_early_init, 1684 .late_init = NULL, 1685 .sw_init = sdma_v4_0_sw_init, 1686 .sw_fini = sdma_v4_0_sw_fini, 1687 .hw_init = sdma_v4_0_hw_init, 1688 .hw_fini = sdma_v4_0_hw_fini, 1689 .suspend = sdma_v4_0_suspend, 1690 .resume = sdma_v4_0_resume, 1691 .is_idle = sdma_v4_0_is_idle, 1692 .wait_for_idle = sdma_v4_0_wait_for_idle, 1693 .soft_reset = sdma_v4_0_soft_reset, 1694 .set_clockgating_state = sdma_v4_0_set_clockgating_state, 1695 .set_powergating_state = sdma_v4_0_set_powergating_state, 1696 .get_clockgating_state = sdma_v4_0_get_clockgating_state, 1697 }; 1698 1699 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = { 1700 .type = AMDGPU_RING_TYPE_SDMA, 1701 .align_mask = 0xf, 1702 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1703 .support_64bit_ptrs = true, 1704 .vmhub = AMDGPU_MMHUB, 1705 .get_rptr = sdma_v4_0_ring_get_rptr, 1706 .get_wptr = sdma_v4_0_ring_get_wptr, 1707 .set_wptr = sdma_v4_0_ring_set_wptr, 1708 .emit_frame_size = 1709 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 1710 3 + /* hdp invalidate */ 1711 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 1712 /* sdma_v4_0_ring_emit_vm_flush */ 1713 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1714 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1715 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 1716 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 1717 .emit_ib = sdma_v4_0_ring_emit_ib, 1718 .emit_fence = sdma_v4_0_ring_emit_fence, 1719 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 1720 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 1721 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 1722 .test_ring = sdma_v4_0_ring_test_ring, 1723 .test_ib = sdma_v4_0_ring_test_ib, 1724 .insert_nop = sdma_v4_0_ring_insert_nop, 1725 .pad_ib = sdma_v4_0_ring_pad_ib, 1726 .emit_wreg = sdma_v4_0_ring_emit_wreg, 1727 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 1728 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1729 }; 1730 1731 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev) 1732 { 1733 int i; 1734 1735 for (i = 0; i < adev->sdma.num_instances; i++) { 1736 adev->sdma.instance[i].ring.funcs = &sdma_v4_0_ring_funcs; 1737 adev->sdma.instance[i].ring.me = i; 1738 } 1739 } 1740 1741 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = { 1742 .set = sdma_v4_0_set_trap_irq_state, 1743 .process = sdma_v4_0_process_trap_irq, 1744 }; 1745 1746 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = { 1747 .process = sdma_v4_0_process_illegal_inst_irq, 1748 }; 1749 1750 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev) 1751 { 1752 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 1753 adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs; 1754 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs; 1755 } 1756 1757 /** 1758 * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine 1759 * 1760 * @ring: amdgpu_ring structure holding ring information 1761 * @src_offset: src GPU address 1762 * @dst_offset: dst GPU address 1763 * @byte_count: number of bytes to xfer 1764 * 1765 * Copy GPU buffers using the DMA engine (VEGA10/12). 1766 * Used by the amdgpu ttm implementation to move pages if 1767 * registered as the asic copy callback. 1768 */ 1769 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib, 1770 uint64_t src_offset, 1771 uint64_t dst_offset, 1772 uint32_t byte_count) 1773 { 1774 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1775 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1776 ib->ptr[ib->length_dw++] = byte_count - 1; 1777 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1778 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1779 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1780 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1781 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1782 } 1783 1784 /** 1785 * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine 1786 * 1787 * @ring: amdgpu_ring structure holding ring information 1788 * @src_data: value to write to buffer 1789 * @dst_offset: dst GPU address 1790 * @byte_count: number of bytes to xfer 1791 * 1792 * Fill GPU buffers using the DMA engine (VEGA10/12). 1793 */ 1794 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib, 1795 uint32_t src_data, 1796 uint64_t dst_offset, 1797 uint32_t byte_count) 1798 { 1799 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1800 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1801 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1802 ib->ptr[ib->length_dw++] = src_data; 1803 ib->ptr[ib->length_dw++] = byte_count - 1; 1804 } 1805 1806 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = { 1807 .copy_max_bytes = 0x400000, 1808 .copy_num_dw = 7, 1809 .emit_copy_buffer = sdma_v4_0_emit_copy_buffer, 1810 1811 .fill_max_bytes = 0x400000, 1812 .fill_num_dw = 5, 1813 .emit_fill_buffer = sdma_v4_0_emit_fill_buffer, 1814 }; 1815 1816 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev) 1817 { 1818 adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs; 1819 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1820 } 1821 1822 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = { 1823 .copy_pte_num_dw = 7, 1824 .copy_pte = sdma_v4_0_vm_copy_pte, 1825 1826 .write_pte = sdma_v4_0_vm_write_pte, 1827 .set_pte_pde = sdma_v4_0_vm_set_pte_pde, 1828 }; 1829 1830 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1831 { 1832 struct drm_gpu_scheduler *sched; 1833 unsigned i; 1834 1835 adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs; 1836 for (i = 0; i < adev->sdma.num_instances; i++) { 1837 sched = &adev->sdma.instance[i].ring.sched; 1838 adev->vm_manager.vm_pte_rqs[i] = 1839 &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL]; 1840 } 1841 adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances; 1842 } 1843 1844 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = { 1845 .type = AMD_IP_BLOCK_TYPE_SDMA, 1846 .major = 4, 1847 .minor = 0, 1848 .rev = 0, 1849 .funcs = &sdma_v4_0_ip_funcs, 1850 }; 1851