1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_ucode.h" 28 #include "amdgpu_trace.h" 29 30 #include "sdma0/sdma0_4_0_offset.h" 31 #include "sdma0/sdma0_4_0_sh_mask.h" 32 #include "sdma1/sdma1_4_0_offset.h" 33 #include "sdma1/sdma1_4_0_sh_mask.h" 34 #include "hdp/hdp_4_0_offset.h" 35 #include "sdma0/sdma0_4_1_default.h" 36 37 #include "soc15_common.h" 38 #include "soc15.h" 39 #include "vega10_sdma_pkt_open.h" 40 41 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin"); 42 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin"); 43 MODULE_FIRMWARE("amdgpu/raven_sdma.bin"); 44 45 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L 46 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L 47 48 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev); 49 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev); 50 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev); 51 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev); 52 53 static const struct soc15_reg_golden golden_settings_sdma_4[] = { 54 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 55 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100), 56 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100), 57 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 58 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 59 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 60 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000), 61 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 62 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 63 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 64 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 65 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 66 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 67 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), 68 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100), 69 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 70 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 71 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 72 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000), 73 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 74 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 75 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 76 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 77 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0) 78 }; 79 80 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = { 81 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 82 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 83 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 84 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002) 85 }; 86 87 static const struct soc15_reg_golden golden_settings_sdma_4_1[] = 88 { 89 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 90 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 91 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100), 92 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 93 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051), 94 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100), 95 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 96 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100), 97 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 98 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0) 99 }; 100 101 static const struct soc15_reg_golden golden_settings_sdma_rv1[] = 102 { 103 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002), 104 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002) 105 }; 106 107 static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev, 108 u32 instance, u32 offset) 109 { 110 return ( 0 == instance ? (adev->reg_offset[SDMA0_HWIP][0][0] + offset) : 111 (adev->reg_offset[SDMA1_HWIP][0][0] + offset)); 112 } 113 114 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) 115 { 116 switch (adev->asic_type) { 117 case CHIP_VEGA10: 118 soc15_program_register_sequence(adev, 119 golden_settings_sdma_4, 120 ARRAY_SIZE(golden_settings_sdma_4)); 121 soc15_program_register_sequence(adev, 122 golden_settings_sdma_vg10, 123 ARRAY_SIZE(golden_settings_sdma_vg10)); 124 break; 125 case CHIP_RAVEN: 126 soc15_program_register_sequence(adev, 127 golden_settings_sdma_4_1, 128 ARRAY_SIZE(golden_settings_sdma_4_1)); 129 soc15_program_register_sequence(adev, 130 golden_settings_sdma_rv1, 131 ARRAY_SIZE(golden_settings_sdma_rv1)); 132 break; 133 default: 134 break; 135 } 136 } 137 138 /** 139 * sdma_v4_0_init_microcode - load ucode images from disk 140 * 141 * @adev: amdgpu_device pointer 142 * 143 * Use the firmware interface to load the ucode images into 144 * the driver (not loaded into hw). 145 * Returns 0 on success, error on failure. 146 */ 147 148 // emulation only, won't work on real chip 149 // vega10 real chip need to use PSP to load firmware 150 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev) 151 { 152 const char *chip_name; 153 char fw_name[30]; 154 int err = 0, i; 155 struct amdgpu_firmware_info *info = NULL; 156 const struct common_firmware_header *header = NULL; 157 const struct sdma_firmware_header_v1_0 *hdr; 158 159 DRM_DEBUG("\n"); 160 161 switch (adev->asic_type) { 162 case CHIP_VEGA10: 163 chip_name = "vega10"; 164 break; 165 case CHIP_RAVEN: 166 chip_name = "raven"; 167 break; 168 default: 169 BUG(); 170 } 171 172 for (i = 0; i < adev->sdma.num_instances; i++) { 173 if (i == 0) 174 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 175 else 176 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); 177 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 178 if (err) 179 goto out; 180 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); 181 if (err) 182 goto out; 183 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 184 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 185 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 186 if (adev->sdma.instance[i].feature_version >= 20) 187 adev->sdma.instance[i].burst_nop = true; 188 DRM_DEBUG("psp_load == '%s'\n", 189 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); 190 191 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 192 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 193 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 194 info->fw = adev->sdma.instance[i].fw; 195 header = (const struct common_firmware_header *)info->fw->data; 196 adev->firmware.fw_size += 197 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 198 } 199 } 200 out: 201 if (err) { 202 DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name); 203 for (i = 0; i < adev->sdma.num_instances; i++) { 204 release_firmware(adev->sdma.instance[i].fw); 205 adev->sdma.instance[i].fw = NULL; 206 } 207 } 208 return err; 209 } 210 211 /** 212 * sdma_v4_0_ring_get_rptr - get the current read pointer 213 * 214 * @ring: amdgpu ring pointer 215 * 216 * Get the current rptr from the hardware (VEGA10+). 217 */ 218 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring) 219 { 220 u64 *rptr; 221 222 /* XXX check if swapping is necessary on BE */ 223 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]); 224 225 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 226 return ((*rptr) >> 2); 227 } 228 229 /** 230 * sdma_v4_0_ring_get_wptr - get the current write pointer 231 * 232 * @ring: amdgpu ring pointer 233 * 234 * Get the current wptr from the hardware (VEGA10+). 235 */ 236 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring) 237 { 238 struct amdgpu_device *adev = ring->adev; 239 u64 wptr; 240 241 if (ring->use_doorbell) { 242 /* XXX check if swapping is necessary on BE */ 243 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 244 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 245 } else { 246 u32 lowbit, highbit; 247 int me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1; 248 249 lowbit = RREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR)) >> 2; 250 highbit = RREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2; 251 252 DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n", 253 me, highbit, lowbit); 254 wptr = highbit; 255 wptr = wptr << 32; 256 wptr |= lowbit; 257 } 258 259 return wptr >> 2; 260 } 261 262 /** 263 * sdma_v4_0_ring_set_wptr - commit the write pointer 264 * 265 * @ring: amdgpu ring pointer 266 * 267 * Write the wptr back to the hardware (VEGA10+). 268 */ 269 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring) 270 { 271 struct amdgpu_device *adev = ring->adev; 272 273 DRM_DEBUG("Setting write pointer\n"); 274 if (ring->use_doorbell) { 275 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 276 277 DRM_DEBUG("Using doorbell -- " 278 "wptr_offs == 0x%08x " 279 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 280 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 281 ring->wptr_offs, 282 lower_32_bits(ring->wptr << 2), 283 upper_32_bits(ring->wptr << 2)); 284 /* XXX check if swapping is necessary on BE */ 285 WRITE_ONCE(*wb, (ring->wptr << 2)); 286 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 287 ring->doorbell_index, ring->wptr << 2); 288 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 289 } else { 290 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1; 291 292 DRM_DEBUG("Not using doorbell -- " 293 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 294 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 295 me, 296 lower_32_bits(ring->wptr << 2), 297 me, 298 upper_32_bits(ring->wptr << 2)); 299 WREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2)); 300 WREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2)); 301 } 302 } 303 304 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 305 { 306 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); 307 int i; 308 309 for (i = 0; i < count; i++) 310 if (sdma && sdma->burst_nop && (i == 0)) 311 amdgpu_ring_write(ring, ring->funcs->nop | 312 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 313 else 314 amdgpu_ring_write(ring, ring->funcs->nop); 315 } 316 317 /** 318 * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine 319 * 320 * @ring: amdgpu ring pointer 321 * @ib: IB object to schedule 322 * 323 * Schedule an IB in the DMA ring (VEGA10). 324 */ 325 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring, 326 struct amdgpu_ib *ib, 327 unsigned vmid, bool ctx_switch) 328 { 329 /* IB packet must end on a 8 DW boundary */ 330 sdma_v4_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8); 331 332 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 333 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 334 /* base must be 32 byte aligned */ 335 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 336 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 337 amdgpu_ring_write(ring, ib->length_dw); 338 amdgpu_ring_write(ring, 0); 339 amdgpu_ring_write(ring, 0); 340 341 } 342 343 /** 344 * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 345 * 346 * @ring: amdgpu ring pointer 347 * 348 * Emit an hdp flush packet on the requested DMA ring. 349 */ 350 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 351 { 352 struct amdgpu_device *adev = ring->adev; 353 u32 ref_and_mask = 0; 354 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg; 355 356 if (ring == &ring->adev->sdma.instance[0].ring) 357 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0; 358 else 359 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1; 360 361 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 362 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 363 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 364 amdgpu_ring_write(ring, (adev->nbio_funcs->get_hdp_flush_done_offset(adev)) << 2); 365 amdgpu_ring_write(ring, (adev->nbio_funcs->get_hdp_flush_req_offset(adev)) << 2); 366 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 367 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 368 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 369 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 370 } 371 372 /** 373 * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring 374 * 375 * @ring: amdgpu ring pointer 376 * @fence: amdgpu fence object 377 * 378 * Add a DMA fence packet to the ring to write 379 * the fence seq number and DMA trap packet to generate 380 * an interrupt if needed (VEGA10). 381 */ 382 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 383 unsigned flags) 384 { 385 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 386 /* write the fence */ 387 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 388 /* zero in first two bits */ 389 BUG_ON(addr & 0x3); 390 amdgpu_ring_write(ring, lower_32_bits(addr)); 391 amdgpu_ring_write(ring, upper_32_bits(addr)); 392 amdgpu_ring_write(ring, lower_32_bits(seq)); 393 394 /* optionally write high bits as well */ 395 if (write64bit) { 396 addr += 4; 397 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 398 /* zero in first two bits */ 399 BUG_ON(addr & 0x3); 400 amdgpu_ring_write(ring, lower_32_bits(addr)); 401 amdgpu_ring_write(ring, upper_32_bits(addr)); 402 amdgpu_ring_write(ring, upper_32_bits(seq)); 403 } 404 405 /* generate an interrupt */ 406 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 407 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 408 } 409 410 411 /** 412 * sdma_v4_0_gfx_stop - stop the gfx async dma engines 413 * 414 * @adev: amdgpu_device pointer 415 * 416 * Stop the gfx async dma ring buffers (VEGA10). 417 */ 418 static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev) 419 { 420 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 421 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 422 u32 rb_cntl, ib_cntl; 423 int i; 424 425 if ((adev->mman.buffer_funcs_ring == sdma0) || 426 (adev->mman.buffer_funcs_ring == sdma1)) 427 amdgpu_ttm_set_buffer_funcs_status(adev, false); 428 429 for (i = 0; i < adev->sdma.num_instances; i++) { 430 rb_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 431 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 432 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 433 ib_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 434 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 435 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 436 } 437 438 sdma0->ready = false; 439 sdma1->ready = false; 440 } 441 442 /** 443 * sdma_v4_0_rlc_stop - stop the compute async dma engines 444 * 445 * @adev: amdgpu_device pointer 446 * 447 * Stop the compute async dma queues (VEGA10). 448 */ 449 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev) 450 { 451 /* XXX todo */ 452 } 453 454 /** 455 * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch 456 * 457 * @adev: amdgpu_device pointer 458 * @enable: enable/disable the DMA MEs context switch. 459 * 460 * Halt or unhalt the async dma engines context switch (VEGA10). 461 */ 462 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 463 { 464 u32 f32_cntl, phase_quantum = 0; 465 int i; 466 467 if (amdgpu_sdma_phase_quantum) { 468 unsigned value = amdgpu_sdma_phase_quantum; 469 unsigned unit = 0; 470 471 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 472 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 473 value = (value + 1) >> 1; 474 unit++; 475 } 476 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 477 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 478 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 479 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 480 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 481 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 482 WARN_ONCE(1, 483 "clamping sdma_phase_quantum to %uK clock cycles\n", 484 value << unit); 485 } 486 phase_quantum = 487 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 488 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 489 } 490 491 for (i = 0; i < adev->sdma.num_instances; i++) { 492 f32_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); 493 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 494 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 495 if (enable && amdgpu_sdma_phase_quantum) { 496 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), 497 phase_quantum); 498 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), 499 phase_quantum); 500 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), 501 phase_quantum); 502 } 503 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); 504 } 505 506 } 507 508 /** 509 * sdma_v4_0_enable - stop the async dma engines 510 * 511 * @adev: amdgpu_device pointer 512 * @enable: enable/disable the DMA MEs. 513 * 514 * Halt or unhalt the async dma engines (VEGA10). 515 */ 516 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable) 517 { 518 u32 f32_cntl; 519 int i; 520 521 if (enable == false) { 522 sdma_v4_0_gfx_stop(adev); 523 sdma_v4_0_rlc_stop(adev); 524 } 525 526 for (i = 0; i < adev->sdma.num_instances; i++) { 527 f32_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 528 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 529 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); 530 } 531 } 532 533 /** 534 * sdma_v4_0_gfx_resume - setup and start the async dma engines 535 * 536 * @adev: amdgpu_device pointer 537 * 538 * Set up the gfx DMA ring buffers and enable them (VEGA10). 539 * Returns 0 for success, error for failure. 540 */ 541 static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev) 542 { 543 struct amdgpu_ring *ring; 544 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 545 u32 rb_bufsz; 546 u32 wb_offset; 547 u32 doorbell; 548 u32 doorbell_offset; 549 u32 temp; 550 u64 wptr_gpu_addr; 551 int i, r; 552 553 for (i = 0; i < adev->sdma.num_instances; i++) { 554 ring = &adev->sdma.instance[i].ring; 555 wb_offset = (ring->rptr_offs * 4); 556 557 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); 558 559 /* Set ring buffer size in dwords */ 560 rb_bufsz = order_base_2(ring->ring_size / 4); 561 rb_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 562 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 563 #ifdef __BIG_ENDIAN 564 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 565 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 566 RPTR_WRITEBACK_SWAP_ENABLE, 1); 567 #endif 568 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 569 570 /* Initialize the ring buffer's read and write pointers */ 571 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); 572 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); 573 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); 574 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); 575 576 /* set the wb address whether it's enabled or not */ 577 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), 578 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 579 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), 580 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 581 582 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 583 584 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8); 585 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40); 586 587 ring->wptr = 0; 588 589 /* before programing wptr to a less value, need set minor_ptr_update first */ 590 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); 591 592 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 593 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2); 594 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); 595 } 596 597 doorbell = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); 598 doorbell_offset = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET)); 599 600 if (ring->use_doorbell) { 601 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 602 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET, 603 OFFSET, ring->doorbell_index); 604 } else { 605 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 606 } 607 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell); 608 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset); 609 adev->nbio_funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 610 ring->doorbell_index); 611 612 if (amdgpu_sriov_vf(adev)) 613 sdma_v4_0_ring_set_wptr(ring); 614 615 /* set minor_ptr_update to 0 after wptr programed */ 616 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); 617 618 /* set utc l1 enable flag always to 1 */ 619 temp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); 620 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 621 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); 622 623 if (!amdgpu_sriov_vf(adev)) { 624 /* unhalt engine */ 625 temp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 626 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 627 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); 628 } 629 630 /* setup the wptr shadow polling */ 631 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 632 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), 633 lower_32_bits(wptr_gpu_addr)); 634 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), 635 upper_32_bits(wptr_gpu_addr)); 636 wptr_poll_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); 637 if (amdgpu_sriov_vf(adev)) 638 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 1); 639 else 640 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 0); 641 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), wptr_poll_cntl); 642 643 /* enable DMA RB */ 644 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 645 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 646 647 ib_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 648 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 649 #ifdef __BIG_ENDIAN 650 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 651 #endif 652 /* enable DMA IBs */ 653 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 654 655 ring->ready = true; 656 657 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ 658 sdma_v4_0_ctx_switch_enable(adev, true); 659 sdma_v4_0_enable(adev, true); 660 } 661 662 r = amdgpu_ring_test_ring(ring); 663 if (r) { 664 ring->ready = false; 665 return r; 666 } 667 668 if (adev->mman.buffer_funcs_ring == ring) 669 amdgpu_ttm_set_buffer_funcs_status(adev, true); 670 671 } 672 673 return 0; 674 } 675 676 static void 677 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable) 678 { 679 uint32_t def, data; 680 681 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) { 682 /* disable idle interrupt */ 683 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 684 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 685 686 if (data != def) 687 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 688 } else { 689 /* disable idle interrupt */ 690 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 691 data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 692 if (data != def) 693 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 694 } 695 } 696 697 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev) 698 { 699 uint32_t def, data; 700 701 /* Enable HW based PG. */ 702 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 703 data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK; 704 if (data != def) 705 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 706 707 /* enable interrupt */ 708 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 709 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 710 if (data != def) 711 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 712 713 /* Configure hold time to filter in-valid power on/off request. Use default right now */ 714 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 715 data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK; 716 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK); 717 /* Configure switch time for hysteresis purpose. Use default right now */ 718 data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK; 719 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK); 720 if(data != def) 721 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 722 } 723 724 static void sdma_v4_0_init_pg(struct amdgpu_device *adev) 725 { 726 if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA)) 727 return; 728 729 switch (adev->asic_type) { 730 case CHIP_RAVEN: 731 sdma_v4_1_init_power_gating(adev); 732 sdma_v4_1_update_power_gating(adev, true); 733 break; 734 default: 735 break; 736 } 737 } 738 739 /** 740 * sdma_v4_0_rlc_resume - setup and start the async dma engines 741 * 742 * @adev: amdgpu_device pointer 743 * 744 * Set up the compute DMA queues and enable them (VEGA10). 745 * Returns 0 for success, error for failure. 746 */ 747 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev) 748 { 749 sdma_v4_0_init_pg(adev); 750 751 return 0; 752 } 753 754 /** 755 * sdma_v4_0_load_microcode - load the sDMA ME ucode 756 * 757 * @adev: amdgpu_device pointer 758 * 759 * Loads the sDMA0/1 ucode. 760 * Returns 0 for success, -EINVAL if the ucode is not available. 761 */ 762 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev) 763 { 764 const struct sdma_firmware_header_v1_0 *hdr; 765 const __le32 *fw_data; 766 u32 fw_size; 767 int i, j; 768 769 /* halt the MEs */ 770 sdma_v4_0_enable(adev, false); 771 772 for (i = 0; i < adev->sdma.num_instances; i++) { 773 if (!adev->sdma.instance[i].fw) 774 return -EINVAL; 775 776 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 777 amdgpu_ucode_print_sdma_hdr(&hdr->header); 778 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 779 780 fw_data = (const __le32 *) 781 (adev->sdma.instance[i].fw->data + 782 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 783 784 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0); 785 786 for (j = 0; j < fw_size; j++) 787 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 788 789 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version); 790 } 791 792 return 0; 793 } 794 795 /** 796 * sdma_v4_0_start - setup and start the async dma engines 797 * 798 * @adev: amdgpu_device pointer 799 * 800 * Set up the DMA engines and enable them (VEGA10). 801 * Returns 0 for success, error for failure. 802 */ 803 static int sdma_v4_0_start(struct amdgpu_device *adev) 804 { 805 int r = 0; 806 807 if (amdgpu_sriov_vf(adev)) { 808 sdma_v4_0_ctx_switch_enable(adev, false); 809 sdma_v4_0_enable(adev, false); 810 811 /* set RB registers */ 812 r = sdma_v4_0_gfx_resume(adev); 813 return r; 814 } 815 816 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 817 r = sdma_v4_0_load_microcode(adev); 818 if (r) 819 return r; 820 } 821 822 /* unhalt the MEs */ 823 sdma_v4_0_enable(adev, true); 824 /* enable sdma ring preemption */ 825 sdma_v4_0_ctx_switch_enable(adev, true); 826 827 /* start the gfx rings and rlc compute queues */ 828 r = sdma_v4_0_gfx_resume(adev); 829 if (r) 830 return r; 831 r = sdma_v4_0_rlc_resume(adev); 832 833 return r; 834 } 835 836 /** 837 * sdma_v4_0_ring_test_ring - simple async dma engine test 838 * 839 * @ring: amdgpu_ring structure holding ring information 840 * 841 * Test the DMA engine by writing using it to write an 842 * value to memory. (VEGA10). 843 * Returns 0 for success, error for failure. 844 */ 845 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring) 846 { 847 struct amdgpu_device *adev = ring->adev; 848 unsigned i; 849 unsigned index; 850 int r; 851 u32 tmp; 852 u64 gpu_addr; 853 854 r = amdgpu_device_wb_get(adev, &index); 855 if (r) { 856 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 857 return r; 858 } 859 860 gpu_addr = adev->wb.gpu_addr + (index * 4); 861 tmp = 0xCAFEDEAD; 862 adev->wb.wb[index] = cpu_to_le32(tmp); 863 864 r = amdgpu_ring_alloc(ring, 5); 865 if (r) { 866 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 867 amdgpu_device_wb_free(adev, index); 868 return r; 869 } 870 871 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 872 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 873 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 874 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 875 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 876 amdgpu_ring_write(ring, 0xDEADBEEF); 877 amdgpu_ring_commit(ring); 878 879 for (i = 0; i < adev->usec_timeout; i++) { 880 tmp = le32_to_cpu(adev->wb.wb[index]); 881 if (tmp == 0xDEADBEEF) 882 break; 883 DRM_UDELAY(1); 884 } 885 886 if (i < adev->usec_timeout) { 887 DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); 888 } else { 889 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 890 ring->idx, tmp); 891 r = -EINVAL; 892 } 893 amdgpu_device_wb_free(adev, index); 894 895 return r; 896 } 897 898 /** 899 * sdma_v4_0_ring_test_ib - test an IB on the DMA engine 900 * 901 * @ring: amdgpu_ring structure holding ring information 902 * 903 * Test a simple IB in the DMA ring (VEGA10). 904 * Returns 0 on success, error on failure. 905 */ 906 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 907 { 908 struct amdgpu_device *adev = ring->adev; 909 struct amdgpu_ib ib; 910 struct dma_fence *f = NULL; 911 unsigned index; 912 long r; 913 u32 tmp = 0; 914 u64 gpu_addr; 915 916 r = amdgpu_device_wb_get(adev, &index); 917 if (r) { 918 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 919 return r; 920 } 921 922 gpu_addr = adev->wb.gpu_addr + (index * 4); 923 tmp = 0xCAFEDEAD; 924 adev->wb.wb[index] = cpu_to_le32(tmp); 925 memset(&ib, 0, sizeof(ib)); 926 r = amdgpu_ib_get(adev, NULL, 256, &ib); 927 if (r) { 928 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 929 goto err0; 930 } 931 932 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 933 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 934 ib.ptr[1] = lower_32_bits(gpu_addr); 935 ib.ptr[2] = upper_32_bits(gpu_addr); 936 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 937 ib.ptr[4] = 0xDEADBEEF; 938 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 939 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 940 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 941 ib.length_dw = 8; 942 943 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 944 if (r) 945 goto err1; 946 947 r = dma_fence_wait_timeout(f, false, timeout); 948 if (r == 0) { 949 DRM_ERROR("amdgpu: IB test timed out\n"); 950 r = -ETIMEDOUT; 951 goto err1; 952 } else if (r < 0) { 953 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 954 goto err1; 955 } 956 tmp = le32_to_cpu(adev->wb.wb[index]); 957 if (tmp == 0xDEADBEEF) { 958 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); 959 r = 0; 960 } else { 961 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); 962 r = -EINVAL; 963 } 964 err1: 965 amdgpu_ib_free(adev, &ib, NULL); 966 dma_fence_put(f); 967 err0: 968 amdgpu_device_wb_free(adev, index); 969 return r; 970 } 971 972 973 /** 974 * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART 975 * 976 * @ib: indirect buffer to fill with commands 977 * @pe: addr of the page entry 978 * @src: src addr to copy from 979 * @count: number of page entries to update 980 * 981 * Update PTEs by copying them from the GART using sDMA (VEGA10). 982 */ 983 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib, 984 uint64_t pe, uint64_t src, 985 unsigned count) 986 { 987 unsigned bytes = count * 8; 988 989 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 990 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 991 ib->ptr[ib->length_dw++] = bytes - 1; 992 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 993 ib->ptr[ib->length_dw++] = lower_32_bits(src); 994 ib->ptr[ib->length_dw++] = upper_32_bits(src); 995 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 996 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 997 998 } 999 1000 /** 1001 * sdma_v4_0_vm_write_pte - update PTEs by writing them manually 1002 * 1003 * @ib: indirect buffer to fill with commands 1004 * @pe: addr of the page entry 1005 * @addr: dst addr to write into pe 1006 * @count: number of page entries to update 1007 * @incr: increase next addr by incr bytes 1008 * @flags: access flags 1009 * 1010 * Update PTEs by writing them manually using sDMA (VEGA10). 1011 */ 1012 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1013 uint64_t value, unsigned count, 1014 uint32_t incr) 1015 { 1016 unsigned ndw = count * 2; 1017 1018 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1019 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1020 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1021 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1022 ib->ptr[ib->length_dw++] = ndw - 1; 1023 for (; ndw > 0; ndw -= 2) { 1024 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1025 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1026 value += incr; 1027 } 1028 } 1029 1030 /** 1031 * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA 1032 * 1033 * @ib: indirect buffer to fill with commands 1034 * @pe: addr of the page entry 1035 * @addr: dst addr to write into pe 1036 * @count: number of page entries to update 1037 * @incr: increase next addr by incr bytes 1038 * @flags: access flags 1039 * 1040 * Update the page tables using sDMA (VEGA10). 1041 */ 1042 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1043 uint64_t pe, 1044 uint64_t addr, unsigned count, 1045 uint32_t incr, uint64_t flags) 1046 { 1047 /* for physically contiguous pages (vram) */ 1048 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1049 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1050 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1051 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1052 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1053 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1054 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1055 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1056 ib->ptr[ib->length_dw++] = 0; 1057 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1058 } 1059 1060 /** 1061 * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw 1062 * 1063 * @ib: indirect buffer to fill with padding 1064 * 1065 */ 1066 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1067 { 1068 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); 1069 u32 pad_count; 1070 int i; 1071 1072 pad_count = (8 - (ib->length_dw & 0x7)) % 8; 1073 for (i = 0; i < pad_count; i++) 1074 if (sdma && sdma->burst_nop && (i == 0)) 1075 ib->ptr[ib->length_dw++] = 1076 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1077 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1078 else 1079 ib->ptr[ib->length_dw++] = 1080 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1081 } 1082 1083 1084 /** 1085 * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline 1086 * 1087 * @ring: amdgpu_ring pointer 1088 * 1089 * Make sure all previous operations are completed (CIK). 1090 */ 1091 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1092 { 1093 uint32_t seq = ring->fence_drv.sync_seq; 1094 uint64_t addr = ring->fence_drv.gpu_addr; 1095 1096 /* wait for idle */ 1097 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1098 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1099 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1100 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1101 amdgpu_ring_write(ring, addr & 0xfffffffc); 1102 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1103 amdgpu_ring_write(ring, seq); /* reference */ 1104 amdgpu_ring_write(ring, 0xfffffff); /* mask */ 1105 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1106 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1107 } 1108 1109 1110 /** 1111 * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA 1112 * 1113 * @ring: amdgpu_ring pointer 1114 * @vm: amdgpu_vm pointer 1115 * 1116 * Update the page table base and flush the VM TLB 1117 * using sDMA (VEGA10). 1118 */ 1119 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1120 unsigned vmid, uint64_t pd_addr) 1121 { 1122 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1123 } 1124 1125 static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring, 1126 uint32_t reg, uint32_t val) 1127 { 1128 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1129 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1130 amdgpu_ring_write(ring, reg); 1131 amdgpu_ring_write(ring, val); 1132 } 1133 1134 static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1135 uint32_t val, uint32_t mask) 1136 { 1137 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1138 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1139 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ 1140 amdgpu_ring_write(ring, reg << 2); 1141 amdgpu_ring_write(ring, 0); 1142 amdgpu_ring_write(ring, val); /* reference */ 1143 amdgpu_ring_write(ring, mask); /* mask */ 1144 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1145 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); 1146 } 1147 1148 static int sdma_v4_0_early_init(void *handle) 1149 { 1150 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1151 1152 if (adev->asic_type == CHIP_RAVEN) 1153 adev->sdma.num_instances = 1; 1154 else 1155 adev->sdma.num_instances = 2; 1156 1157 sdma_v4_0_set_ring_funcs(adev); 1158 sdma_v4_0_set_buffer_funcs(adev); 1159 sdma_v4_0_set_vm_pte_funcs(adev); 1160 sdma_v4_0_set_irq_funcs(adev); 1161 1162 return 0; 1163 } 1164 1165 1166 static int sdma_v4_0_sw_init(void *handle) 1167 { 1168 struct amdgpu_ring *ring; 1169 int r, i; 1170 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1171 1172 /* SDMA trap event */ 1173 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0, 224, 1174 &adev->sdma.trap_irq); 1175 if (r) 1176 return r; 1177 1178 /* SDMA trap event */ 1179 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1, 224, 1180 &adev->sdma.trap_irq); 1181 if (r) 1182 return r; 1183 1184 r = sdma_v4_0_init_microcode(adev); 1185 if (r) { 1186 DRM_ERROR("Failed to load sdma firmware!\n"); 1187 return r; 1188 } 1189 1190 for (i = 0; i < adev->sdma.num_instances; i++) { 1191 ring = &adev->sdma.instance[i].ring; 1192 ring->ring_obj = NULL; 1193 ring->use_doorbell = true; 1194 1195 DRM_INFO("use_doorbell being set to: [%s]\n", 1196 ring->use_doorbell?"true":"false"); 1197 1198 ring->doorbell_index = (i == 0) ? 1199 (AMDGPU_DOORBELL64_sDMA_ENGINE0 << 1) //get DWORD offset 1200 : (AMDGPU_DOORBELL64_sDMA_ENGINE1 << 1); // get DWORD offset 1201 1202 sprintf(ring->name, "sdma%d", i); 1203 r = amdgpu_ring_init(adev, ring, 1024, 1204 &adev->sdma.trap_irq, 1205 (i == 0) ? 1206 AMDGPU_SDMA_IRQ_TRAP0 : 1207 AMDGPU_SDMA_IRQ_TRAP1); 1208 if (r) 1209 return r; 1210 } 1211 1212 return r; 1213 } 1214 1215 static int sdma_v4_0_sw_fini(void *handle) 1216 { 1217 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1218 int i; 1219 1220 for (i = 0; i < adev->sdma.num_instances; i++) 1221 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1222 1223 for (i = 0; i < adev->sdma.num_instances; i++) { 1224 release_firmware(adev->sdma.instance[i].fw); 1225 adev->sdma.instance[i].fw = NULL; 1226 } 1227 1228 return 0; 1229 } 1230 1231 static int sdma_v4_0_hw_init(void *handle) 1232 { 1233 int r; 1234 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1235 1236 sdma_v4_0_init_golden_registers(adev); 1237 1238 r = sdma_v4_0_start(adev); 1239 1240 return r; 1241 } 1242 1243 static int sdma_v4_0_hw_fini(void *handle) 1244 { 1245 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1246 1247 if (amdgpu_sriov_vf(adev)) 1248 return 0; 1249 1250 sdma_v4_0_ctx_switch_enable(adev, false); 1251 sdma_v4_0_enable(adev, false); 1252 1253 return 0; 1254 } 1255 1256 static int sdma_v4_0_suspend(void *handle) 1257 { 1258 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1259 1260 return sdma_v4_0_hw_fini(adev); 1261 } 1262 1263 static int sdma_v4_0_resume(void *handle) 1264 { 1265 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1266 1267 return sdma_v4_0_hw_init(adev); 1268 } 1269 1270 static bool sdma_v4_0_is_idle(void *handle) 1271 { 1272 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1273 u32 i; 1274 1275 for (i = 0; i < adev->sdma.num_instances; i++) { 1276 u32 tmp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG)); 1277 1278 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1279 return false; 1280 } 1281 1282 return true; 1283 } 1284 1285 static int sdma_v4_0_wait_for_idle(void *handle) 1286 { 1287 unsigned i; 1288 u32 sdma0, sdma1; 1289 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1290 1291 for (i = 0; i < adev->usec_timeout; i++) { 1292 sdma0 = RREG32(sdma_v4_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG)); 1293 sdma1 = RREG32(sdma_v4_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG)); 1294 1295 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK) 1296 return 0; 1297 udelay(1); 1298 } 1299 return -ETIMEDOUT; 1300 } 1301 1302 static int sdma_v4_0_soft_reset(void *handle) 1303 { 1304 /* todo */ 1305 1306 return 0; 1307 } 1308 1309 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev, 1310 struct amdgpu_irq_src *source, 1311 unsigned type, 1312 enum amdgpu_interrupt_state state) 1313 { 1314 u32 sdma_cntl; 1315 1316 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_TRAP0) ? 1317 sdma_v4_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) : 1318 sdma_v4_0_get_reg_offset(adev, 1, mmSDMA0_CNTL); 1319 1320 sdma_cntl = RREG32(reg_offset); 1321 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1322 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1323 WREG32(reg_offset, sdma_cntl); 1324 1325 return 0; 1326 } 1327 1328 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev, 1329 struct amdgpu_irq_src *source, 1330 struct amdgpu_iv_entry *entry) 1331 { 1332 DRM_DEBUG("IH: SDMA trap\n"); 1333 switch (entry->client_id) { 1334 case SOC15_IH_CLIENTID_SDMA0: 1335 switch (entry->ring_id) { 1336 case 0: 1337 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1338 break; 1339 case 1: 1340 /* XXX compute */ 1341 break; 1342 case 2: 1343 /* XXX compute */ 1344 break; 1345 case 3: 1346 /* XXX page queue*/ 1347 break; 1348 } 1349 break; 1350 case SOC15_IH_CLIENTID_SDMA1: 1351 switch (entry->ring_id) { 1352 case 0: 1353 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1354 break; 1355 case 1: 1356 /* XXX compute */ 1357 break; 1358 case 2: 1359 /* XXX compute */ 1360 break; 1361 case 3: 1362 /* XXX page queue*/ 1363 break; 1364 } 1365 break; 1366 } 1367 return 0; 1368 } 1369 1370 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1371 struct amdgpu_irq_src *source, 1372 struct amdgpu_iv_entry *entry) 1373 { 1374 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1375 schedule_work(&adev->reset_work); 1376 return 0; 1377 } 1378 1379 1380 static void sdma_v4_0_update_medium_grain_clock_gating( 1381 struct amdgpu_device *adev, 1382 bool enable) 1383 { 1384 uint32_t data, def; 1385 1386 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1387 /* enable sdma0 clock gating */ 1388 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 1389 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1390 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1391 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1392 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1393 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1394 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1395 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1396 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1397 if (def != data) 1398 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data); 1399 1400 if (adev->sdma.num_instances > 1) { 1401 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL)); 1402 data &= ~(SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1403 SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1404 SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1405 SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1406 SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1407 SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1408 SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1409 SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1410 if (def != data) 1411 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data); 1412 } 1413 } else { 1414 /* disable sdma0 clock gating */ 1415 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 1416 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1417 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1418 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1419 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1420 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1421 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1422 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1423 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1424 1425 if (def != data) 1426 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data); 1427 1428 if (adev->sdma.num_instances > 1) { 1429 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL)); 1430 data |= (SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1431 SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1432 SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1433 SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1434 SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1435 SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1436 SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1437 SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1438 if (def != data) 1439 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data); 1440 } 1441 } 1442 } 1443 1444 1445 static void sdma_v4_0_update_medium_grain_light_sleep( 1446 struct amdgpu_device *adev, 1447 bool enable) 1448 { 1449 uint32_t data, def; 1450 1451 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1452 /* 1-not override: enable sdma0 mem light sleep */ 1453 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1454 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1455 if (def != data) 1456 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1457 1458 /* 1-not override: enable sdma1 mem light sleep */ 1459 if (adev->sdma.num_instances > 1) { 1460 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL)); 1461 data |= SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1462 if (def != data) 1463 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data); 1464 } 1465 } else { 1466 /* 0-override:disable sdma0 mem light sleep */ 1467 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1468 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1469 if (def != data) 1470 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1471 1472 /* 0-override:disable sdma1 mem light sleep */ 1473 if (adev->sdma.num_instances > 1) { 1474 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL)); 1475 data &= ~SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1476 if (def != data) 1477 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data); 1478 } 1479 } 1480 } 1481 1482 static int sdma_v4_0_set_clockgating_state(void *handle, 1483 enum amd_clockgating_state state) 1484 { 1485 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1486 1487 if (amdgpu_sriov_vf(adev)) 1488 return 0; 1489 1490 switch (adev->asic_type) { 1491 case CHIP_VEGA10: 1492 case CHIP_RAVEN: 1493 sdma_v4_0_update_medium_grain_clock_gating(adev, 1494 state == AMD_CG_STATE_GATE ? true : false); 1495 sdma_v4_0_update_medium_grain_light_sleep(adev, 1496 state == AMD_CG_STATE_GATE ? true : false); 1497 break; 1498 default: 1499 break; 1500 } 1501 return 0; 1502 } 1503 1504 static int sdma_v4_0_set_powergating_state(void *handle, 1505 enum amd_powergating_state state) 1506 { 1507 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1508 1509 switch (adev->asic_type) { 1510 case CHIP_RAVEN: 1511 sdma_v4_1_update_power_gating(adev, 1512 state == AMD_PG_STATE_GATE ? true : false); 1513 break; 1514 default: 1515 break; 1516 } 1517 1518 return 0; 1519 } 1520 1521 static void sdma_v4_0_get_clockgating_state(void *handle, u32 *flags) 1522 { 1523 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1524 int data; 1525 1526 if (amdgpu_sriov_vf(adev)) 1527 *flags = 0; 1528 1529 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1530 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 1531 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK)) 1532 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1533 1534 /* AMD_CG_SUPPORT_SDMA_LS */ 1535 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1536 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1537 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1538 } 1539 1540 const struct amd_ip_funcs sdma_v4_0_ip_funcs = { 1541 .name = "sdma_v4_0", 1542 .early_init = sdma_v4_0_early_init, 1543 .late_init = NULL, 1544 .sw_init = sdma_v4_0_sw_init, 1545 .sw_fini = sdma_v4_0_sw_fini, 1546 .hw_init = sdma_v4_0_hw_init, 1547 .hw_fini = sdma_v4_0_hw_fini, 1548 .suspend = sdma_v4_0_suspend, 1549 .resume = sdma_v4_0_resume, 1550 .is_idle = sdma_v4_0_is_idle, 1551 .wait_for_idle = sdma_v4_0_wait_for_idle, 1552 .soft_reset = sdma_v4_0_soft_reset, 1553 .set_clockgating_state = sdma_v4_0_set_clockgating_state, 1554 .set_powergating_state = sdma_v4_0_set_powergating_state, 1555 .get_clockgating_state = sdma_v4_0_get_clockgating_state, 1556 }; 1557 1558 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = { 1559 .type = AMDGPU_RING_TYPE_SDMA, 1560 .align_mask = 0xf, 1561 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1562 .support_64bit_ptrs = true, 1563 .vmhub = AMDGPU_MMHUB, 1564 .get_rptr = sdma_v4_0_ring_get_rptr, 1565 .get_wptr = sdma_v4_0_ring_get_wptr, 1566 .set_wptr = sdma_v4_0_ring_set_wptr, 1567 .emit_frame_size = 1568 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 1569 3 + /* hdp invalidate */ 1570 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 1571 /* sdma_v4_0_ring_emit_vm_flush */ 1572 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1573 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1574 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 1575 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 1576 .emit_ib = sdma_v4_0_ring_emit_ib, 1577 .emit_fence = sdma_v4_0_ring_emit_fence, 1578 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 1579 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 1580 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 1581 .test_ring = sdma_v4_0_ring_test_ring, 1582 .test_ib = sdma_v4_0_ring_test_ib, 1583 .insert_nop = sdma_v4_0_ring_insert_nop, 1584 .pad_ib = sdma_v4_0_ring_pad_ib, 1585 .emit_wreg = sdma_v4_0_ring_emit_wreg, 1586 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 1587 }; 1588 1589 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev) 1590 { 1591 int i; 1592 1593 for (i = 0; i < adev->sdma.num_instances; i++) 1594 adev->sdma.instance[i].ring.funcs = &sdma_v4_0_ring_funcs; 1595 } 1596 1597 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = { 1598 .set = sdma_v4_0_set_trap_irq_state, 1599 .process = sdma_v4_0_process_trap_irq, 1600 }; 1601 1602 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = { 1603 .process = sdma_v4_0_process_illegal_inst_irq, 1604 }; 1605 1606 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev) 1607 { 1608 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 1609 adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs; 1610 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs; 1611 } 1612 1613 /** 1614 * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine 1615 * 1616 * @ring: amdgpu_ring structure holding ring information 1617 * @src_offset: src GPU address 1618 * @dst_offset: dst GPU address 1619 * @byte_count: number of bytes to xfer 1620 * 1621 * Copy GPU buffers using the DMA engine (VEGA10). 1622 * Used by the amdgpu ttm implementation to move pages if 1623 * registered as the asic copy callback. 1624 */ 1625 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib, 1626 uint64_t src_offset, 1627 uint64_t dst_offset, 1628 uint32_t byte_count) 1629 { 1630 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1631 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1632 ib->ptr[ib->length_dw++] = byte_count - 1; 1633 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1634 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1635 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1636 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1637 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1638 } 1639 1640 /** 1641 * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine 1642 * 1643 * @ring: amdgpu_ring structure holding ring information 1644 * @src_data: value to write to buffer 1645 * @dst_offset: dst GPU address 1646 * @byte_count: number of bytes to xfer 1647 * 1648 * Fill GPU buffers using the DMA engine (VEGA10). 1649 */ 1650 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib, 1651 uint32_t src_data, 1652 uint64_t dst_offset, 1653 uint32_t byte_count) 1654 { 1655 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1656 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1657 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1658 ib->ptr[ib->length_dw++] = src_data; 1659 ib->ptr[ib->length_dw++] = byte_count - 1; 1660 } 1661 1662 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = { 1663 .copy_max_bytes = 0x400000, 1664 .copy_num_dw = 7, 1665 .emit_copy_buffer = sdma_v4_0_emit_copy_buffer, 1666 1667 .fill_max_bytes = 0x400000, 1668 .fill_num_dw = 5, 1669 .emit_fill_buffer = sdma_v4_0_emit_fill_buffer, 1670 }; 1671 1672 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev) 1673 { 1674 if (adev->mman.buffer_funcs == NULL) { 1675 adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs; 1676 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1677 } 1678 } 1679 1680 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = { 1681 .copy_pte_num_dw = 7, 1682 .copy_pte = sdma_v4_0_vm_copy_pte, 1683 1684 .write_pte = sdma_v4_0_vm_write_pte, 1685 .set_pte_pde = sdma_v4_0_vm_set_pte_pde, 1686 }; 1687 1688 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1689 { 1690 unsigned i; 1691 1692 if (adev->vm_manager.vm_pte_funcs == NULL) { 1693 adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs; 1694 for (i = 0; i < adev->sdma.num_instances; i++) 1695 adev->vm_manager.vm_pte_rings[i] = 1696 &adev->sdma.instance[i].ring; 1697 1698 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances; 1699 } 1700 } 1701 1702 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = { 1703 .type = AMD_IP_BLOCK_TYPE_SDMA, 1704 .major = 4, 1705 .minor = 0, 1706 .rev = 0, 1707 .funcs = &sdma_v4_0_ip_funcs, 1708 }; 1709