1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "sdma0/sdma0_4_2_offset.h" 34 #include "sdma0/sdma0_4_2_sh_mask.h" 35 #include "sdma1/sdma1_4_2_offset.h" 36 #include "sdma1/sdma1_4_2_sh_mask.h" 37 #include "sdma2/sdma2_4_2_2_offset.h" 38 #include "sdma2/sdma2_4_2_2_sh_mask.h" 39 #include "sdma3/sdma3_4_2_2_offset.h" 40 #include "sdma3/sdma3_4_2_2_sh_mask.h" 41 #include "sdma4/sdma4_4_2_2_offset.h" 42 #include "sdma4/sdma4_4_2_2_sh_mask.h" 43 #include "sdma5/sdma5_4_2_2_offset.h" 44 #include "sdma5/sdma5_4_2_2_sh_mask.h" 45 #include "sdma6/sdma6_4_2_2_offset.h" 46 #include "sdma6/sdma6_4_2_2_sh_mask.h" 47 #include "sdma7/sdma7_4_2_2_offset.h" 48 #include "sdma7/sdma7_4_2_2_sh_mask.h" 49 #include "hdp/hdp_4_0_offset.h" 50 #include "sdma0/sdma0_4_1_default.h" 51 52 #include "soc15_common.h" 53 #include "soc15.h" 54 #include "vega10_sdma_pkt_open.h" 55 56 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h" 57 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h" 58 59 #include "amdgpu_ras.h" 60 61 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin"); 62 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin"); 63 MODULE_FIRMWARE("amdgpu/vega12_sdma.bin"); 64 MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin"); 65 MODULE_FIRMWARE("amdgpu/vega20_sdma.bin"); 66 MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin"); 67 MODULE_FIRMWARE("amdgpu/raven_sdma.bin"); 68 MODULE_FIRMWARE("amdgpu/picasso_sdma.bin"); 69 MODULE_FIRMWARE("amdgpu/raven2_sdma.bin"); 70 MODULE_FIRMWARE("amdgpu/arcturus_sdma.bin"); 71 MODULE_FIRMWARE("amdgpu/renoir_sdma.bin"); 72 73 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L 74 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L 75 76 #define WREG32_SDMA(instance, offset, value) \ 77 WREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)), value) 78 #define RREG32_SDMA(instance, offset) \ 79 RREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset))) 80 81 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev); 82 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev); 83 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev); 84 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev); 85 static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev); 86 87 static const struct soc15_reg_golden golden_settings_sdma_4[] = { 88 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 89 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100), 90 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100), 91 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 92 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 93 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 94 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000), 95 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 96 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 97 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 98 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 99 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 100 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000), 101 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), 102 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100), 103 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 104 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 105 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 106 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000), 107 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 108 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 109 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 110 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 111 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0), 112 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xfc000000, 0x00000000) 113 }; 114 115 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = { 116 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 117 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 118 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 119 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 120 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 121 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 122 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 123 }; 124 125 static const struct soc15_reg_golden golden_settings_sdma_vg12[] = { 126 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), 127 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001), 128 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 129 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 130 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), 131 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001), 132 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 133 }; 134 135 static const struct soc15_reg_golden golden_settings_sdma_4_1[] = { 136 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 137 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 138 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100), 139 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 140 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051), 141 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100), 142 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 143 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100), 144 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 145 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 146 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000) 147 }; 148 149 static const struct soc15_reg_golden golden_settings_sdma0_4_2_init[] = { 150 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 151 }; 152 153 static const struct soc15_reg_golden golden_settings_sdma0_4_2[] = 154 { 155 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 156 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 157 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 158 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 159 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 160 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 161 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 162 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 163 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RD_BURST_CNTL, 0x0000000f, 0x00000003), 164 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 165 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 166 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 167 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 168 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 169 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 170 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 171 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 172 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 173 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 174 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 175 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 176 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 177 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 178 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 179 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 180 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 181 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 182 }; 183 184 static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = { 185 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 186 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), 187 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 188 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 189 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 190 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 191 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 192 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 193 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RD_BURST_CNTL, 0x0000000f, 0x00000003), 194 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 195 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 196 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 197 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 198 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 199 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 200 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 201 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 202 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 203 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 204 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 205 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 206 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 207 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 208 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 209 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 210 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0), 211 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 212 }; 213 214 static const struct soc15_reg_golden golden_settings_sdma_rv1[] = 215 { 216 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002), 217 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002) 218 }; 219 220 static const struct soc15_reg_golden golden_settings_sdma_rv2[] = 221 { 222 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00003001), 223 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003001) 224 }; 225 226 static const struct soc15_reg_golden golden_settings_sdma_arct[] = 227 { 228 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 229 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 230 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 231 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 232 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 233 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 234 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 235 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 236 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 237 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 238 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 239 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 240 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 241 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 242 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 243 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 244 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 245 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 246 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 247 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 248 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 249 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 250 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 251 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 252 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 253 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 254 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 255 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 256 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 257 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 258 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 259 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_UTCL1_TIMEOUT, 0xffffffff, 0x00010001) 260 }; 261 262 static const struct soc15_reg_golden golden_settings_sdma_4_3[] = { 263 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 264 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 265 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002), 266 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002), 267 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 268 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003fff07, 0x40000051), 269 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 270 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 271 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 272 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x03fbe1fe) 273 }; 274 275 static const struct soc15_ras_field_entry sdma_v4_0_ras_fields[] = { 276 { "SDMA_UCODE_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 277 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UCODE_BUF_SED), 278 0, 0, 279 }, 280 { "SDMA_RB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 281 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_RB_CMD_BUF_SED), 282 0, 0, 283 }, 284 { "SDMA_IB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 285 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_IB_CMD_BUF_SED), 286 0, 0, 287 }, 288 { "SDMA_UTCL1_RD_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 289 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UTCL1_RD_FIFO_SED), 290 0, 0, 291 }, 292 { "SDMA_UTCL1_RDBST_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 293 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UTCL1_RDBST_FIFO_SED), 294 0, 0, 295 }, 296 { "SDMA_DATA_LUT_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 297 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_DATA_LUT_FIFO_SED), 298 0, 0, 299 }, 300 { "SDMA_MBANK_DATA_BUF0_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 301 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF0_SED), 302 0, 0, 303 }, 304 { "SDMA_MBANK_DATA_BUF1_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 305 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF1_SED), 306 0, 0, 307 }, 308 { "SDMA_MBANK_DATA_BUF2_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 309 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF2_SED), 310 0, 0, 311 }, 312 { "SDMA_MBANK_DATA_BUF3_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 313 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF3_SED), 314 0, 0, 315 }, 316 { "SDMA_MBANK_DATA_BUF4_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 317 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF4_SED), 318 0, 0, 319 }, 320 { "SDMA_MBANK_DATA_BUF5_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 321 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF5_SED), 322 0, 0, 323 }, 324 { "SDMA_MBANK_DATA_BUF6_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 325 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF6_SED), 326 0, 0, 327 }, 328 { "SDMA_MBANK_DATA_BUF7_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 329 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF7_SED), 330 0, 0, 331 }, 332 { "SDMA_MBANK_DATA_BUF8_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 333 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF8_SED), 334 0, 0, 335 }, 336 { "SDMA_MBANK_DATA_BUF9_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 337 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF9_SED), 338 0, 0, 339 }, 340 { "SDMA_MBANK_DATA_BUF10_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 341 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF10_SED), 342 0, 0, 343 }, 344 { "SDMA_MBANK_DATA_BUF11_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 345 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF11_SED), 346 0, 0, 347 }, 348 { "SDMA_MBANK_DATA_BUF12_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 349 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF12_SED), 350 0, 0, 351 }, 352 { "SDMA_MBANK_DATA_BUF13_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 353 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF13_SED), 354 0, 0, 355 }, 356 { "SDMA_MBANK_DATA_BUF14_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 357 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF14_SED), 358 0, 0, 359 }, 360 { "SDMA_MBANK_DATA_BUF15_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 361 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF15_SED), 362 0, 0, 363 }, 364 { "SDMA_SPLIT_DAT_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 365 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_SPLIT_DAT_BUF_SED), 366 0, 0, 367 }, 368 { "SDMA_MC_WR_ADDR_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 369 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MC_WR_ADDR_FIFO_SED), 370 0, 0, 371 }, 372 }; 373 374 static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev, 375 u32 instance, u32 offset) 376 { 377 switch (instance) { 378 case 0: 379 return (adev->reg_offset[SDMA0_HWIP][0][0] + offset); 380 case 1: 381 return (adev->reg_offset[SDMA1_HWIP][0][0] + offset); 382 case 2: 383 return (adev->reg_offset[SDMA2_HWIP][0][1] + offset); 384 case 3: 385 return (adev->reg_offset[SDMA3_HWIP][0][1] + offset); 386 case 4: 387 return (adev->reg_offset[SDMA4_HWIP][0][1] + offset); 388 case 5: 389 return (adev->reg_offset[SDMA5_HWIP][0][1] + offset); 390 case 6: 391 return (adev->reg_offset[SDMA6_HWIP][0][1] + offset); 392 case 7: 393 return (adev->reg_offset[SDMA7_HWIP][0][1] + offset); 394 default: 395 break; 396 } 397 return 0; 398 } 399 400 static unsigned sdma_v4_0_seq_to_irq_id(int seq_num) 401 { 402 switch (seq_num) { 403 case 0: 404 return SOC15_IH_CLIENTID_SDMA0; 405 case 1: 406 return SOC15_IH_CLIENTID_SDMA1; 407 case 2: 408 return SOC15_IH_CLIENTID_SDMA2; 409 case 3: 410 return SOC15_IH_CLIENTID_SDMA3; 411 case 4: 412 return SOC15_IH_CLIENTID_SDMA4; 413 case 5: 414 return SOC15_IH_CLIENTID_SDMA5; 415 case 6: 416 return SOC15_IH_CLIENTID_SDMA6; 417 case 7: 418 return SOC15_IH_CLIENTID_SDMA7; 419 default: 420 break; 421 } 422 return -EINVAL; 423 } 424 425 static int sdma_v4_0_irq_id_to_seq(unsigned client_id) 426 { 427 switch (client_id) { 428 case SOC15_IH_CLIENTID_SDMA0: 429 return 0; 430 case SOC15_IH_CLIENTID_SDMA1: 431 return 1; 432 case SOC15_IH_CLIENTID_SDMA2: 433 return 2; 434 case SOC15_IH_CLIENTID_SDMA3: 435 return 3; 436 case SOC15_IH_CLIENTID_SDMA4: 437 return 4; 438 case SOC15_IH_CLIENTID_SDMA5: 439 return 5; 440 case SOC15_IH_CLIENTID_SDMA6: 441 return 6; 442 case SOC15_IH_CLIENTID_SDMA7: 443 return 7; 444 default: 445 break; 446 } 447 return -EINVAL; 448 } 449 450 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) 451 { 452 switch (adev->asic_type) { 453 case CHIP_VEGA10: 454 soc15_program_register_sequence(adev, 455 golden_settings_sdma_4, 456 ARRAY_SIZE(golden_settings_sdma_4)); 457 soc15_program_register_sequence(adev, 458 golden_settings_sdma_vg10, 459 ARRAY_SIZE(golden_settings_sdma_vg10)); 460 break; 461 case CHIP_VEGA12: 462 soc15_program_register_sequence(adev, 463 golden_settings_sdma_4, 464 ARRAY_SIZE(golden_settings_sdma_4)); 465 soc15_program_register_sequence(adev, 466 golden_settings_sdma_vg12, 467 ARRAY_SIZE(golden_settings_sdma_vg12)); 468 break; 469 case CHIP_VEGA20: 470 soc15_program_register_sequence(adev, 471 golden_settings_sdma0_4_2_init, 472 ARRAY_SIZE(golden_settings_sdma0_4_2_init)); 473 soc15_program_register_sequence(adev, 474 golden_settings_sdma0_4_2, 475 ARRAY_SIZE(golden_settings_sdma0_4_2)); 476 soc15_program_register_sequence(adev, 477 golden_settings_sdma1_4_2, 478 ARRAY_SIZE(golden_settings_sdma1_4_2)); 479 break; 480 case CHIP_ARCTURUS: 481 soc15_program_register_sequence(adev, 482 golden_settings_sdma_arct, 483 ARRAY_SIZE(golden_settings_sdma_arct)); 484 break; 485 case CHIP_RAVEN: 486 soc15_program_register_sequence(adev, 487 golden_settings_sdma_4_1, 488 ARRAY_SIZE(golden_settings_sdma_4_1)); 489 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 490 soc15_program_register_sequence(adev, 491 golden_settings_sdma_rv2, 492 ARRAY_SIZE(golden_settings_sdma_rv2)); 493 else 494 soc15_program_register_sequence(adev, 495 golden_settings_sdma_rv1, 496 ARRAY_SIZE(golden_settings_sdma_rv1)); 497 break; 498 case CHIP_RENOIR: 499 soc15_program_register_sequence(adev, 500 golden_settings_sdma_4_3, 501 ARRAY_SIZE(golden_settings_sdma_4_3)); 502 break; 503 default: 504 break; 505 } 506 } 507 508 static int sdma_v4_0_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst) 509 { 510 int err = 0; 511 const struct sdma_firmware_header_v1_0 *hdr; 512 513 err = amdgpu_ucode_validate(sdma_inst->fw); 514 if (err) 515 return err; 516 517 hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data; 518 sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version); 519 sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version); 520 521 if (sdma_inst->feature_version >= 20) 522 sdma_inst->burst_nop = true; 523 524 return 0; 525 } 526 527 static void sdma_v4_0_destroy_inst_ctx(struct amdgpu_device *adev) 528 { 529 int i; 530 531 for (i = 0; i < adev->sdma.num_instances; i++) { 532 if (adev->sdma.instance[i].fw != NULL) 533 release_firmware(adev->sdma.instance[i].fw); 534 535 /* arcturus shares the same FW memory across 536 all SDMA isntances */ 537 if (adev->asic_type == CHIP_ARCTURUS) 538 break; 539 } 540 541 memset((void*)adev->sdma.instance, 0, 542 sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES); 543 } 544 545 /** 546 * sdma_v4_0_init_microcode - load ucode images from disk 547 * 548 * @adev: amdgpu_device pointer 549 * 550 * Use the firmware interface to load the ucode images into 551 * the driver (not loaded into hw). 552 * Returns 0 on success, error on failure. 553 */ 554 555 // emulation only, won't work on real chip 556 // vega10 real chip need to use PSP to load firmware 557 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev) 558 { 559 const char *chip_name; 560 char fw_name[30]; 561 int err = 0, i; 562 struct amdgpu_firmware_info *info = NULL; 563 const struct common_firmware_header *header = NULL; 564 565 DRM_DEBUG("\n"); 566 567 switch (adev->asic_type) { 568 case CHIP_VEGA10: 569 chip_name = "vega10"; 570 break; 571 case CHIP_VEGA12: 572 chip_name = "vega12"; 573 break; 574 case CHIP_VEGA20: 575 chip_name = "vega20"; 576 break; 577 case CHIP_RAVEN: 578 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 579 chip_name = "raven2"; 580 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 581 chip_name = "picasso"; 582 else 583 chip_name = "raven"; 584 break; 585 case CHIP_ARCTURUS: 586 chip_name = "arcturus"; 587 break; 588 case CHIP_RENOIR: 589 chip_name = "renoir"; 590 break; 591 default: 592 BUG(); 593 } 594 595 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 596 597 err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev); 598 if (err) 599 goto out; 600 601 err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[0]); 602 if (err) 603 goto out; 604 605 for (i = 1; i < adev->sdma.num_instances; i++) { 606 if (adev->asic_type == CHIP_ARCTURUS) { 607 /* Acturus will leverage the same FW memory 608 for every SDMA instance */ 609 memcpy((void*)&adev->sdma.instance[i], 610 (void*)&adev->sdma.instance[0], 611 sizeof(struct amdgpu_sdma_instance)); 612 } 613 else { 614 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i); 615 616 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 617 if (err) 618 goto out; 619 620 err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[i]); 621 if (err) 622 goto out; 623 } 624 } 625 626 DRM_DEBUG("psp_load == '%s'\n", 627 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); 628 629 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 630 for (i = 0; i < adev->sdma.num_instances; i++) { 631 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 632 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 633 info->fw = adev->sdma.instance[i].fw; 634 header = (const struct common_firmware_header *)info->fw->data; 635 adev->firmware.fw_size += 636 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 637 } 638 } 639 640 out: 641 if (err) { 642 DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name); 643 sdma_v4_0_destroy_inst_ctx(adev); 644 } 645 return err; 646 } 647 648 /** 649 * sdma_v4_0_ring_get_rptr - get the current read pointer 650 * 651 * @ring: amdgpu ring pointer 652 * 653 * Get the current rptr from the hardware (VEGA10+). 654 */ 655 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring) 656 { 657 u64 *rptr; 658 659 /* XXX check if swapping is necessary on BE */ 660 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]); 661 662 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 663 return ((*rptr) >> 2); 664 } 665 666 /** 667 * sdma_v4_0_ring_get_wptr - get the current write pointer 668 * 669 * @ring: amdgpu ring pointer 670 * 671 * Get the current wptr from the hardware (VEGA10+). 672 */ 673 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring) 674 { 675 struct amdgpu_device *adev = ring->adev; 676 u64 wptr; 677 678 if (ring->use_doorbell) { 679 /* XXX check if swapping is necessary on BE */ 680 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 681 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 682 } else { 683 wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI); 684 wptr = wptr << 32; 685 wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR); 686 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", 687 ring->me, wptr); 688 } 689 690 return wptr >> 2; 691 } 692 693 /** 694 * sdma_v4_0_page_ring_set_wptr - commit the write pointer 695 * 696 * @ring: amdgpu ring pointer 697 * 698 * Write the wptr back to the hardware (VEGA10+). 699 */ 700 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring) 701 { 702 struct amdgpu_device *adev = ring->adev; 703 704 DRM_DEBUG("Setting write pointer\n"); 705 if (ring->use_doorbell) { 706 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 707 708 DRM_DEBUG("Using doorbell -- " 709 "wptr_offs == 0x%08x " 710 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 711 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 712 ring->wptr_offs, 713 lower_32_bits(ring->wptr << 2), 714 upper_32_bits(ring->wptr << 2)); 715 /* XXX check if swapping is necessary on BE */ 716 WRITE_ONCE(*wb, (ring->wptr << 2)); 717 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 718 ring->doorbell_index, ring->wptr << 2); 719 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 720 } else { 721 DRM_DEBUG("Not using doorbell -- " 722 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 723 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 724 ring->me, 725 lower_32_bits(ring->wptr << 2), 726 ring->me, 727 upper_32_bits(ring->wptr << 2)); 728 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR, 729 lower_32_bits(ring->wptr << 2)); 730 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI, 731 upper_32_bits(ring->wptr << 2)); 732 } 733 } 734 735 /** 736 * sdma_v4_0_page_ring_get_wptr - get the current write pointer 737 * 738 * @ring: amdgpu ring pointer 739 * 740 * Get the current wptr from the hardware (VEGA10+). 741 */ 742 static uint64_t sdma_v4_0_page_ring_get_wptr(struct amdgpu_ring *ring) 743 { 744 struct amdgpu_device *adev = ring->adev; 745 u64 wptr; 746 747 if (ring->use_doorbell) { 748 /* XXX check if swapping is necessary on BE */ 749 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 750 } else { 751 wptr = RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI); 752 wptr = wptr << 32; 753 wptr |= RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR); 754 } 755 756 return wptr >> 2; 757 } 758 759 /** 760 * sdma_v4_0_ring_set_wptr - commit the write pointer 761 * 762 * @ring: amdgpu ring pointer 763 * 764 * Write the wptr back to the hardware (VEGA10+). 765 */ 766 static void sdma_v4_0_page_ring_set_wptr(struct amdgpu_ring *ring) 767 { 768 struct amdgpu_device *adev = ring->adev; 769 770 if (ring->use_doorbell) { 771 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 772 773 /* XXX check if swapping is necessary on BE */ 774 WRITE_ONCE(*wb, (ring->wptr << 2)); 775 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 776 } else { 777 uint64_t wptr = ring->wptr << 2; 778 779 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR, 780 lower_32_bits(wptr)); 781 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI, 782 upper_32_bits(wptr)); 783 } 784 } 785 786 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 787 { 788 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 789 int i; 790 791 for (i = 0; i < count; i++) 792 if (sdma && sdma->burst_nop && (i == 0)) 793 amdgpu_ring_write(ring, ring->funcs->nop | 794 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 795 else 796 amdgpu_ring_write(ring, ring->funcs->nop); 797 } 798 799 /** 800 * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine 801 * 802 * @ring: amdgpu ring pointer 803 * @ib: IB object to schedule 804 * 805 * Schedule an IB in the DMA ring (VEGA10). 806 */ 807 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring, 808 struct amdgpu_job *job, 809 struct amdgpu_ib *ib, 810 uint32_t flags) 811 { 812 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 813 814 /* IB packet must end on a 8 DW boundary */ 815 sdma_v4_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 816 817 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 818 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 819 /* base must be 32 byte aligned */ 820 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 821 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 822 amdgpu_ring_write(ring, ib->length_dw); 823 amdgpu_ring_write(ring, 0); 824 amdgpu_ring_write(ring, 0); 825 826 } 827 828 static void sdma_v4_0_wait_reg_mem(struct amdgpu_ring *ring, 829 int mem_space, int hdp, 830 uint32_t addr0, uint32_t addr1, 831 uint32_t ref, uint32_t mask, 832 uint32_t inv) 833 { 834 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 835 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) | 836 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) | 837 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 838 if (mem_space) { 839 /* memory */ 840 amdgpu_ring_write(ring, addr0); 841 amdgpu_ring_write(ring, addr1); 842 } else { 843 /* registers */ 844 amdgpu_ring_write(ring, addr0 << 2); 845 amdgpu_ring_write(ring, addr1 << 2); 846 } 847 amdgpu_ring_write(ring, ref); /* reference */ 848 amdgpu_ring_write(ring, mask); /* mask */ 849 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 850 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */ 851 } 852 853 /** 854 * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 855 * 856 * @ring: amdgpu ring pointer 857 * 858 * Emit an hdp flush packet on the requested DMA ring. 859 */ 860 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 861 { 862 struct amdgpu_device *adev = ring->adev; 863 u32 ref_and_mask = 0; 864 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 865 866 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; 867 868 sdma_v4_0_wait_reg_mem(ring, 0, 1, 869 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 870 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 871 ref_and_mask, ref_and_mask, 10); 872 } 873 874 /** 875 * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring 876 * 877 * @ring: amdgpu ring pointer 878 * @fence: amdgpu fence object 879 * 880 * Add a DMA fence packet to the ring to write 881 * the fence seq number and DMA trap packet to generate 882 * an interrupt if needed (VEGA10). 883 */ 884 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 885 unsigned flags) 886 { 887 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 888 /* write the fence */ 889 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 890 /* zero in first two bits */ 891 BUG_ON(addr & 0x3); 892 amdgpu_ring_write(ring, lower_32_bits(addr)); 893 amdgpu_ring_write(ring, upper_32_bits(addr)); 894 amdgpu_ring_write(ring, lower_32_bits(seq)); 895 896 /* optionally write high bits as well */ 897 if (write64bit) { 898 addr += 4; 899 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 900 /* zero in first two bits */ 901 BUG_ON(addr & 0x3); 902 amdgpu_ring_write(ring, lower_32_bits(addr)); 903 amdgpu_ring_write(ring, upper_32_bits(addr)); 904 amdgpu_ring_write(ring, upper_32_bits(seq)); 905 } 906 907 /* generate an interrupt */ 908 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 909 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 910 } 911 912 913 /** 914 * sdma_v4_0_gfx_stop - stop the gfx async dma engines 915 * 916 * @adev: amdgpu_device pointer 917 * 918 * Stop the gfx async dma ring buffers (VEGA10). 919 */ 920 static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev) 921 { 922 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; 923 u32 rb_cntl, ib_cntl; 924 int i, unset = 0; 925 926 for (i = 0; i < adev->sdma.num_instances; i++) { 927 sdma[i] = &adev->sdma.instance[i].ring; 928 929 if ((adev->mman.buffer_funcs_ring == sdma[i]) && unset != 1) { 930 amdgpu_ttm_set_buffer_funcs_status(adev, false); 931 unset = 1; 932 } 933 934 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL); 935 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 936 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 937 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL); 938 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 939 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl); 940 } 941 } 942 943 /** 944 * sdma_v4_0_rlc_stop - stop the compute async dma engines 945 * 946 * @adev: amdgpu_device pointer 947 * 948 * Stop the compute async dma queues (VEGA10). 949 */ 950 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev) 951 { 952 /* XXX todo */ 953 } 954 955 /** 956 * sdma_v4_0_page_stop - stop the page async dma engines 957 * 958 * @adev: amdgpu_device pointer 959 * 960 * Stop the page async dma ring buffers (VEGA10). 961 */ 962 static void sdma_v4_0_page_stop(struct amdgpu_device *adev) 963 { 964 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; 965 u32 rb_cntl, ib_cntl; 966 int i; 967 bool unset = false; 968 969 for (i = 0; i < adev->sdma.num_instances; i++) { 970 sdma[i] = &adev->sdma.instance[i].page; 971 972 if ((adev->mman.buffer_funcs_ring == sdma[i]) && 973 (unset == false)) { 974 amdgpu_ttm_set_buffer_funcs_status(adev, false); 975 unset = true; 976 } 977 978 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL); 979 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, 980 RB_ENABLE, 0); 981 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 982 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL); 983 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, 984 IB_ENABLE, 0); 985 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl); 986 } 987 } 988 989 /** 990 * sdma_v4_0_ctx_switch_enable - stop the async dma engines context switch 991 * 992 * @adev: amdgpu_device pointer 993 * @enable: enable/disable the DMA MEs context switch. 994 * 995 * Halt or unhalt the async dma engines context switch (VEGA10). 996 */ 997 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 998 { 999 u32 f32_cntl, phase_quantum = 0; 1000 int i; 1001 1002 if (amdgpu_sdma_phase_quantum) { 1003 unsigned value = amdgpu_sdma_phase_quantum; 1004 unsigned unit = 0; 1005 1006 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 1007 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 1008 value = (value + 1) >> 1; 1009 unit++; 1010 } 1011 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 1012 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 1013 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 1014 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 1015 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 1016 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 1017 WARN_ONCE(1, 1018 "clamping sdma_phase_quantum to %uK clock cycles\n", 1019 value << unit); 1020 } 1021 phase_quantum = 1022 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 1023 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 1024 } 1025 1026 for (i = 0; i < adev->sdma.num_instances; i++) { 1027 f32_cntl = RREG32_SDMA(i, mmSDMA0_CNTL); 1028 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 1029 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 1030 if (enable && amdgpu_sdma_phase_quantum) { 1031 WREG32_SDMA(i, mmSDMA0_PHASE0_QUANTUM, phase_quantum); 1032 WREG32_SDMA(i, mmSDMA0_PHASE1_QUANTUM, phase_quantum); 1033 WREG32_SDMA(i, mmSDMA0_PHASE2_QUANTUM, phase_quantum); 1034 } 1035 WREG32_SDMA(i, mmSDMA0_CNTL, f32_cntl); 1036 } 1037 1038 } 1039 1040 /** 1041 * sdma_v4_0_enable - stop the async dma engines 1042 * 1043 * @adev: amdgpu_device pointer 1044 * @enable: enable/disable the DMA MEs. 1045 * 1046 * Halt or unhalt the async dma engines (VEGA10). 1047 */ 1048 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable) 1049 { 1050 u32 f32_cntl; 1051 int i; 1052 1053 if (enable == false) { 1054 sdma_v4_0_gfx_stop(adev); 1055 sdma_v4_0_rlc_stop(adev); 1056 if (adev->sdma.has_page_queue) 1057 sdma_v4_0_page_stop(adev); 1058 } 1059 1060 for (i = 0; i < adev->sdma.num_instances; i++) { 1061 f32_cntl = RREG32_SDMA(i, mmSDMA0_F32_CNTL); 1062 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 1063 WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl); 1064 } 1065 } 1066 1067 /** 1068 * sdma_v4_0_rb_cntl - get parameters for rb_cntl 1069 */ 1070 static uint32_t sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl) 1071 { 1072 /* Set ring buffer size in dwords */ 1073 uint32_t rb_bufsz = order_base_2(ring->ring_size / 4); 1074 1075 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 1076 #ifdef __BIG_ENDIAN 1077 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 1078 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 1079 RPTR_WRITEBACK_SWAP_ENABLE, 1); 1080 #endif 1081 return rb_cntl; 1082 } 1083 1084 /** 1085 * sdma_v4_0_gfx_resume - setup and start the async dma engines 1086 * 1087 * @adev: amdgpu_device pointer 1088 * @i: instance to resume 1089 * 1090 * Set up the gfx DMA ring buffers and enable them (VEGA10). 1091 * Returns 0 for success, error for failure. 1092 */ 1093 static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i) 1094 { 1095 struct amdgpu_ring *ring = &adev->sdma.instance[i].ring; 1096 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 1097 u32 wb_offset; 1098 u32 doorbell; 1099 u32 doorbell_offset; 1100 u64 wptr_gpu_addr; 1101 1102 wb_offset = (ring->rptr_offs * 4); 1103 1104 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL); 1105 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl); 1106 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 1107 1108 /* Initialize the ring buffer's read and write pointers */ 1109 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR, 0); 1110 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_HI, 0); 1111 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR, 0); 1112 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_HI, 0); 1113 1114 /* set the wb address whether it's enabled or not */ 1115 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI, 1116 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 1117 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 1118 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 1119 1120 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 1121 RPTR_WRITEBACK_ENABLE, 1); 1122 1123 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE, ring->gpu_addr >> 8); 1124 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE_HI, ring->gpu_addr >> 40); 1125 1126 ring->wptr = 0; 1127 1128 /* before programing wptr to a less value, need set minor_ptr_update first */ 1129 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 1); 1130 1131 doorbell = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL); 1132 doorbell_offset = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET); 1133 1134 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1135 ring->use_doorbell); 1136 doorbell_offset = REG_SET_FIELD(doorbell_offset, 1137 SDMA0_GFX_DOORBELL_OFFSET, 1138 OFFSET, ring->doorbell_index); 1139 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL, doorbell); 1140 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET, doorbell_offset); 1141 1142 sdma_v4_0_ring_set_wptr(ring); 1143 1144 /* set minor_ptr_update to 0 after wptr programed */ 1145 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 0); 1146 1147 /* setup the wptr shadow polling */ 1148 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1149 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO, 1150 lower_32_bits(wptr_gpu_addr)); 1151 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI, 1152 upper_32_bits(wptr_gpu_addr)); 1153 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL); 1154 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 1155 SDMA0_GFX_RB_WPTR_POLL_CNTL, 1156 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 1157 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 1158 1159 /* enable DMA RB */ 1160 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 1161 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 1162 1163 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL); 1164 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 1165 #ifdef __BIG_ENDIAN 1166 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 1167 #endif 1168 /* enable DMA IBs */ 1169 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl); 1170 1171 ring->sched.ready = true; 1172 } 1173 1174 /** 1175 * sdma_v4_0_page_resume - setup and start the async dma engines 1176 * 1177 * @adev: amdgpu_device pointer 1178 * @i: instance to resume 1179 * 1180 * Set up the page DMA ring buffers and enable them (VEGA10). 1181 * Returns 0 for success, error for failure. 1182 */ 1183 static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i) 1184 { 1185 struct amdgpu_ring *ring = &adev->sdma.instance[i].page; 1186 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 1187 u32 wb_offset; 1188 u32 doorbell; 1189 u32 doorbell_offset; 1190 u64 wptr_gpu_addr; 1191 1192 wb_offset = (ring->rptr_offs * 4); 1193 1194 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL); 1195 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl); 1196 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 1197 1198 /* Initialize the ring buffer's read and write pointers */ 1199 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR, 0); 1200 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_HI, 0); 1201 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR, 0); 1202 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_HI, 0); 1203 1204 /* set the wb address whether it's enabled or not */ 1205 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_HI, 1206 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 1207 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 1208 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 1209 1210 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, 1211 RPTR_WRITEBACK_ENABLE, 1); 1212 1213 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE, ring->gpu_addr >> 8); 1214 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE_HI, ring->gpu_addr >> 40); 1215 1216 ring->wptr = 0; 1217 1218 /* before programing wptr to a less value, need set minor_ptr_update first */ 1219 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 1); 1220 1221 doorbell = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL); 1222 doorbell_offset = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET); 1223 1224 doorbell = REG_SET_FIELD(doorbell, SDMA0_PAGE_DOORBELL, ENABLE, 1225 ring->use_doorbell); 1226 doorbell_offset = REG_SET_FIELD(doorbell_offset, 1227 SDMA0_PAGE_DOORBELL_OFFSET, 1228 OFFSET, ring->doorbell_index); 1229 WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL, doorbell); 1230 WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET, doorbell_offset); 1231 1232 /* paging queue doorbell range is setup at sdma_v4_0_gfx_resume */ 1233 sdma_v4_0_page_ring_set_wptr(ring); 1234 1235 /* set minor_ptr_update to 0 after wptr programed */ 1236 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 0); 1237 1238 /* setup the wptr shadow polling */ 1239 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1240 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO, 1241 lower_32_bits(wptr_gpu_addr)); 1242 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI, 1243 upper_32_bits(wptr_gpu_addr)); 1244 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL); 1245 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 1246 SDMA0_PAGE_RB_WPTR_POLL_CNTL, 1247 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 1248 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 1249 1250 /* enable DMA RB */ 1251 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, RB_ENABLE, 1); 1252 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 1253 1254 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL); 1255 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_ENABLE, 1); 1256 #ifdef __BIG_ENDIAN 1257 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1); 1258 #endif 1259 /* enable DMA IBs */ 1260 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl); 1261 1262 ring->sched.ready = true; 1263 } 1264 1265 static void 1266 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable) 1267 { 1268 uint32_t def, data; 1269 1270 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) { 1271 /* enable idle interrupt */ 1272 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 1273 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 1274 1275 if (data != def) 1276 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 1277 } else { 1278 /* disable idle interrupt */ 1279 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 1280 data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 1281 if (data != def) 1282 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 1283 } 1284 } 1285 1286 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev) 1287 { 1288 uint32_t def, data; 1289 1290 /* Enable HW based PG. */ 1291 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1292 data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK; 1293 if (data != def) 1294 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1295 1296 /* enable interrupt */ 1297 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 1298 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 1299 if (data != def) 1300 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 1301 1302 /* Configure hold time to filter in-valid power on/off request. Use default right now */ 1303 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1304 data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK; 1305 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK); 1306 /* Configure switch time for hysteresis purpose. Use default right now */ 1307 data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK; 1308 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK); 1309 if(data != def) 1310 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1311 } 1312 1313 static void sdma_v4_0_init_pg(struct amdgpu_device *adev) 1314 { 1315 if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA)) 1316 return; 1317 1318 switch (adev->asic_type) { 1319 case CHIP_RAVEN: 1320 case CHIP_RENOIR: 1321 sdma_v4_1_init_power_gating(adev); 1322 sdma_v4_1_update_power_gating(adev, true); 1323 break; 1324 default: 1325 break; 1326 } 1327 } 1328 1329 /** 1330 * sdma_v4_0_rlc_resume - setup and start the async dma engines 1331 * 1332 * @adev: amdgpu_device pointer 1333 * 1334 * Set up the compute DMA queues and enable them (VEGA10). 1335 * Returns 0 for success, error for failure. 1336 */ 1337 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev) 1338 { 1339 sdma_v4_0_init_pg(adev); 1340 1341 return 0; 1342 } 1343 1344 /** 1345 * sdma_v4_0_load_microcode - load the sDMA ME ucode 1346 * 1347 * @adev: amdgpu_device pointer 1348 * 1349 * Loads the sDMA0/1 ucode. 1350 * Returns 0 for success, -EINVAL if the ucode is not available. 1351 */ 1352 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev) 1353 { 1354 const struct sdma_firmware_header_v1_0 *hdr; 1355 const __le32 *fw_data; 1356 u32 fw_size; 1357 int i, j; 1358 1359 /* halt the MEs */ 1360 sdma_v4_0_enable(adev, false); 1361 1362 for (i = 0; i < adev->sdma.num_instances; i++) { 1363 if (!adev->sdma.instance[i].fw) 1364 return -EINVAL; 1365 1366 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 1367 amdgpu_ucode_print_sdma_hdr(&hdr->header); 1368 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1369 1370 fw_data = (const __le32 *) 1371 (adev->sdma.instance[i].fw->data + 1372 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1373 1374 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 0); 1375 1376 for (j = 0; j < fw_size; j++) 1377 WREG32_SDMA(i, mmSDMA0_UCODE_DATA, 1378 le32_to_cpup(fw_data++)); 1379 1380 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 1381 adev->sdma.instance[i].fw_version); 1382 } 1383 1384 return 0; 1385 } 1386 1387 /** 1388 * sdma_v4_0_start - setup and start the async dma engines 1389 * 1390 * @adev: amdgpu_device pointer 1391 * 1392 * Set up the DMA engines and enable them (VEGA10). 1393 * Returns 0 for success, error for failure. 1394 */ 1395 static int sdma_v4_0_start(struct amdgpu_device *adev) 1396 { 1397 struct amdgpu_ring *ring; 1398 int i, r = 0; 1399 1400 if (amdgpu_sriov_vf(adev)) { 1401 sdma_v4_0_ctx_switch_enable(adev, false); 1402 sdma_v4_0_enable(adev, false); 1403 } else { 1404 1405 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1406 r = sdma_v4_0_load_microcode(adev); 1407 if (r) 1408 return r; 1409 } 1410 1411 /* unhalt the MEs */ 1412 sdma_v4_0_enable(adev, true); 1413 /* enable sdma ring preemption */ 1414 sdma_v4_0_ctx_switch_enable(adev, true); 1415 } 1416 1417 /* start the gfx rings and rlc compute queues */ 1418 for (i = 0; i < adev->sdma.num_instances; i++) { 1419 uint32_t temp; 1420 1421 WREG32_SDMA(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL, 0); 1422 sdma_v4_0_gfx_resume(adev, i); 1423 if (adev->sdma.has_page_queue) 1424 sdma_v4_0_page_resume(adev, i); 1425 1426 /* set utc l1 enable flag always to 1 */ 1427 temp = RREG32_SDMA(i, mmSDMA0_CNTL); 1428 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 1429 WREG32_SDMA(i, mmSDMA0_CNTL, temp); 1430 1431 if (!amdgpu_sriov_vf(adev)) { 1432 /* unhalt engine */ 1433 temp = RREG32_SDMA(i, mmSDMA0_F32_CNTL); 1434 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 1435 WREG32_SDMA(i, mmSDMA0_F32_CNTL, temp); 1436 } 1437 } 1438 1439 if (amdgpu_sriov_vf(adev)) { 1440 sdma_v4_0_ctx_switch_enable(adev, true); 1441 sdma_v4_0_enable(adev, true); 1442 } else { 1443 r = sdma_v4_0_rlc_resume(adev); 1444 if (r) 1445 return r; 1446 } 1447 1448 for (i = 0; i < adev->sdma.num_instances; i++) { 1449 ring = &adev->sdma.instance[i].ring; 1450 1451 r = amdgpu_ring_test_helper(ring); 1452 if (r) 1453 return r; 1454 1455 if (adev->sdma.has_page_queue) { 1456 struct amdgpu_ring *page = &adev->sdma.instance[i].page; 1457 1458 r = amdgpu_ring_test_helper(page); 1459 if (r) 1460 return r; 1461 1462 if (adev->mman.buffer_funcs_ring == page) 1463 amdgpu_ttm_set_buffer_funcs_status(adev, true); 1464 } 1465 1466 if (adev->mman.buffer_funcs_ring == ring) 1467 amdgpu_ttm_set_buffer_funcs_status(adev, true); 1468 } 1469 1470 return r; 1471 } 1472 1473 /** 1474 * sdma_v4_0_ring_test_ring - simple async dma engine test 1475 * 1476 * @ring: amdgpu_ring structure holding ring information 1477 * 1478 * Test the DMA engine by writing using it to write an 1479 * value to memory. (VEGA10). 1480 * Returns 0 for success, error for failure. 1481 */ 1482 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring) 1483 { 1484 struct amdgpu_device *adev = ring->adev; 1485 unsigned i; 1486 unsigned index; 1487 int r; 1488 u32 tmp; 1489 u64 gpu_addr; 1490 1491 r = amdgpu_device_wb_get(adev, &index); 1492 if (r) 1493 return r; 1494 1495 gpu_addr = adev->wb.gpu_addr + (index * 4); 1496 tmp = 0xCAFEDEAD; 1497 adev->wb.wb[index] = cpu_to_le32(tmp); 1498 1499 r = amdgpu_ring_alloc(ring, 5); 1500 if (r) 1501 goto error_free_wb; 1502 1503 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1504 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 1505 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 1506 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 1507 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 1508 amdgpu_ring_write(ring, 0xDEADBEEF); 1509 amdgpu_ring_commit(ring); 1510 1511 for (i = 0; i < adev->usec_timeout; i++) { 1512 tmp = le32_to_cpu(adev->wb.wb[index]); 1513 if (tmp == 0xDEADBEEF) 1514 break; 1515 udelay(1); 1516 } 1517 1518 if (i >= adev->usec_timeout) 1519 r = -ETIMEDOUT; 1520 1521 error_free_wb: 1522 amdgpu_device_wb_free(adev, index); 1523 return r; 1524 } 1525 1526 /** 1527 * sdma_v4_0_ring_test_ib - test an IB on the DMA engine 1528 * 1529 * @ring: amdgpu_ring structure holding ring information 1530 * 1531 * Test a simple IB in the DMA ring (VEGA10). 1532 * Returns 0 on success, error on failure. 1533 */ 1534 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1535 { 1536 struct amdgpu_device *adev = ring->adev; 1537 struct amdgpu_ib ib; 1538 struct dma_fence *f = NULL; 1539 unsigned index; 1540 long r; 1541 u32 tmp = 0; 1542 u64 gpu_addr; 1543 1544 r = amdgpu_device_wb_get(adev, &index); 1545 if (r) 1546 return r; 1547 1548 gpu_addr = adev->wb.gpu_addr + (index * 4); 1549 tmp = 0xCAFEDEAD; 1550 adev->wb.wb[index] = cpu_to_le32(tmp); 1551 memset(&ib, 0, sizeof(ib)); 1552 r = amdgpu_ib_get(adev, NULL, 256, 1553 AMDGPU_IB_POOL_DIRECT, &ib); 1554 if (r) 1555 goto err0; 1556 1557 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1558 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1559 ib.ptr[1] = lower_32_bits(gpu_addr); 1560 ib.ptr[2] = upper_32_bits(gpu_addr); 1561 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1562 ib.ptr[4] = 0xDEADBEEF; 1563 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1564 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1565 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1566 ib.length_dw = 8; 1567 1568 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1569 if (r) 1570 goto err1; 1571 1572 r = dma_fence_wait_timeout(f, false, timeout); 1573 if (r == 0) { 1574 r = -ETIMEDOUT; 1575 goto err1; 1576 } else if (r < 0) { 1577 goto err1; 1578 } 1579 tmp = le32_to_cpu(adev->wb.wb[index]); 1580 if (tmp == 0xDEADBEEF) 1581 r = 0; 1582 else 1583 r = -EINVAL; 1584 1585 err1: 1586 amdgpu_ib_free(adev, &ib, NULL); 1587 dma_fence_put(f); 1588 err0: 1589 amdgpu_device_wb_free(adev, index); 1590 return r; 1591 } 1592 1593 1594 /** 1595 * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART 1596 * 1597 * @ib: indirect buffer to fill with commands 1598 * @pe: addr of the page entry 1599 * @src: src addr to copy from 1600 * @count: number of page entries to update 1601 * 1602 * Update PTEs by copying them from the GART using sDMA (VEGA10). 1603 */ 1604 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib, 1605 uint64_t pe, uint64_t src, 1606 unsigned count) 1607 { 1608 unsigned bytes = count * 8; 1609 1610 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1611 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1612 ib->ptr[ib->length_dw++] = bytes - 1; 1613 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1614 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1615 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1616 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1617 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1618 1619 } 1620 1621 /** 1622 * sdma_v4_0_vm_write_pte - update PTEs by writing them manually 1623 * 1624 * @ib: indirect buffer to fill with commands 1625 * @pe: addr of the page entry 1626 * @addr: dst addr to write into pe 1627 * @count: number of page entries to update 1628 * @incr: increase next addr by incr bytes 1629 * @flags: access flags 1630 * 1631 * Update PTEs by writing them manually using sDMA (VEGA10). 1632 */ 1633 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1634 uint64_t value, unsigned count, 1635 uint32_t incr) 1636 { 1637 unsigned ndw = count * 2; 1638 1639 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1640 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1641 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1642 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1643 ib->ptr[ib->length_dw++] = ndw - 1; 1644 for (; ndw > 0; ndw -= 2) { 1645 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1646 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1647 value += incr; 1648 } 1649 } 1650 1651 /** 1652 * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA 1653 * 1654 * @ib: indirect buffer to fill with commands 1655 * @pe: addr of the page entry 1656 * @addr: dst addr to write into pe 1657 * @count: number of page entries to update 1658 * @incr: increase next addr by incr bytes 1659 * @flags: access flags 1660 * 1661 * Update the page tables using sDMA (VEGA10). 1662 */ 1663 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1664 uint64_t pe, 1665 uint64_t addr, unsigned count, 1666 uint32_t incr, uint64_t flags) 1667 { 1668 /* for physically contiguous pages (vram) */ 1669 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1670 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1671 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1672 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1673 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1674 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1675 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1676 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1677 ib->ptr[ib->length_dw++] = 0; 1678 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1679 } 1680 1681 /** 1682 * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw 1683 * 1684 * @ib: indirect buffer to fill with padding 1685 * 1686 */ 1687 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1688 { 1689 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1690 u32 pad_count; 1691 int i; 1692 1693 pad_count = (-ib->length_dw) & 7; 1694 for (i = 0; i < pad_count; i++) 1695 if (sdma && sdma->burst_nop && (i == 0)) 1696 ib->ptr[ib->length_dw++] = 1697 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1698 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1699 else 1700 ib->ptr[ib->length_dw++] = 1701 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1702 } 1703 1704 1705 /** 1706 * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline 1707 * 1708 * @ring: amdgpu_ring pointer 1709 * 1710 * Make sure all previous operations are completed (CIK). 1711 */ 1712 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1713 { 1714 uint32_t seq = ring->fence_drv.sync_seq; 1715 uint64_t addr = ring->fence_drv.gpu_addr; 1716 1717 /* wait for idle */ 1718 sdma_v4_0_wait_reg_mem(ring, 1, 0, 1719 addr & 0xfffffffc, 1720 upper_32_bits(addr) & 0xffffffff, 1721 seq, 0xffffffff, 4); 1722 } 1723 1724 1725 /** 1726 * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA 1727 * 1728 * @ring: amdgpu_ring pointer 1729 * @vm: amdgpu_vm pointer 1730 * 1731 * Update the page table base and flush the VM TLB 1732 * using sDMA (VEGA10). 1733 */ 1734 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1735 unsigned vmid, uint64_t pd_addr) 1736 { 1737 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1738 } 1739 1740 static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring, 1741 uint32_t reg, uint32_t val) 1742 { 1743 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1744 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1745 amdgpu_ring_write(ring, reg); 1746 amdgpu_ring_write(ring, val); 1747 } 1748 1749 static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1750 uint32_t val, uint32_t mask) 1751 { 1752 sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10); 1753 } 1754 1755 static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev) 1756 { 1757 uint fw_version = adev->sdma.instance[0].fw_version; 1758 1759 switch (adev->asic_type) { 1760 case CHIP_VEGA10: 1761 return fw_version >= 430; 1762 case CHIP_VEGA12: 1763 /*return fw_version >= 31;*/ 1764 return false; 1765 case CHIP_VEGA20: 1766 return fw_version >= 123; 1767 default: 1768 return false; 1769 } 1770 } 1771 1772 static int sdma_v4_0_early_init(void *handle) 1773 { 1774 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1775 int r; 1776 1777 if (adev->flags & AMD_IS_APU) 1778 adev->sdma.num_instances = 1; 1779 else if (adev->asic_type == CHIP_ARCTURUS) 1780 adev->sdma.num_instances = 8; 1781 else 1782 adev->sdma.num_instances = 2; 1783 1784 r = sdma_v4_0_init_microcode(adev); 1785 if (r) { 1786 DRM_ERROR("Failed to load sdma firmware!\n"); 1787 return r; 1788 } 1789 1790 /* TODO: Page queue breaks driver reload under SRIOV */ 1791 if ((adev->asic_type == CHIP_VEGA10) && amdgpu_sriov_vf((adev))) 1792 adev->sdma.has_page_queue = false; 1793 else if (sdma_v4_0_fw_support_paging_queue(adev)) 1794 adev->sdma.has_page_queue = true; 1795 1796 sdma_v4_0_set_ring_funcs(adev); 1797 sdma_v4_0_set_buffer_funcs(adev); 1798 sdma_v4_0_set_vm_pte_funcs(adev); 1799 sdma_v4_0_set_irq_funcs(adev); 1800 sdma_v4_0_set_ras_funcs(adev); 1801 1802 return 0; 1803 } 1804 1805 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev, 1806 void *err_data, 1807 struct amdgpu_iv_entry *entry); 1808 1809 static int sdma_v4_0_late_init(void *handle) 1810 { 1811 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1812 struct ras_ih_if ih_info = { 1813 .cb = sdma_v4_0_process_ras_data_cb, 1814 }; 1815 1816 if (adev->sdma.funcs && adev->sdma.funcs->reset_ras_error_count) 1817 adev->sdma.funcs->reset_ras_error_count(adev); 1818 1819 if (adev->sdma.funcs && adev->sdma.funcs->ras_late_init) 1820 return adev->sdma.funcs->ras_late_init(adev, &ih_info); 1821 else 1822 return 0; 1823 } 1824 1825 static int sdma_v4_0_sw_init(void *handle) 1826 { 1827 struct amdgpu_ring *ring; 1828 int r, i; 1829 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1830 1831 /* SDMA trap event */ 1832 for (i = 0; i < adev->sdma.num_instances; i++) { 1833 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1834 SDMA0_4_0__SRCID__SDMA_TRAP, 1835 &adev->sdma.trap_irq); 1836 if (r) 1837 return r; 1838 } 1839 1840 /* SDMA SRAM ECC event */ 1841 for (i = 0; i < adev->sdma.num_instances; i++) { 1842 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1843 SDMA0_4_0__SRCID__SDMA_SRAM_ECC, 1844 &adev->sdma.ecc_irq); 1845 if (r) 1846 return r; 1847 } 1848 1849 for (i = 0; i < adev->sdma.num_instances; i++) { 1850 ring = &adev->sdma.instance[i].ring; 1851 ring->ring_obj = NULL; 1852 ring->use_doorbell = true; 1853 1854 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1855 ring->use_doorbell?"true":"false"); 1856 1857 /* doorbell size is 2 dwords, get DWORD offset */ 1858 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1; 1859 1860 sprintf(ring->name, "sdma%d", i); 1861 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1862 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1863 AMDGPU_RING_PRIO_DEFAULT); 1864 if (r) 1865 return r; 1866 1867 if (adev->sdma.has_page_queue) { 1868 ring = &adev->sdma.instance[i].page; 1869 ring->ring_obj = NULL; 1870 ring->use_doorbell = true; 1871 1872 /* paging queue use same doorbell index/routing as gfx queue 1873 * with 0x400 (4096 dwords) offset on second doorbell page 1874 */ 1875 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1; 1876 ring->doorbell_index += 0x400; 1877 1878 sprintf(ring->name, "page%d", i); 1879 r = amdgpu_ring_init(adev, ring, 1024, 1880 &adev->sdma.trap_irq, 1881 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1882 AMDGPU_RING_PRIO_DEFAULT); 1883 if (r) 1884 return r; 1885 } 1886 } 1887 1888 return r; 1889 } 1890 1891 static int sdma_v4_0_sw_fini(void *handle) 1892 { 1893 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1894 int i; 1895 1896 if (adev->sdma.funcs && adev->sdma.funcs->ras_fini) 1897 adev->sdma.funcs->ras_fini(adev); 1898 1899 for (i = 0; i < adev->sdma.num_instances; i++) { 1900 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1901 if (adev->sdma.has_page_queue) 1902 amdgpu_ring_fini(&adev->sdma.instance[i].page); 1903 } 1904 1905 sdma_v4_0_destroy_inst_ctx(adev); 1906 1907 return 0; 1908 } 1909 1910 static int sdma_v4_0_hw_init(void *handle) 1911 { 1912 int r; 1913 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1914 1915 if (adev->flags & AMD_IS_APU) 1916 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false); 1917 1918 if (!amdgpu_sriov_vf(adev)) 1919 sdma_v4_0_init_golden_registers(adev); 1920 1921 r = sdma_v4_0_start(adev); 1922 1923 return r; 1924 } 1925 1926 static int sdma_v4_0_hw_fini(void *handle) 1927 { 1928 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1929 int i; 1930 1931 if (amdgpu_sriov_vf(adev)) 1932 return 0; 1933 1934 for (i = 0; i < adev->sdma.num_instances; i++) { 1935 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, 1936 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 1937 } 1938 1939 sdma_v4_0_ctx_switch_enable(adev, false); 1940 sdma_v4_0_enable(adev, false); 1941 1942 if (adev->flags & AMD_IS_APU) 1943 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true); 1944 1945 return 0; 1946 } 1947 1948 static int sdma_v4_0_suspend(void *handle) 1949 { 1950 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1951 1952 return sdma_v4_0_hw_fini(adev); 1953 } 1954 1955 static int sdma_v4_0_resume(void *handle) 1956 { 1957 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1958 1959 return sdma_v4_0_hw_init(adev); 1960 } 1961 1962 static bool sdma_v4_0_is_idle(void *handle) 1963 { 1964 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1965 u32 i; 1966 1967 for (i = 0; i < adev->sdma.num_instances; i++) { 1968 u32 tmp = RREG32_SDMA(i, mmSDMA0_STATUS_REG); 1969 1970 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1971 return false; 1972 } 1973 1974 return true; 1975 } 1976 1977 static int sdma_v4_0_wait_for_idle(void *handle) 1978 { 1979 unsigned i, j; 1980 u32 sdma[AMDGPU_MAX_SDMA_INSTANCES]; 1981 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1982 1983 for (i = 0; i < adev->usec_timeout; i++) { 1984 for (j = 0; j < adev->sdma.num_instances; j++) { 1985 sdma[j] = RREG32_SDMA(j, mmSDMA0_STATUS_REG); 1986 if (!(sdma[j] & SDMA0_STATUS_REG__IDLE_MASK)) 1987 break; 1988 } 1989 if (j == adev->sdma.num_instances) 1990 return 0; 1991 udelay(1); 1992 } 1993 return -ETIMEDOUT; 1994 } 1995 1996 static int sdma_v4_0_soft_reset(void *handle) 1997 { 1998 /* todo */ 1999 2000 return 0; 2001 } 2002 2003 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev, 2004 struct amdgpu_irq_src *source, 2005 unsigned type, 2006 enum amdgpu_interrupt_state state) 2007 { 2008 u32 sdma_cntl; 2009 2010 sdma_cntl = RREG32_SDMA(type, mmSDMA0_CNTL); 2011 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 2012 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2013 WREG32_SDMA(type, mmSDMA0_CNTL, sdma_cntl); 2014 2015 return 0; 2016 } 2017 2018 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev, 2019 struct amdgpu_irq_src *source, 2020 struct amdgpu_iv_entry *entry) 2021 { 2022 uint32_t instance; 2023 2024 DRM_DEBUG("IH: SDMA trap\n"); 2025 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 2026 switch (entry->ring_id) { 2027 case 0: 2028 amdgpu_fence_process(&adev->sdma.instance[instance].ring); 2029 break; 2030 case 1: 2031 if (adev->asic_type == CHIP_VEGA20) 2032 amdgpu_fence_process(&adev->sdma.instance[instance].page); 2033 break; 2034 case 2: 2035 /* XXX compute */ 2036 break; 2037 case 3: 2038 if (adev->asic_type != CHIP_VEGA20) 2039 amdgpu_fence_process(&adev->sdma.instance[instance].page); 2040 break; 2041 } 2042 return 0; 2043 } 2044 2045 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev, 2046 void *err_data, 2047 struct amdgpu_iv_entry *entry) 2048 { 2049 int instance; 2050 2051 /* When “Full RAS” is enabled, the per-IP interrupt sources should 2052 * be disabled and the driver should only look for the aggregated 2053 * interrupt via sync flood 2054 */ 2055 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 2056 goto out; 2057 2058 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 2059 if (instance < 0) 2060 goto out; 2061 2062 amdgpu_sdma_process_ras_data_cb(adev, err_data, entry); 2063 2064 out: 2065 return AMDGPU_RAS_SUCCESS; 2066 } 2067 2068 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev, 2069 struct amdgpu_irq_src *source, 2070 struct amdgpu_iv_entry *entry) 2071 { 2072 int instance; 2073 2074 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 2075 2076 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 2077 if (instance < 0) 2078 return 0; 2079 2080 switch (entry->ring_id) { 2081 case 0: 2082 drm_sched_fault(&adev->sdma.instance[instance].ring.sched); 2083 break; 2084 } 2085 return 0; 2086 } 2087 2088 static int sdma_v4_0_set_ecc_irq_state(struct amdgpu_device *adev, 2089 struct amdgpu_irq_src *source, 2090 unsigned type, 2091 enum amdgpu_interrupt_state state) 2092 { 2093 u32 sdma_edc_config; 2094 2095 sdma_edc_config = RREG32_SDMA(type, mmSDMA0_EDC_CONFIG); 2096 sdma_edc_config = REG_SET_FIELD(sdma_edc_config, SDMA0_EDC_CONFIG, ECC_INT_ENABLE, 2097 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2098 WREG32_SDMA(type, mmSDMA0_EDC_CONFIG, sdma_edc_config); 2099 2100 return 0; 2101 } 2102 2103 static void sdma_v4_0_update_medium_grain_clock_gating( 2104 struct amdgpu_device *adev, 2105 bool enable) 2106 { 2107 uint32_t data, def; 2108 int i; 2109 2110 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 2111 for (i = 0; i < adev->sdma.num_instances; i++) { 2112 def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL); 2113 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 2114 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 2115 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 2116 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 2117 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 2118 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 2119 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 2120 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 2121 if (def != data) 2122 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data); 2123 } 2124 } else { 2125 for (i = 0; i < adev->sdma.num_instances; i++) { 2126 def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL); 2127 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 2128 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 2129 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 2130 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 2131 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 2132 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 2133 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 2134 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 2135 if (def != data) 2136 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data); 2137 } 2138 } 2139 } 2140 2141 2142 static void sdma_v4_0_update_medium_grain_light_sleep( 2143 struct amdgpu_device *adev, 2144 bool enable) 2145 { 2146 uint32_t data, def; 2147 int i; 2148 2149 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 2150 for (i = 0; i < adev->sdma.num_instances; i++) { 2151 /* 1-not override: enable sdma mem light sleep */ 2152 def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL); 2153 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 2154 if (def != data) 2155 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data); 2156 } 2157 } else { 2158 for (i = 0; i < adev->sdma.num_instances; i++) { 2159 /* 0-override:disable sdma mem light sleep */ 2160 def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL); 2161 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 2162 if (def != data) 2163 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data); 2164 } 2165 } 2166 } 2167 2168 static int sdma_v4_0_set_clockgating_state(void *handle, 2169 enum amd_clockgating_state state) 2170 { 2171 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2172 2173 if (amdgpu_sriov_vf(adev)) 2174 return 0; 2175 2176 switch (adev->asic_type) { 2177 case CHIP_VEGA10: 2178 case CHIP_VEGA12: 2179 case CHIP_VEGA20: 2180 case CHIP_RAVEN: 2181 case CHIP_ARCTURUS: 2182 case CHIP_RENOIR: 2183 sdma_v4_0_update_medium_grain_clock_gating(adev, 2184 state == AMD_CG_STATE_GATE); 2185 sdma_v4_0_update_medium_grain_light_sleep(adev, 2186 state == AMD_CG_STATE_GATE); 2187 break; 2188 default: 2189 break; 2190 } 2191 return 0; 2192 } 2193 2194 static int sdma_v4_0_set_powergating_state(void *handle, 2195 enum amd_powergating_state state) 2196 { 2197 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2198 2199 switch (adev->asic_type) { 2200 case CHIP_RAVEN: 2201 case CHIP_RENOIR: 2202 sdma_v4_1_update_power_gating(adev, 2203 state == AMD_PG_STATE_GATE ? true : false); 2204 break; 2205 default: 2206 break; 2207 } 2208 2209 return 0; 2210 } 2211 2212 static void sdma_v4_0_get_clockgating_state(void *handle, u32 *flags) 2213 { 2214 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2215 int data; 2216 2217 if (amdgpu_sriov_vf(adev)) 2218 *flags = 0; 2219 2220 /* AMD_CG_SUPPORT_SDMA_MGCG */ 2221 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 2222 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK)) 2223 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 2224 2225 /* AMD_CG_SUPPORT_SDMA_LS */ 2226 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 2227 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 2228 *flags |= AMD_CG_SUPPORT_SDMA_LS; 2229 } 2230 2231 const struct amd_ip_funcs sdma_v4_0_ip_funcs = { 2232 .name = "sdma_v4_0", 2233 .early_init = sdma_v4_0_early_init, 2234 .late_init = sdma_v4_0_late_init, 2235 .sw_init = sdma_v4_0_sw_init, 2236 .sw_fini = sdma_v4_0_sw_fini, 2237 .hw_init = sdma_v4_0_hw_init, 2238 .hw_fini = sdma_v4_0_hw_fini, 2239 .suspend = sdma_v4_0_suspend, 2240 .resume = sdma_v4_0_resume, 2241 .is_idle = sdma_v4_0_is_idle, 2242 .wait_for_idle = sdma_v4_0_wait_for_idle, 2243 .soft_reset = sdma_v4_0_soft_reset, 2244 .set_clockgating_state = sdma_v4_0_set_clockgating_state, 2245 .set_powergating_state = sdma_v4_0_set_powergating_state, 2246 .get_clockgating_state = sdma_v4_0_get_clockgating_state, 2247 }; 2248 2249 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = { 2250 .type = AMDGPU_RING_TYPE_SDMA, 2251 .align_mask = 0xf, 2252 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2253 .support_64bit_ptrs = true, 2254 .vmhub = AMDGPU_MMHUB_0, 2255 .get_rptr = sdma_v4_0_ring_get_rptr, 2256 .get_wptr = sdma_v4_0_ring_get_wptr, 2257 .set_wptr = sdma_v4_0_ring_set_wptr, 2258 .emit_frame_size = 2259 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2260 3 + /* hdp invalidate */ 2261 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2262 /* sdma_v4_0_ring_emit_vm_flush */ 2263 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2264 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2265 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2266 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2267 .emit_ib = sdma_v4_0_ring_emit_ib, 2268 .emit_fence = sdma_v4_0_ring_emit_fence, 2269 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2270 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2271 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2272 .test_ring = sdma_v4_0_ring_test_ring, 2273 .test_ib = sdma_v4_0_ring_test_ib, 2274 .insert_nop = sdma_v4_0_ring_insert_nop, 2275 .pad_ib = sdma_v4_0_ring_pad_ib, 2276 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2277 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2278 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2279 }; 2280 2281 /* 2282 * On Arcturus, SDMA instance 5~7 has a different vmhub type(AMDGPU_MMHUB_1). 2283 * So create a individual constant ring_funcs for those instances. 2284 */ 2285 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs_2nd_mmhub = { 2286 .type = AMDGPU_RING_TYPE_SDMA, 2287 .align_mask = 0xf, 2288 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2289 .support_64bit_ptrs = true, 2290 .vmhub = AMDGPU_MMHUB_1, 2291 .get_rptr = sdma_v4_0_ring_get_rptr, 2292 .get_wptr = sdma_v4_0_ring_get_wptr, 2293 .set_wptr = sdma_v4_0_ring_set_wptr, 2294 .emit_frame_size = 2295 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2296 3 + /* hdp invalidate */ 2297 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2298 /* sdma_v4_0_ring_emit_vm_flush */ 2299 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2300 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2301 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2302 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2303 .emit_ib = sdma_v4_0_ring_emit_ib, 2304 .emit_fence = sdma_v4_0_ring_emit_fence, 2305 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2306 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2307 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2308 .test_ring = sdma_v4_0_ring_test_ring, 2309 .test_ib = sdma_v4_0_ring_test_ib, 2310 .insert_nop = sdma_v4_0_ring_insert_nop, 2311 .pad_ib = sdma_v4_0_ring_pad_ib, 2312 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2313 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2314 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2315 }; 2316 2317 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = { 2318 .type = AMDGPU_RING_TYPE_SDMA, 2319 .align_mask = 0xf, 2320 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2321 .support_64bit_ptrs = true, 2322 .vmhub = AMDGPU_MMHUB_0, 2323 .get_rptr = sdma_v4_0_ring_get_rptr, 2324 .get_wptr = sdma_v4_0_page_ring_get_wptr, 2325 .set_wptr = sdma_v4_0_page_ring_set_wptr, 2326 .emit_frame_size = 2327 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2328 3 + /* hdp invalidate */ 2329 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2330 /* sdma_v4_0_ring_emit_vm_flush */ 2331 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2332 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2333 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2334 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2335 .emit_ib = sdma_v4_0_ring_emit_ib, 2336 .emit_fence = sdma_v4_0_ring_emit_fence, 2337 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2338 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2339 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2340 .test_ring = sdma_v4_0_ring_test_ring, 2341 .test_ib = sdma_v4_0_ring_test_ib, 2342 .insert_nop = sdma_v4_0_ring_insert_nop, 2343 .pad_ib = sdma_v4_0_ring_pad_ib, 2344 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2345 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2346 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2347 }; 2348 2349 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs_2nd_mmhub = { 2350 .type = AMDGPU_RING_TYPE_SDMA, 2351 .align_mask = 0xf, 2352 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2353 .support_64bit_ptrs = true, 2354 .vmhub = AMDGPU_MMHUB_1, 2355 .get_rptr = sdma_v4_0_ring_get_rptr, 2356 .get_wptr = sdma_v4_0_page_ring_get_wptr, 2357 .set_wptr = sdma_v4_0_page_ring_set_wptr, 2358 .emit_frame_size = 2359 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2360 3 + /* hdp invalidate */ 2361 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2362 /* sdma_v4_0_ring_emit_vm_flush */ 2363 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2364 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2365 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2366 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2367 .emit_ib = sdma_v4_0_ring_emit_ib, 2368 .emit_fence = sdma_v4_0_ring_emit_fence, 2369 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2370 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2371 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2372 .test_ring = sdma_v4_0_ring_test_ring, 2373 .test_ib = sdma_v4_0_ring_test_ib, 2374 .insert_nop = sdma_v4_0_ring_insert_nop, 2375 .pad_ib = sdma_v4_0_ring_pad_ib, 2376 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2377 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2378 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2379 }; 2380 2381 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev) 2382 { 2383 int i; 2384 2385 for (i = 0; i < adev->sdma.num_instances; i++) { 2386 if (adev->asic_type == CHIP_ARCTURUS && i >= 5) 2387 adev->sdma.instance[i].ring.funcs = 2388 &sdma_v4_0_ring_funcs_2nd_mmhub; 2389 else 2390 adev->sdma.instance[i].ring.funcs = 2391 &sdma_v4_0_ring_funcs; 2392 adev->sdma.instance[i].ring.me = i; 2393 if (adev->sdma.has_page_queue) { 2394 if (adev->asic_type == CHIP_ARCTURUS && i >= 5) 2395 adev->sdma.instance[i].page.funcs = 2396 &sdma_v4_0_page_ring_funcs_2nd_mmhub; 2397 else 2398 adev->sdma.instance[i].page.funcs = 2399 &sdma_v4_0_page_ring_funcs; 2400 adev->sdma.instance[i].page.me = i; 2401 } 2402 } 2403 } 2404 2405 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = { 2406 .set = sdma_v4_0_set_trap_irq_state, 2407 .process = sdma_v4_0_process_trap_irq, 2408 }; 2409 2410 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = { 2411 .process = sdma_v4_0_process_illegal_inst_irq, 2412 }; 2413 2414 static const struct amdgpu_irq_src_funcs sdma_v4_0_ecc_irq_funcs = { 2415 .set = sdma_v4_0_set_ecc_irq_state, 2416 .process = amdgpu_sdma_process_ecc_irq, 2417 }; 2418 2419 2420 2421 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev) 2422 { 2423 switch (adev->sdma.num_instances) { 2424 case 1: 2425 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1; 2426 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1; 2427 break; 2428 case 8: 2429 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 2430 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 2431 break; 2432 case 2: 2433 default: 2434 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2; 2435 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2; 2436 break; 2437 } 2438 adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs; 2439 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs; 2440 adev->sdma.ecc_irq.funcs = &sdma_v4_0_ecc_irq_funcs; 2441 } 2442 2443 /** 2444 * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine 2445 * 2446 * @ring: amdgpu_ring structure holding ring information 2447 * @src_offset: src GPU address 2448 * @dst_offset: dst GPU address 2449 * @byte_count: number of bytes to xfer 2450 * 2451 * Copy GPU buffers using the DMA engine (VEGA10/12). 2452 * Used by the amdgpu ttm implementation to move pages if 2453 * registered as the asic copy callback. 2454 */ 2455 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib, 2456 uint64_t src_offset, 2457 uint64_t dst_offset, 2458 uint32_t byte_count, 2459 bool tmz) 2460 { 2461 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 2462 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 2463 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0); 2464 ib->ptr[ib->length_dw++] = byte_count - 1; 2465 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 2466 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 2467 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 2468 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2469 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2470 } 2471 2472 /** 2473 * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine 2474 * 2475 * @ring: amdgpu_ring structure holding ring information 2476 * @src_data: value to write to buffer 2477 * @dst_offset: dst GPU address 2478 * @byte_count: number of bytes to xfer 2479 * 2480 * Fill GPU buffers using the DMA engine (VEGA10/12). 2481 */ 2482 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib, 2483 uint32_t src_data, 2484 uint64_t dst_offset, 2485 uint32_t byte_count) 2486 { 2487 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 2488 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2489 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2490 ib->ptr[ib->length_dw++] = src_data; 2491 ib->ptr[ib->length_dw++] = byte_count - 1; 2492 } 2493 2494 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = { 2495 .copy_max_bytes = 0x400000, 2496 .copy_num_dw = 7, 2497 .emit_copy_buffer = sdma_v4_0_emit_copy_buffer, 2498 2499 .fill_max_bytes = 0x400000, 2500 .fill_num_dw = 5, 2501 .emit_fill_buffer = sdma_v4_0_emit_fill_buffer, 2502 }; 2503 2504 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev) 2505 { 2506 adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs; 2507 if (adev->sdma.has_page_queue) 2508 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page; 2509 else 2510 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 2511 } 2512 2513 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = { 2514 .copy_pte_num_dw = 7, 2515 .copy_pte = sdma_v4_0_vm_copy_pte, 2516 2517 .write_pte = sdma_v4_0_vm_write_pte, 2518 .set_pte_pde = sdma_v4_0_vm_set_pte_pde, 2519 }; 2520 2521 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev) 2522 { 2523 struct drm_gpu_scheduler *sched; 2524 unsigned i; 2525 2526 adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs; 2527 for (i = 0; i < adev->sdma.num_instances; i++) { 2528 if (adev->sdma.has_page_queue) 2529 sched = &adev->sdma.instance[i].page.sched; 2530 else 2531 sched = &adev->sdma.instance[i].ring.sched; 2532 adev->vm_manager.vm_pte_scheds[i] = sched; 2533 } 2534 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 2535 } 2536 2537 static void sdma_v4_0_get_ras_error_count(uint32_t value, 2538 uint32_t instance, 2539 uint32_t *sec_count) 2540 { 2541 uint32_t i; 2542 uint32_t sec_cnt; 2543 2544 /* double bits error (multiple bits) error detection is not supported */ 2545 for (i = 0; i < ARRAY_SIZE(sdma_v4_0_ras_fields); i++) { 2546 /* the SDMA_EDC_COUNTER register in each sdma instance 2547 * shares the same sed shift_mask 2548 * */ 2549 sec_cnt = (value & 2550 sdma_v4_0_ras_fields[i].sec_count_mask) >> 2551 sdma_v4_0_ras_fields[i].sec_count_shift; 2552 if (sec_cnt) { 2553 DRM_INFO("Detected %s in SDMA%d, SED %d\n", 2554 sdma_v4_0_ras_fields[i].name, 2555 instance, sec_cnt); 2556 *sec_count += sec_cnt; 2557 } 2558 } 2559 } 2560 2561 static int sdma_v4_0_query_ras_error_count(struct amdgpu_device *adev, 2562 uint32_t instance, void *ras_error_status) 2563 { 2564 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 2565 uint32_t sec_count = 0; 2566 uint32_t reg_value = 0; 2567 2568 reg_value = RREG32_SDMA(instance, mmSDMA0_EDC_COUNTER); 2569 /* double bit error is not supported */ 2570 if (reg_value) 2571 sdma_v4_0_get_ras_error_count(reg_value, 2572 instance, &sec_count); 2573 /* err_data->ce_count should be initialized to 0 2574 * before calling into this function */ 2575 err_data->ce_count += sec_count; 2576 /* double bit error is not supported 2577 * set ue count to 0 */ 2578 err_data->ue_count = 0; 2579 2580 return 0; 2581 }; 2582 2583 static void sdma_v4_0_reset_ras_error_count(struct amdgpu_device *adev) 2584 { 2585 int i; 2586 2587 /* read back edc counter registers to clear the counters */ 2588 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 2589 for (i = 0; i < adev->sdma.num_instances; i++) 2590 RREG32_SDMA(i, mmSDMA0_EDC_COUNTER); 2591 } 2592 } 2593 2594 static const struct amdgpu_sdma_ras_funcs sdma_v4_0_ras_funcs = { 2595 .ras_late_init = amdgpu_sdma_ras_late_init, 2596 .ras_fini = amdgpu_sdma_ras_fini, 2597 .query_ras_error_count = sdma_v4_0_query_ras_error_count, 2598 .reset_ras_error_count = sdma_v4_0_reset_ras_error_count, 2599 }; 2600 2601 static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev) 2602 { 2603 switch (adev->asic_type) { 2604 case CHIP_VEGA20: 2605 case CHIP_ARCTURUS: 2606 adev->sdma.funcs = &sdma_v4_0_ras_funcs; 2607 break; 2608 default: 2609 break; 2610 } 2611 } 2612 2613 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = { 2614 .type = AMD_IP_BLOCK_TYPE_SDMA, 2615 .major = 4, 2616 .minor = 0, 2617 .rev = 0, 2618 .funcs = &sdma_v4_0_ip_funcs, 2619 }; 2620