1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "sdma0/sdma0_4_2_offset.h" 34 #include "sdma0/sdma0_4_2_sh_mask.h" 35 #include "sdma1/sdma1_4_2_offset.h" 36 #include "sdma1/sdma1_4_2_sh_mask.h" 37 #include "sdma2/sdma2_4_2_2_offset.h" 38 #include "sdma2/sdma2_4_2_2_sh_mask.h" 39 #include "sdma3/sdma3_4_2_2_offset.h" 40 #include "sdma3/sdma3_4_2_2_sh_mask.h" 41 #include "sdma4/sdma4_4_2_2_offset.h" 42 #include "sdma4/sdma4_4_2_2_sh_mask.h" 43 #include "sdma5/sdma5_4_2_2_offset.h" 44 #include "sdma5/sdma5_4_2_2_sh_mask.h" 45 #include "sdma6/sdma6_4_2_2_offset.h" 46 #include "sdma6/sdma6_4_2_2_sh_mask.h" 47 #include "sdma7/sdma7_4_2_2_offset.h" 48 #include "sdma7/sdma7_4_2_2_sh_mask.h" 49 #include "hdp/hdp_4_0_offset.h" 50 #include "sdma0/sdma0_4_1_default.h" 51 52 #include "soc15_common.h" 53 #include "soc15.h" 54 #include "vega10_sdma_pkt_open.h" 55 56 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h" 57 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h" 58 59 #include "amdgpu_ras.h" 60 61 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin"); 62 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin"); 63 MODULE_FIRMWARE("amdgpu/vega12_sdma.bin"); 64 MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin"); 65 MODULE_FIRMWARE("amdgpu/vega20_sdma.bin"); 66 MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin"); 67 MODULE_FIRMWARE("amdgpu/raven_sdma.bin"); 68 MODULE_FIRMWARE("amdgpu/picasso_sdma.bin"); 69 MODULE_FIRMWARE("amdgpu/raven2_sdma.bin"); 70 MODULE_FIRMWARE("amdgpu/arcturus_sdma.bin"); 71 MODULE_FIRMWARE("amdgpu/arcturus_sdma1.bin"); 72 MODULE_FIRMWARE("amdgpu/arcturus_sdma2.bin"); 73 MODULE_FIRMWARE("amdgpu/arcturus_sdma3.bin"); 74 MODULE_FIRMWARE("amdgpu/arcturus_sdma4.bin"); 75 MODULE_FIRMWARE("amdgpu/arcturus_sdma5.bin"); 76 MODULE_FIRMWARE("amdgpu/arcturus_sdma6.bin"); 77 MODULE_FIRMWARE("amdgpu/arcturus_sdma7.bin"); 78 79 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L 80 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L 81 82 #define WREG32_SDMA(instance, offset, value) \ 83 WREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)), value) 84 #define RREG32_SDMA(instance, offset) \ 85 RREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset))) 86 87 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev); 88 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev); 89 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev); 90 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev); 91 92 static const struct soc15_reg_golden golden_settings_sdma_4[] = { 93 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 94 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100), 95 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100), 96 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 97 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 98 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 99 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000), 100 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 101 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 102 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 103 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 104 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 105 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000), 106 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), 107 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100), 108 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 109 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 110 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 111 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000), 112 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 113 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 114 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 115 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 116 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0), 117 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xfc000000, 0x00000000) 118 }; 119 120 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = { 121 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 122 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 123 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 124 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 125 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002) 126 }; 127 128 static const struct soc15_reg_golden golden_settings_sdma_vg12[] = { 129 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), 130 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001), 131 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 132 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), 133 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001) 134 }; 135 136 static const struct soc15_reg_golden golden_settings_sdma_4_1[] = { 137 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 138 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 139 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100), 140 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 141 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051), 142 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100), 143 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 144 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100), 145 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 146 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 147 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000) 148 }; 149 150 static const struct soc15_reg_golden golden_settings_sdma0_4_2_init[] = { 151 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 152 }; 153 154 static const struct soc15_reg_golden golden_settings_sdma0_4_2[] = 155 { 156 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 157 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 158 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 159 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 160 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 161 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 162 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 163 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 164 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RD_BURST_CNTL, 0x0000000f, 0x00000003), 165 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 166 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 167 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 168 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 169 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 170 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 171 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 172 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 173 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 174 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 175 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 176 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 177 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 178 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 179 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 180 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 181 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 182 }; 183 184 static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = { 185 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 186 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), 187 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 188 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 189 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 190 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 191 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 192 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 193 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RD_BURST_CNTL, 0x0000000f, 0x00000003), 194 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 195 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 196 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 197 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 198 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 199 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 200 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 201 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 202 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 203 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 204 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 205 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 206 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 207 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 208 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 209 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 210 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0), 211 }; 212 213 static const struct soc15_reg_golden golden_settings_sdma_rv1[] = 214 { 215 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002), 216 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002) 217 }; 218 219 static const struct soc15_reg_golden golden_settings_sdma_rv2[] = 220 { 221 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00003001), 222 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003001) 223 }; 224 225 static const struct soc15_reg_golden golden_settings_sdma_arct[] = 226 { 227 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 228 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 229 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 230 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 231 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 232 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 233 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 234 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 235 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 236 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 237 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 238 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 239 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 240 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 241 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 242 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 243 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 244 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 245 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 246 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 247 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 248 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 249 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 250 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002) 251 }; 252 253 static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev, 254 u32 instance, u32 offset) 255 { 256 switch (instance) { 257 case 0: 258 return (adev->reg_offset[SDMA0_HWIP][0][0] + offset); 259 case 1: 260 return (adev->reg_offset[SDMA1_HWIP][0][0] + offset); 261 case 2: 262 return (adev->reg_offset[SDMA2_HWIP][0][1] + offset); 263 case 3: 264 return (adev->reg_offset[SDMA3_HWIP][0][1] + offset); 265 case 4: 266 return (adev->reg_offset[SDMA4_HWIP][0][1] + offset); 267 case 5: 268 return (adev->reg_offset[SDMA5_HWIP][0][1] + offset); 269 case 6: 270 return (adev->reg_offset[SDMA6_HWIP][0][1] + offset); 271 case 7: 272 return (adev->reg_offset[SDMA7_HWIP][0][1] + offset); 273 default: 274 break; 275 } 276 return 0; 277 } 278 279 static unsigned sdma_v4_0_seq_to_irq_id(int seq_num) 280 { 281 switch (seq_num) { 282 case 0: 283 return SOC15_IH_CLIENTID_SDMA0; 284 case 1: 285 return SOC15_IH_CLIENTID_SDMA1; 286 case 2: 287 return SOC15_IH_CLIENTID_SDMA2; 288 case 3: 289 return SOC15_IH_CLIENTID_SDMA3; 290 case 4: 291 return SOC15_IH_CLIENTID_SDMA4; 292 case 5: 293 return SOC15_IH_CLIENTID_SDMA5; 294 case 6: 295 return SOC15_IH_CLIENTID_SDMA6; 296 case 7: 297 return SOC15_IH_CLIENTID_SDMA7; 298 default: 299 break; 300 } 301 return -EINVAL; 302 } 303 304 static int sdma_v4_0_irq_id_to_seq(unsigned client_id) 305 { 306 switch (client_id) { 307 case SOC15_IH_CLIENTID_SDMA0: 308 return 0; 309 case SOC15_IH_CLIENTID_SDMA1: 310 return 1; 311 case SOC15_IH_CLIENTID_SDMA2: 312 return 2; 313 case SOC15_IH_CLIENTID_SDMA3: 314 return 3; 315 case SOC15_IH_CLIENTID_SDMA4: 316 return 4; 317 case SOC15_IH_CLIENTID_SDMA5: 318 return 5; 319 case SOC15_IH_CLIENTID_SDMA6: 320 return 6; 321 case SOC15_IH_CLIENTID_SDMA7: 322 return 7; 323 default: 324 break; 325 } 326 return -EINVAL; 327 } 328 329 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) 330 { 331 switch (adev->asic_type) { 332 case CHIP_VEGA10: 333 if (!amdgpu_virt_support_skip_setting(adev)) { 334 soc15_program_register_sequence(adev, 335 golden_settings_sdma_4, 336 ARRAY_SIZE(golden_settings_sdma_4)); 337 soc15_program_register_sequence(adev, 338 golden_settings_sdma_vg10, 339 ARRAY_SIZE(golden_settings_sdma_vg10)); 340 } 341 break; 342 case CHIP_VEGA12: 343 soc15_program_register_sequence(adev, 344 golden_settings_sdma_4, 345 ARRAY_SIZE(golden_settings_sdma_4)); 346 soc15_program_register_sequence(adev, 347 golden_settings_sdma_vg12, 348 ARRAY_SIZE(golden_settings_sdma_vg12)); 349 break; 350 case CHIP_VEGA20: 351 soc15_program_register_sequence(adev, 352 golden_settings_sdma0_4_2_init, 353 ARRAY_SIZE(golden_settings_sdma0_4_2_init)); 354 soc15_program_register_sequence(adev, 355 golden_settings_sdma0_4_2, 356 ARRAY_SIZE(golden_settings_sdma0_4_2)); 357 soc15_program_register_sequence(adev, 358 golden_settings_sdma1_4_2, 359 ARRAY_SIZE(golden_settings_sdma1_4_2)); 360 break; 361 case CHIP_ARCTURUS: 362 soc15_program_register_sequence(adev, 363 golden_settings_sdma_arct, 364 ARRAY_SIZE(golden_settings_sdma_arct)); 365 break; 366 case CHIP_RAVEN: 367 soc15_program_register_sequence(adev, 368 golden_settings_sdma_4_1, 369 ARRAY_SIZE(golden_settings_sdma_4_1)); 370 if (adev->rev_id >= 8) 371 soc15_program_register_sequence(adev, 372 golden_settings_sdma_rv2, 373 ARRAY_SIZE(golden_settings_sdma_rv2)); 374 else 375 soc15_program_register_sequence(adev, 376 golden_settings_sdma_rv1, 377 ARRAY_SIZE(golden_settings_sdma_rv1)); 378 break; 379 default: 380 break; 381 } 382 } 383 384 /** 385 * sdma_v4_0_init_microcode - load ucode images from disk 386 * 387 * @adev: amdgpu_device pointer 388 * 389 * Use the firmware interface to load the ucode images into 390 * the driver (not loaded into hw). 391 * Returns 0 on success, error on failure. 392 */ 393 394 // emulation only, won't work on real chip 395 // vega10 real chip need to use PSP to load firmware 396 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev) 397 { 398 const char *chip_name; 399 char fw_name[30]; 400 int err = 0, i; 401 struct amdgpu_firmware_info *info = NULL; 402 const struct common_firmware_header *header = NULL; 403 const struct sdma_firmware_header_v1_0 *hdr; 404 405 DRM_DEBUG("\n"); 406 407 switch (adev->asic_type) { 408 case CHIP_VEGA10: 409 chip_name = "vega10"; 410 break; 411 case CHIP_VEGA12: 412 chip_name = "vega12"; 413 break; 414 case CHIP_VEGA20: 415 chip_name = "vega20"; 416 break; 417 case CHIP_RAVEN: 418 if (adev->rev_id >= 8) 419 chip_name = "raven2"; 420 else if (adev->pdev->device == 0x15d8) 421 chip_name = "picasso"; 422 else 423 chip_name = "raven"; 424 break; 425 case CHIP_ARCTURUS: 426 chip_name = "arcturus"; 427 break; 428 default: 429 BUG(); 430 } 431 432 for (i = 0; i < adev->sdma.num_instances; i++) { 433 if (i == 0) 434 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 435 else 436 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i); 437 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 438 if (err) 439 goto out; 440 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); 441 if (err) 442 goto out; 443 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 444 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 445 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 446 if (adev->sdma.instance[i].feature_version >= 20) 447 adev->sdma.instance[i].burst_nop = true; 448 DRM_DEBUG("psp_load == '%s'\n", 449 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); 450 451 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 452 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 453 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 454 info->fw = adev->sdma.instance[i].fw; 455 header = (const struct common_firmware_header *)info->fw->data; 456 adev->firmware.fw_size += 457 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 458 } 459 } 460 out: 461 if (err) { 462 DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name); 463 for (i = 0; i < adev->sdma.num_instances; i++) { 464 release_firmware(adev->sdma.instance[i].fw); 465 adev->sdma.instance[i].fw = NULL; 466 } 467 } 468 return err; 469 } 470 471 /** 472 * sdma_v4_0_ring_get_rptr - get the current read pointer 473 * 474 * @ring: amdgpu ring pointer 475 * 476 * Get the current rptr from the hardware (VEGA10+). 477 */ 478 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring) 479 { 480 u64 *rptr; 481 482 /* XXX check if swapping is necessary on BE */ 483 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]); 484 485 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 486 return ((*rptr) >> 2); 487 } 488 489 /** 490 * sdma_v4_0_ring_get_wptr - get the current write pointer 491 * 492 * @ring: amdgpu ring pointer 493 * 494 * Get the current wptr from the hardware (VEGA10+). 495 */ 496 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring) 497 { 498 struct amdgpu_device *adev = ring->adev; 499 u64 wptr; 500 501 if (ring->use_doorbell) { 502 /* XXX check if swapping is necessary on BE */ 503 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 504 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 505 } else { 506 wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI); 507 wptr = wptr << 32; 508 wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR); 509 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", 510 ring->me, wptr); 511 } 512 513 return wptr >> 2; 514 } 515 516 /** 517 * sdma_v4_0_ring_set_wptr - commit the write pointer 518 * 519 * @ring: amdgpu ring pointer 520 * 521 * Write the wptr back to the hardware (VEGA10+). 522 */ 523 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring) 524 { 525 struct amdgpu_device *adev = ring->adev; 526 527 DRM_DEBUG("Setting write pointer\n"); 528 if (ring->use_doorbell) { 529 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 530 531 DRM_DEBUG("Using doorbell -- " 532 "wptr_offs == 0x%08x " 533 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 534 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 535 ring->wptr_offs, 536 lower_32_bits(ring->wptr << 2), 537 upper_32_bits(ring->wptr << 2)); 538 /* XXX check if swapping is necessary on BE */ 539 WRITE_ONCE(*wb, (ring->wptr << 2)); 540 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 541 ring->doorbell_index, ring->wptr << 2); 542 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 543 } else { 544 DRM_DEBUG("Not using doorbell -- " 545 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 546 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 547 ring->me, 548 lower_32_bits(ring->wptr << 2), 549 ring->me, 550 upper_32_bits(ring->wptr << 2)); 551 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR, 552 lower_32_bits(ring->wptr << 2)); 553 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI, 554 upper_32_bits(ring->wptr << 2)); 555 } 556 } 557 558 /** 559 * sdma_v4_0_page_ring_get_wptr - get the current write pointer 560 * 561 * @ring: amdgpu ring pointer 562 * 563 * Get the current wptr from the hardware (VEGA10+). 564 */ 565 static uint64_t sdma_v4_0_page_ring_get_wptr(struct amdgpu_ring *ring) 566 { 567 struct amdgpu_device *adev = ring->adev; 568 u64 wptr; 569 570 if (ring->use_doorbell) { 571 /* XXX check if swapping is necessary on BE */ 572 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 573 } else { 574 wptr = RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI); 575 wptr = wptr << 32; 576 wptr |= RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR); 577 } 578 579 return wptr >> 2; 580 } 581 582 /** 583 * sdma_v4_0_ring_set_wptr - commit the write pointer 584 * 585 * @ring: amdgpu ring pointer 586 * 587 * Write the wptr back to the hardware (VEGA10+). 588 */ 589 static void sdma_v4_0_page_ring_set_wptr(struct amdgpu_ring *ring) 590 { 591 struct amdgpu_device *adev = ring->adev; 592 593 if (ring->use_doorbell) { 594 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 595 596 /* XXX check if swapping is necessary on BE */ 597 WRITE_ONCE(*wb, (ring->wptr << 2)); 598 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 599 } else { 600 uint64_t wptr = ring->wptr << 2; 601 602 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR, 603 lower_32_bits(wptr)); 604 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI, 605 upper_32_bits(wptr)); 606 } 607 } 608 609 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 610 { 611 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 612 int i; 613 614 for (i = 0; i < count; i++) 615 if (sdma && sdma->burst_nop && (i == 0)) 616 amdgpu_ring_write(ring, ring->funcs->nop | 617 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 618 else 619 amdgpu_ring_write(ring, ring->funcs->nop); 620 } 621 622 /** 623 * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine 624 * 625 * @ring: amdgpu ring pointer 626 * @ib: IB object to schedule 627 * 628 * Schedule an IB in the DMA ring (VEGA10). 629 */ 630 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring, 631 struct amdgpu_job *job, 632 struct amdgpu_ib *ib, 633 uint32_t flags) 634 { 635 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 636 637 /* IB packet must end on a 8 DW boundary */ 638 sdma_v4_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8); 639 640 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 641 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 642 /* base must be 32 byte aligned */ 643 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 644 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 645 amdgpu_ring_write(ring, ib->length_dw); 646 amdgpu_ring_write(ring, 0); 647 amdgpu_ring_write(ring, 0); 648 649 } 650 651 static void sdma_v4_0_wait_reg_mem(struct amdgpu_ring *ring, 652 int mem_space, int hdp, 653 uint32_t addr0, uint32_t addr1, 654 uint32_t ref, uint32_t mask, 655 uint32_t inv) 656 { 657 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 658 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) | 659 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) | 660 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 661 if (mem_space) { 662 /* memory */ 663 amdgpu_ring_write(ring, addr0); 664 amdgpu_ring_write(ring, addr1); 665 } else { 666 /* registers */ 667 amdgpu_ring_write(ring, addr0 << 2); 668 amdgpu_ring_write(ring, addr1 << 2); 669 } 670 amdgpu_ring_write(ring, ref); /* reference */ 671 amdgpu_ring_write(ring, mask); /* mask */ 672 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 673 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */ 674 } 675 676 /** 677 * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 678 * 679 * @ring: amdgpu ring pointer 680 * 681 * Emit an hdp flush packet on the requested DMA ring. 682 */ 683 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 684 { 685 struct amdgpu_device *adev = ring->adev; 686 u32 ref_and_mask = 0; 687 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg; 688 689 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; 690 691 sdma_v4_0_wait_reg_mem(ring, 0, 1, 692 adev->nbio_funcs->get_hdp_flush_done_offset(adev), 693 adev->nbio_funcs->get_hdp_flush_req_offset(adev), 694 ref_and_mask, ref_and_mask, 10); 695 } 696 697 /** 698 * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring 699 * 700 * @ring: amdgpu ring pointer 701 * @fence: amdgpu fence object 702 * 703 * Add a DMA fence packet to the ring to write 704 * the fence seq number and DMA trap packet to generate 705 * an interrupt if needed (VEGA10). 706 */ 707 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 708 unsigned flags) 709 { 710 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 711 /* write the fence */ 712 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 713 /* zero in first two bits */ 714 BUG_ON(addr & 0x3); 715 amdgpu_ring_write(ring, lower_32_bits(addr)); 716 amdgpu_ring_write(ring, upper_32_bits(addr)); 717 amdgpu_ring_write(ring, lower_32_bits(seq)); 718 719 /* optionally write high bits as well */ 720 if (write64bit) { 721 addr += 4; 722 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 723 /* zero in first two bits */ 724 BUG_ON(addr & 0x3); 725 amdgpu_ring_write(ring, lower_32_bits(addr)); 726 amdgpu_ring_write(ring, upper_32_bits(addr)); 727 amdgpu_ring_write(ring, upper_32_bits(seq)); 728 } 729 730 /* generate an interrupt */ 731 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 732 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 733 } 734 735 736 /** 737 * sdma_v4_0_gfx_stop - stop the gfx async dma engines 738 * 739 * @adev: amdgpu_device pointer 740 * 741 * Stop the gfx async dma ring buffers (VEGA10). 742 */ 743 static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev) 744 { 745 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; 746 u32 rb_cntl, ib_cntl; 747 int i, unset = 0; 748 749 for (i = 0; i < adev->sdma.num_instances; i++) { 750 sdma[i] = &adev->sdma.instance[i].ring; 751 752 if ((adev->mman.buffer_funcs_ring == sdma[i]) && unset != 1) { 753 amdgpu_ttm_set_buffer_funcs_status(adev, false); 754 unset = 1; 755 } 756 757 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL); 758 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 759 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 760 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL); 761 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 762 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl); 763 764 sdma[i]->sched.ready = false; 765 } 766 } 767 768 /** 769 * sdma_v4_0_rlc_stop - stop the compute async dma engines 770 * 771 * @adev: amdgpu_device pointer 772 * 773 * Stop the compute async dma queues (VEGA10). 774 */ 775 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev) 776 { 777 /* XXX todo */ 778 } 779 780 /** 781 * sdma_v4_0_page_stop - stop the page async dma engines 782 * 783 * @adev: amdgpu_device pointer 784 * 785 * Stop the page async dma ring buffers (VEGA10). 786 */ 787 static void sdma_v4_0_page_stop(struct amdgpu_device *adev) 788 { 789 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; 790 u32 rb_cntl, ib_cntl; 791 int i; 792 bool unset = false; 793 794 for (i = 0; i < adev->sdma.num_instances; i++) { 795 sdma[i] = &adev->sdma.instance[i].page; 796 797 if ((adev->mman.buffer_funcs_ring == sdma[i]) && 798 (unset == false)) { 799 amdgpu_ttm_set_buffer_funcs_status(adev, false); 800 unset = true; 801 } 802 803 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL); 804 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, 805 RB_ENABLE, 0); 806 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 807 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL); 808 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, 809 IB_ENABLE, 0); 810 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl); 811 812 sdma[i]->sched.ready = false; 813 } 814 } 815 816 /** 817 * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch 818 * 819 * @adev: amdgpu_device pointer 820 * @enable: enable/disable the DMA MEs context switch. 821 * 822 * Halt or unhalt the async dma engines context switch (VEGA10). 823 */ 824 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 825 { 826 u32 f32_cntl, phase_quantum = 0; 827 int i; 828 829 if (amdgpu_sdma_phase_quantum) { 830 unsigned value = amdgpu_sdma_phase_quantum; 831 unsigned unit = 0; 832 833 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 834 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 835 value = (value + 1) >> 1; 836 unit++; 837 } 838 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 839 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 840 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 841 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 842 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 843 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 844 WARN_ONCE(1, 845 "clamping sdma_phase_quantum to %uK clock cycles\n", 846 value << unit); 847 } 848 phase_quantum = 849 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 850 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 851 } 852 853 for (i = 0; i < adev->sdma.num_instances; i++) { 854 f32_cntl = RREG32_SDMA(i, mmSDMA0_CNTL); 855 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 856 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 857 if (enable && amdgpu_sdma_phase_quantum) { 858 WREG32_SDMA(i, mmSDMA0_PHASE0_QUANTUM, phase_quantum); 859 WREG32_SDMA(i, mmSDMA0_PHASE1_QUANTUM, phase_quantum); 860 WREG32_SDMA(i, mmSDMA0_PHASE2_QUANTUM, phase_quantum); 861 } 862 WREG32_SDMA(i, mmSDMA0_CNTL, f32_cntl); 863 } 864 865 } 866 867 /** 868 * sdma_v4_0_enable - stop the async dma engines 869 * 870 * @adev: amdgpu_device pointer 871 * @enable: enable/disable the DMA MEs. 872 * 873 * Halt or unhalt the async dma engines (VEGA10). 874 */ 875 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable) 876 { 877 u32 f32_cntl; 878 int i; 879 880 if (enable == false) { 881 sdma_v4_0_gfx_stop(adev); 882 sdma_v4_0_rlc_stop(adev); 883 if (adev->sdma.has_page_queue) 884 sdma_v4_0_page_stop(adev); 885 } 886 887 for (i = 0; i < adev->sdma.num_instances; i++) { 888 f32_cntl = RREG32_SDMA(i, mmSDMA0_F32_CNTL); 889 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 890 WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl); 891 } 892 } 893 894 /** 895 * sdma_v4_0_rb_cntl - get parameters for rb_cntl 896 */ 897 static uint32_t sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl) 898 { 899 /* Set ring buffer size in dwords */ 900 uint32_t rb_bufsz = order_base_2(ring->ring_size / 4); 901 902 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 903 #ifdef __BIG_ENDIAN 904 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 905 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 906 RPTR_WRITEBACK_SWAP_ENABLE, 1); 907 #endif 908 return rb_cntl; 909 } 910 911 /** 912 * sdma_v4_0_gfx_resume - setup and start the async dma engines 913 * 914 * @adev: amdgpu_device pointer 915 * @i: instance to resume 916 * 917 * Set up the gfx DMA ring buffers and enable them (VEGA10). 918 * Returns 0 for success, error for failure. 919 */ 920 static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i) 921 { 922 struct amdgpu_ring *ring = &adev->sdma.instance[i].ring; 923 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 924 u32 wb_offset; 925 u32 doorbell; 926 u32 doorbell_offset; 927 u64 wptr_gpu_addr; 928 929 wb_offset = (ring->rptr_offs * 4); 930 931 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL); 932 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl); 933 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 934 935 /* Initialize the ring buffer's read and write pointers */ 936 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR, 0); 937 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_HI, 0); 938 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR, 0); 939 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_HI, 0); 940 941 /* set the wb address whether it's enabled or not */ 942 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI, 943 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 944 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 945 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 946 947 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 948 RPTR_WRITEBACK_ENABLE, 1); 949 950 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE, ring->gpu_addr >> 8); 951 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE_HI, ring->gpu_addr >> 40); 952 953 ring->wptr = 0; 954 955 /* before programing wptr to a less value, need set minor_ptr_update first */ 956 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 1); 957 958 doorbell = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL); 959 doorbell_offset = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET); 960 961 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 962 ring->use_doorbell); 963 doorbell_offset = REG_SET_FIELD(doorbell_offset, 964 SDMA0_GFX_DOORBELL_OFFSET, 965 OFFSET, ring->doorbell_index); 966 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL, doorbell); 967 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET, doorbell_offset); 968 969 sdma_v4_0_ring_set_wptr(ring); 970 971 /* set minor_ptr_update to 0 after wptr programed */ 972 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 0); 973 974 /* setup the wptr shadow polling */ 975 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 976 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO, 977 lower_32_bits(wptr_gpu_addr)); 978 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI, 979 upper_32_bits(wptr_gpu_addr)); 980 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL); 981 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 982 SDMA0_GFX_RB_WPTR_POLL_CNTL, 983 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 984 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 985 986 /* enable DMA RB */ 987 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 988 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 989 990 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL); 991 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 992 #ifdef __BIG_ENDIAN 993 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 994 #endif 995 /* enable DMA IBs */ 996 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl); 997 998 ring->sched.ready = true; 999 } 1000 1001 /** 1002 * sdma_v4_0_page_resume - setup and start the async dma engines 1003 * 1004 * @adev: amdgpu_device pointer 1005 * @i: instance to resume 1006 * 1007 * Set up the page DMA ring buffers and enable them (VEGA10). 1008 * Returns 0 for success, error for failure. 1009 */ 1010 static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i) 1011 { 1012 struct amdgpu_ring *ring = &adev->sdma.instance[i].page; 1013 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 1014 u32 wb_offset; 1015 u32 doorbell; 1016 u32 doorbell_offset; 1017 u64 wptr_gpu_addr; 1018 1019 wb_offset = (ring->rptr_offs * 4); 1020 1021 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL); 1022 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl); 1023 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 1024 1025 /* Initialize the ring buffer's read and write pointers */ 1026 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR, 0); 1027 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_HI, 0); 1028 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR, 0); 1029 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_HI, 0); 1030 1031 /* set the wb address whether it's enabled or not */ 1032 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_HI, 1033 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 1034 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 1035 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 1036 1037 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, 1038 RPTR_WRITEBACK_ENABLE, 1); 1039 1040 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE, ring->gpu_addr >> 8); 1041 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE_HI, ring->gpu_addr >> 40); 1042 1043 ring->wptr = 0; 1044 1045 /* before programing wptr to a less value, need set minor_ptr_update first */ 1046 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 1); 1047 1048 doorbell = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL); 1049 doorbell_offset = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET); 1050 1051 doorbell = REG_SET_FIELD(doorbell, SDMA0_PAGE_DOORBELL, ENABLE, 1052 ring->use_doorbell); 1053 doorbell_offset = REG_SET_FIELD(doorbell_offset, 1054 SDMA0_PAGE_DOORBELL_OFFSET, 1055 OFFSET, ring->doorbell_index); 1056 WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL, doorbell); 1057 WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET, doorbell_offset); 1058 1059 /* paging queue doorbell range is setup at sdma_v4_0_gfx_resume */ 1060 sdma_v4_0_page_ring_set_wptr(ring); 1061 1062 /* set minor_ptr_update to 0 after wptr programed */ 1063 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 0); 1064 1065 /* setup the wptr shadow polling */ 1066 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1067 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO, 1068 lower_32_bits(wptr_gpu_addr)); 1069 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI, 1070 upper_32_bits(wptr_gpu_addr)); 1071 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL); 1072 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 1073 SDMA0_PAGE_RB_WPTR_POLL_CNTL, 1074 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 1075 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 1076 1077 /* enable DMA RB */ 1078 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, RB_ENABLE, 1); 1079 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 1080 1081 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL); 1082 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_ENABLE, 1); 1083 #ifdef __BIG_ENDIAN 1084 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1); 1085 #endif 1086 /* enable DMA IBs */ 1087 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl); 1088 1089 ring->sched.ready = true; 1090 } 1091 1092 static void 1093 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable) 1094 { 1095 uint32_t def, data; 1096 1097 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) { 1098 /* enable idle interrupt */ 1099 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 1100 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 1101 1102 if (data != def) 1103 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 1104 } else { 1105 /* disable idle interrupt */ 1106 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 1107 data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 1108 if (data != def) 1109 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 1110 } 1111 } 1112 1113 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev) 1114 { 1115 uint32_t def, data; 1116 1117 /* Enable HW based PG. */ 1118 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1119 data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK; 1120 if (data != def) 1121 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1122 1123 /* enable interrupt */ 1124 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 1125 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 1126 if (data != def) 1127 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 1128 1129 /* Configure hold time to filter in-valid power on/off request. Use default right now */ 1130 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1131 data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK; 1132 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK); 1133 /* Configure switch time for hysteresis purpose. Use default right now */ 1134 data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK; 1135 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK); 1136 if(data != def) 1137 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1138 } 1139 1140 static void sdma_v4_0_init_pg(struct amdgpu_device *adev) 1141 { 1142 if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA)) 1143 return; 1144 1145 switch (adev->asic_type) { 1146 case CHIP_RAVEN: 1147 sdma_v4_1_init_power_gating(adev); 1148 sdma_v4_1_update_power_gating(adev, true); 1149 break; 1150 default: 1151 break; 1152 } 1153 } 1154 1155 /** 1156 * sdma_v4_0_rlc_resume - setup and start the async dma engines 1157 * 1158 * @adev: amdgpu_device pointer 1159 * 1160 * Set up the compute DMA queues and enable them (VEGA10). 1161 * Returns 0 for success, error for failure. 1162 */ 1163 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev) 1164 { 1165 sdma_v4_0_init_pg(adev); 1166 1167 return 0; 1168 } 1169 1170 /** 1171 * sdma_v4_0_load_microcode - load the sDMA ME ucode 1172 * 1173 * @adev: amdgpu_device pointer 1174 * 1175 * Loads the sDMA0/1 ucode. 1176 * Returns 0 for success, -EINVAL if the ucode is not available. 1177 */ 1178 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev) 1179 { 1180 const struct sdma_firmware_header_v1_0 *hdr; 1181 const __le32 *fw_data; 1182 u32 fw_size; 1183 int i, j; 1184 1185 /* halt the MEs */ 1186 sdma_v4_0_enable(adev, false); 1187 1188 for (i = 0; i < adev->sdma.num_instances; i++) { 1189 if (!adev->sdma.instance[i].fw) 1190 return -EINVAL; 1191 1192 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 1193 amdgpu_ucode_print_sdma_hdr(&hdr->header); 1194 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1195 1196 fw_data = (const __le32 *) 1197 (adev->sdma.instance[i].fw->data + 1198 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1199 1200 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 0); 1201 1202 for (j = 0; j < fw_size; j++) 1203 WREG32_SDMA(i, mmSDMA0_UCODE_DATA, 1204 le32_to_cpup(fw_data++)); 1205 1206 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 1207 adev->sdma.instance[i].fw_version); 1208 } 1209 1210 return 0; 1211 } 1212 1213 /** 1214 * sdma_v4_0_start - setup and start the async dma engines 1215 * 1216 * @adev: amdgpu_device pointer 1217 * 1218 * Set up the DMA engines and enable them (VEGA10). 1219 * Returns 0 for success, error for failure. 1220 */ 1221 static int sdma_v4_0_start(struct amdgpu_device *adev) 1222 { 1223 struct amdgpu_ring *ring; 1224 int i, r = 0; 1225 1226 if (amdgpu_sriov_vf(adev)) { 1227 sdma_v4_0_ctx_switch_enable(adev, false); 1228 sdma_v4_0_enable(adev, false); 1229 } else { 1230 1231 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1232 r = sdma_v4_0_load_microcode(adev); 1233 if (r) 1234 return r; 1235 } 1236 1237 /* unhalt the MEs */ 1238 sdma_v4_0_enable(adev, true); 1239 /* enable sdma ring preemption */ 1240 sdma_v4_0_ctx_switch_enable(adev, true); 1241 } 1242 1243 /* start the gfx rings and rlc compute queues */ 1244 for (i = 0; i < adev->sdma.num_instances; i++) { 1245 uint32_t temp; 1246 1247 WREG32_SDMA(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL, 0); 1248 sdma_v4_0_gfx_resume(adev, i); 1249 if (adev->sdma.has_page_queue) 1250 sdma_v4_0_page_resume(adev, i); 1251 1252 /* set utc l1 enable flag always to 1 */ 1253 temp = RREG32_SDMA(i, mmSDMA0_CNTL); 1254 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 1255 WREG32_SDMA(i, mmSDMA0_CNTL, temp); 1256 1257 if (!amdgpu_sriov_vf(adev)) { 1258 /* unhalt engine */ 1259 temp = RREG32_SDMA(i, mmSDMA0_F32_CNTL); 1260 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 1261 WREG32_SDMA(i, mmSDMA0_F32_CNTL, temp); 1262 } 1263 } 1264 1265 if (amdgpu_sriov_vf(adev)) { 1266 sdma_v4_0_ctx_switch_enable(adev, true); 1267 sdma_v4_0_enable(adev, true); 1268 } else { 1269 r = sdma_v4_0_rlc_resume(adev); 1270 if (r) 1271 return r; 1272 } 1273 1274 for (i = 0; i < adev->sdma.num_instances; i++) { 1275 ring = &adev->sdma.instance[i].ring; 1276 1277 r = amdgpu_ring_test_helper(ring); 1278 if (r) 1279 return r; 1280 1281 if (adev->sdma.has_page_queue) { 1282 struct amdgpu_ring *page = &adev->sdma.instance[i].page; 1283 1284 r = amdgpu_ring_test_helper(page); 1285 if (r) 1286 return r; 1287 1288 if (adev->mman.buffer_funcs_ring == page) 1289 amdgpu_ttm_set_buffer_funcs_status(adev, true); 1290 } 1291 1292 if (adev->mman.buffer_funcs_ring == ring) 1293 amdgpu_ttm_set_buffer_funcs_status(adev, true); 1294 } 1295 1296 return r; 1297 } 1298 1299 /** 1300 * sdma_v4_0_ring_test_ring - simple async dma engine test 1301 * 1302 * @ring: amdgpu_ring structure holding ring information 1303 * 1304 * Test the DMA engine by writing using it to write an 1305 * value to memory. (VEGA10). 1306 * Returns 0 for success, error for failure. 1307 */ 1308 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring) 1309 { 1310 struct amdgpu_device *adev = ring->adev; 1311 unsigned i; 1312 unsigned index; 1313 int r; 1314 u32 tmp; 1315 u64 gpu_addr; 1316 1317 r = amdgpu_device_wb_get(adev, &index); 1318 if (r) 1319 return r; 1320 1321 gpu_addr = adev->wb.gpu_addr + (index * 4); 1322 tmp = 0xCAFEDEAD; 1323 adev->wb.wb[index] = cpu_to_le32(tmp); 1324 1325 r = amdgpu_ring_alloc(ring, 5); 1326 if (r) 1327 goto error_free_wb; 1328 1329 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1330 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 1331 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 1332 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 1333 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 1334 amdgpu_ring_write(ring, 0xDEADBEEF); 1335 amdgpu_ring_commit(ring); 1336 1337 for (i = 0; i < adev->usec_timeout; i++) { 1338 tmp = le32_to_cpu(adev->wb.wb[index]); 1339 if (tmp == 0xDEADBEEF) 1340 break; 1341 udelay(1); 1342 } 1343 1344 if (i >= adev->usec_timeout) 1345 r = -ETIMEDOUT; 1346 1347 error_free_wb: 1348 amdgpu_device_wb_free(adev, index); 1349 return r; 1350 } 1351 1352 /** 1353 * sdma_v4_0_ring_test_ib - test an IB on the DMA engine 1354 * 1355 * @ring: amdgpu_ring structure holding ring information 1356 * 1357 * Test a simple IB in the DMA ring (VEGA10). 1358 * Returns 0 on success, error on failure. 1359 */ 1360 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1361 { 1362 struct amdgpu_device *adev = ring->adev; 1363 struct amdgpu_ib ib; 1364 struct dma_fence *f = NULL; 1365 unsigned index; 1366 long r; 1367 u32 tmp = 0; 1368 u64 gpu_addr; 1369 1370 r = amdgpu_device_wb_get(adev, &index); 1371 if (r) 1372 return r; 1373 1374 gpu_addr = adev->wb.gpu_addr + (index * 4); 1375 tmp = 0xCAFEDEAD; 1376 adev->wb.wb[index] = cpu_to_le32(tmp); 1377 memset(&ib, 0, sizeof(ib)); 1378 r = amdgpu_ib_get(adev, NULL, 256, &ib); 1379 if (r) 1380 goto err0; 1381 1382 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1383 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1384 ib.ptr[1] = lower_32_bits(gpu_addr); 1385 ib.ptr[2] = upper_32_bits(gpu_addr); 1386 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1387 ib.ptr[4] = 0xDEADBEEF; 1388 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1389 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1390 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1391 ib.length_dw = 8; 1392 1393 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1394 if (r) 1395 goto err1; 1396 1397 r = dma_fence_wait_timeout(f, false, timeout); 1398 if (r == 0) { 1399 r = -ETIMEDOUT; 1400 goto err1; 1401 } else if (r < 0) { 1402 goto err1; 1403 } 1404 tmp = le32_to_cpu(adev->wb.wb[index]); 1405 if (tmp == 0xDEADBEEF) 1406 r = 0; 1407 else 1408 r = -EINVAL; 1409 1410 err1: 1411 amdgpu_ib_free(adev, &ib, NULL); 1412 dma_fence_put(f); 1413 err0: 1414 amdgpu_device_wb_free(adev, index); 1415 return r; 1416 } 1417 1418 1419 /** 1420 * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART 1421 * 1422 * @ib: indirect buffer to fill with commands 1423 * @pe: addr of the page entry 1424 * @src: src addr to copy from 1425 * @count: number of page entries to update 1426 * 1427 * Update PTEs by copying them from the GART using sDMA (VEGA10). 1428 */ 1429 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib, 1430 uint64_t pe, uint64_t src, 1431 unsigned count) 1432 { 1433 unsigned bytes = count * 8; 1434 1435 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1436 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1437 ib->ptr[ib->length_dw++] = bytes - 1; 1438 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1439 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1440 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1441 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1442 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1443 1444 } 1445 1446 /** 1447 * sdma_v4_0_vm_write_pte - update PTEs by writing them manually 1448 * 1449 * @ib: indirect buffer to fill with commands 1450 * @pe: addr of the page entry 1451 * @addr: dst addr to write into pe 1452 * @count: number of page entries to update 1453 * @incr: increase next addr by incr bytes 1454 * @flags: access flags 1455 * 1456 * Update PTEs by writing them manually using sDMA (VEGA10). 1457 */ 1458 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1459 uint64_t value, unsigned count, 1460 uint32_t incr) 1461 { 1462 unsigned ndw = count * 2; 1463 1464 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1465 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1466 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1467 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1468 ib->ptr[ib->length_dw++] = ndw - 1; 1469 for (; ndw > 0; ndw -= 2) { 1470 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1471 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1472 value += incr; 1473 } 1474 } 1475 1476 /** 1477 * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA 1478 * 1479 * @ib: indirect buffer to fill with commands 1480 * @pe: addr of the page entry 1481 * @addr: dst addr to write into pe 1482 * @count: number of page entries to update 1483 * @incr: increase next addr by incr bytes 1484 * @flags: access flags 1485 * 1486 * Update the page tables using sDMA (VEGA10). 1487 */ 1488 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1489 uint64_t pe, 1490 uint64_t addr, unsigned count, 1491 uint32_t incr, uint64_t flags) 1492 { 1493 /* for physically contiguous pages (vram) */ 1494 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1495 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1496 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1497 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1498 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1499 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1500 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1501 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1502 ib->ptr[ib->length_dw++] = 0; 1503 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1504 } 1505 1506 /** 1507 * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw 1508 * 1509 * @ib: indirect buffer to fill with padding 1510 * 1511 */ 1512 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1513 { 1514 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1515 u32 pad_count; 1516 int i; 1517 1518 pad_count = (8 - (ib->length_dw & 0x7)) % 8; 1519 for (i = 0; i < pad_count; i++) 1520 if (sdma && sdma->burst_nop && (i == 0)) 1521 ib->ptr[ib->length_dw++] = 1522 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1523 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1524 else 1525 ib->ptr[ib->length_dw++] = 1526 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1527 } 1528 1529 1530 /** 1531 * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline 1532 * 1533 * @ring: amdgpu_ring pointer 1534 * 1535 * Make sure all previous operations are completed (CIK). 1536 */ 1537 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1538 { 1539 uint32_t seq = ring->fence_drv.sync_seq; 1540 uint64_t addr = ring->fence_drv.gpu_addr; 1541 1542 /* wait for idle */ 1543 sdma_v4_0_wait_reg_mem(ring, 1, 0, 1544 addr & 0xfffffffc, 1545 upper_32_bits(addr) & 0xffffffff, 1546 seq, 0xffffffff, 4); 1547 } 1548 1549 1550 /** 1551 * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA 1552 * 1553 * @ring: amdgpu_ring pointer 1554 * @vm: amdgpu_vm pointer 1555 * 1556 * Update the page table base and flush the VM TLB 1557 * using sDMA (VEGA10). 1558 */ 1559 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1560 unsigned vmid, uint64_t pd_addr) 1561 { 1562 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1563 } 1564 1565 static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring, 1566 uint32_t reg, uint32_t val) 1567 { 1568 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1569 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1570 amdgpu_ring_write(ring, reg); 1571 amdgpu_ring_write(ring, val); 1572 } 1573 1574 static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1575 uint32_t val, uint32_t mask) 1576 { 1577 sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10); 1578 } 1579 1580 static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev) 1581 { 1582 uint fw_version = adev->sdma.instance[0].fw_version; 1583 1584 switch (adev->asic_type) { 1585 case CHIP_VEGA10: 1586 return fw_version >= 430; 1587 case CHIP_VEGA12: 1588 /*return fw_version >= 31;*/ 1589 return false; 1590 case CHIP_VEGA20: 1591 return fw_version >= 123; 1592 default: 1593 return false; 1594 } 1595 } 1596 1597 static int sdma_v4_0_early_init(void *handle) 1598 { 1599 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1600 int r; 1601 1602 if (adev->asic_type == CHIP_RAVEN) 1603 adev->sdma.num_instances = 1; 1604 else if (adev->asic_type == CHIP_ARCTURUS) 1605 adev->sdma.num_instances = 8; 1606 else 1607 adev->sdma.num_instances = 2; 1608 1609 r = sdma_v4_0_init_microcode(adev); 1610 if (r) { 1611 DRM_ERROR("Failed to load sdma firmware!\n"); 1612 return r; 1613 } 1614 1615 /* TODO: Page queue breaks driver reload under SRIOV */ 1616 if ((adev->asic_type == CHIP_VEGA10) && amdgpu_sriov_vf((adev))) 1617 adev->sdma.has_page_queue = false; 1618 else if (sdma_v4_0_fw_support_paging_queue(adev)) 1619 adev->sdma.has_page_queue = true; 1620 1621 sdma_v4_0_set_ring_funcs(adev); 1622 sdma_v4_0_set_buffer_funcs(adev); 1623 sdma_v4_0_set_vm_pte_funcs(adev); 1624 sdma_v4_0_set_irq_funcs(adev); 1625 1626 return 0; 1627 } 1628 1629 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev, 1630 struct amdgpu_iv_entry *entry); 1631 1632 static int sdma_v4_0_late_init(void *handle) 1633 { 1634 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1635 struct ras_common_if **ras_if = &adev->sdma.ras_if; 1636 struct ras_ih_if ih_info = { 1637 .cb = sdma_v4_0_process_ras_data_cb, 1638 }; 1639 struct ras_fs_if fs_info = { 1640 .sysfs_name = "sdma_err_count", 1641 .debugfs_name = "sdma_err_inject", 1642 }; 1643 struct ras_common_if ras_block = { 1644 .block = AMDGPU_RAS_BLOCK__SDMA, 1645 .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 1646 .sub_block_index = 0, 1647 .name = "sdma", 1648 }; 1649 int r, i; 1650 1651 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 1652 amdgpu_ras_feature_enable_on_boot(adev, &ras_block, 0); 1653 return 0; 1654 } 1655 1656 /* handle resume path. */ 1657 if (*ras_if) { 1658 /* resend ras TA enable cmd during resume. 1659 * prepare to handle failure. 1660 */ 1661 ih_info.head = **ras_if; 1662 r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1); 1663 if (r) { 1664 if (r == -EAGAIN) { 1665 /* request a gpu reset. will run again. */ 1666 amdgpu_ras_request_reset_on_boot(adev, 1667 AMDGPU_RAS_BLOCK__SDMA); 1668 return 0; 1669 } 1670 /* fail to enable ras, cleanup all. */ 1671 goto irq; 1672 } 1673 /* enable successfully. continue. */ 1674 goto resume; 1675 } 1676 1677 *ras_if = kmalloc(sizeof(**ras_if), GFP_KERNEL); 1678 if (!*ras_if) 1679 return -ENOMEM; 1680 1681 **ras_if = ras_block; 1682 1683 r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1); 1684 if (r) { 1685 if (r == -EAGAIN) { 1686 amdgpu_ras_request_reset_on_boot(adev, 1687 AMDGPU_RAS_BLOCK__SDMA); 1688 r = 0; 1689 } 1690 goto feature; 1691 } 1692 1693 ih_info.head = **ras_if; 1694 fs_info.head = **ras_if; 1695 1696 r = amdgpu_ras_interrupt_add_handler(adev, &ih_info); 1697 if (r) 1698 goto interrupt; 1699 1700 amdgpu_ras_debugfs_create(adev, &fs_info); 1701 1702 r = amdgpu_ras_sysfs_create(adev, &fs_info); 1703 if (r) 1704 goto sysfs; 1705 resume: 1706 for (i = 0; i < adev->sdma.num_instances; i++) { 1707 r = amdgpu_irq_get(adev, &adev->sdma.ecc_irq, 1708 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 1709 if (r) 1710 goto irq; 1711 } 1712 1713 return 0; 1714 irq: 1715 amdgpu_ras_sysfs_remove(adev, *ras_if); 1716 sysfs: 1717 amdgpu_ras_debugfs_remove(adev, *ras_if); 1718 amdgpu_ras_interrupt_remove_handler(adev, &ih_info); 1719 interrupt: 1720 amdgpu_ras_feature_enable(adev, *ras_if, 0); 1721 feature: 1722 kfree(*ras_if); 1723 *ras_if = NULL; 1724 return r; 1725 } 1726 1727 static int sdma_v4_0_sw_init(void *handle) 1728 { 1729 struct amdgpu_ring *ring; 1730 int r, i; 1731 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1732 1733 /* SDMA trap event */ 1734 for (i = 0; i < adev->sdma.num_instances; i++) { 1735 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1736 SDMA0_4_0__SRCID__SDMA_TRAP, 1737 &adev->sdma.trap_irq); 1738 if (r) 1739 return r; 1740 } 1741 1742 /* SDMA SRAM ECC event */ 1743 for (i = 0; i < adev->sdma.num_instances; i++) { 1744 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1745 SDMA0_4_0__SRCID__SDMA_SRAM_ECC, 1746 &adev->sdma.ecc_irq); 1747 if (r) 1748 return r; 1749 } 1750 1751 for (i = 0; i < adev->sdma.num_instances; i++) { 1752 ring = &adev->sdma.instance[i].ring; 1753 ring->ring_obj = NULL; 1754 ring->use_doorbell = true; 1755 1756 DRM_INFO("use_doorbell being set to: [%s]\n", 1757 ring->use_doorbell?"true":"false"); 1758 1759 /* doorbell size is 2 dwords, get DWORD offset */ 1760 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1; 1761 1762 sprintf(ring->name, "sdma%d", i); 1763 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1764 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 1765 if (r) 1766 return r; 1767 1768 if (adev->sdma.has_page_queue) { 1769 ring = &adev->sdma.instance[i].page; 1770 ring->ring_obj = NULL; 1771 ring->use_doorbell = true; 1772 1773 /* paging queue use same doorbell index/routing as gfx queue 1774 * with 0x400 (4096 dwords) offset on second doorbell page 1775 */ 1776 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1; 1777 ring->doorbell_index += 0x400; 1778 1779 sprintf(ring->name, "page%d", i); 1780 r = amdgpu_ring_init(adev, ring, 1024, 1781 &adev->sdma.trap_irq, 1782 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 1783 if (r) 1784 return r; 1785 } 1786 } 1787 1788 return r; 1789 } 1790 1791 static int sdma_v4_0_sw_fini(void *handle) 1792 { 1793 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1794 int i; 1795 1796 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA) && 1797 adev->sdma.ras_if) { 1798 struct ras_common_if *ras_if = adev->sdma.ras_if; 1799 struct ras_ih_if ih_info = { 1800 .head = *ras_if, 1801 }; 1802 1803 /*remove fs first*/ 1804 amdgpu_ras_debugfs_remove(adev, ras_if); 1805 amdgpu_ras_sysfs_remove(adev, ras_if); 1806 /*remove the IH*/ 1807 amdgpu_ras_interrupt_remove_handler(adev, &ih_info); 1808 amdgpu_ras_feature_enable(adev, ras_if, 0); 1809 kfree(ras_if); 1810 } 1811 1812 for (i = 0; i < adev->sdma.num_instances; i++) { 1813 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1814 if (adev->sdma.has_page_queue) 1815 amdgpu_ring_fini(&adev->sdma.instance[i].page); 1816 } 1817 1818 for (i = 0; i < adev->sdma.num_instances; i++) { 1819 release_firmware(adev->sdma.instance[i].fw); 1820 adev->sdma.instance[i].fw = NULL; 1821 } 1822 1823 return 0; 1824 } 1825 1826 static int sdma_v4_0_hw_init(void *handle) 1827 { 1828 int r; 1829 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1830 1831 if (adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs && 1832 adev->powerplay.pp_funcs->set_powergating_by_smu) 1833 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false); 1834 1835 sdma_v4_0_init_golden_registers(adev); 1836 1837 r = sdma_v4_0_start(adev); 1838 1839 return r; 1840 } 1841 1842 static int sdma_v4_0_hw_fini(void *handle) 1843 { 1844 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1845 int i; 1846 1847 if (amdgpu_sriov_vf(adev)) 1848 return 0; 1849 1850 for (i = 0; i < adev->sdma.num_instances; i++) { 1851 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, 1852 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 1853 } 1854 1855 sdma_v4_0_ctx_switch_enable(adev, false); 1856 sdma_v4_0_enable(adev, false); 1857 1858 if (adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs 1859 && adev->powerplay.pp_funcs->set_powergating_by_smu) 1860 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true); 1861 1862 return 0; 1863 } 1864 1865 static int sdma_v4_0_suspend(void *handle) 1866 { 1867 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1868 1869 return sdma_v4_0_hw_fini(adev); 1870 } 1871 1872 static int sdma_v4_0_resume(void *handle) 1873 { 1874 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1875 1876 return sdma_v4_0_hw_init(adev); 1877 } 1878 1879 static bool sdma_v4_0_is_idle(void *handle) 1880 { 1881 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1882 u32 i; 1883 1884 for (i = 0; i < adev->sdma.num_instances; i++) { 1885 u32 tmp = RREG32_SDMA(i, mmSDMA0_STATUS_REG); 1886 1887 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1888 return false; 1889 } 1890 1891 return true; 1892 } 1893 1894 static int sdma_v4_0_wait_for_idle(void *handle) 1895 { 1896 unsigned i, j; 1897 u32 sdma[AMDGPU_MAX_SDMA_INSTANCES]; 1898 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1899 1900 for (i = 0; i < adev->usec_timeout; i++) { 1901 for (j = 0; j < adev->sdma.num_instances; j++) { 1902 sdma[j] = RREG32_SDMA(j, mmSDMA0_STATUS_REG); 1903 if (!(sdma[j] & SDMA0_STATUS_REG__IDLE_MASK)) 1904 break; 1905 } 1906 if (j == adev->sdma.num_instances) 1907 return 0; 1908 udelay(1); 1909 } 1910 return -ETIMEDOUT; 1911 } 1912 1913 static int sdma_v4_0_soft_reset(void *handle) 1914 { 1915 /* todo */ 1916 1917 return 0; 1918 } 1919 1920 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev, 1921 struct amdgpu_irq_src *source, 1922 unsigned type, 1923 enum amdgpu_interrupt_state state) 1924 { 1925 u32 sdma_cntl; 1926 1927 sdma_cntl = RREG32_SDMA(type, mmSDMA0_CNTL); 1928 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1929 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1930 WREG32_SDMA(type, mmSDMA0_CNTL, sdma_cntl); 1931 1932 return 0; 1933 } 1934 1935 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev, 1936 struct amdgpu_irq_src *source, 1937 struct amdgpu_iv_entry *entry) 1938 { 1939 uint32_t instance; 1940 1941 DRM_DEBUG("IH: SDMA trap\n"); 1942 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 1943 switch (entry->ring_id) { 1944 case 0: 1945 amdgpu_fence_process(&adev->sdma.instance[instance].ring); 1946 break; 1947 case 1: 1948 if (adev->asic_type == CHIP_VEGA20) 1949 amdgpu_fence_process(&adev->sdma.instance[instance].page); 1950 break; 1951 case 2: 1952 /* XXX compute */ 1953 break; 1954 case 3: 1955 if (adev->asic_type != CHIP_VEGA20) 1956 amdgpu_fence_process(&adev->sdma.instance[instance].page); 1957 break; 1958 } 1959 return 0; 1960 } 1961 1962 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev, 1963 struct amdgpu_iv_entry *entry) 1964 { 1965 uint32_t instance, err_source; 1966 1967 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 1968 if (instance < 0) 1969 return 0; 1970 1971 switch (entry->src_id) { 1972 case SDMA0_4_0__SRCID__SDMA_SRAM_ECC: 1973 err_source = 0; 1974 break; 1975 case SDMA0_4_0__SRCID__SDMA_ECC: 1976 err_source = 1; 1977 break; 1978 default: 1979 return 0; 1980 } 1981 1982 kgd2kfd_set_sram_ecc_flag(adev->kfd.dev); 1983 1984 amdgpu_ras_reset_gpu(adev, 0); 1985 1986 return AMDGPU_RAS_UE; 1987 } 1988 1989 static int sdma_v4_0_process_ecc_irq(struct amdgpu_device *adev, 1990 struct amdgpu_irq_src *source, 1991 struct amdgpu_iv_entry *entry) 1992 { 1993 struct ras_common_if *ras_if = adev->sdma.ras_if; 1994 struct ras_dispatch_if ih_data = { 1995 .entry = entry, 1996 }; 1997 1998 if (!ras_if) 1999 return 0; 2000 2001 ih_data.head = *ras_if; 2002 2003 amdgpu_ras_interrupt_dispatch(adev, &ih_data); 2004 return 0; 2005 } 2006 2007 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev, 2008 struct amdgpu_irq_src *source, 2009 struct amdgpu_iv_entry *entry) 2010 { 2011 int instance; 2012 2013 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 2014 2015 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 2016 if (instance < 0) 2017 return 0; 2018 2019 switch (entry->ring_id) { 2020 case 0: 2021 drm_sched_fault(&adev->sdma.instance[instance].ring.sched); 2022 break; 2023 } 2024 return 0; 2025 } 2026 2027 static int sdma_v4_0_set_ecc_irq_state(struct amdgpu_device *adev, 2028 struct amdgpu_irq_src *source, 2029 unsigned type, 2030 enum amdgpu_interrupt_state state) 2031 { 2032 u32 sdma_edc_config; 2033 2034 sdma_edc_config = RREG32_SDMA(type, mmSDMA0_EDC_CONFIG); 2035 sdma_edc_config = REG_SET_FIELD(sdma_edc_config, SDMA0_EDC_CONFIG, ECC_INT_ENABLE, 2036 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2037 WREG32_SDMA(type, mmSDMA0_EDC_CONFIG, sdma_edc_config); 2038 2039 return 0; 2040 } 2041 2042 static void sdma_v4_0_update_medium_grain_clock_gating( 2043 struct amdgpu_device *adev, 2044 bool enable) 2045 { 2046 uint32_t data, def; 2047 2048 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 2049 /* enable sdma0 clock gating */ 2050 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 2051 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 2052 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 2053 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 2054 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 2055 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 2056 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 2057 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 2058 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 2059 if (def != data) 2060 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data); 2061 2062 if (adev->sdma.num_instances > 1) { 2063 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL)); 2064 data &= ~(SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK | 2065 SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK | 2066 SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK | 2067 SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK | 2068 SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK | 2069 SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK | 2070 SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK | 2071 SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK); 2072 if (def != data) 2073 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data); 2074 } 2075 } else { 2076 /* disable sdma0 clock gating */ 2077 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 2078 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 2079 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 2080 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 2081 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 2082 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 2083 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 2084 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 2085 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 2086 2087 if (def != data) 2088 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data); 2089 2090 if (adev->sdma.num_instances > 1) { 2091 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL)); 2092 data |= (SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK | 2093 SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK | 2094 SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK | 2095 SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK | 2096 SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK | 2097 SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK | 2098 SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK | 2099 SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK); 2100 if (def != data) 2101 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data); 2102 } 2103 } 2104 } 2105 2106 2107 static void sdma_v4_0_update_medium_grain_light_sleep( 2108 struct amdgpu_device *adev, 2109 bool enable) 2110 { 2111 uint32_t data, def; 2112 2113 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 2114 /* 1-not override: enable sdma0 mem light sleep */ 2115 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 2116 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 2117 if (def != data) 2118 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 2119 2120 /* 1-not override: enable sdma1 mem light sleep */ 2121 if (adev->sdma.num_instances > 1) { 2122 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL)); 2123 data |= SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 2124 if (def != data) 2125 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data); 2126 } 2127 } else { 2128 /* 0-override:disable sdma0 mem light sleep */ 2129 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 2130 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 2131 if (def != data) 2132 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 2133 2134 /* 0-override:disable sdma1 mem light sleep */ 2135 if (adev->sdma.num_instances > 1) { 2136 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL)); 2137 data &= ~SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 2138 if (def != data) 2139 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data); 2140 } 2141 } 2142 } 2143 2144 static int sdma_v4_0_set_clockgating_state(void *handle, 2145 enum amd_clockgating_state state) 2146 { 2147 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2148 2149 if (amdgpu_sriov_vf(adev)) 2150 return 0; 2151 2152 switch (adev->asic_type) { 2153 case CHIP_VEGA10: 2154 case CHIP_VEGA12: 2155 case CHIP_VEGA20: 2156 case CHIP_RAVEN: 2157 sdma_v4_0_update_medium_grain_clock_gating(adev, 2158 state == AMD_CG_STATE_GATE ? true : false); 2159 sdma_v4_0_update_medium_grain_light_sleep(adev, 2160 state == AMD_CG_STATE_GATE ? true : false); 2161 break; 2162 default: 2163 break; 2164 } 2165 return 0; 2166 } 2167 2168 static int sdma_v4_0_set_powergating_state(void *handle, 2169 enum amd_powergating_state state) 2170 { 2171 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2172 2173 switch (adev->asic_type) { 2174 case CHIP_RAVEN: 2175 sdma_v4_1_update_power_gating(adev, 2176 state == AMD_PG_STATE_GATE ? true : false); 2177 break; 2178 default: 2179 break; 2180 } 2181 2182 return 0; 2183 } 2184 2185 static void sdma_v4_0_get_clockgating_state(void *handle, u32 *flags) 2186 { 2187 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2188 int data; 2189 2190 if (amdgpu_sriov_vf(adev)) 2191 *flags = 0; 2192 2193 /* AMD_CG_SUPPORT_SDMA_MGCG */ 2194 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 2195 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK)) 2196 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 2197 2198 /* AMD_CG_SUPPORT_SDMA_LS */ 2199 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 2200 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 2201 *flags |= AMD_CG_SUPPORT_SDMA_LS; 2202 } 2203 2204 const struct amd_ip_funcs sdma_v4_0_ip_funcs = { 2205 .name = "sdma_v4_0", 2206 .early_init = sdma_v4_0_early_init, 2207 .late_init = sdma_v4_0_late_init, 2208 .sw_init = sdma_v4_0_sw_init, 2209 .sw_fini = sdma_v4_0_sw_fini, 2210 .hw_init = sdma_v4_0_hw_init, 2211 .hw_fini = sdma_v4_0_hw_fini, 2212 .suspend = sdma_v4_0_suspend, 2213 .resume = sdma_v4_0_resume, 2214 .is_idle = sdma_v4_0_is_idle, 2215 .wait_for_idle = sdma_v4_0_wait_for_idle, 2216 .soft_reset = sdma_v4_0_soft_reset, 2217 .set_clockgating_state = sdma_v4_0_set_clockgating_state, 2218 .set_powergating_state = sdma_v4_0_set_powergating_state, 2219 .get_clockgating_state = sdma_v4_0_get_clockgating_state, 2220 }; 2221 2222 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = { 2223 .type = AMDGPU_RING_TYPE_SDMA, 2224 .align_mask = 0xf, 2225 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2226 .support_64bit_ptrs = true, 2227 .vmhub = AMDGPU_MMHUB_0, 2228 .get_rptr = sdma_v4_0_ring_get_rptr, 2229 .get_wptr = sdma_v4_0_ring_get_wptr, 2230 .set_wptr = sdma_v4_0_ring_set_wptr, 2231 .emit_frame_size = 2232 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2233 3 + /* hdp invalidate */ 2234 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2235 /* sdma_v4_0_ring_emit_vm_flush */ 2236 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2237 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2238 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2239 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2240 .emit_ib = sdma_v4_0_ring_emit_ib, 2241 .emit_fence = sdma_v4_0_ring_emit_fence, 2242 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2243 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2244 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2245 .test_ring = sdma_v4_0_ring_test_ring, 2246 .test_ib = sdma_v4_0_ring_test_ib, 2247 .insert_nop = sdma_v4_0_ring_insert_nop, 2248 .pad_ib = sdma_v4_0_ring_pad_ib, 2249 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2250 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2251 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2252 }; 2253 2254 /* 2255 * On Arcturus, SDMA instance 5~7 has a different vmhub type(AMDGPU_MMHUB_1). 2256 * So create a individual constant ring_funcs for those instances. 2257 */ 2258 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs_2nd_mmhub = { 2259 .type = AMDGPU_RING_TYPE_SDMA, 2260 .align_mask = 0xf, 2261 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2262 .support_64bit_ptrs = true, 2263 .vmhub = AMDGPU_MMHUB_1, 2264 .get_rptr = sdma_v4_0_ring_get_rptr, 2265 .get_wptr = sdma_v4_0_ring_get_wptr, 2266 .set_wptr = sdma_v4_0_ring_set_wptr, 2267 .emit_frame_size = 2268 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2269 3 + /* hdp invalidate */ 2270 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2271 /* sdma_v4_0_ring_emit_vm_flush */ 2272 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2273 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2274 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2275 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2276 .emit_ib = sdma_v4_0_ring_emit_ib, 2277 .emit_fence = sdma_v4_0_ring_emit_fence, 2278 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2279 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2280 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2281 .test_ring = sdma_v4_0_ring_test_ring, 2282 .test_ib = sdma_v4_0_ring_test_ib, 2283 .insert_nop = sdma_v4_0_ring_insert_nop, 2284 .pad_ib = sdma_v4_0_ring_pad_ib, 2285 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2286 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2287 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2288 }; 2289 2290 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = { 2291 .type = AMDGPU_RING_TYPE_SDMA, 2292 .align_mask = 0xf, 2293 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2294 .support_64bit_ptrs = true, 2295 .vmhub = AMDGPU_MMHUB_0, 2296 .get_rptr = sdma_v4_0_ring_get_rptr, 2297 .get_wptr = sdma_v4_0_page_ring_get_wptr, 2298 .set_wptr = sdma_v4_0_page_ring_set_wptr, 2299 .emit_frame_size = 2300 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2301 3 + /* hdp invalidate */ 2302 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2303 /* sdma_v4_0_ring_emit_vm_flush */ 2304 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2305 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2306 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2307 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2308 .emit_ib = sdma_v4_0_ring_emit_ib, 2309 .emit_fence = sdma_v4_0_ring_emit_fence, 2310 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2311 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2312 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2313 .test_ring = sdma_v4_0_ring_test_ring, 2314 .test_ib = sdma_v4_0_ring_test_ib, 2315 .insert_nop = sdma_v4_0_ring_insert_nop, 2316 .pad_ib = sdma_v4_0_ring_pad_ib, 2317 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2318 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2319 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2320 }; 2321 2322 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs_2nd_mmhub = { 2323 .type = AMDGPU_RING_TYPE_SDMA, 2324 .align_mask = 0xf, 2325 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2326 .support_64bit_ptrs = true, 2327 .vmhub = AMDGPU_MMHUB_1, 2328 .get_rptr = sdma_v4_0_ring_get_rptr, 2329 .get_wptr = sdma_v4_0_page_ring_get_wptr, 2330 .set_wptr = sdma_v4_0_page_ring_set_wptr, 2331 .emit_frame_size = 2332 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2333 3 + /* hdp invalidate */ 2334 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2335 /* sdma_v4_0_ring_emit_vm_flush */ 2336 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2337 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2338 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2339 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2340 .emit_ib = sdma_v4_0_ring_emit_ib, 2341 .emit_fence = sdma_v4_0_ring_emit_fence, 2342 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2343 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2344 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2345 .test_ring = sdma_v4_0_ring_test_ring, 2346 .test_ib = sdma_v4_0_ring_test_ib, 2347 .insert_nop = sdma_v4_0_ring_insert_nop, 2348 .pad_ib = sdma_v4_0_ring_pad_ib, 2349 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2350 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2351 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2352 }; 2353 2354 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev) 2355 { 2356 int i; 2357 2358 for (i = 0; i < adev->sdma.num_instances; i++) { 2359 if (adev->asic_type == CHIP_ARCTURUS && i >= 5) 2360 adev->sdma.instance[i].ring.funcs = 2361 &sdma_v4_0_ring_funcs_2nd_mmhub; 2362 else 2363 adev->sdma.instance[i].ring.funcs = 2364 &sdma_v4_0_ring_funcs; 2365 adev->sdma.instance[i].ring.me = i; 2366 if (adev->sdma.has_page_queue) { 2367 if (adev->asic_type == CHIP_ARCTURUS && i >= 5) 2368 adev->sdma.instance[i].page.funcs = 2369 &sdma_v4_0_page_ring_funcs_2nd_mmhub; 2370 else 2371 adev->sdma.instance[i].page.funcs = 2372 &sdma_v4_0_page_ring_funcs; 2373 adev->sdma.instance[i].page.me = i; 2374 } 2375 } 2376 } 2377 2378 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = { 2379 .set = sdma_v4_0_set_trap_irq_state, 2380 .process = sdma_v4_0_process_trap_irq, 2381 }; 2382 2383 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = { 2384 .process = sdma_v4_0_process_illegal_inst_irq, 2385 }; 2386 2387 static const struct amdgpu_irq_src_funcs sdma_v4_0_ecc_irq_funcs = { 2388 .set = sdma_v4_0_set_ecc_irq_state, 2389 .process = sdma_v4_0_process_ecc_irq, 2390 }; 2391 2392 2393 2394 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev) 2395 { 2396 switch (adev->sdma.num_instances) { 2397 case 1: 2398 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1; 2399 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1; 2400 break; 2401 case 8: 2402 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 2403 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 2404 break; 2405 case 2: 2406 default: 2407 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2; 2408 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2; 2409 break; 2410 } 2411 adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs; 2412 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs; 2413 adev->sdma.ecc_irq.funcs = &sdma_v4_0_ecc_irq_funcs; 2414 } 2415 2416 /** 2417 * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine 2418 * 2419 * @ring: amdgpu_ring structure holding ring information 2420 * @src_offset: src GPU address 2421 * @dst_offset: dst GPU address 2422 * @byte_count: number of bytes to xfer 2423 * 2424 * Copy GPU buffers using the DMA engine (VEGA10/12). 2425 * Used by the amdgpu ttm implementation to move pages if 2426 * registered as the asic copy callback. 2427 */ 2428 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib, 2429 uint64_t src_offset, 2430 uint64_t dst_offset, 2431 uint32_t byte_count) 2432 { 2433 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 2434 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 2435 ib->ptr[ib->length_dw++] = byte_count - 1; 2436 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 2437 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 2438 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 2439 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2440 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2441 } 2442 2443 /** 2444 * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine 2445 * 2446 * @ring: amdgpu_ring structure holding ring information 2447 * @src_data: value to write to buffer 2448 * @dst_offset: dst GPU address 2449 * @byte_count: number of bytes to xfer 2450 * 2451 * Fill GPU buffers using the DMA engine (VEGA10/12). 2452 */ 2453 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib, 2454 uint32_t src_data, 2455 uint64_t dst_offset, 2456 uint32_t byte_count) 2457 { 2458 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 2459 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2460 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2461 ib->ptr[ib->length_dw++] = src_data; 2462 ib->ptr[ib->length_dw++] = byte_count - 1; 2463 } 2464 2465 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = { 2466 .copy_max_bytes = 0x400000, 2467 .copy_num_dw = 7, 2468 .emit_copy_buffer = sdma_v4_0_emit_copy_buffer, 2469 2470 .fill_max_bytes = 0x400000, 2471 .fill_num_dw = 5, 2472 .emit_fill_buffer = sdma_v4_0_emit_fill_buffer, 2473 }; 2474 2475 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev) 2476 { 2477 adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs; 2478 if (adev->sdma.has_page_queue && adev->sdma.num_instances > 1) 2479 adev->mman.buffer_funcs_ring = &adev->sdma.instance[1].page; 2480 else 2481 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 2482 } 2483 2484 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = { 2485 .copy_pte_num_dw = 7, 2486 .copy_pte = sdma_v4_0_vm_copy_pte, 2487 2488 .write_pte = sdma_v4_0_vm_write_pte, 2489 .set_pte_pde = sdma_v4_0_vm_set_pte_pde, 2490 }; 2491 2492 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev) 2493 { 2494 struct drm_gpu_scheduler *sched; 2495 unsigned i; 2496 2497 adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs; 2498 if (adev->sdma.has_page_queue && adev->sdma.num_instances > 1) { 2499 for (i = 1; i < adev->sdma.num_instances; i++) { 2500 sched = &adev->sdma.instance[i].page.sched; 2501 adev->vm_manager.vm_pte_rqs[i - 1] = 2502 &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL]; 2503 } 2504 adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances - 1; 2505 adev->vm_manager.page_fault = &adev->sdma.instance[0].page; 2506 } else { 2507 for (i = 0; i < adev->sdma.num_instances; i++) { 2508 sched = &adev->sdma.instance[i].ring.sched; 2509 adev->vm_manager.vm_pte_rqs[i] = 2510 &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL]; 2511 } 2512 adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances; 2513 } 2514 } 2515 2516 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = { 2517 .type = AMD_IP_BLOCK_TYPE_SDMA, 2518 .major = 4, 2519 .minor = 0, 2520 .rev = 0, 2521 .funcs = &sdma_v4_0_ip_funcs, 2522 }; 2523