1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_ucode.h" 28 #include "amdgpu_trace.h" 29 #include "vi.h" 30 #include "vid.h" 31 32 #include "oss/oss_3_0_d.h" 33 #include "oss/oss_3_0_sh_mask.h" 34 35 #include "gmc/gmc_8_1_d.h" 36 #include "gmc/gmc_8_1_sh_mask.h" 37 38 #include "gca/gfx_8_0_d.h" 39 #include "gca/gfx_8_0_enum.h" 40 #include "gca/gfx_8_0_sh_mask.h" 41 42 #include "bif/bif_5_0_d.h" 43 #include "bif/bif_5_0_sh_mask.h" 44 45 #include "tonga_sdma_pkt_open.h" 46 47 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev); 48 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev); 49 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev); 50 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev); 51 52 MODULE_FIRMWARE("amdgpu/tonga_sdma.bin"); 53 MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin"); 54 MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin"); 55 MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin"); 56 MODULE_FIRMWARE("amdgpu/fiji_sdma.bin"); 57 MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin"); 58 59 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = 60 { 61 SDMA0_REGISTER_OFFSET, 62 SDMA1_REGISTER_OFFSET 63 }; 64 65 static const u32 golden_settings_tonga_a11[] = 66 { 67 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 68 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 69 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 70 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 71 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 72 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 73 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 74 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 75 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 76 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 77 }; 78 79 static const u32 tonga_mgcg_cgcg_init[] = 80 { 81 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 82 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 83 }; 84 85 static const u32 golden_settings_fiji_a10[] = 86 { 87 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 88 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 89 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 90 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 91 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 92 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 93 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 94 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 95 }; 96 97 static const u32 fiji_mgcg_cgcg_init[] = 98 { 99 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 100 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 101 }; 102 103 static const u32 cz_golden_settings_a11[] = 104 { 105 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 106 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 107 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, 108 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, 109 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, 110 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, 111 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 112 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 113 mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100, 114 mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800, 115 mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100, 116 mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100, 117 }; 118 119 static const u32 cz_mgcg_cgcg_init[] = 120 { 121 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 122 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 123 }; 124 125 /* 126 * sDMA - System DMA 127 * Starting with CIK, the GPU has new asynchronous 128 * DMA engines. These engines are used for compute 129 * and gfx. There are two DMA engines (SDMA0, SDMA1) 130 * and each one supports 1 ring buffer used for gfx 131 * and 2 queues used for compute. 132 * 133 * The programming model is very similar to the CP 134 * (ring buffer, IBs, etc.), but sDMA has it's own 135 * packet format that is different from the PM4 format 136 * used by the CP. sDMA supports copying data, writing 137 * embedded data, solid fills, and a number of other 138 * things. It also has support for tiling/detiling of 139 * buffers. 140 */ 141 142 static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev) 143 { 144 switch (adev->asic_type) { 145 case CHIP_FIJI: 146 amdgpu_program_register_sequence(adev, 147 fiji_mgcg_cgcg_init, 148 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); 149 amdgpu_program_register_sequence(adev, 150 golden_settings_fiji_a10, 151 (const u32)ARRAY_SIZE(golden_settings_fiji_a10)); 152 break; 153 case CHIP_TONGA: 154 amdgpu_program_register_sequence(adev, 155 tonga_mgcg_cgcg_init, 156 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); 157 amdgpu_program_register_sequence(adev, 158 golden_settings_tonga_a11, 159 (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); 160 break; 161 case CHIP_CARRIZO: 162 amdgpu_program_register_sequence(adev, 163 cz_mgcg_cgcg_init, 164 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); 165 amdgpu_program_register_sequence(adev, 166 cz_golden_settings_a11, 167 (const u32)ARRAY_SIZE(cz_golden_settings_a11)); 168 break; 169 default: 170 break; 171 } 172 } 173 174 /** 175 * sdma_v3_0_init_microcode - load ucode images from disk 176 * 177 * @adev: amdgpu_device pointer 178 * 179 * Use the firmware interface to load the ucode images into 180 * the driver (not loaded into hw). 181 * Returns 0 on success, error on failure. 182 */ 183 static int sdma_v3_0_init_microcode(struct amdgpu_device *adev) 184 { 185 const char *chip_name; 186 char fw_name[30]; 187 int err, i; 188 struct amdgpu_firmware_info *info = NULL; 189 const struct common_firmware_header *header = NULL; 190 const struct sdma_firmware_header_v1_0 *hdr; 191 192 DRM_DEBUG("\n"); 193 194 switch (adev->asic_type) { 195 case CHIP_TONGA: 196 chip_name = "tonga"; 197 break; 198 case CHIP_FIJI: 199 chip_name = "fiji"; 200 break; 201 case CHIP_CARRIZO: 202 chip_name = "carrizo"; 203 break; 204 default: BUG(); 205 } 206 207 for (i = 0; i < SDMA_MAX_INSTANCE; i++) { 208 if (i == 0) 209 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 210 else 211 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); 212 err = request_firmware(&adev->sdma[i].fw, fw_name, adev->dev); 213 if (err) 214 goto out; 215 err = amdgpu_ucode_validate(adev->sdma[i].fw); 216 if (err) 217 goto out; 218 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data; 219 adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 220 adev->sdma[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 221 222 if (adev->firmware.smu_load) { 223 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 224 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 225 info->fw = adev->sdma[i].fw; 226 header = (const struct common_firmware_header *)info->fw->data; 227 adev->firmware.fw_size += 228 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 229 } 230 } 231 out: 232 if (err) { 233 printk(KERN_ERR 234 "sdma_v3_0: Failed to load firmware \"%s\"\n", 235 fw_name); 236 for (i = 0; i < SDMA_MAX_INSTANCE; i++) { 237 release_firmware(adev->sdma[i].fw); 238 adev->sdma[i].fw = NULL; 239 } 240 } 241 return err; 242 } 243 244 /** 245 * sdma_v3_0_ring_get_rptr - get the current read pointer 246 * 247 * @ring: amdgpu ring pointer 248 * 249 * Get the current rptr from the hardware (VI+). 250 */ 251 static uint32_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring) 252 { 253 u32 rptr; 254 255 /* XXX check if swapping is necessary on BE */ 256 rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2; 257 258 return rptr; 259 } 260 261 /** 262 * sdma_v3_0_ring_get_wptr - get the current write pointer 263 * 264 * @ring: amdgpu ring pointer 265 * 266 * Get the current wptr from the hardware (VI+). 267 */ 268 static uint32_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring) 269 { 270 struct amdgpu_device *adev = ring->adev; 271 u32 wptr; 272 273 if (ring->use_doorbell) { 274 /* XXX check if swapping is necessary on BE */ 275 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2; 276 } else { 277 int me = (ring == &ring->adev->sdma[0].ring) ? 0 : 1; 278 279 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2; 280 } 281 282 return wptr; 283 } 284 285 /** 286 * sdma_v3_0_ring_set_wptr - commit the write pointer 287 * 288 * @ring: amdgpu ring pointer 289 * 290 * Write the wptr back to the hardware (VI+). 291 */ 292 static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring) 293 { 294 struct amdgpu_device *adev = ring->adev; 295 296 if (ring->use_doorbell) { 297 /* XXX check if swapping is necessary on BE */ 298 adev->wb.wb[ring->wptr_offs] = ring->wptr << 2; 299 WDOORBELL32(ring->doorbell_index, ring->wptr << 2); 300 } else { 301 int me = (ring == &ring->adev->sdma[0].ring) ? 0 : 1; 302 303 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2); 304 } 305 } 306 307 /** 308 * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine 309 * 310 * @ring: amdgpu ring pointer 311 * @ib: IB object to schedule 312 * 313 * Schedule an IB in the DMA ring (VI). 314 */ 315 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring, 316 struct amdgpu_ib *ib) 317 { 318 u32 vmid = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf; 319 u32 next_rptr = ring->wptr + 5; 320 321 while ((next_rptr & 7) != 2) 322 next_rptr++; 323 next_rptr += 6; 324 325 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 326 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 327 amdgpu_ring_write(ring, lower_32_bits(ring->next_rptr_gpu_addr) & 0xfffffffc); 328 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); 329 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); 330 amdgpu_ring_write(ring, next_rptr); 331 332 /* IB packet must end on a 8 DW boundary */ 333 while ((ring->wptr & 7) != 2) 334 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_NOP)); 335 336 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 337 SDMA_PKT_INDIRECT_HEADER_VMID(vmid)); 338 /* base must be 32 byte aligned */ 339 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 340 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 341 amdgpu_ring_write(ring, ib->length_dw); 342 amdgpu_ring_write(ring, 0); 343 amdgpu_ring_write(ring, 0); 344 345 } 346 347 /** 348 * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 349 * 350 * @ring: amdgpu ring pointer 351 * 352 * Emit an hdp flush packet on the requested DMA ring. 353 */ 354 static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 355 { 356 u32 ref_and_mask = 0; 357 358 if (ring == &ring->adev->sdma[0].ring) 359 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); 360 else 361 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); 362 363 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 364 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 365 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 366 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); 367 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); 368 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 369 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 370 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 371 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 372 } 373 374 /** 375 * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring 376 * 377 * @ring: amdgpu ring pointer 378 * @fence: amdgpu fence object 379 * 380 * Add a DMA fence packet to the ring to write 381 * the fence seq number and DMA trap packet to generate 382 * an interrupt if needed (VI). 383 */ 384 static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 385 unsigned flags) 386 { 387 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 388 /* write the fence */ 389 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 390 amdgpu_ring_write(ring, lower_32_bits(addr)); 391 amdgpu_ring_write(ring, upper_32_bits(addr)); 392 amdgpu_ring_write(ring, lower_32_bits(seq)); 393 394 /* optionally write high bits as well */ 395 if (write64bit) { 396 addr += 4; 397 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 398 amdgpu_ring_write(ring, lower_32_bits(addr)); 399 amdgpu_ring_write(ring, upper_32_bits(addr)); 400 amdgpu_ring_write(ring, upper_32_bits(seq)); 401 } 402 403 /* generate an interrupt */ 404 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 405 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 406 } 407 408 409 /** 410 * sdma_v3_0_ring_emit_semaphore - emit a semaphore on the dma ring 411 * 412 * @ring: amdgpu_ring structure holding ring information 413 * @semaphore: amdgpu semaphore object 414 * @emit_wait: wait or signal semaphore 415 * 416 * Add a DMA semaphore packet to the ring wait on or signal 417 * other rings (VI). 418 */ 419 static bool sdma_v3_0_ring_emit_semaphore(struct amdgpu_ring *ring, 420 struct amdgpu_semaphore *semaphore, 421 bool emit_wait) 422 { 423 u64 addr = semaphore->gpu_addr; 424 u32 sig = emit_wait ? 0 : 1; 425 426 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SEM) | 427 SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(sig)); 428 amdgpu_ring_write(ring, lower_32_bits(addr) & 0xfffffff8); 429 amdgpu_ring_write(ring, upper_32_bits(addr)); 430 431 return true; 432 } 433 434 /** 435 * sdma_v3_0_gfx_stop - stop the gfx async dma engines 436 * 437 * @adev: amdgpu_device pointer 438 * 439 * Stop the gfx async dma ring buffers (VI). 440 */ 441 static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev) 442 { 443 struct amdgpu_ring *sdma0 = &adev->sdma[0].ring; 444 struct amdgpu_ring *sdma1 = &adev->sdma[1].ring; 445 u32 rb_cntl, ib_cntl; 446 int i; 447 448 if ((adev->mman.buffer_funcs_ring == sdma0) || 449 (adev->mman.buffer_funcs_ring == sdma1)) 450 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); 451 452 for (i = 0; i < SDMA_MAX_INSTANCE; i++) { 453 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 454 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 455 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 456 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 457 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 458 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 459 } 460 sdma0->ready = false; 461 sdma1->ready = false; 462 } 463 464 /** 465 * sdma_v3_0_rlc_stop - stop the compute async dma engines 466 * 467 * @adev: amdgpu_device pointer 468 * 469 * Stop the compute async dma queues (VI). 470 */ 471 static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev) 472 { 473 /* XXX todo */ 474 } 475 476 /** 477 * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch 478 * 479 * @adev: amdgpu_device pointer 480 * @enable: enable/disable the DMA MEs context switch. 481 * 482 * Halt or unhalt the async dma engines context switch (VI). 483 */ 484 static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 485 { 486 u32 f32_cntl; 487 int i; 488 489 for (i = 0; i < SDMA_MAX_INSTANCE; i++) { 490 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); 491 if (enable) 492 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 493 AUTO_CTXSW_ENABLE, 1); 494 else 495 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 496 AUTO_CTXSW_ENABLE, 0); 497 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); 498 } 499 } 500 501 /** 502 * sdma_v3_0_enable - stop the async dma engines 503 * 504 * @adev: amdgpu_device pointer 505 * @enable: enable/disable the DMA MEs. 506 * 507 * Halt or unhalt the async dma engines (VI). 508 */ 509 static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable) 510 { 511 u32 f32_cntl; 512 int i; 513 514 if (enable == false) { 515 sdma_v3_0_gfx_stop(adev); 516 sdma_v3_0_rlc_stop(adev); 517 } 518 519 for (i = 0; i < SDMA_MAX_INSTANCE; i++) { 520 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); 521 if (enable) 522 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); 523 else 524 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); 525 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); 526 } 527 } 528 529 /** 530 * sdma_v3_0_gfx_resume - setup and start the async dma engines 531 * 532 * @adev: amdgpu_device pointer 533 * 534 * Set up the gfx DMA ring buffers and enable them (VI). 535 * Returns 0 for success, error for failure. 536 */ 537 static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) 538 { 539 struct amdgpu_ring *ring; 540 u32 rb_cntl, ib_cntl; 541 u32 rb_bufsz; 542 u32 wb_offset; 543 u32 doorbell; 544 int i, j, r; 545 546 for (i = 0; i < SDMA_MAX_INSTANCE; i++) { 547 ring = &adev->sdma[i].ring; 548 wb_offset = (ring->rptr_offs * 4); 549 550 mutex_lock(&adev->srbm_mutex); 551 for (j = 0; j < 16; j++) { 552 vi_srbm_select(adev, 0, 0, 0, j); 553 /* SDMA GFX */ 554 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); 555 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); 556 } 557 vi_srbm_select(adev, 0, 0, 0, 0); 558 mutex_unlock(&adev->srbm_mutex); 559 560 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); 561 562 /* Set ring buffer size in dwords */ 563 rb_bufsz = order_base_2(ring->ring_size / 4); 564 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 565 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 566 #ifdef __BIG_ENDIAN 567 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 568 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 569 RPTR_WRITEBACK_SWAP_ENABLE, 1); 570 #endif 571 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 572 573 /* Initialize the ring buffer's read and write pointers */ 574 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); 575 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); 576 577 /* set the wb address whether it's enabled or not */ 578 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], 579 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 580 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], 581 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 582 583 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 584 585 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); 586 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); 587 588 ring->wptr = 0; 589 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2); 590 591 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]); 592 593 if (ring->use_doorbell) { 594 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, 595 OFFSET, ring->doorbell_index); 596 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 597 } else { 598 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 599 } 600 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell); 601 602 /* enable DMA RB */ 603 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 604 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 605 606 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 607 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 608 #ifdef __BIG_ENDIAN 609 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 610 #endif 611 /* enable DMA IBs */ 612 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 613 614 ring->ready = true; 615 616 r = amdgpu_ring_test_ring(ring); 617 if (r) { 618 ring->ready = false; 619 return r; 620 } 621 622 if (adev->mman.buffer_funcs_ring == ring) 623 amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size); 624 } 625 626 return 0; 627 } 628 629 /** 630 * sdma_v3_0_rlc_resume - setup and start the async dma engines 631 * 632 * @adev: amdgpu_device pointer 633 * 634 * Set up the compute DMA queues and enable them (VI). 635 * Returns 0 for success, error for failure. 636 */ 637 static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev) 638 { 639 /* XXX todo */ 640 return 0; 641 } 642 643 /** 644 * sdma_v3_0_load_microcode - load the sDMA ME ucode 645 * 646 * @adev: amdgpu_device pointer 647 * 648 * Loads the sDMA0/1 ucode. 649 * Returns 0 for success, -EINVAL if the ucode is not available. 650 */ 651 static int sdma_v3_0_load_microcode(struct amdgpu_device *adev) 652 { 653 const struct sdma_firmware_header_v1_0 *hdr; 654 const __le32 *fw_data; 655 u32 fw_size; 656 int i, j; 657 658 if (!adev->sdma[0].fw || !adev->sdma[1].fw) 659 return -EINVAL; 660 661 /* halt the MEs */ 662 sdma_v3_0_enable(adev, false); 663 664 for (i = 0; i < SDMA_MAX_INSTANCE; i++) { 665 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data; 666 amdgpu_ucode_print_sdma_hdr(&hdr->header); 667 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 668 fw_data = (const __le32 *) 669 (adev->sdma[i].fw->data + 670 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 671 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0); 672 for (j = 0; j < fw_size; j++) 673 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++)); 674 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma[i].fw_version); 675 } 676 677 return 0; 678 } 679 680 /** 681 * sdma_v3_0_start - setup and start the async dma engines 682 * 683 * @adev: amdgpu_device pointer 684 * 685 * Set up the DMA engines and enable them (VI). 686 * Returns 0 for success, error for failure. 687 */ 688 static int sdma_v3_0_start(struct amdgpu_device *adev) 689 { 690 int r; 691 692 if (!adev->firmware.smu_load) { 693 r = sdma_v3_0_load_microcode(adev); 694 if (r) 695 return r; 696 } else { 697 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, 698 AMDGPU_UCODE_ID_SDMA0); 699 if (r) 700 return -EINVAL; 701 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, 702 AMDGPU_UCODE_ID_SDMA1); 703 if (r) 704 return -EINVAL; 705 } 706 707 /* unhalt the MEs */ 708 sdma_v3_0_enable(adev, true); 709 /* enable sdma ring preemption */ 710 sdma_v3_0_ctx_switch_enable(adev, true); 711 712 /* start the gfx rings and rlc compute queues */ 713 r = sdma_v3_0_gfx_resume(adev); 714 if (r) 715 return r; 716 r = sdma_v3_0_rlc_resume(adev); 717 if (r) 718 return r; 719 720 return 0; 721 } 722 723 /** 724 * sdma_v3_0_ring_test_ring - simple async dma engine test 725 * 726 * @ring: amdgpu_ring structure holding ring information 727 * 728 * Test the DMA engine by writing using it to write an 729 * value to memory. (VI). 730 * Returns 0 for success, error for failure. 731 */ 732 static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring) 733 { 734 struct amdgpu_device *adev = ring->adev; 735 unsigned i; 736 unsigned index; 737 int r; 738 u32 tmp; 739 u64 gpu_addr; 740 741 r = amdgpu_wb_get(adev, &index); 742 if (r) { 743 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 744 return r; 745 } 746 747 gpu_addr = adev->wb.gpu_addr + (index * 4); 748 tmp = 0xCAFEDEAD; 749 adev->wb.wb[index] = cpu_to_le32(tmp); 750 751 r = amdgpu_ring_lock(ring, 5); 752 if (r) { 753 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 754 amdgpu_wb_free(adev, index); 755 return r; 756 } 757 758 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 759 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 760 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 761 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 762 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); 763 amdgpu_ring_write(ring, 0xDEADBEEF); 764 amdgpu_ring_unlock_commit(ring); 765 766 for (i = 0; i < adev->usec_timeout; i++) { 767 tmp = le32_to_cpu(adev->wb.wb[index]); 768 if (tmp == 0xDEADBEEF) 769 break; 770 DRM_UDELAY(1); 771 } 772 773 if (i < adev->usec_timeout) { 774 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 775 } else { 776 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 777 ring->idx, tmp); 778 r = -EINVAL; 779 } 780 amdgpu_wb_free(adev, index); 781 782 return r; 783 } 784 785 /** 786 * sdma_v3_0_ring_test_ib - test an IB on the DMA engine 787 * 788 * @ring: amdgpu_ring structure holding ring information 789 * 790 * Test a simple IB in the DMA ring (VI). 791 * Returns 0 on success, error on failure. 792 */ 793 static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring) 794 { 795 struct amdgpu_device *adev = ring->adev; 796 struct amdgpu_ib ib; 797 struct fence *f = NULL; 798 unsigned i; 799 unsigned index; 800 int r; 801 u32 tmp = 0; 802 u64 gpu_addr; 803 804 r = amdgpu_wb_get(adev, &index); 805 if (r) { 806 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 807 return r; 808 } 809 810 gpu_addr = adev->wb.gpu_addr + (index * 4); 811 tmp = 0xCAFEDEAD; 812 adev->wb.wb[index] = cpu_to_le32(tmp); 813 memset(&ib, 0, sizeof(ib)); 814 r = amdgpu_ib_get(ring, NULL, 256, &ib); 815 if (r) { 816 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r); 817 goto err0; 818 } 819 820 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 821 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 822 ib.ptr[1] = lower_32_bits(gpu_addr); 823 ib.ptr[2] = upper_32_bits(gpu_addr); 824 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1); 825 ib.ptr[4] = 0xDEADBEEF; 826 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 827 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 828 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 829 ib.length_dw = 8; 830 831 r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, &ib, 1, NULL, 832 AMDGPU_FENCE_OWNER_UNDEFINED, 833 &f); 834 if (r) 835 goto err1; 836 837 r = fence_wait(f, false); 838 if (r) { 839 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); 840 goto err1; 841 } 842 for (i = 0; i < adev->usec_timeout; i++) { 843 tmp = le32_to_cpu(adev->wb.wb[index]); 844 if (tmp == 0xDEADBEEF) 845 break; 846 DRM_UDELAY(1); 847 } 848 if (i < adev->usec_timeout) { 849 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", 850 ring->idx, i); 851 goto err1; 852 } else { 853 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); 854 r = -EINVAL; 855 } 856 err1: 857 fence_put(f); 858 amdgpu_ib_free(adev, &ib); 859 err0: 860 amdgpu_wb_free(adev, index); 861 return r; 862 } 863 864 /** 865 * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART 866 * 867 * @ib: indirect buffer to fill with commands 868 * @pe: addr of the page entry 869 * @src: src addr to copy from 870 * @count: number of page entries to update 871 * 872 * Update PTEs by copying them from the GART using sDMA (CIK). 873 */ 874 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib, 875 uint64_t pe, uint64_t src, 876 unsigned count) 877 { 878 while (count) { 879 unsigned bytes = count * 8; 880 if (bytes > 0x1FFFF8) 881 bytes = 0x1FFFF8; 882 883 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 884 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 885 ib->ptr[ib->length_dw++] = bytes; 886 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 887 ib->ptr[ib->length_dw++] = lower_32_bits(src); 888 ib->ptr[ib->length_dw++] = upper_32_bits(src); 889 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 890 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 891 892 pe += bytes; 893 src += bytes; 894 count -= bytes / 8; 895 } 896 } 897 898 /** 899 * sdma_v3_0_vm_write_pte - update PTEs by writing them manually 900 * 901 * @ib: indirect buffer to fill with commands 902 * @pe: addr of the page entry 903 * @addr: dst addr to write into pe 904 * @count: number of page entries to update 905 * @incr: increase next addr by incr bytes 906 * @flags: access flags 907 * 908 * Update PTEs by writing them manually using sDMA (CIK). 909 */ 910 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, 911 uint64_t pe, 912 uint64_t addr, unsigned count, 913 uint32_t incr, uint32_t flags) 914 { 915 uint64_t value; 916 unsigned ndw; 917 918 while (count) { 919 ndw = count * 2; 920 if (ndw > 0xFFFFE) 921 ndw = 0xFFFFE; 922 923 /* for non-physically contiguous pages (system) */ 924 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 925 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 926 ib->ptr[ib->length_dw++] = pe; 927 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 928 ib->ptr[ib->length_dw++] = ndw; 929 for (; ndw > 0; ndw -= 2, --count, pe += 8) { 930 if (flags & AMDGPU_PTE_SYSTEM) { 931 value = amdgpu_vm_map_gart(ib->ring->adev, addr); 932 value &= 0xFFFFFFFFFFFFF000ULL; 933 } else if (flags & AMDGPU_PTE_VALID) { 934 value = addr; 935 } else { 936 value = 0; 937 } 938 addr += incr; 939 value |= flags; 940 ib->ptr[ib->length_dw++] = value; 941 ib->ptr[ib->length_dw++] = upper_32_bits(value); 942 } 943 } 944 } 945 946 /** 947 * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA 948 * 949 * @ib: indirect buffer to fill with commands 950 * @pe: addr of the page entry 951 * @addr: dst addr to write into pe 952 * @count: number of page entries to update 953 * @incr: increase next addr by incr bytes 954 * @flags: access flags 955 * 956 * Update the page tables using sDMA (CIK). 957 */ 958 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, 959 uint64_t pe, 960 uint64_t addr, unsigned count, 961 uint32_t incr, uint32_t flags) 962 { 963 uint64_t value; 964 unsigned ndw; 965 966 while (count) { 967 ndw = count; 968 if (ndw > 0x7FFFF) 969 ndw = 0x7FFFF; 970 971 if (flags & AMDGPU_PTE_VALID) 972 value = addr; 973 else 974 value = 0; 975 976 /* for physically contiguous pages (vram) */ 977 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE); 978 ib->ptr[ib->length_dw++] = pe; /* dst addr */ 979 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 980 ib->ptr[ib->length_dw++] = flags; /* mask */ 981 ib->ptr[ib->length_dw++] = 0; 982 ib->ptr[ib->length_dw++] = value; /* value */ 983 ib->ptr[ib->length_dw++] = upper_32_bits(value); 984 ib->ptr[ib->length_dw++] = incr; /* increment size */ 985 ib->ptr[ib->length_dw++] = 0; 986 ib->ptr[ib->length_dw++] = ndw; /* number of entries */ 987 988 pe += ndw * 8; 989 addr += ndw * incr; 990 count -= ndw; 991 } 992 } 993 994 /** 995 * sdma_v3_0_vm_pad_ib - pad the IB to the required number of dw 996 * 997 * @ib: indirect buffer to fill with padding 998 * 999 */ 1000 static void sdma_v3_0_vm_pad_ib(struct amdgpu_ib *ib) 1001 { 1002 while (ib->length_dw & 0x7) 1003 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1004 } 1005 1006 /** 1007 * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA 1008 * 1009 * @ring: amdgpu_ring pointer 1010 * @vm: amdgpu_vm pointer 1011 * 1012 * Update the page table base and flush the VM TLB 1013 * using sDMA (VI). 1014 */ 1015 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1016 unsigned vm_id, uint64_t pd_addr) 1017 { 1018 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1019 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1020 if (vm_id < 8) { 1021 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id)); 1022 } else { 1023 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8)); 1024 } 1025 amdgpu_ring_write(ring, pd_addr >> 12); 1026 1027 /* flush TLB */ 1028 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1029 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1030 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 1031 amdgpu_ring_write(ring, 1 << vm_id); 1032 1033 /* wait for flush */ 1034 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1035 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1036 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */ 1037 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); 1038 amdgpu_ring_write(ring, 0); 1039 amdgpu_ring_write(ring, 0); /* reference */ 1040 amdgpu_ring_write(ring, 0); /* mask */ 1041 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1042 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 1043 } 1044 1045 static int sdma_v3_0_early_init(void *handle) 1046 { 1047 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1048 1049 sdma_v3_0_set_ring_funcs(adev); 1050 sdma_v3_0_set_buffer_funcs(adev); 1051 sdma_v3_0_set_vm_pte_funcs(adev); 1052 sdma_v3_0_set_irq_funcs(adev); 1053 1054 return 0; 1055 } 1056 1057 static int sdma_v3_0_sw_init(void *handle) 1058 { 1059 struct amdgpu_ring *ring; 1060 int r; 1061 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1062 1063 /* SDMA trap event */ 1064 r = amdgpu_irq_add_id(adev, 224, &adev->sdma_trap_irq); 1065 if (r) 1066 return r; 1067 1068 /* SDMA Privileged inst */ 1069 r = amdgpu_irq_add_id(adev, 241, &adev->sdma_illegal_inst_irq); 1070 if (r) 1071 return r; 1072 1073 /* SDMA Privileged inst */ 1074 r = amdgpu_irq_add_id(adev, 247, &adev->sdma_illegal_inst_irq); 1075 if (r) 1076 return r; 1077 1078 r = sdma_v3_0_init_microcode(adev); 1079 if (r) { 1080 DRM_ERROR("Failed to load sdma firmware!\n"); 1081 return r; 1082 } 1083 1084 ring = &adev->sdma[0].ring; 1085 ring->ring_obj = NULL; 1086 ring->use_doorbell = true; 1087 ring->doorbell_index = AMDGPU_DOORBELL_sDMA_ENGINE0; 1088 1089 ring = &adev->sdma[1].ring; 1090 ring->ring_obj = NULL; 1091 ring->use_doorbell = true; 1092 ring->doorbell_index = AMDGPU_DOORBELL_sDMA_ENGINE1; 1093 1094 ring = &adev->sdma[0].ring; 1095 sprintf(ring->name, "sdma0"); 1096 r = amdgpu_ring_init(adev, ring, 256 * 1024, 1097 SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, 1098 &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP0, 1099 AMDGPU_RING_TYPE_SDMA); 1100 if (r) 1101 return r; 1102 1103 ring = &adev->sdma[1].ring; 1104 sprintf(ring->name, "sdma1"); 1105 r = amdgpu_ring_init(adev, ring, 256 * 1024, 1106 SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, 1107 &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP1, 1108 AMDGPU_RING_TYPE_SDMA); 1109 if (r) 1110 return r; 1111 1112 return r; 1113 } 1114 1115 static int sdma_v3_0_sw_fini(void *handle) 1116 { 1117 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1118 1119 amdgpu_ring_fini(&adev->sdma[0].ring); 1120 amdgpu_ring_fini(&adev->sdma[1].ring); 1121 1122 return 0; 1123 } 1124 1125 static int sdma_v3_0_hw_init(void *handle) 1126 { 1127 int r; 1128 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1129 1130 sdma_v3_0_init_golden_registers(adev); 1131 1132 r = sdma_v3_0_start(adev); 1133 if (r) 1134 return r; 1135 1136 return r; 1137 } 1138 1139 static int sdma_v3_0_hw_fini(void *handle) 1140 { 1141 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1142 1143 sdma_v3_0_ctx_switch_enable(adev, false); 1144 sdma_v3_0_enable(adev, false); 1145 1146 return 0; 1147 } 1148 1149 static int sdma_v3_0_suspend(void *handle) 1150 { 1151 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1152 1153 return sdma_v3_0_hw_fini(adev); 1154 } 1155 1156 static int sdma_v3_0_resume(void *handle) 1157 { 1158 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1159 1160 return sdma_v3_0_hw_init(adev); 1161 } 1162 1163 static bool sdma_v3_0_is_idle(void *handle) 1164 { 1165 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1166 u32 tmp = RREG32(mmSRBM_STATUS2); 1167 1168 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | 1169 SRBM_STATUS2__SDMA1_BUSY_MASK)) 1170 return false; 1171 1172 return true; 1173 } 1174 1175 static int sdma_v3_0_wait_for_idle(void *handle) 1176 { 1177 unsigned i; 1178 u32 tmp; 1179 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1180 1181 for (i = 0; i < adev->usec_timeout; i++) { 1182 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | 1183 SRBM_STATUS2__SDMA1_BUSY_MASK); 1184 1185 if (!tmp) 1186 return 0; 1187 udelay(1); 1188 } 1189 return -ETIMEDOUT; 1190 } 1191 1192 static void sdma_v3_0_print_status(void *handle) 1193 { 1194 int i, j; 1195 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1196 1197 dev_info(adev->dev, "VI SDMA registers\n"); 1198 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", 1199 RREG32(mmSRBM_STATUS2)); 1200 for (i = 0; i < SDMA_MAX_INSTANCE; i++) { 1201 dev_info(adev->dev, " SDMA%d_STATUS_REG=0x%08X\n", 1202 i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i])); 1203 dev_info(adev->dev, " SDMA%d_F32_CNTL=0x%08X\n", 1204 i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i])); 1205 dev_info(adev->dev, " SDMA%d_CNTL=0x%08X\n", 1206 i, RREG32(mmSDMA0_CNTL + sdma_offsets[i])); 1207 dev_info(adev->dev, " SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n", 1208 i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i])); 1209 dev_info(adev->dev, " SDMA%d_GFX_IB_CNTL=0x%08X\n", 1210 i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i])); 1211 dev_info(adev->dev, " SDMA%d_GFX_RB_CNTL=0x%08X\n", 1212 i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i])); 1213 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR=0x%08X\n", 1214 i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i])); 1215 dev_info(adev->dev, " SDMA%d_GFX_RB_WPTR=0x%08X\n", 1216 i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i])); 1217 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n", 1218 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i])); 1219 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n", 1220 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i])); 1221 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE=0x%08X\n", 1222 i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i])); 1223 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE_HI=0x%08X\n", 1224 i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i])); 1225 dev_info(adev->dev, " SDMA%d_GFX_DOORBELL=0x%08X\n", 1226 i, RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i])); 1227 mutex_lock(&adev->srbm_mutex); 1228 for (j = 0; j < 16; j++) { 1229 vi_srbm_select(adev, 0, 0, 0, j); 1230 dev_info(adev->dev, " VM %d:\n", j); 1231 dev_info(adev->dev, " SDMA%d_GFX_VIRTUAL_ADDR=0x%08X\n", 1232 i, RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i])); 1233 dev_info(adev->dev, " SDMA%d_GFX_APE1_CNTL=0x%08X\n", 1234 i, RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i])); 1235 } 1236 vi_srbm_select(adev, 0, 0, 0, 0); 1237 mutex_unlock(&adev->srbm_mutex); 1238 } 1239 } 1240 1241 static int sdma_v3_0_soft_reset(void *handle) 1242 { 1243 u32 srbm_soft_reset = 0; 1244 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1245 u32 tmp = RREG32(mmSRBM_STATUS2); 1246 1247 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) { 1248 /* sdma0 */ 1249 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); 1250 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); 1251 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); 1252 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK; 1253 } 1254 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) { 1255 /* sdma1 */ 1256 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); 1257 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); 1258 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); 1259 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK; 1260 } 1261 1262 if (srbm_soft_reset) { 1263 sdma_v3_0_print_status((void *)adev); 1264 1265 tmp = RREG32(mmSRBM_SOFT_RESET); 1266 tmp |= srbm_soft_reset; 1267 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1268 WREG32(mmSRBM_SOFT_RESET, tmp); 1269 tmp = RREG32(mmSRBM_SOFT_RESET); 1270 1271 udelay(50); 1272 1273 tmp &= ~srbm_soft_reset; 1274 WREG32(mmSRBM_SOFT_RESET, tmp); 1275 tmp = RREG32(mmSRBM_SOFT_RESET); 1276 1277 /* Wait a little for things to settle down */ 1278 udelay(50); 1279 1280 sdma_v3_0_print_status((void *)adev); 1281 } 1282 1283 return 0; 1284 } 1285 1286 static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev, 1287 struct amdgpu_irq_src *source, 1288 unsigned type, 1289 enum amdgpu_interrupt_state state) 1290 { 1291 u32 sdma_cntl; 1292 1293 switch (type) { 1294 case AMDGPU_SDMA_IRQ_TRAP0: 1295 switch (state) { 1296 case AMDGPU_IRQ_STATE_DISABLE: 1297 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1298 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1299 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1300 break; 1301 case AMDGPU_IRQ_STATE_ENABLE: 1302 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1303 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1304 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1305 break; 1306 default: 1307 break; 1308 } 1309 break; 1310 case AMDGPU_SDMA_IRQ_TRAP1: 1311 switch (state) { 1312 case AMDGPU_IRQ_STATE_DISABLE: 1313 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1314 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1315 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1316 break; 1317 case AMDGPU_IRQ_STATE_ENABLE: 1318 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1319 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1320 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1321 break; 1322 default: 1323 break; 1324 } 1325 break; 1326 default: 1327 break; 1328 } 1329 return 0; 1330 } 1331 1332 static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev, 1333 struct amdgpu_irq_src *source, 1334 struct amdgpu_iv_entry *entry) 1335 { 1336 u8 instance_id, queue_id; 1337 1338 instance_id = (entry->ring_id & 0x3) >> 0; 1339 queue_id = (entry->ring_id & 0xc) >> 2; 1340 DRM_DEBUG("IH: SDMA trap\n"); 1341 switch (instance_id) { 1342 case 0: 1343 switch (queue_id) { 1344 case 0: 1345 amdgpu_fence_process(&adev->sdma[0].ring); 1346 break; 1347 case 1: 1348 /* XXX compute */ 1349 break; 1350 case 2: 1351 /* XXX compute */ 1352 break; 1353 } 1354 break; 1355 case 1: 1356 switch (queue_id) { 1357 case 0: 1358 amdgpu_fence_process(&adev->sdma[1].ring); 1359 break; 1360 case 1: 1361 /* XXX compute */ 1362 break; 1363 case 2: 1364 /* XXX compute */ 1365 break; 1366 } 1367 break; 1368 } 1369 return 0; 1370 } 1371 1372 static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1373 struct amdgpu_irq_src *source, 1374 struct amdgpu_iv_entry *entry) 1375 { 1376 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1377 schedule_work(&adev->reset_work); 1378 return 0; 1379 } 1380 1381 static int sdma_v3_0_set_clockgating_state(void *handle, 1382 enum amd_clockgating_state state) 1383 { 1384 return 0; 1385 } 1386 1387 static int sdma_v3_0_set_powergating_state(void *handle, 1388 enum amd_powergating_state state) 1389 { 1390 return 0; 1391 } 1392 1393 const struct amd_ip_funcs sdma_v3_0_ip_funcs = { 1394 .early_init = sdma_v3_0_early_init, 1395 .late_init = NULL, 1396 .sw_init = sdma_v3_0_sw_init, 1397 .sw_fini = sdma_v3_0_sw_fini, 1398 .hw_init = sdma_v3_0_hw_init, 1399 .hw_fini = sdma_v3_0_hw_fini, 1400 .suspend = sdma_v3_0_suspend, 1401 .resume = sdma_v3_0_resume, 1402 .is_idle = sdma_v3_0_is_idle, 1403 .wait_for_idle = sdma_v3_0_wait_for_idle, 1404 .soft_reset = sdma_v3_0_soft_reset, 1405 .print_status = sdma_v3_0_print_status, 1406 .set_clockgating_state = sdma_v3_0_set_clockgating_state, 1407 .set_powergating_state = sdma_v3_0_set_powergating_state, 1408 }; 1409 1410 /** 1411 * sdma_v3_0_ring_is_lockup - Check if the DMA engine is locked up 1412 * 1413 * @ring: amdgpu_ring structure holding ring information 1414 * 1415 * Check if the async DMA engine is locked up (VI). 1416 * Returns true if the engine appears to be locked up, false if not. 1417 */ 1418 static bool sdma_v3_0_ring_is_lockup(struct amdgpu_ring *ring) 1419 { 1420 1421 if (sdma_v3_0_is_idle(ring->adev)) { 1422 amdgpu_ring_lockup_update(ring); 1423 return false; 1424 } 1425 return amdgpu_ring_test_lockup(ring); 1426 } 1427 1428 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { 1429 .get_rptr = sdma_v3_0_ring_get_rptr, 1430 .get_wptr = sdma_v3_0_ring_get_wptr, 1431 .set_wptr = sdma_v3_0_ring_set_wptr, 1432 .parse_cs = NULL, 1433 .emit_ib = sdma_v3_0_ring_emit_ib, 1434 .emit_fence = sdma_v3_0_ring_emit_fence, 1435 .emit_semaphore = sdma_v3_0_ring_emit_semaphore, 1436 .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush, 1437 .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush, 1438 .test_ring = sdma_v3_0_ring_test_ring, 1439 .test_ib = sdma_v3_0_ring_test_ib, 1440 .is_lockup = sdma_v3_0_ring_is_lockup, 1441 }; 1442 1443 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev) 1444 { 1445 adev->sdma[0].ring.funcs = &sdma_v3_0_ring_funcs; 1446 adev->sdma[1].ring.funcs = &sdma_v3_0_ring_funcs; 1447 } 1448 1449 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = { 1450 .set = sdma_v3_0_set_trap_irq_state, 1451 .process = sdma_v3_0_process_trap_irq, 1452 }; 1453 1454 static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = { 1455 .process = sdma_v3_0_process_illegal_inst_irq, 1456 }; 1457 1458 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev) 1459 { 1460 adev->sdma_trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 1461 adev->sdma_trap_irq.funcs = &sdma_v3_0_trap_irq_funcs; 1462 adev->sdma_illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs; 1463 } 1464 1465 /** 1466 * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine 1467 * 1468 * @ring: amdgpu_ring structure holding ring information 1469 * @src_offset: src GPU address 1470 * @dst_offset: dst GPU address 1471 * @byte_count: number of bytes to xfer 1472 * 1473 * Copy GPU buffers using the DMA engine (VI). 1474 * Used by the amdgpu ttm implementation to move pages if 1475 * registered as the asic copy callback. 1476 */ 1477 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib, 1478 uint64_t src_offset, 1479 uint64_t dst_offset, 1480 uint32_t byte_count) 1481 { 1482 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1483 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1484 ib->ptr[ib->length_dw++] = byte_count; 1485 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1486 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1487 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1488 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1489 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1490 } 1491 1492 /** 1493 * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine 1494 * 1495 * @ring: amdgpu_ring structure holding ring information 1496 * @src_data: value to write to buffer 1497 * @dst_offset: dst GPU address 1498 * @byte_count: number of bytes to xfer 1499 * 1500 * Fill GPU buffers using the DMA engine (VI). 1501 */ 1502 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ring *ring, 1503 uint32_t src_data, 1504 uint64_t dst_offset, 1505 uint32_t byte_count) 1506 { 1507 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL)); 1508 amdgpu_ring_write(ring, lower_32_bits(dst_offset)); 1509 amdgpu_ring_write(ring, upper_32_bits(dst_offset)); 1510 amdgpu_ring_write(ring, src_data); 1511 amdgpu_ring_write(ring, byte_count); 1512 } 1513 1514 static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = { 1515 .copy_max_bytes = 0x1fffff, 1516 .copy_num_dw = 7, 1517 .emit_copy_buffer = sdma_v3_0_emit_copy_buffer, 1518 1519 .fill_max_bytes = 0x1fffff, 1520 .fill_num_dw = 5, 1521 .emit_fill_buffer = sdma_v3_0_emit_fill_buffer, 1522 }; 1523 1524 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev) 1525 { 1526 if (adev->mman.buffer_funcs == NULL) { 1527 adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs; 1528 adev->mman.buffer_funcs_ring = &adev->sdma[0].ring; 1529 } 1530 } 1531 1532 static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = { 1533 .copy_pte = sdma_v3_0_vm_copy_pte, 1534 .write_pte = sdma_v3_0_vm_write_pte, 1535 .set_pte_pde = sdma_v3_0_vm_set_pte_pde, 1536 .pad_ib = sdma_v3_0_vm_pad_ib, 1537 }; 1538 1539 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1540 { 1541 if (adev->vm_manager.vm_pte_funcs == NULL) { 1542 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs; 1543 adev->vm_manager.vm_pte_funcs_ring = &adev->sdma[0].ring; 1544 adev->vm_manager.vm_pte_funcs_ring->is_pte_ring = true; 1545 } 1546 } 1547