1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 25 #include <linux/delay.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 #include "vi.h" 33 #include "vid.h" 34 35 #include "oss/oss_3_0_d.h" 36 #include "oss/oss_3_0_sh_mask.h" 37 38 #include "gmc/gmc_8_1_d.h" 39 #include "gmc/gmc_8_1_sh_mask.h" 40 41 #include "gca/gfx_8_0_d.h" 42 #include "gca/gfx_8_0_enum.h" 43 #include "gca/gfx_8_0_sh_mask.h" 44 45 #include "bif/bif_5_0_d.h" 46 #include "bif/bif_5_0_sh_mask.h" 47 48 #include "tonga_sdma_pkt_open.h" 49 50 #include "ivsrcid/ivsrcid_vislands30.h" 51 52 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev); 53 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev); 54 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev); 55 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev); 56 57 MODULE_FIRMWARE("amdgpu/tonga_sdma.bin"); 58 MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin"); 59 MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin"); 60 MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin"); 61 MODULE_FIRMWARE("amdgpu/fiji_sdma.bin"); 62 MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin"); 63 MODULE_FIRMWARE("amdgpu/stoney_sdma.bin"); 64 MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin"); 65 MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin"); 66 MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin"); 67 MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin"); 68 MODULE_FIRMWARE("amdgpu/polaris12_sdma.bin"); 69 MODULE_FIRMWARE("amdgpu/polaris12_sdma1.bin"); 70 MODULE_FIRMWARE("amdgpu/vegam_sdma.bin"); 71 MODULE_FIRMWARE("amdgpu/vegam_sdma1.bin"); 72 73 74 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = 75 { 76 SDMA0_REGISTER_OFFSET, 77 SDMA1_REGISTER_OFFSET 78 }; 79 80 static const u32 golden_settings_tonga_a11[] = 81 { 82 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 83 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 84 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 85 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 86 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 87 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 88 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 89 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 90 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 91 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 92 }; 93 94 static const u32 tonga_mgcg_cgcg_init[] = 95 { 96 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 97 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 98 }; 99 100 static const u32 golden_settings_fiji_a10[] = 101 { 102 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 103 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 104 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 105 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 106 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 107 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 108 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 109 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 110 }; 111 112 static const u32 fiji_mgcg_cgcg_init[] = 113 { 114 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 115 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 116 }; 117 118 static const u32 golden_settings_polaris11_a11[] = 119 { 120 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 121 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 122 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 123 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 124 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 125 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 126 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 127 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 128 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 129 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 130 }; 131 132 static const u32 golden_settings_polaris10_a11[] = 133 { 134 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 135 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 136 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 137 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 138 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 139 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 140 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 141 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 142 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 143 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 144 }; 145 146 static const u32 cz_golden_settings_a11[] = 147 { 148 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 149 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 150 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, 151 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, 152 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, 153 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, 154 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 155 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 156 mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100, 157 mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800, 158 mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100, 159 mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100, 160 }; 161 162 static const u32 cz_mgcg_cgcg_init[] = 163 { 164 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 165 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 166 }; 167 168 static const u32 stoney_golden_settings_a11[] = 169 { 170 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, 171 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, 172 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, 173 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, 174 }; 175 176 static const u32 stoney_mgcg_cgcg_init[] = 177 { 178 mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100, 179 }; 180 181 /* 182 * sDMA - System DMA 183 * Starting with CIK, the GPU has new asynchronous 184 * DMA engines. These engines are used for compute 185 * and gfx. There are two DMA engines (SDMA0, SDMA1) 186 * and each one supports 1 ring buffer used for gfx 187 * and 2 queues used for compute. 188 * 189 * The programming model is very similar to the CP 190 * (ring buffer, IBs, etc.), but sDMA has it's own 191 * packet format that is different from the PM4 format 192 * used by the CP. sDMA supports copying data, writing 193 * embedded data, solid fills, and a number of other 194 * things. It also has support for tiling/detiling of 195 * buffers. 196 */ 197 198 static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev) 199 { 200 switch (adev->asic_type) { 201 case CHIP_FIJI: 202 amdgpu_device_program_register_sequence(adev, 203 fiji_mgcg_cgcg_init, 204 ARRAY_SIZE(fiji_mgcg_cgcg_init)); 205 amdgpu_device_program_register_sequence(adev, 206 golden_settings_fiji_a10, 207 ARRAY_SIZE(golden_settings_fiji_a10)); 208 break; 209 case CHIP_TONGA: 210 amdgpu_device_program_register_sequence(adev, 211 tonga_mgcg_cgcg_init, 212 ARRAY_SIZE(tonga_mgcg_cgcg_init)); 213 amdgpu_device_program_register_sequence(adev, 214 golden_settings_tonga_a11, 215 ARRAY_SIZE(golden_settings_tonga_a11)); 216 break; 217 case CHIP_POLARIS11: 218 case CHIP_POLARIS12: 219 case CHIP_VEGAM: 220 amdgpu_device_program_register_sequence(adev, 221 golden_settings_polaris11_a11, 222 ARRAY_SIZE(golden_settings_polaris11_a11)); 223 break; 224 case CHIP_POLARIS10: 225 amdgpu_device_program_register_sequence(adev, 226 golden_settings_polaris10_a11, 227 ARRAY_SIZE(golden_settings_polaris10_a11)); 228 break; 229 case CHIP_CARRIZO: 230 amdgpu_device_program_register_sequence(adev, 231 cz_mgcg_cgcg_init, 232 ARRAY_SIZE(cz_mgcg_cgcg_init)); 233 amdgpu_device_program_register_sequence(adev, 234 cz_golden_settings_a11, 235 ARRAY_SIZE(cz_golden_settings_a11)); 236 break; 237 case CHIP_STONEY: 238 amdgpu_device_program_register_sequence(adev, 239 stoney_mgcg_cgcg_init, 240 ARRAY_SIZE(stoney_mgcg_cgcg_init)); 241 amdgpu_device_program_register_sequence(adev, 242 stoney_golden_settings_a11, 243 ARRAY_SIZE(stoney_golden_settings_a11)); 244 break; 245 default: 246 break; 247 } 248 } 249 250 static void sdma_v3_0_free_microcode(struct amdgpu_device *adev) 251 { 252 int i; 253 254 for (i = 0; i < adev->sdma.num_instances; i++) 255 amdgpu_ucode_release(&adev->sdma.instance[i].fw); 256 } 257 258 /** 259 * sdma_v3_0_init_microcode - load ucode images from disk 260 * 261 * @adev: amdgpu_device pointer 262 * 263 * Use the firmware interface to load the ucode images into 264 * the driver (not loaded into hw). 265 * Returns 0 on success, error on failure. 266 */ 267 static int sdma_v3_0_init_microcode(struct amdgpu_device *adev) 268 { 269 const char *chip_name; 270 char fw_name[30]; 271 int err = 0, i; 272 struct amdgpu_firmware_info *info = NULL; 273 const struct common_firmware_header *header = NULL; 274 const struct sdma_firmware_header_v1_0 *hdr; 275 276 DRM_DEBUG("\n"); 277 278 switch (adev->asic_type) { 279 case CHIP_TONGA: 280 chip_name = "tonga"; 281 break; 282 case CHIP_FIJI: 283 chip_name = "fiji"; 284 break; 285 case CHIP_POLARIS10: 286 chip_name = "polaris10"; 287 break; 288 case CHIP_POLARIS11: 289 chip_name = "polaris11"; 290 break; 291 case CHIP_POLARIS12: 292 chip_name = "polaris12"; 293 break; 294 case CHIP_VEGAM: 295 chip_name = "vegam"; 296 break; 297 case CHIP_CARRIZO: 298 chip_name = "carrizo"; 299 break; 300 case CHIP_STONEY: 301 chip_name = "stoney"; 302 break; 303 default: BUG(); 304 } 305 306 for (i = 0; i < adev->sdma.num_instances; i++) { 307 if (i == 0) 308 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 309 else 310 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); 311 err = amdgpu_ucode_request(adev, &adev->sdma.instance[i].fw, fw_name); 312 if (err) 313 goto out; 314 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 315 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 316 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 317 if (adev->sdma.instance[i].feature_version >= 20) 318 adev->sdma.instance[i].burst_nop = true; 319 320 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 321 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 322 info->fw = adev->sdma.instance[i].fw; 323 header = (const struct common_firmware_header *)info->fw->data; 324 adev->firmware.fw_size += 325 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 326 327 } 328 out: 329 if (err) { 330 pr_err("sdma_v3_0: Failed to load firmware \"%s\"\n", fw_name); 331 for (i = 0; i < adev->sdma.num_instances; i++) 332 amdgpu_ucode_release(&adev->sdma.instance[i].fw); 333 } 334 return err; 335 } 336 337 /** 338 * sdma_v3_0_ring_get_rptr - get the current read pointer 339 * 340 * @ring: amdgpu ring pointer 341 * 342 * Get the current rptr from the hardware (VI+). 343 */ 344 static uint64_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring) 345 { 346 /* XXX check if swapping is necessary on BE */ 347 return *ring->rptr_cpu_addr >> 2; 348 } 349 350 /** 351 * sdma_v3_0_ring_get_wptr - get the current write pointer 352 * 353 * @ring: amdgpu ring pointer 354 * 355 * Get the current wptr from the hardware (VI+). 356 */ 357 static uint64_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring) 358 { 359 struct amdgpu_device *adev = ring->adev; 360 u32 wptr; 361 362 if (ring->use_doorbell || ring->use_pollmem) { 363 /* XXX check if swapping is necessary on BE */ 364 wptr = *ring->wptr_cpu_addr >> 2; 365 } else { 366 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2; 367 } 368 369 return wptr; 370 } 371 372 /** 373 * sdma_v3_0_ring_set_wptr - commit the write pointer 374 * 375 * @ring: amdgpu ring pointer 376 * 377 * Write the wptr back to the hardware (VI+). 378 */ 379 static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring) 380 { 381 struct amdgpu_device *adev = ring->adev; 382 383 if (ring->use_doorbell) { 384 u32 *wb = (u32 *)ring->wptr_cpu_addr; 385 /* XXX check if swapping is necessary on BE */ 386 WRITE_ONCE(*wb, ring->wptr << 2); 387 WDOORBELL32(ring->doorbell_index, ring->wptr << 2); 388 } else if (ring->use_pollmem) { 389 u32 *wb = (u32 *)ring->wptr_cpu_addr; 390 391 WRITE_ONCE(*wb, ring->wptr << 2); 392 } else { 393 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], ring->wptr << 2); 394 } 395 } 396 397 static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 398 { 399 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 400 int i; 401 402 for (i = 0; i < count; i++) 403 if (sdma && sdma->burst_nop && (i == 0)) 404 amdgpu_ring_write(ring, ring->funcs->nop | 405 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 406 else 407 amdgpu_ring_write(ring, ring->funcs->nop); 408 } 409 410 /** 411 * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine 412 * 413 * @ring: amdgpu ring pointer 414 * @job: job to retrieve vmid from 415 * @ib: IB object to schedule 416 * @flags: unused 417 * 418 * Schedule an IB in the DMA ring (VI). 419 */ 420 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring, 421 struct amdgpu_job *job, 422 struct amdgpu_ib *ib, 423 uint32_t flags) 424 { 425 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 426 427 /* IB packet must end on a 8 DW boundary */ 428 sdma_v3_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 429 430 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 431 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 432 /* base must be 32 byte aligned */ 433 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 434 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 435 amdgpu_ring_write(ring, ib->length_dw); 436 amdgpu_ring_write(ring, 0); 437 amdgpu_ring_write(ring, 0); 438 439 } 440 441 /** 442 * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 443 * 444 * @ring: amdgpu ring pointer 445 * 446 * Emit an hdp flush packet on the requested DMA ring. 447 */ 448 static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 449 { 450 u32 ref_and_mask = 0; 451 452 if (ring->me == 0) 453 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); 454 else 455 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); 456 457 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 458 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 459 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 460 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); 461 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); 462 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 463 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 464 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 465 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 466 } 467 468 /** 469 * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring 470 * 471 * @ring: amdgpu ring pointer 472 * @addr: address 473 * @seq: sequence number 474 * @flags: fence related flags 475 * 476 * Add a DMA fence packet to the ring to write 477 * the fence seq number and DMA trap packet to generate 478 * an interrupt if needed (VI). 479 */ 480 static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 481 unsigned flags) 482 { 483 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 484 /* write the fence */ 485 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 486 amdgpu_ring_write(ring, lower_32_bits(addr)); 487 amdgpu_ring_write(ring, upper_32_bits(addr)); 488 amdgpu_ring_write(ring, lower_32_bits(seq)); 489 490 /* optionally write high bits as well */ 491 if (write64bit) { 492 addr += 4; 493 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 494 amdgpu_ring_write(ring, lower_32_bits(addr)); 495 amdgpu_ring_write(ring, upper_32_bits(addr)); 496 amdgpu_ring_write(ring, upper_32_bits(seq)); 497 } 498 499 /* generate an interrupt */ 500 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 501 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 502 } 503 504 /** 505 * sdma_v3_0_gfx_stop - stop the gfx async dma engines 506 * 507 * @adev: amdgpu_device pointer 508 * 509 * Stop the gfx async dma ring buffers (VI). 510 */ 511 static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev) 512 { 513 u32 rb_cntl, ib_cntl; 514 int i; 515 516 amdgpu_sdma_unset_buffer_funcs_helper(adev); 517 518 for (i = 0; i < adev->sdma.num_instances; i++) { 519 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 520 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 521 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 522 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 523 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 524 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 525 } 526 } 527 528 /** 529 * sdma_v3_0_rlc_stop - stop the compute async dma engines 530 * 531 * @adev: amdgpu_device pointer 532 * 533 * Stop the compute async dma queues (VI). 534 */ 535 static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev) 536 { 537 /* XXX todo */ 538 } 539 540 /** 541 * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch 542 * 543 * @adev: amdgpu_device pointer 544 * @enable: enable/disable the DMA MEs context switch. 545 * 546 * Halt or unhalt the async dma engines context switch (VI). 547 */ 548 static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 549 { 550 u32 f32_cntl, phase_quantum = 0; 551 int i; 552 553 if (amdgpu_sdma_phase_quantum) { 554 unsigned value = amdgpu_sdma_phase_quantum; 555 unsigned unit = 0; 556 557 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 558 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 559 value = (value + 1) >> 1; 560 unit++; 561 } 562 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 563 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 564 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 565 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 566 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 567 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 568 WARN_ONCE(1, 569 "clamping sdma_phase_quantum to %uK clock cycles\n", 570 value << unit); 571 } 572 phase_quantum = 573 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 574 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 575 } 576 577 for (i = 0; i < adev->sdma.num_instances; i++) { 578 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); 579 if (enable) { 580 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 581 AUTO_CTXSW_ENABLE, 1); 582 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 583 ATC_L1_ENABLE, 1); 584 if (amdgpu_sdma_phase_quantum) { 585 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i], 586 phase_quantum); 587 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i], 588 phase_quantum); 589 } 590 } else { 591 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 592 AUTO_CTXSW_ENABLE, 0); 593 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 594 ATC_L1_ENABLE, 1); 595 } 596 597 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); 598 } 599 } 600 601 /** 602 * sdma_v3_0_enable - stop the async dma engines 603 * 604 * @adev: amdgpu_device pointer 605 * @enable: enable/disable the DMA MEs. 606 * 607 * Halt or unhalt the async dma engines (VI). 608 */ 609 static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable) 610 { 611 u32 f32_cntl; 612 int i; 613 614 if (!enable) { 615 sdma_v3_0_gfx_stop(adev); 616 sdma_v3_0_rlc_stop(adev); 617 } 618 619 for (i = 0; i < adev->sdma.num_instances; i++) { 620 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); 621 if (enable) 622 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); 623 else 624 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); 625 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); 626 } 627 } 628 629 /** 630 * sdma_v3_0_gfx_resume - setup and start the async dma engines 631 * 632 * @adev: amdgpu_device pointer 633 * 634 * Set up the gfx DMA ring buffers and enable them (VI). 635 * Returns 0 for success, error for failure. 636 */ 637 static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) 638 { 639 struct amdgpu_ring *ring; 640 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 641 u32 rb_bufsz; 642 u32 doorbell; 643 u64 wptr_gpu_addr; 644 int i, j, r; 645 646 for (i = 0; i < adev->sdma.num_instances; i++) { 647 ring = &adev->sdma.instance[i].ring; 648 amdgpu_ring_clear_ring(ring); 649 650 mutex_lock(&adev->srbm_mutex); 651 for (j = 0; j < 16; j++) { 652 vi_srbm_select(adev, 0, 0, 0, j); 653 /* SDMA GFX */ 654 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); 655 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); 656 } 657 vi_srbm_select(adev, 0, 0, 0, 0); 658 mutex_unlock(&adev->srbm_mutex); 659 660 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], 661 adev->gfx.config.gb_addr_config & 0x70); 662 663 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); 664 665 /* Set ring buffer size in dwords */ 666 rb_bufsz = order_base_2(ring->ring_size / 4); 667 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 668 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 669 #ifdef __BIG_ENDIAN 670 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 671 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 672 RPTR_WRITEBACK_SWAP_ENABLE, 1); 673 #endif 674 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 675 676 /* Initialize the ring buffer's read and write pointers */ 677 ring->wptr = 0; 678 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); 679 sdma_v3_0_ring_set_wptr(ring); 680 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); 681 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); 682 683 /* set the wb address whether it's enabled or not */ 684 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], 685 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); 686 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], 687 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); 688 689 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 690 691 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); 692 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); 693 694 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]); 695 696 if (ring->use_doorbell) { 697 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, 698 OFFSET, ring->doorbell_index); 699 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 700 } else { 701 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 702 } 703 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell); 704 705 /* setup the wptr shadow polling */ 706 wptr_gpu_addr = ring->wptr_gpu_addr; 707 708 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i], 709 lower_32_bits(wptr_gpu_addr)); 710 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i], 711 upper_32_bits(wptr_gpu_addr)); 712 wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]); 713 if (ring->use_pollmem) { 714 /*wptr polling is not enogh fast, directly clean the wptr register */ 715 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); 716 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 717 SDMA0_GFX_RB_WPTR_POLL_CNTL, 718 ENABLE, 1); 719 } else { 720 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 721 SDMA0_GFX_RB_WPTR_POLL_CNTL, 722 ENABLE, 0); 723 } 724 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i], wptr_poll_cntl); 725 726 /* enable DMA RB */ 727 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 728 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 729 730 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 731 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 732 #ifdef __BIG_ENDIAN 733 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 734 #endif 735 /* enable DMA IBs */ 736 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 737 738 ring->sched.ready = true; 739 } 740 741 /* unhalt the MEs */ 742 sdma_v3_0_enable(adev, true); 743 /* enable sdma ring preemption */ 744 sdma_v3_0_ctx_switch_enable(adev, true); 745 746 for (i = 0; i < adev->sdma.num_instances; i++) { 747 ring = &adev->sdma.instance[i].ring; 748 r = amdgpu_ring_test_helper(ring); 749 if (r) 750 return r; 751 752 if (adev->mman.buffer_funcs_ring == ring) 753 amdgpu_ttm_set_buffer_funcs_status(adev, true); 754 } 755 756 return 0; 757 } 758 759 /** 760 * sdma_v3_0_rlc_resume - setup and start the async dma engines 761 * 762 * @adev: amdgpu_device pointer 763 * 764 * Set up the compute DMA queues and enable them (VI). 765 * Returns 0 for success, error for failure. 766 */ 767 static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev) 768 { 769 /* XXX todo */ 770 return 0; 771 } 772 773 /** 774 * sdma_v3_0_start - setup and start the async dma engines 775 * 776 * @adev: amdgpu_device pointer 777 * 778 * Set up the DMA engines and enable them (VI). 779 * Returns 0 for success, error for failure. 780 */ 781 static int sdma_v3_0_start(struct amdgpu_device *adev) 782 { 783 int r; 784 785 /* disable sdma engine before programing it */ 786 sdma_v3_0_ctx_switch_enable(adev, false); 787 sdma_v3_0_enable(adev, false); 788 789 /* start the gfx rings and rlc compute queues */ 790 r = sdma_v3_0_gfx_resume(adev); 791 if (r) 792 return r; 793 r = sdma_v3_0_rlc_resume(adev); 794 if (r) 795 return r; 796 797 return 0; 798 } 799 800 /** 801 * sdma_v3_0_ring_test_ring - simple async dma engine test 802 * 803 * @ring: amdgpu_ring structure holding ring information 804 * 805 * Test the DMA engine by writing using it to write an 806 * value to memory. (VI). 807 * Returns 0 for success, error for failure. 808 */ 809 static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring) 810 { 811 struct amdgpu_device *adev = ring->adev; 812 unsigned i; 813 unsigned index; 814 int r; 815 u32 tmp; 816 u64 gpu_addr; 817 818 r = amdgpu_device_wb_get(adev, &index); 819 if (r) 820 return r; 821 822 gpu_addr = adev->wb.gpu_addr + (index * 4); 823 tmp = 0xCAFEDEAD; 824 adev->wb.wb[index] = cpu_to_le32(tmp); 825 826 r = amdgpu_ring_alloc(ring, 5); 827 if (r) 828 goto error_free_wb; 829 830 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 831 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 832 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 833 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 834 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); 835 amdgpu_ring_write(ring, 0xDEADBEEF); 836 amdgpu_ring_commit(ring); 837 838 for (i = 0; i < adev->usec_timeout; i++) { 839 tmp = le32_to_cpu(adev->wb.wb[index]); 840 if (tmp == 0xDEADBEEF) 841 break; 842 udelay(1); 843 } 844 845 if (i >= adev->usec_timeout) 846 r = -ETIMEDOUT; 847 848 error_free_wb: 849 amdgpu_device_wb_free(adev, index); 850 return r; 851 } 852 853 /** 854 * sdma_v3_0_ring_test_ib - test an IB on the DMA engine 855 * 856 * @ring: amdgpu_ring structure holding ring information 857 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 858 * 859 * Test a simple IB in the DMA ring (VI). 860 * Returns 0 on success, error on failure. 861 */ 862 static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 863 { 864 struct amdgpu_device *adev = ring->adev; 865 struct amdgpu_ib ib; 866 struct dma_fence *f = NULL; 867 unsigned index; 868 u32 tmp = 0; 869 u64 gpu_addr; 870 long r; 871 872 r = amdgpu_device_wb_get(adev, &index); 873 if (r) 874 return r; 875 876 gpu_addr = adev->wb.gpu_addr + (index * 4); 877 tmp = 0xCAFEDEAD; 878 adev->wb.wb[index] = cpu_to_le32(tmp); 879 memset(&ib, 0, sizeof(ib)); 880 r = amdgpu_ib_get(adev, NULL, 256, 881 AMDGPU_IB_POOL_DIRECT, &ib); 882 if (r) 883 goto err0; 884 885 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 886 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 887 ib.ptr[1] = lower_32_bits(gpu_addr); 888 ib.ptr[2] = upper_32_bits(gpu_addr); 889 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1); 890 ib.ptr[4] = 0xDEADBEEF; 891 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 892 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 893 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 894 ib.length_dw = 8; 895 896 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 897 if (r) 898 goto err1; 899 900 r = dma_fence_wait_timeout(f, false, timeout); 901 if (r == 0) { 902 r = -ETIMEDOUT; 903 goto err1; 904 } else if (r < 0) { 905 goto err1; 906 } 907 tmp = le32_to_cpu(adev->wb.wb[index]); 908 if (tmp == 0xDEADBEEF) 909 r = 0; 910 else 911 r = -EINVAL; 912 err1: 913 amdgpu_ib_free(adev, &ib, NULL); 914 dma_fence_put(f); 915 err0: 916 amdgpu_device_wb_free(adev, index); 917 return r; 918 } 919 920 /** 921 * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART 922 * 923 * @ib: indirect buffer to fill with commands 924 * @pe: addr of the page entry 925 * @src: src addr to copy from 926 * @count: number of page entries to update 927 * 928 * Update PTEs by copying them from the GART using sDMA (CIK). 929 */ 930 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib, 931 uint64_t pe, uint64_t src, 932 unsigned count) 933 { 934 unsigned bytes = count * 8; 935 936 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 937 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 938 ib->ptr[ib->length_dw++] = bytes; 939 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 940 ib->ptr[ib->length_dw++] = lower_32_bits(src); 941 ib->ptr[ib->length_dw++] = upper_32_bits(src); 942 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 943 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 944 } 945 946 /** 947 * sdma_v3_0_vm_write_pte - update PTEs by writing them manually 948 * 949 * @ib: indirect buffer to fill with commands 950 * @pe: addr of the page entry 951 * @value: dst addr to write into pe 952 * @count: number of page entries to update 953 * @incr: increase next addr by incr bytes 954 * 955 * Update PTEs by writing them manually using sDMA (CIK). 956 */ 957 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 958 uint64_t value, unsigned count, 959 uint32_t incr) 960 { 961 unsigned ndw = count * 2; 962 963 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 964 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 965 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 966 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 967 ib->ptr[ib->length_dw++] = ndw; 968 for (; ndw > 0; ndw -= 2) { 969 ib->ptr[ib->length_dw++] = lower_32_bits(value); 970 ib->ptr[ib->length_dw++] = upper_32_bits(value); 971 value += incr; 972 } 973 } 974 975 /** 976 * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA 977 * 978 * @ib: indirect buffer to fill with commands 979 * @pe: addr of the page entry 980 * @addr: dst addr to write into pe 981 * @count: number of page entries to update 982 * @incr: increase next addr by incr bytes 983 * @flags: access flags 984 * 985 * Update the page tables using sDMA (CIK). 986 */ 987 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe, 988 uint64_t addr, unsigned count, 989 uint32_t incr, uint64_t flags) 990 { 991 /* for physically contiguous pages (vram) */ 992 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE); 993 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 994 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 995 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 996 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 997 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 998 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 999 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1000 ib->ptr[ib->length_dw++] = 0; 1001 ib->ptr[ib->length_dw++] = count; /* number of entries */ 1002 } 1003 1004 /** 1005 * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw 1006 * 1007 * @ring: amdgpu_ring structure holding ring information 1008 * @ib: indirect buffer to fill with padding 1009 * 1010 */ 1011 static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1012 { 1013 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1014 u32 pad_count; 1015 int i; 1016 1017 pad_count = (-ib->length_dw) & 7; 1018 for (i = 0; i < pad_count; i++) 1019 if (sdma && sdma->burst_nop && (i == 0)) 1020 ib->ptr[ib->length_dw++] = 1021 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1022 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1023 else 1024 ib->ptr[ib->length_dw++] = 1025 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1026 } 1027 1028 /** 1029 * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline 1030 * 1031 * @ring: amdgpu_ring pointer 1032 * 1033 * Make sure all previous operations are completed (CIK). 1034 */ 1035 static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1036 { 1037 uint32_t seq = ring->fence_drv.sync_seq; 1038 uint64_t addr = ring->fence_drv.gpu_addr; 1039 1040 /* wait for idle */ 1041 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1042 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1043 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1044 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1045 amdgpu_ring_write(ring, addr & 0xfffffffc); 1046 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1047 amdgpu_ring_write(ring, seq); /* reference */ 1048 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1049 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1050 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1051 } 1052 1053 /** 1054 * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA 1055 * 1056 * @ring: amdgpu_ring pointer 1057 * @vmid: vmid number to use 1058 * @pd_addr: address 1059 * 1060 * Update the page table base and flush the VM TLB 1061 * using sDMA (VI). 1062 */ 1063 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1064 unsigned vmid, uint64_t pd_addr) 1065 { 1066 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1067 1068 /* wait for flush */ 1069 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1070 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1071 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */ 1072 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); 1073 amdgpu_ring_write(ring, 0); 1074 amdgpu_ring_write(ring, 0); /* reference */ 1075 amdgpu_ring_write(ring, 0); /* mask */ 1076 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1077 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 1078 } 1079 1080 static void sdma_v3_0_ring_emit_wreg(struct amdgpu_ring *ring, 1081 uint32_t reg, uint32_t val) 1082 { 1083 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1084 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1085 amdgpu_ring_write(ring, reg); 1086 amdgpu_ring_write(ring, val); 1087 } 1088 1089 static int sdma_v3_0_early_init(void *handle) 1090 { 1091 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1092 1093 switch (adev->asic_type) { 1094 case CHIP_STONEY: 1095 adev->sdma.num_instances = 1; 1096 break; 1097 default: 1098 adev->sdma.num_instances = SDMA_MAX_INSTANCE; 1099 break; 1100 } 1101 1102 sdma_v3_0_set_ring_funcs(adev); 1103 sdma_v3_0_set_buffer_funcs(adev); 1104 sdma_v3_0_set_vm_pte_funcs(adev); 1105 sdma_v3_0_set_irq_funcs(adev); 1106 1107 return 0; 1108 } 1109 1110 static int sdma_v3_0_sw_init(void *handle) 1111 { 1112 struct amdgpu_ring *ring; 1113 int r, i; 1114 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1115 1116 /* SDMA trap event */ 1117 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP, 1118 &adev->sdma.trap_irq); 1119 if (r) 1120 return r; 1121 1122 /* SDMA Privileged inst */ 1123 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 241, 1124 &adev->sdma.illegal_inst_irq); 1125 if (r) 1126 return r; 1127 1128 /* SDMA Privileged inst */ 1129 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE, 1130 &adev->sdma.illegal_inst_irq); 1131 if (r) 1132 return r; 1133 1134 r = sdma_v3_0_init_microcode(adev); 1135 if (r) { 1136 DRM_ERROR("Failed to load sdma firmware!\n"); 1137 return r; 1138 } 1139 1140 for (i = 0; i < adev->sdma.num_instances; i++) { 1141 ring = &adev->sdma.instance[i].ring; 1142 ring->ring_obj = NULL; 1143 if (!amdgpu_sriov_vf(adev)) { 1144 ring->use_doorbell = true; 1145 ring->doorbell_index = adev->doorbell_index.sdma_engine[i]; 1146 } else { 1147 ring->use_pollmem = true; 1148 } 1149 1150 sprintf(ring->name, "sdma%d", i); 1151 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1152 (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 : 1153 AMDGPU_SDMA_IRQ_INSTANCE1, 1154 AMDGPU_RING_PRIO_DEFAULT, NULL); 1155 if (r) 1156 return r; 1157 } 1158 1159 return r; 1160 } 1161 1162 static int sdma_v3_0_sw_fini(void *handle) 1163 { 1164 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1165 int i; 1166 1167 for (i = 0; i < adev->sdma.num_instances; i++) 1168 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1169 1170 sdma_v3_0_free_microcode(adev); 1171 return 0; 1172 } 1173 1174 static int sdma_v3_0_hw_init(void *handle) 1175 { 1176 int r; 1177 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1178 1179 sdma_v3_0_init_golden_registers(adev); 1180 1181 r = sdma_v3_0_start(adev); 1182 if (r) 1183 return r; 1184 1185 return r; 1186 } 1187 1188 static int sdma_v3_0_hw_fini(void *handle) 1189 { 1190 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1191 1192 sdma_v3_0_ctx_switch_enable(adev, false); 1193 sdma_v3_0_enable(adev, false); 1194 1195 return 0; 1196 } 1197 1198 static int sdma_v3_0_suspend(void *handle) 1199 { 1200 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1201 1202 return sdma_v3_0_hw_fini(adev); 1203 } 1204 1205 static int sdma_v3_0_resume(void *handle) 1206 { 1207 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1208 1209 return sdma_v3_0_hw_init(adev); 1210 } 1211 1212 static bool sdma_v3_0_is_idle(void *handle) 1213 { 1214 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1215 u32 tmp = RREG32(mmSRBM_STATUS2); 1216 1217 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | 1218 SRBM_STATUS2__SDMA1_BUSY_MASK)) 1219 return false; 1220 1221 return true; 1222 } 1223 1224 static int sdma_v3_0_wait_for_idle(void *handle) 1225 { 1226 unsigned i; 1227 u32 tmp; 1228 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1229 1230 for (i = 0; i < adev->usec_timeout; i++) { 1231 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | 1232 SRBM_STATUS2__SDMA1_BUSY_MASK); 1233 1234 if (!tmp) 1235 return 0; 1236 udelay(1); 1237 } 1238 return -ETIMEDOUT; 1239 } 1240 1241 static bool sdma_v3_0_check_soft_reset(void *handle) 1242 { 1243 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1244 u32 srbm_soft_reset = 0; 1245 u32 tmp = RREG32(mmSRBM_STATUS2); 1246 1247 if ((tmp & SRBM_STATUS2__SDMA_BUSY_MASK) || 1248 (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)) { 1249 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK; 1250 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK; 1251 } 1252 1253 if (srbm_soft_reset) { 1254 adev->sdma.srbm_soft_reset = srbm_soft_reset; 1255 return true; 1256 } else { 1257 adev->sdma.srbm_soft_reset = 0; 1258 return false; 1259 } 1260 } 1261 1262 static int sdma_v3_0_pre_soft_reset(void *handle) 1263 { 1264 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1265 u32 srbm_soft_reset = 0; 1266 1267 if (!adev->sdma.srbm_soft_reset) 1268 return 0; 1269 1270 srbm_soft_reset = adev->sdma.srbm_soft_reset; 1271 1272 if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) || 1273 REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) { 1274 sdma_v3_0_ctx_switch_enable(adev, false); 1275 sdma_v3_0_enable(adev, false); 1276 } 1277 1278 return 0; 1279 } 1280 1281 static int sdma_v3_0_post_soft_reset(void *handle) 1282 { 1283 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1284 u32 srbm_soft_reset = 0; 1285 1286 if (!adev->sdma.srbm_soft_reset) 1287 return 0; 1288 1289 srbm_soft_reset = adev->sdma.srbm_soft_reset; 1290 1291 if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) || 1292 REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) { 1293 sdma_v3_0_gfx_resume(adev); 1294 sdma_v3_0_rlc_resume(adev); 1295 } 1296 1297 return 0; 1298 } 1299 1300 static int sdma_v3_0_soft_reset(void *handle) 1301 { 1302 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1303 u32 srbm_soft_reset = 0; 1304 u32 tmp; 1305 1306 if (!adev->sdma.srbm_soft_reset) 1307 return 0; 1308 1309 srbm_soft_reset = adev->sdma.srbm_soft_reset; 1310 1311 if (srbm_soft_reset) { 1312 tmp = RREG32(mmSRBM_SOFT_RESET); 1313 tmp |= srbm_soft_reset; 1314 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1315 WREG32(mmSRBM_SOFT_RESET, tmp); 1316 tmp = RREG32(mmSRBM_SOFT_RESET); 1317 1318 udelay(50); 1319 1320 tmp &= ~srbm_soft_reset; 1321 WREG32(mmSRBM_SOFT_RESET, tmp); 1322 tmp = RREG32(mmSRBM_SOFT_RESET); 1323 1324 /* Wait a little for things to settle down */ 1325 udelay(50); 1326 } 1327 1328 return 0; 1329 } 1330 1331 static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev, 1332 struct amdgpu_irq_src *source, 1333 unsigned type, 1334 enum amdgpu_interrupt_state state) 1335 { 1336 u32 sdma_cntl; 1337 1338 switch (type) { 1339 case AMDGPU_SDMA_IRQ_INSTANCE0: 1340 switch (state) { 1341 case AMDGPU_IRQ_STATE_DISABLE: 1342 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1343 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1344 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1345 break; 1346 case AMDGPU_IRQ_STATE_ENABLE: 1347 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1348 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1349 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1350 break; 1351 default: 1352 break; 1353 } 1354 break; 1355 case AMDGPU_SDMA_IRQ_INSTANCE1: 1356 switch (state) { 1357 case AMDGPU_IRQ_STATE_DISABLE: 1358 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1359 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1360 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1361 break; 1362 case AMDGPU_IRQ_STATE_ENABLE: 1363 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1364 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1365 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1366 break; 1367 default: 1368 break; 1369 } 1370 break; 1371 default: 1372 break; 1373 } 1374 return 0; 1375 } 1376 1377 static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev, 1378 struct amdgpu_irq_src *source, 1379 struct amdgpu_iv_entry *entry) 1380 { 1381 u8 instance_id, queue_id; 1382 1383 instance_id = (entry->ring_id & 0x3) >> 0; 1384 queue_id = (entry->ring_id & 0xc) >> 2; 1385 DRM_DEBUG("IH: SDMA trap\n"); 1386 switch (instance_id) { 1387 case 0: 1388 switch (queue_id) { 1389 case 0: 1390 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1391 break; 1392 case 1: 1393 /* XXX compute */ 1394 break; 1395 case 2: 1396 /* XXX compute */ 1397 break; 1398 } 1399 break; 1400 case 1: 1401 switch (queue_id) { 1402 case 0: 1403 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1404 break; 1405 case 1: 1406 /* XXX compute */ 1407 break; 1408 case 2: 1409 /* XXX compute */ 1410 break; 1411 } 1412 break; 1413 } 1414 return 0; 1415 } 1416 1417 static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1418 struct amdgpu_irq_src *source, 1419 struct amdgpu_iv_entry *entry) 1420 { 1421 u8 instance_id, queue_id; 1422 1423 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1424 instance_id = (entry->ring_id & 0x3) >> 0; 1425 queue_id = (entry->ring_id & 0xc) >> 2; 1426 1427 if (instance_id <= 1 && queue_id == 0) 1428 drm_sched_fault(&adev->sdma.instance[instance_id].ring.sched); 1429 return 0; 1430 } 1431 1432 static void sdma_v3_0_update_sdma_medium_grain_clock_gating( 1433 struct amdgpu_device *adev, 1434 bool enable) 1435 { 1436 uint32_t temp, data; 1437 int i; 1438 1439 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1440 for (i = 0; i < adev->sdma.num_instances; i++) { 1441 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]); 1442 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1443 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1444 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1445 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1446 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1447 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1448 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1449 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1450 if (data != temp) 1451 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); 1452 } 1453 } else { 1454 for (i = 0; i < adev->sdma.num_instances; i++) { 1455 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]); 1456 data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1457 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1458 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1459 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1460 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1461 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1462 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1463 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK; 1464 1465 if (data != temp) 1466 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); 1467 } 1468 } 1469 } 1470 1471 static void sdma_v3_0_update_sdma_medium_grain_light_sleep( 1472 struct amdgpu_device *adev, 1473 bool enable) 1474 { 1475 uint32_t temp, data; 1476 int i; 1477 1478 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1479 for (i = 0; i < adev->sdma.num_instances; i++) { 1480 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); 1481 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1482 1483 if (temp != data) 1484 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); 1485 } 1486 } else { 1487 for (i = 0; i < adev->sdma.num_instances; i++) { 1488 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); 1489 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1490 1491 if (temp != data) 1492 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); 1493 } 1494 } 1495 } 1496 1497 static int sdma_v3_0_set_clockgating_state(void *handle, 1498 enum amd_clockgating_state state) 1499 { 1500 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1501 1502 if (amdgpu_sriov_vf(adev)) 1503 return 0; 1504 1505 switch (adev->asic_type) { 1506 case CHIP_FIJI: 1507 case CHIP_CARRIZO: 1508 case CHIP_STONEY: 1509 sdma_v3_0_update_sdma_medium_grain_clock_gating(adev, 1510 state == AMD_CG_STATE_GATE); 1511 sdma_v3_0_update_sdma_medium_grain_light_sleep(adev, 1512 state == AMD_CG_STATE_GATE); 1513 break; 1514 default: 1515 break; 1516 } 1517 return 0; 1518 } 1519 1520 static int sdma_v3_0_set_powergating_state(void *handle, 1521 enum amd_powergating_state state) 1522 { 1523 return 0; 1524 } 1525 1526 static void sdma_v3_0_get_clockgating_state(void *handle, u64 *flags) 1527 { 1528 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1529 int data; 1530 1531 if (amdgpu_sriov_vf(adev)) 1532 *flags = 0; 1533 1534 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1535 data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[0]); 1536 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK)) 1537 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1538 1539 /* AMD_CG_SUPPORT_SDMA_LS */ 1540 data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[0]); 1541 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1542 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1543 } 1544 1545 static const struct amd_ip_funcs sdma_v3_0_ip_funcs = { 1546 .name = "sdma_v3_0", 1547 .early_init = sdma_v3_0_early_init, 1548 .late_init = NULL, 1549 .sw_init = sdma_v3_0_sw_init, 1550 .sw_fini = sdma_v3_0_sw_fini, 1551 .hw_init = sdma_v3_0_hw_init, 1552 .hw_fini = sdma_v3_0_hw_fini, 1553 .suspend = sdma_v3_0_suspend, 1554 .resume = sdma_v3_0_resume, 1555 .is_idle = sdma_v3_0_is_idle, 1556 .wait_for_idle = sdma_v3_0_wait_for_idle, 1557 .check_soft_reset = sdma_v3_0_check_soft_reset, 1558 .pre_soft_reset = sdma_v3_0_pre_soft_reset, 1559 .post_soft_reset = sdma_v3_0_post_soft_reset, 1560 .soft_reset = sdma_v3_0_soft_reset, 1561 .set_clockgating_state = sdma_v3_0_set_clockgating_state, 1562 .set_powergating_state = sdma_v3_0_set_powergating_state, 1563 .get_clockgating_state = sdma_v3_0_get_clockgating_state, 1564 }; 1565 1566 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { 1567 .type = AMDGPU_RING_TYPE_SDMA, 1568 .align_mask = 0xf, 1569 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1570 .support_64bit_ptrs = false, 1571 .secure_submission_supported = true, 1572 .get_rptr = sdma_v3_0_ring_get_rptr, 1573 .get_wptr = sdma_v3_0_ring_get_wptr, 1574 .set_wptr = sdma_v3_0_ring_set_wptr, 1575 .emit_frame_size = 1576 6 + /* sdma_v3_0_ring_emit_hdp_flush */ 1577 3 + /* hdp invalidate */ 1578 6 + /* sdma_v3_0_ring_emit_pipeline_sync */ 1579 VI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v3_0_ring_emit_vm_flush */ 1580 10 + 10 + 10, /* sdma_v3_0_ring_emit_fence x3 for user fence, vm fence */ 1581 .emit_ib_size = 7 + 6, /* sdma_v3_0_ring_emit_ib */ 1582 .emit_ib = sdma_v3_0_ring_emit_ib, 1583 .emit_fence = sdma_v3_0_ring_emit_fence, 1584 .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync, 1585 .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush, 1586 .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush, 1587 .test_ring = sdma_v3_0_ring_test_ring, 1588 .test_ib = sdma_v3_0_ring_test_ib, 1589 .insert_nop = sdma_v3_0_ring_insert_nop, 1590 .pad_ib = sdma_v3_0_ring_pad_ib, 1591 .emit_wreg = sdma_v3_0_ring_emit_wreg, 1592 }; 1593 1594 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev) 1595 { 1596 int i; 1597 1598 for (i = 0; i < adev->sdma.num_instances; i++) { 1599 adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs; 1600 adev->sdma.instance[i].ring.me = i; 1601 } 1602 } 1603 1604 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = { 1605 .set = sdma_v3_0_set_trap_irq_state, 1606 .process = sdma_v3_0_process_trap_irq, 1607 }; 1608 1609 static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = { 1610 .process = sdma_v3_0_process_illegal_inst_irq, 1611 }; 1612 1613 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev) 1614 { 1615 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 1616 adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs; 1617 adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs; 1618 } 1619 1620 /** 1621 * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine 1622 * 1623 * @ib: indirect buffer to copy to 1624 * @src_offset: src GPU address 1625 * @dst_offset: dst GPU address 1626 * @byte_count: number of bytes to xfer 1627 * @tmz: unused 1628 * 1629 * Copy GPU buffers using the DMA engine (VI). 1630 * Used by the amdgpu ttm implementation to move pages if 1631 * registered as the asic copy callback. 1632 */ 1633 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib, 1634 uint64_t src_offset, 1635 uint64_t dst_offset, 1636 uint32_t byte_count, 1637 bool tmz) 1638 { 1639 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1640 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1641 ib->ptr[ib->length_dw++] = byte_count; 1642 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1643 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1644 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1645 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1646 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1647 } 1648 1649 /** 1650 * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine 1651 * 1652 * @ib: indirect buffer to copy to 1653 * @src_data: value to write to buffer 1654 * @dst_offset: dst GPU address 1655 * @byte_count: number of bytes to xfer 1656 * 1657 * Fill GPU buffers using the DMA engine (VI). 1658 */ 1659 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib, 1660 uint32_t src_data, 1661 uint64_t dst_offset, 1662 uint32_t byte_count) 1663 { 1664 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1665 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1666 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1667 ib->ptr[ib->length_dw++] = src_data; 1668 ib->ptr[ib->length_dw++] = byte_count; 1669 } 1670 1671 static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = { 1672 .copy_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */ 1673 .copy_num_dw = 7, 1674 .emit_copy_buffer = sdma_v3_0_emit_copy_buffer, 1675 1676 .fill_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */ 1677 .fill_num_dw = 5, 1678 .emit_fill_buffer = sdma_v3_0_emit_fill_buffer, 1679 }; 1680 1681 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev) 1682 { 1683 adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs; 1684 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1685 } 1686 1687 static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = { 1688 .copy_pte_num_dw = 7, 1689 .copy_pte = sdma_v3_0_vm_copy_pte, 1690 1691 .write_pte = sdma_v3_0_vm_write_pte, 1692 .set_pte_pde = sdma_v3_0_vm_set_pte_pde, 1693 }; 1694 1695 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1696 { 1697 unsigned i; 1698 1699 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs; 1700 for (i = 0; i < adev->sdma.num_instances; i++) { 1701 adev->vm_manager.vm_pte_scheds[i] = 1702 &adev->sdma.instance[i].ring.sched; 1703 } 1704 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 1705 } 1706 1707 const struct amdgpu_ip_block_version sdma_v3_0_ip_block = 1708 { 1709 .type = AMD_IP_BLOCK_TYPE_SDMA, 1710 .major = 3, 1711 .minor = 0, 1712 .rev = 0, 1713 .funcs = &sdma_v3_0_ip_funcs, 1714 }; 1715 1716 const struct amdgpu_ip_block_version sdma_v3_1_ip_block = 1717 { 1718 .type = AMD_IP_BLOCK_TYPE_SDMA, 1719 .major = 3, 1720 .minor = 1, 1721 .rev = 0, 1722 .funcs = &sdma_v3_0_ip_funcs, 1723 }; 1724