1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_ucode.h" 28 #include "amdgpu_trace.h" 29 #include "vi.h" 30 #include "vid.h" 31 32 #include "oss/oss_3_0_d.h" 33 #include "oss/oss_3_0_sh_mask.h" 34 35 #include "gmc/gmc_8_1_d.h" 36 #include "gmc/gmc_8_1_sh_mask.h" 37 38 #include "gca/gfx_8_0_d.h" 39 #include "gca/gfx_8_0_enum.h" 40 #include "gca/gfx_8_0_sh_mask.h" 41 42 #include "bif/bif_5_0_d.h" 43 #include "bif/bif_5_0_sh_mask.h" 44 45 #include "tonga_sdma_pkt_open.h" 46 47 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev); 48 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev); 49 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev); 50 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev); 51 52 MODULE_FIRMWARE("amdgpu/tonga_sdma.bin"); 53 MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin"); 54 MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin"); 55 MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin"); 56 MODULE_FIRMWARE("amdgpu/fiji_sdma.bin"); 57 MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin"); 58 MODULE_FIRMWARE("amdgpu/stoney_sdma.bin"); 59 60 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = 61 { 62 SDMA0_REGISTER_OFFSET, 63 SDMA1_REGISTER_OFFSET 64 }; 65 66 static const u32 golden_settings_tonga_a11[] = 67 { 68 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 69 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 70 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 71 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 72 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 73 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 74 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 75 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 76 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 77 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 78 }; 79 80 static const u32 tonga_mgcg_cgcg_init[] = 81 { 82 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 83 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 84 }; 85 86 static const u32 golden_settings_fiji_a10[] = 87 { 88 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 89 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 90 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 91 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 92 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 93 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 94 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 95 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 96 }; 97 98 static const u32 fiji_mgcg_cgcg_init[] = 99 { 100 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 101 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 102 }; 103 104 static const u32 cz_golden_settings_a11[] = 105 { 106 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 107 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 108 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, 109 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, 110 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, 111 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, 112 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 113 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 114 mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100, 115 mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800, 116 mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100, 117 mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100, 118 }; 119 120 static const u32 cz_mgcg_cgcg_init[] = 121 { 122 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 123 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 124 }; 125 126 static const u32 stoney_golden_settings_a11[] = 127 { 128 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, 129 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, 130 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, 131 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, 132 }; 133 134 static const u32 stoney_mgcg_cgcg_init[] = 135 { 136 mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100, 137 }; 138 139 /* 140 * sDMA - System DMA 141 * Starting with CIK, the GPU has new asynchronous 142 * DMA engines. These engines are used for compute 143 * and gfx. There are two DMA engines (SDMA0, SDMA1) 144 * and each one supports 1 ring buffer used for gfx 145 * and 2 queues used for compute. 146 * 147 * The programming model is very similar to the CP 148 * (ring buffer, IBs, etc.), but sDMA has it's own 149 * packet format that is different from the PM4 format 150 * used by the CP. sDMA supports copying data, writing 151 * embedded data, solid fills, and a number of other 152 * things. It also has support for tiling/detiling of 153 * buffers. 154 */ 155 156 static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev) 157 { 158 switch (adev->asic_type) { 159 case CHIP_FIJI: 160 amdgpu_program_register_sequence(adev, 161 fiji_mgcg_cgcg_init, 162 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); 163 amdgpu_program_register_sequence(adev, 164 golden_settings_fiji_a10, 165 (const u32)ARRAY_SIZE(golden_settings_fiji_a10)); 166 break; 167 case CHIP_TONGA: 168 amdgpu_program_register_sequence(adev, 169 tonga_mgcg_cgcg_init, 170 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); 171 amdgpu_program_register_sequence(adev, 172 golden_settings_tonga_a11, 173 (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); 174 break; 175 case CHIP_CARRIZO: 176 amdgpu_program_register_sequence(adev, 177 cz_mgcg_cgcg_init, 178 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); 179 amdgpu_program_register_sequence(adev, 180 cz_golden_settings_a11, 181 (const u32)ARRAY_SIZE(cz_golden_settings_a11)); 182 break; 183 case CHIP_STONEY: 184 amdgpu_program_register_sequence(adev, 185 stoney_mgcg_cgcg_init, 186 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); 187 amdgpu_program_register_sequence(adev, 188 stoney_golden_settings_a11, 189 (const u32)ARRAY_SIZE(stoney_golden_settings_a11)); 190 break; 191 default: 192 break; 193 } 194 } 195 196 /** 197 * sdma_v3_0_init_microcode - load ucode images from disk 198 * 199 * @adev: amdgpu_device pointer 200 * 201 * Use the firmware interface to load the ucode images into 202 * the driver (not loaded into hw). 203 * Returns 0 on success, error on failure. 204 */ 205 static int sdma_v3_0_init_microcode(struct amdgpu_device *adev) 206 { 207 const char *chip_name; 208 char fw_name[30]; 209 int err = 0, i; 210 struct amdgpu_firmware_info *info = NULL; 211 const struct common_firmware_header *header = NULL; 212 const struct sdma_firmware_header_v1_0 *hdr; 213 214 DRM_DEBUG("\n"); 215 216 switch (adev->asic_type) { 217 case CHIP_TONGA: 218 chip_name = "tonga"; 219 break; 220 case CHIP_FIJI: 221 chip_name = "fiji"; 222 break; 223 case CHIP_CARRIZO: 224 chip_name = "carrizo"; 225 break; 226 case CHIP_STONEY: 227 chip_name = "stoney"; 228 break; 229 default: BUG(); 230 } 231 232 for (i = 0; i < adev->sdma.num_instances; i++) { 233 if (i == 0) 234 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 235 else 236 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); 237 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 238 if (err) 239 goto out; 240 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); 241 if (err) 242 goto out; 243 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 244 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 245 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 246 if (adev->sdma.instance[i].feature_version >= 20) 247 adev->sdma.instance[i].burst_nop = true; 248 249 if (adev->firmware.smu_load) { 250 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 251 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 252 info->fw = adev->sdma.instance[i].fw; 253 header = (const struct common_firmware_header *)info->fw->data; 254 adev->firmware.fw_size += 255 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 256 } 257 } 258 out: 259 if (err) { 260 printk(KERN_ERR 261 "sdma_v3_0: Failed to load firmware \"%s\"\n", 262 fw_name); 263 for (i = 0; i < adev->sdma.num_instances; i++) { 264 release_firmware(adev->sdma.instance[i].fw); 265 adev->sdma.instance[i].fw = NULL; 266 } 267 } 268 return err; 269 } 270 271 /** 272 * sdma_v3_0_ring_get_rptr - get the current read pointer 273 * 274 * @ring: amdgpu ring pointer 275 * 276 * Get the current rptr from the hardware (VI+). 277 */ 278 static uint32_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring) 279 { 280 u32 rptr; 281 282 /* XXX check if swapping is necessary on BE */ 283 rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2; 284 285 return rptr; 286 } 287 288 /** 289 * sdma_v3_0_ring_get_wptr - get the current write pointer 290 * 291 * @ring: amdgpu ring pointer 292 * 293 * Get the current wptr from the hardware (VI+). 294 */ 295 static uint32_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring) 296 { 297 struct amdgpu_device *adev = ring->adev; 298 u32 wptr; 299 300 if (ring->use_doorbell) { 301 /* XXX check if swapping is necessary on BE */ 302 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2; 303 } else { 304 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1; 305 306 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2; 307 } 308 309 return wptr; 310 } 311 312 /** 313 * sdma_v3_0_ring_set_wptr - commit the write pointer 314 * 315 * @ring: amdgpu ring pointer 316 * 317 * Write the wptr back to the hardware (VI+). 318 */ 319 static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring) 320 { 321 struct amdgpu_device *adev = ring->adev; 322 323 if (ring->use_doorbell) { 324 /* XXX check if swapping is necessary on BE */ 325 adev->wb.wb[ring->wptr_offs] = ring->wptr << 2; 326 WDOORBELL32(ring->doorbell_index, ring->wptr << 2); 327 } else { 328 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1; 329 330 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2); 331 } 332 } 333 334 static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 335 { 336 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); 337 int i; 338 339 for (i = 0; i < count; i++) 340 if (sdma && sdma->burst_nop && (i == 0)) 341 amdgpu_ring_write(ring, ring->nop | 342 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 343 else 344 amdgpu_ring_write(ring, ring->nop); 345 } 346 347 /** 348 * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine 349 * 350 * @ring: amdgpu ring pointer 351 * @ib: IB object to schedule 352 * 353 * Schedule an IB in the DMA ring (VI). 354 */ 355 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring, 356 struct amdgpu_ib *ib) 357 { 358 u32 vmid = ib->vm_id & 0xf; 359 u32 next_rptr = ring->wptr + 5; 360 361 while ((next_rptr & 7) != 2) 362 next_rptr++; 363 next_rptr += 6; 364 365 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 366 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 367 amdgpu_ring_write(ring, lower_32_bits(ring->next_rptr_gpu_addr) & 0xfffffffc); 368 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); 369 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); 370 amdgpu_ring_write(ring, next_rptr); 371 372 /* IB packet must end on a 8 DW boundary */ 373 sdma_v3_0_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8); 374 375 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 376 SDMA_PKT_INDIRECT_HEADER_VMID(vmid)); 377 /* base must be 32 byte aligned */ 378 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 379 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 380 amdgpu_ring_write(ring, ib->length_dw); 381 amdgpu_ring_write(ring, 0); 382 amdgpu_ring_write(ring, 0); 383 384 } 385 386 /** 387 * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 388 * 389 * @ring: amdgpu ring pointer 390 * 391 * Emit an hdp flush packet on the requested DMA ring. 392 */ 393 static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 394 { 395 u32 ref_and_mask = 0; 396 397 if (ring == &ring->adev->sdma.instance[0].ring) 398 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); 399 else 400 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); 401 402 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 403 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 404 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 405 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); 406 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); 407 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 408 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 409 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 410 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 411 } 412 413 static void sdma_v3_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) 414 { 415 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 416 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 417 amdgpu_ring_write(ring, mmHDP_DEBUG0); 418 amdgpu_ring_write(ring, 1); 419 } 420 421 /** 422 * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring 423 * 424 * @ring: amdgpu ring pointer 425 * @fence: amdgpu fence object 426 * 427 * Add a DMA fence packet to the ring to write 428 * the fence seq number and DMA trap packet to generate 429 * an interrupt if needed (VI). 430 */ 431 static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 432 unsigned flags) 433 { 434 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 435 /* write the fence */ 436 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 437 amdgpu_ring_write(ring, lower_32_bits(addr)); 438 amdgpu_ring_write(ring, upper_32_bits(addr)); 439 amdgpu_ring_write(ring, lower_32_bits(seq)); 440 441 /* optionally write high bits as well */ 442 if (write64bit) { 443 addr += 4; 444 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 445 amdgpu_ring_write(ring, lower_32_bits(addr)); 446 amdgpu_ring_write(ring, upper_32_bits(addr)); 447 amdgpu_ring_write(ring, upper_32_bits(seq)); 448 } 449 450 /* generate an interrupt */ 451 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 452 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 453 } 454 455 /** 456 * sdma_v3_0_gfx_stop - stop the gfx async dma engines 457 * 458 * @adev: amdgpu_device pointer 459 * 460 * Stop the gfx async dma ring buffers (VI). 461 */ 462 static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev) 463 { 464 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 465 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 466 u32 rb_cntl, ib_cntl; 467 int i; 468 469 if ((adev->mman.buffer_funcs_ring == sdma0) || 470 (adev->mman.buffer_funcs_ring == sdma1)) 471 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); 472 473 for (i = 0; i < adev->sdma.num_instances; i++) { 474 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 475 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 476 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 477 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 478 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 479 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 480 } 481 sdma0->ready = false; 482 sdma1->ready = false; 483 } 484 485 /** 486 * sdma_v3_0_rlc_stop - stop the compute async dma engines 487 * 488 * @adev: amdgpu_device pointer 489 * 490 * Stop the compute async dma queues (VI). 491 */ 492 static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev) 493 { 494 /* XXX todo */ 495 } 496 497 /** 498 * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch 499 * 500 * @adev: amdgpu_device pointer 501 * @enable: enable/disable the DMA MEs context switch. 502 * 503 * Halt or unhalt the async dma engines context switch (VI). 504 */ 505 static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 506 { 507 u32 f32_cntl; 508 int i; 509 510 for (i = 0; i < adev->sdma.num_instances; i++) { 511 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); 512 if (enable) 513 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 514 AUTO_CTXSW_ENABLE, 1); 515 else 516 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 517 AUTO_CTXSW_ENABLE, 0); 518 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); 519 } 520 } 521 522 /** 523 * sdma_v3_0_enable - stop the async dma engines 524 * 525 * @adev: amdgpu_device pointer 526 * @enable: enable/disable the DMA MEs. 527 * 528 * Halt or unhalt the async dma engines (VI). 529 */ 530 static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable) 531 { 532 u32 f32_cntl; 533 int i; 534 535 if (enable == false) { 536 sdma_v3_0_gfx_stop(adev); 537 sdma_v3_0_rlc_stop(adev); 538 } 539 540 for (i = 0; i < adev->sdma.num_instances; i++) { 541 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); 542 if (enable) 543 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); 544 else 545 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); 546 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); 547 } 548 } 549 550 /** 551 * sdma_v3_0_gfx_resume - setup and start the async dma engines 552 * 553 * @adev: amdgpu_device pointer 554 * 555 * Set up the gfx DMA ring buffers and enable them (VI). 556 * Returns 0 for success, error for failure. 557 */ 558 static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) 559 { 560 struct amdgpu_ring *ring; 561 u32 rb_cntl, ib_cntl; 562 u32 rb_bufsz; 563 u32 wb_offset; 564 u32 doorbell; 565 int i, j, r; 566 567 for (i = 0; i < adev->sdma.num_instances; i++) { 568 ring = &adev->sdma.instance[i].ring; 569 wb_offset = (ring->rptr_offs * 4); 570 571 mutex_lock(&adev->srbm_mutex); 572 for (j = 0; j < 16; j++) { 573 vi_srbm_select(adev, 0, 0, 0, j); 574 /* SDMA GFX */ 575 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); 576 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); 577 } 578 vi_srbm_select(adev, 0, 0, 0, 0); 579 mutex_unlock(&adev->srbm_mutex); 580 581 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], 582 adev->gfx.config.gb_addr_config & 0x70); 583 584 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); 585 586 /* Set ring buffer size in dwords */ 587 rb_bufsz = order_base_2(ring->ring_size / 4); 588 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 589 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 590 #ifdef __BIG_ENDIAN 591 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 592 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 593 RPTR_WRITEBACK_SWAP_ENABLE, 1); 594 #endif 595 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 596 597 /* Initialize the ring buffer's read and write pointers */ 598 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); 599 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); 600 601 /* set the wb address whether it's enabled or not */ 602 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], 603 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 604 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], 605 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 606 607 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 608 609 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); 610 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); 611 612 ring->wptr = 0; 613 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2); 614 615 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]); 616 617 if (ring->use_doorbell) { 618 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, 619 OFFSET, ring->doorbell_index); 620 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 621 } else { 622 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 623 } 624 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell); 625 626 /* enable DMA RB */ 627 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 628 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 629 630 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 631 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 632 #ifdef __BIG_ENDIAN 633 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 634 #endif 635 /* enable DMA IBs */ 636 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 637 638 ring->ready = true; 639 640 r = amdgpu_ring_test_ring(ring); 641 if (r) { 642 ring->ready = false; 643 return r; 644 } 645 646 if (adev->mman.buffer_funcs_ring == ring) 647 amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size); 648 } 649 650 return 0; 651 } 652 653 /** 654 * sdma_v3_0_rlc_resume - setup and start the async dma engines 655 * 656 * @adev: amdgpu_device pointer 657 * 658 * Set up the compute DMA queues and enable them (VI). 659 * Returns 0 for success, error for failure. 660 */ 661 static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev) 662 { 663 /* XXX todo */ 664 return 0; 665 } 666 667 /** 668 * sdma_v3_0_load_microcode - load the sDMA ME ucode 669 * 670 * @adev: amdgpu_device pointer 671 * 672 * Loads the sDMA0/1 ucode. 673 * Returns 0 for success, -EINVAL if the ucode is not available. 674 */ 675 static int sdma_v3_0_load_microcode(struct amdgpu_device *adev) 676 { 677 const struct sdma_firmware_header_v1_0 *hdr; 678 const __le32 *fw_data; 679 u32 fw_size; 680 int i, j; 681 682 /* halt the MEs */ 683 sdma_v3_0_enable(adev, false); 684 685 for (i = 0; i < adev->sdma.num_instances; i++) { 686 if (!adev->sdma.instance[i].fw) 687 return -EINVAL; 688 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 689 amdgpu_ucode_print_sdma_hdr(&hdr->header); 690 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 691 fw_data = (const __le32 *) 692 (adev->sdma.instance[i].fw->data + 693 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 694 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0); 695 for (j = 0; j < fw_size; j++) 696 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++)); 697 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version); 698 } 699 700 return 0; 701 } 702 703 /** 704 * sdma_v3_0_start - setup and start the async dma engines 705 * 706 * @adev: amdgpu_device pointer 707 * 708 * Set up the DMA engines and enable them (VI). 709 * Returns 0 for success, error for failure. 710 */ 711 static int sdma_v3_0_start(struct amdgpu_device *adev) 712 { 713 int r, i; 714 715 if (!adev->pp_enabled) { 716 if (!adev->firmware.smu_load) { 717 r = sdma_v3_0_load_microcode(adev); 718 if (r) 719 return r; 720 } else { 721 for (i = 0; i < adev->sdma.num_instances; i++) { 722 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, 723 (i == 0) ? 724 AMDGPU_UCODE_ID_SDMA0 : 725 AMDGPU_UCODE_ID_SDMA1); 726 if (r) 727 return -EINVAL; 728 } 729 } 730 } 731 732 /* unhalt the MEs */ 733 sdma_v3_0_enable(adev, true); 734 /* enable sdma ring preemption */ 735 sdma_v3_0_ctx_switch_enable(adev, true); 736 737 /* start the gfx rings and rlc compute queues */ 738 r = sdma_v3_0_gfx_resume(adev); 739 if (r) 740 return r; 741 r = sdma_v3_0_rlc_resume(adev); 742 if (r) 743 return r; 744 745 return 0; 746 } 747 748 /** 749 * sdma_v3_0_ring_test_ring - simple async dma engine test 750 * 751 * @ring: amdgpu_ring structure holding ring information 752 * 753 * Test the DMA engine by writing using it to write an 754 * value to memory. (VI). 755 * Returns 0 for success, error for failure. 756 */ 757 static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring) 758 { 759 struct amdgpu_device *adev = ring->adev; 760 unsigned i; 761 unsigned index; 762 int r; 763 u32 tmp; 764 u64 gpu_addr; 765 766 r = amdgpu_wb_get(adev, &index); 767 if (r) { 768 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 769 return r; 770 } 771 772 gpu_addr = adev->wb.gpu_addr + (index * 4); 773 tmp = 0xCAFEDEAD; 774 adev->wb.wb[index] = cpu_to_le32(tmp); 775 776 r = amdgpu_ring_alloc(ring, 5); 777 if (r) { 778 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 779 amdgpu_wb_free(adev, index); 780 return r; 781 } 782 783 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 784 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 785 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 786 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 787 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); 788 amdgpu_ring_write(ring, 0xDEADBEEF); 789 amdgpu_ring_commit(ring); 790 791 for (i = 0; i < adev->usec_timeout; i++) { 792 tmp = le32_to_cpu(adev->wb.wb[index]); 793 if (tmp == 0xDEADBEEF) 794 break; 795 DRM_UDELAY(1); 796 } 797 798 if (i < adev->usec_timeout) { 799 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 800 } else { 801 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 802 ring->idx, tmp); 803 r = -EINVAL; 804 } 805 amdgpu_wb_free(adev, index); 806 807 return r; 808 } 809 810 /** 811 * sdma_v3_0_ring_test_ib - test an IB on the DMA engine 812 * 813 * @ring: amdgpu_ring structure holding ring information 814 * 815 * Test a simple IB in the DMA ring (VI). 816 * Returns 0 on success, error on failure. 817 */ 818 static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring) 819 { 820 struct amdgpu_device *adev = ring->adev; 821 struct amdgpu_ib ib; 822 struct fence *f = NULL; 823 unsigned i; 824 unsigned index; 825 int r; 826 u32 tmp = 0; 827 u64 gpu_addr; 828 829 r = amdgpu_wb_get(adev, &index); 830 if (r) { 831 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 832 return r; 833 } 834 835 gpu_addr = adev->wb.gpu_addr + (index * 4); 836 tmp = 0xCAFEDEAD; 837 adev->wb.wb[index] = cpu_to_le32(tmp); 838 memset(&ib, 0, sizeof(ib)); 839 r = amdgpu_ib_get(adev, NULL, 256, &ib); 840 if (r) { 841 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r); 842 goto err0; 843 } 844 845 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 846 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 847 ib.ptr[1] = lower_32_bits(gpu_addr); 848 ib.ptr[2] = upper_32_bits(gpu_addr); 849 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1); 850 ib.ptr[4] = 0xDEADBEEF; 851 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 852 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 853 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 854 ib.length_dw = 8; 855 856 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 857 if (r) 858 goto err1; 859 860 r = fence_wait(f, false); 861 if (r) { 862 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); 863 goto err1; 864 } 865 for (i = 0; i < adev->usec_timeout; i++) { 866 tmp = le32_to_cpu(adev->wb.wb[index]); 867 if (tmp == 0xDEADBEEF) 868 break; 869 DRM_UDELAY(1); 870 } 871 if (i < adev->usec_timeout) { 872 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", 873 ring->idx, i); 874 goto err1; 875 } else { 876 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); 877 r = -EINVAL; 878 } 879 err1: 880 fence_put(f); 881 amdgpu_ib_free(adev, &ib, NULL); 882 fence_put(f); 883 err0: 884 amdgpu_wb_free(adev, index); 885 return r; 886 } 887 888 /** 889 * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART 890 * 891 * @ib: indirect buffer to fill with commands 892 * @pe: addr of the page entry 893 * @src: src addr to copy from 894 * @count: number of page entries to update 895 * 896 * Update PTEs by copying them from the GART using sDMA (CIK). 897 */ 898 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib, 899 uint64_t pe, uint64_t src, 900 unsigned count) 901 { 902 while (count) { 903 unsigned bytes = count * 8; 904 if (bytes > 0x1FFFF8) 905 bytes = 0x1FFFF8; 906 907 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 908 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 909 ib->ptr[ib->length_dw++] = bytes; 910 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 911 ib->ptr[ib->length_dw++] = lower_32_bits(src); 912 ib->ptr[ib->length_dw++] = upper_32_bits(src); 913 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 914 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 915 916 pe += bytes; 917 src += bytes; 918 count -= bytes / 8; 919 } 920 } 921 922 /** 923 * sdma_v3_0_vm_write_pte - update PTEs by writing them manually 924 * 925 * @ib: indirect buffer to fill with commands 926 * @pe: addr of the page entry 927 * @addr: dst addr to write into pe 928 * @count: number of page entries to update 929 * @incr: increase next addr by incr bytes 930 * @flags: access flags 931 * 932 * Update PTEs by writing them manually using sDMA (CIK). 933 */ 934 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, 935 const dma_addr_t *pages_addr, uint64_t pe, 936 uint64_t addr, unsigned count, 937 uint32_t incr, uint32_t flags) 938 { 939 uint64_t value; 940 unsigned ndw; 941 942 while (count) { 943 ndw = count * 2; 944 if (ndw > 0xFFFFE) 945 ndw = 0xFFFFE; 946 947 /* for non-physically contiguous pages (system) */ 948 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 949 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 950 ib->ptr[ib->length_dw++] = pe; 951 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 952 ib->ptr[ib->length_dw++] = ndw; 953 for (; ndw > 0; ndw -= 2, --count, pe += 8) { 954 value = amdgpu_vm_map_gart(pages_addr, addr); 955 addr += incr; 956 value |= flags; 957 ib->ptr[ib->length_dw++] = value; 958 ib->ptr[ib->length_dw++] = upper_32_bits(value); 959 } 960 } 961 } 962 963 /** 964 * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA 965 * 966 * @ib: indirect buffer to fill with commands 967 * @pe: addr of the page entry 968 * @addr: dst addr to write into pe 969 * @count: number of page entries to update 970 * @incr: increase next addr by incr bytes 971 * @flags: access flags 972 * 973 * Update the page tables using sDMA (CIK). 974 */ 975 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, 976 uint64_t pe, 977 uint64_t addr, unsigned count, 978 uint32_t incr, uint32_t flags) 979 { 980 uint64_t value; 981 unsigned ndw; 982 983 while (count) { 984 ndw = count; 985 if (ndw > 0x7FFFF) 986 ndw = 0x7FFFF; 987 988 if (flags & AMDGPU_PTE_VALID) 989 value = addr; 990 else 991 value = 0; 992 993 /* for physically contiguous pages (vram) */ 994 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE); 995 ib->ptr[ib->length_dw++] = pe; /* dst addr */ 996 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 997 ib->ptr[ib->length_dw++] = flags; /* mask */ 998 ib->ptr[ib->length_dw++] = 0; 999 ib->ptr[ib->length_dw++] = value; /* value */ 1000 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1001 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1002 ib->ptr[ib->length_dw++] = 0; 1003 ib->ptr[ib->length_dw++] = ndw; /* number of entries */ 1004 1005 pe += ndw * 8; 1006 addr += ndw * incr; 1007 count -= ndw; 1008 } 1009 } 1010 1011 /** 1012 * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw 1013 * 1014 * @ib: indirect buffer to fill with padding 1015 * 1016 */ 1017 static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1018 { 1019 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); 1020 u32 pad_count; 1021 int i; 1022 1023 pad_count = (8 - (ib->length_dw & 0x7)) % 8; 1024 for (i = 0; i < pad_count; i++) 1025 if (sdma && sdma->burst_nop && (i == 0)) 1026 ib->ptr[ib->length_dw++] = 1027 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1028 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1029 else 1030 ib->ptr[ib->length_dw++] = 1031 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1032 } 1033 1034 /** 1035 * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline 1036 * 1037 * @ring: amdgpu_ring pointer 1038 * 1039 * Make sure all previous operations are completed (CIK). 1040 */ 1041 static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1042 { 1043 uint32_t seq = ring->fence_drv.sync_seq; 1044 uint64_t addr = ring->fence_drv.gpu_addr; 1045 1046 /* wait for idle */ 1047 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1048 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1049 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1050 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1051 amdgpu_ring_write(ring, addr & 0xfffffffc); 1052 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1053 amdgpu_ring_write(ring, seq); /* reference */ 1054 amdgpu_ring_write(ring, 0xfffffff); /* mask */ 1055 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1056 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1057 } 1058 1059 /** 1060 * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA 1061 * 1062 * @ring: amdgpu_ring pointer 1063 * @vm: amdgpu_vm pointer 1064 * 1065 * Update the page table base and flush the VM TLB 1066 * using sDMA (VI). 1067 */ 1068 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1069 unsigned vm_id, uint64_t pd_addr) 1070 { 1071 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1072 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1073 if (vm_id < 8) { 1074 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id)); 1075 } else { 1076 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8)); 1077 } 1078 amdgpu_ring_write(ring, pd_addr >> 12); 1079 1080 /* flush TLB */ 1081 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1082 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1083 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 1084 amdgpu_ring_write(ring, 1 << vm_id); 1085 1086 /* wait for flush */ 1087 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1088 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1089 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */ 1090 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); 1091 amdgpu_ring_write(ring, 0); 1092 amdgpu_ring_write(ring, 0); /* reference */ 1093 amdgpu_ring_write(ring, 0); /* mask */ 1094 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1095 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 1096 } 1097 1098 static int sdma_v3_0_early_init(void *handle) 1099 { 1100 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1101 1102 switch (adev->asic_type) { 1103 case CHIP_STONEY: 1104 adev->sdma.num_instances = 1; 1105 break; 1106 default: 1107 adev->sdma.num_instances = SDMA_MAX_INSTANCE; 1108 break; 1109 } 1110 1111 sdma_v3_0_set_ring_funcs(adev); 1112 sdma_v3_0_set_buffer_funcs(adev); 1113 sdma_v3_0_set_vm_pte_funcs(adev); 1114 sdma_v3_0_set_irq_funcs(adev); 1115 1116 return 0; 1117 } 1118 1119 static int sdma_v3_0_sw_init(void *handle) 1120 { 1121 struct amdgpu_ring *ring; 1122 int r, i; 1123 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1124 1125 /* SDMA trap event */ 1126 r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq); 1127 if (r) 1128 return r; 1129 1130 /* SDMA Privileged inst */ 1131 r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq); 1132 if (r) 1133 return r; 1134 1135 /* SDMA Privileged inst */ 1136 r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq); 1137 if (r) 1138 return r; 1139 1140 r = sdma_v3_0_init_microcode(adev); 1141 if (r) { 1142 DRM_ERROR("Failed to load sdma firmware!\n"); 1143 return r; 1144 } 1145 1146 for (i = 0; i < adev->sdma.num_instances; i++) { 1147 ring = &adev->sdma.instance[i].ring; 1148 ring->ring_obj = NULL; 1149 ring->use_doorbell = true; 1150 ring->doorbell_index = (i == 0) ? 1151 AMDGPU_DOORBELL_sDMA_ENGINE0 : AMDGPU_DOORBELL_sDMA_ENGINE1; 1152 1153 sprintf(ring->name, "sdma%d", i); 1154 r = amdgpu_ring_init(adev, ring, 256 * 1024, 1155 SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, 1156 &adev->sdma.trap_irq, 1157 (i == 0) ? 1158 AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1, 1159 AMDGPU_RING_TYPE_SDMA); 1160 if (r) 1161 return r; 1162 } 1163 1164 return r; 1165 } 1166 1167 static int sdma_v3_0_sw_fini(void *handle) 1168 { 1169 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1170 int i; 1171 1172 for (i = 0; i < adev->sdma.num_instances; i++) 1173 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1174 1175 return 0; 1176 } 1177 1178 static int sdma_v3_0_hw_init(void *handle) 1179 { 1180 int r; 1181 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1182 1183 sdma_v3_0_init_golden_registers(adev); 1184 1185 r = sdma_v3_0_start(adev); 1186 if (r) 1187 return r; 1188 1189 return r; 1190 } 1191 1192 static int sdma_v3_0_hw_fini(void *handle) 1193 { 1194 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1195 1196 sdma_v3_0_ctx_switch_enable(adev, false); 1197 sdma_v3_0_enable(adev, false); 1198 1199 return 0; 1200 } 1201 1202 static int sdma_v3_0_suspend(void *handle) 1203 { 1204 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1205 1206 return sdma_v3_0_hw_fini(adev); 1207 } 1208 1209 static int sdma_v3_0_resume(void *handle) 1210 { 1211 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1212 1213 return sdma_v3_0_hw_init(adev); 1214 } 1215 1216 static bool sdma_v3_0_is_idle(void *handle) 1217 { 1218 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1219 u32 tmp = RREG32(mmSRBM_STATUS2); 1220 1221 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | 1222 SRBM_STATUS2__SDMA1_BUSY_MASK)) 1223 return false; 1224 1225 return true; 1226 } 1227 1228 static int sdma_v3_0_wait_for_idle(void *handle) 1229 { 1230 unsigned i; 1231 u32 tmp; 1232 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1233 1234 for (i = 0; i < adev->usec_timeout; i++) { 1235 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | 1236 SRBM_STATUS2__SDMA1_BUSY_MASK); 1237 1238 if (!tmp) 1239 return 0; 1240 udelay(1); 1241 } 1242 return -ETIMEDOUT; 1243 } 1244 1245 static void sdma_v3_0_print_status(void *handle) 1246 { 1247 int i, j; 1248 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1249 1250 dev_info(adev->dev, "VI SDMA registers\n"); 1251 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", 1252 RREG32(mmSRBM_STATUS2)); 1253 for (i = 0; i < adev->sdma.num_instances; i++) { 1254 dev_info(adev->dev, " SDMA%d_STATUS_REG=0x%08X\n", 1255 i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i])); 1256 dev_info(adev->dev, " SDMA%d_F32_CNTL=0x%08X\n", 1257 i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i])); 1258 dev_info(adev->dev, " SDMA%d_CNTL=0x%08X\n", 1259 i, RREG32(mmSDMA0_CNTL + sdma_offsets[i])); 1260 dev_info(adev->dev, " SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n", 1261 i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i])); 1262 dev_info(adev->dev, " SDMA%d_GFX_IB_CNTL=0x%08X\n", 1263 i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i])); 1264 dev_info(adev->dev, " SDMA%d_GFX_RB_CNTL=0x%08X\n", 1265 i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i])); 1266 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR=0x%08X\n", 1267 i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i])); 1268 dev_info(adev->dev, " SDMA%d_GFX_RB_WPTR=0x%08X\n", 1269 i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i])); 1270 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n", 1271 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i])); 1272 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n", 1273 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i])); 1274 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE=0x%08X\n", 1275 i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i])); 1276 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE_HI=0x%08X\n", 1277 i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i])); 1278 dev_info(adev->dev, " SDMA%d_GFX_DOORBELL=0x%08X\n", 1279 i, RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i])); 1280 dev_info(adev->dev, " SDMA%d_TILING_CONFIG=0x%08X\n", 1281 i, RREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i])); 1282 mutex_lock(&adev->srbm_mutex); 1283 for (j = 0; j < 16; j++) { 1284 vi_srbm_select(adev, 0, 0, 0, j); 1285 dev_info(adev->dev, " VM %d:\n", j); 1286 dev_info(adev->dev, " SDMA%d_GFX_VIRTUAL_ADDR=0x%08X\n", 1287 i, RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i])); 1288 dev_info(adev->dev, " SDMA%d_GFX_APE1_CNTL=0x%08X\n", 1289 i, RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i])); 1290 } 1291 vi_srbm_select(adev, 0, 0, 0, 0); 1292 mutex_unlock(&adev->srbm_mutex); 1293 } 1294 } 1295 1296 static int sdma_v3_0_soft_reset(void *handle) 1297 { 1298 u32 srbm_soft_reset = 0; 1299 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1300 u32 tmp = RREG32(mmSRBM_STATUS2); 1301 1302 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) { 1303 /* sdma0 */ 1304 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); 1305 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); 1306 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); 1307 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK; 1308 } 1309 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) { 1310 /* sdma1 */ 1311 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); 1312 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); 1313 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); 1314 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK; 1315 } 1316 1317 if (srbm_soft_reset) { 1318 sdma_v3_0_print_status((void *)adev); 1319 1320 tmp = RREG32(mmSRBM_SOFT_RESET); 1321 tmp |= srbm_soft_reset; 1322 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1323 WREG32(mmSRBM_SOFT_RESET, tmp); 1324 tmp = RREG32(mmSRBM_SOFT_RESET); 1325 1326 udelay(50); 1327 1328 tmp &= ~srbm_soft_reset; 1329 WREG32(mmSRBM_SOFT_RESET, tmp); 1330 tmp = RREG32(mmSRBM_SOFT_RESET); 1331 1332 /* Wait a little for things to settle down */ 1333 udelay(50); 1334 1335 sdma_v3_0_print_status((void *)adev); 1336 } 1337 1338 return 0; 1339 } 1340 1341 static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev, 1342 struct amdgpu_irq_src *source, 1343 unsigned type, 1344 enum amdgpu_interrupt_state state) 1345 { 1346 u32 sdma_cntl; 1347 1348 switch (type) { 1349 case AMDGPU_SDMA_IRQ_TRAP0: 1350 switch (state) { 1351 case AMDGPU_IRQ_STATE_DISABLE: 1352 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1353 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1354 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1355 break; 1356 case AMDGPU_IRQ_STATE_ENABLE: 1357 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1358 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1359 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1360 break; 1361 default: 1362 break; 1363 } 1364 break; 1365 case AMDGPU_SDMA_IRQ_TRAP1: 1366 switch (state) { 1367 case AMDGPU_IRQ_STATE_DISABLE: 1368 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1369 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1370 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1371 break; 1372 case AMDGPU_IRQ_STATE_ENABLE: 1373 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1374 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1375 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1376 break; 1377 default: 1378 break; 1379 } 1380 break; 1381 default: 1382 break; 1383 } 1384 return 0; 1385 } 1386 1387 static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev, 1388 struct amdgpu_irq_src *source, 1389 struct amdgpu_iv_entry *entry) 1390 { 1391 u8 instance_id, queue_id; 1392 1393 instance_id = (entry->ring_id & 0x3) >> 0; 1394 queue_id = (entry->ring_id & 0xc) >> 2; 1395 DRM_DEBUG("IH: SDMA trap\n"); 1396 switch (instance_id) { 1397 case 0: 1398 switch (queue_id) { 1399 case 0: 1400 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1401 break; 1402 case 1: 1403 /* XXX compute */ 1404 break; 1405 case 2: 1406 /* XXX compute */ 1407 break; 1408 } 1409 break; 1410 case 1: 1411 switch (queue_id) { 1412 case 0: 1413 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1414 break; 1415 case 1: 1416 /* XXX compute */ 1417 break; 1418 case 2: 1419 /* XXX compute */ 1420 break; 1421 } 1422 break; 1423 } 1424 return 0; 1425 } 1426 1427 static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1428 struct amdgpu_irq_src *source, 1429 struct amdgpu_iv_entry *entry) 1430 { 1431 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1432 schedule_work(&adev->reset_work); 1433 return 0; 1434 } 1435 1436 static void fiji_update_sdma_medium_grain_clock_gating( 1437 struct amdgpu_device *adev, 1438 bool enable) 1439 { 1440 uint32_t temp, data; 1441 1442 if (enable) { 1443 temp = data = RREG32(mmSDMA0_CLK_CTRL); 1444 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1445 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1446 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1447 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1448 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1449 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1450 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1451 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1452 if (data != temp) 1453 WREG32(mmSDMA0_CLK_CTRL, data); 1454 1455 temp = data = RREG32(mmSDMA1_CLK_CTRL); 1456 data &= ~(SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1457 SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1458 SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1459 SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1460 SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1461 SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1462 SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1463 SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1464 1465 if (data != temp) 1466 WREG32(mmSDMA1_CLK_CTRL, data); 1467 } else { 1468 temp = data = RREG32(mmSDMA0_CLK_CTRL); 1469 data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1470 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1471 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1472 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1473 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1474 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1475 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1476 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK; 1477 1478 if (data != temp) 1479 WREG32(mmSDMA0_CLK_CTRL, data); 1480 1481 temp = data = RREG32(mmSDMA1_CLK_CTRL); 1482 data |= SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1483 SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1484 SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1485 SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1486 SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1487 SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1488 SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1489 SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK; 1490 1491 if (data != temp) 1492 WREG32(mmSDMA1_CLK_CTRL, data); 1493 } 1494 } 1495 1496 static void fiji_update_sdma_medium_grain_light_sleep( 1497 struct amdgpu_device *adev, 1498 bool enable) 1499 { 1500 uint32_t temp, data; 1501 1502 if (enable) { 1503 temp = data = RREG32(mmSDMA0_POWER_CNTL); 1504 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1505 1506 if (temp != data) 1507 WREG32(mmSDMA0_POWER_CNTL, data); 1508 1509 temp = data = RREG32(mmSDMA1_POWER_CNTL); 1510 data |= SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1511 1512 if (temp != data) 1513 WREG32(mmSDMA1_POWER_CNTL, data); 1514 } else { 1515 temp = data = RREG32(mmSDMA0_POWER_CNTL); 1516 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1517 1518 if (temp != data) 1519 WREG32(mmSDMA0_POWER_CNTL, data); 1520 1521 temp = data = RREG32(mmSDMA1_POWER_CNTL); 1522 data &= ~SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1523 1524 if (temp != data) 1525 WREG32(mmSDMA1_POWER_CNTL, data); 1526 } 1527 } 1528 1529 static int sdma_v3_0_set_clockgating_state(void *handle, 1530 enum amd_clockgating_state state) 1531 { 1532 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1533 1534 switch (adev->asic_type) { 1535 case CHIP_FIJI: 1536 fiji_update_sdma_medium_grain_clock_gating(adev, 1537 state == AMD_CG_STATE_GATE ? true : false); 1538 fiji_update_sdma_medium_grain_light_sleep(adev, 1539 state == AMD_CG_STATE_GATE ? true : false); 1540 break; 1541 default: 1542 break; 1543 } 1544 return 0; 1545 } 1546 1547 static int sdma_v3_0_set_powergating_state(void *handle, 1548 enum amd_powergating_state state) 1549 { 1550 return 0; 1551 } 1552 1553 const struct amd_ip_funcs sdma_v3_0_ip_funcs = { 1554 .early_init = sdma_v3_0_early_init, 1555 .late_init = NULL, 1556 .sw_init = sdma_v3_0_sw_init, 1557 .sw_fini = sdma_v3_0_sw_fini, 1558 .hw_init = sdma_v3_0_hw_init, 1559 .hw_fini = sdma_v3_0_hw_fini, 1560 .suspend = sdma_v3_0_suspend, 1561 .resume = sdma_v3_0_resume, 1562 .is_idle = sdma_v3_0_is_idle, 1563 .wait_for_idle = sdma_v3_0_wait_for_idle, 1564 .soft_reset = sdma_v3_0_soft_reset, 1565 .print_status = sdma_v3_0_print_status, 1566 .set_clockgating_state = sdma_v3_0_set_clockgating_state, 1567 .set_powergating_state = sdma_v3_0_set_powergating_state, 1568 }; 1569 1570 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { 1571 .get_rptr = sdma_v3_0_ring_get_rptr, 1572 .get_wptr = sdma_v3_0_ring_get_wptr, 1573 .set_wptr = sdma_v3_0_ring_set_wptr, 1574 .parse_cs = NULL, 1575 .emit_ib = sdma_v3_0_ring_emit_ib, 1576 .emit_fence = sdma_v3_0_ring_emit_fence, 1577 .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync, 1578 .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush, 1579 .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush, 1580 .emit_hdp_invalidate = sdma_v3_0_ring_emit_hdp_invalidate, 1581 .test_ring = sdma_v3_0_ring_test_ring, 1582 .test_ib = sdma_v3_0_ring_test_ib, 1583 .insert_nop = sdma_v3_0_ring_insert_nop, 1584 .pad_ib = sdma_v3_0_ring_pad_ib, 1585 }; 1586 1587 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev) 1588 { 1589 int i; 1590 1591 for (i = 0; i < adev->sdma.num_instances; i++) 1592 adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs; 1593 } 1594 1595 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = { 1596 .set = sdma_v3_0_set_trap_irq_state, 1597 .process = sdma_v3_0_process_trap_irq, 1598 }; 1599 1600 static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = { 1601 .process = sdma_v3_0_process_illegal_inst_irq, 1602 }; 1603 1604 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev) 1605 { 1606 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 1607 adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs; 1608 adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs; 1609 } 1610 1611 /** 1612 * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine 1613 * 1614 * @ring: amdgpu_ring structure holding ring information 1615 * @src_offset: src GPU address 1616 * @dst_offset: dst GPU address 1617 * @byte_count: number of bytes to xfer 1618 * 1619 * Copy GPU buffers using the DMA engine (VI). 1620 * Used by the amdgpu ttm implementation to move pages if 1621 * registered as the asic copy callback. 1622 */ 1623 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib, 1624 uint64_t src_offset, 1625 uint64_t dst_offset, 1626 uint32_t byte_count) 1627 { 1628 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1629 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1630 ib->ptr[ib->length_dw++] = byte_count; 1631 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1632 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1633 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1634 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1635 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1636 } 1637 1638 /** 1639 * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine 1640 * 1641 * @ring: amdgpu_ring structure holding ring information 1642 * @src_data: value to write to buffer 1643 * @dst_offset: dst GPU address 1644 * @byte_count: number of bytes to xfer 1645 * 1646 * Fill GPU buffers using the DMA engine (VI). 1647 */ 1648 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib, 1649 uint32_t src_data, 1650 uint64_t dst_offset, 1651 uint32_t byte_count) 1652 { 1653 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1654 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1655 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1656 ib->ptr[ib->length_dw++] = src_data; 1657 ib->ptr[ib->length_dw++] = byte_count; 1658 } 1659 1660 static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = { 1661 .copy_max_bytes = 0x1fffff, 1662 .copy_num_dw = 7, 1663 .emit_copy_buffer = sdma_v3_0_emit_copy_buffer, 1664 1665 .fill_max_bytes = 0x1fffff, 1666 .fill_num_dw = 5, 1667 .emit_fill_buffer = sdma_v3_0_emit_fill_buffer, 1668 }; 1669 1670 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev) 1671 { 1672 if (adev->mman.buffer_funcs == NULL) { 1673 adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs; 1674 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1675 } 1676 } 1677 1678 static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = { 1679 .copy_pte = sdma_v3_0_vm_copy_pte, 1680 .write_pte = sdma_v3_0_vm_write_pte, 1681 .set_pte_pde = sdma_v3_0_vm_set_pte_pde, 1682 }; 1683 1684 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1685 { 1686 unsigned i; 1687 1688 if (adev->vm_manager.vm_pte_funcs == NULL) { 1689 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs; 1690 for (i = 0; i < adev->sdma.num_instances; i++) 1691 adev->vm_manager.vm_pte_rings[i] = 1692 &adev->sdma.instance[i].ring; 1693 1694 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances; 1695 } 1696 } 1697