1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_ucode.h" 28 #include "amdgpu_trace.h" 29 #include "vi.h" 30 #include "vid.h" 31 32 #include "oss/oss_3_0_d.h" 33 #include "oss/oss_3_0_sh_mask.h" 34 35 #include "gmc/gmc_8_1_d.h" 36 #include "gmc/gmc_8_1_sh_mask.h" 37 38 #include "gca/gfx_8_0_d.h" 39 #include "gca/gfx_8_0_enum.h" 40 #include "gca/gfx_8_0_sh_mask.h" 41 42 #include "bif/bif_5_0_d.h" 43 #include "bif/bif_5_0_sh_mask.h" 44 45 #include "tonga_sdma_pkt_open.h" 46 47 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev); 48 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev); 49 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev); 50 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev); 51 52 MODULE_FIRMWARE("amdgpu/tonga_sdma.bin"); 53 MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin"); 54 MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin"); 55 MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin"); 56 MODULE_FIRMWARE("amdgpu/fiji_sdma.bin"); 57 MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin"); 58 MODULE_FIRMWARE("amdgpu/stoney_sdma.bin"); 59 60 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = 61 { 62 SDMA0_REGISTER_OFFSET, 63 SDMA1_REGISTER_OFFSET 64 }; 65 66 static const u32 golden_settings_tonga_a11[] = 67 { 68 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 69 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 70 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 71 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 72 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 73 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 74 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 75 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 76 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 77 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 78 }; 79 80 static const u32 tonga_mgcg_cgcg_init[] = 81 { 82 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 83 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 84 }; 85 86 static const u32 golden_settings_fiji_a10[] = 87 { 88 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 89 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 90 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 91 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 92 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 93 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 94 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 95 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 96 }; 97 98 static const u32 fiji_mgcg_cgcg_init[] = 99 { 100 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 101 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 102 }; 103 104 static const u32 cz_golden_settings_a11[] = 105 { 106 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 107 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 108 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, 109 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, 110 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, 111 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, 112 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 113 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 114 mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100, 115 mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800, 116 mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100, 117 mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100, 118 }; 119 120 static const u32 cz_mgcg_cgcg_init[] = 121 { 122 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 123 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 124 }; 125 126 static const u32 stoney_golden_settings_a11[] = 127 { 128 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, 129 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, 130 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, 131 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, 132 }; 133 134 static const u32 stoney_mgcg_cgcg_init[] = 135 { 136 mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100, 137 }; 138 139 /* 140 * sDMA - System DMA 141 * Starting with CIK, the GPU has new asynchronous 142 * DMA engines. These engines are used for compute 143 * and gfx. There are two DMA engines (SDMA0, SDMA1) 144 * and each one supports 1 ring buffer used for gfx 145 * and 2 queues used for compute. 146 * 147 * The programming model is very similar to the CP 148 * (ring buffer, IBs, etc.), but sDMA has it's own 149 * packet format that is different from the PM4 format 150 * used by the CP. sDMA supports copying data, writing 151 * embedded data, solid fills, and a number of other 152 * things. It also has support for tiling/detiling of 153 * buffers. 154 */ 155 156 static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev) 157 { 158 switch (adev->asic_type) { 159 case CHIP_FIJI: 160 amdgpu_program_register_sequence(adev, 161 fiji_mgcg_cgcg_init, 162 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); 163 amdgpu_program_register_sequence(adev, 164 golden_settings_fiji_a10, 165 (const u32)ARRAY_SIZE(golden_settings_fiji_a10)); 166 break; 167 case CHIP_TONGA: 168 amdgpu_program_register_sequence(adev, 169 tonga_mgcg_cgcg_init, 170 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); 171 amdgpu_program_register_sequence(adev, 172 golden_settings_tonga_a11, 173 (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); 174 break; 175 case CHIP_CARRIZO: 176 amdgpu_program_register_sequence(adev, 177 cz_mgcg_cgcg_init, 178 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); 179 amdgpu_program_register_sequence(adev, 180 cz_golden_settings_a11, 181 (const u32)ARRAY_SIZE(cz_golden_settings_a11)); 182 break; 183 case CHIP_STONEY: 184 amdgpu_program_register_sequence(adev, 185 stoney_mgcg_cgcg_init, 186 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); 187 amdgpu_program_register_sequence(adev, 188 stoney_golden_settings_a11, 189 (const u32)ARRAY_SIZE(stoney_golden_settings_a11)); 190 break; 191 default: 192 break; 193 } 194 } 195 196 /** 197 * sdma_v3_0_init_microcode - load ucode images from disk 198 * 199 * @adev: amdgpu_device pointer 200 * 201 * Use the firmware interface to load the ucode images into 202 * the driver (not loaded into hw). 203 * Returns 0 on success, error on failure. 204 */ 205 static int sdma_v3_0_init_microcode(struct amdgpu_device *adev) 206 { 207 const char *chip_name; 208 char fw_name[30]; 209 int err = 0, i; 210 struct amdgpu_firmware_info *info = NULL; 211 const struct common_firmware_header *header = NULL; 212 const struct sdma_firmware_header_v1_0 *hdr; 213 214 DRM_DEBUG("\n"); 215 216 switch (adev->asic_type) { 217 case CHIP_TONGA: 218 chip_name = "tonga"; 219 break; 220 case CHIP_FIJI: 221 chip_name = "fiji"; 222 break; 223 case CHIP_CARRIZO: 224 chip_name = "carrizo"; 225 break; 226 case CHIP_STONEY: 227 chip_name = "stoney"; 228 break; 229 default: BUG(); 230 } 231 232 for (i = 0; i < adev->sdma.num_instances; i++) { 233 if (i == 0) 234 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 235 else 236 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); 237 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 238 if (err) 239 goto out; 240 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); 241 if (err) 242 goto out; 243 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 244 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 245 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 246 if (adev->sdma.instance[i].feature_version >= 20) 247 adev->sdma.instance[i].burst_nop = true; 248 249 if (adev->firmware.smu_load) { 250 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 251 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 252 info->fw = adev->sdma.instance[i].fw; 253 header = (const struct common_firmware_header *)info->fw->data; 254 adev->firmware.fw_size += 255 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 256 } 257 } 258 out: 259 if (err) { 260 printk(KERN_ERR 261 "sdma_v3_0: Failed to load firmware \"%s\"\n", 262 fw_name); 263 for (i = 0; i < adev->sdma.num_instances; i++) { 264 release_firmware(adev->sdma.instance[i].fw); 265 adev->sdma.instance[i].fw = NULL; 266 } 267 } 268 return err; 269 } 270 271 /** 272 * sdma_v3_0_ring_get_rptr - get the current read pointer 273 * 274 * @ring: amdgpu ring pointer 275 * 276 * Get the current rptr from the hardware (VI+). 277 */ 278 static uint32_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring) 279 { 280 u32 rptr; 281 282 /* XXX check if swapping is necessary on BE */ 283 rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2; 284 285 return rptr; 286 } 287 288 /** 289 * sdma_v3_0_ring_get_wptr - get the current write pointer 290 * 291 * @ring: amdgpu ring pointer 292 * 293 * Get the current wptr from the hardware (VI+). 294 */ 295 static uint32_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring) 296 { 297 struct amdgpu_device *adev = ring->adev; 298 u32 wptr; 299 300 if (ring->use_doorbell) { 301 /* XXX check if swapping is necessary on BE */ 302 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2; 303 } else { 304 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1; 305 306 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2; 307 } 308 309 return wptr; 310 } 311 312 /** 313 * sdma_v3_0_ring_set_wptr - commit the write pointer 314 * 315 * @ring: amdgpu ring pointer 316 * 317 * Write the wptr back to the hardware (VI+). 318 */ 319 static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring) 320 { 321 struct amdgpu_device *adev = ring->adev; 322 323 if (ring->use_doorbell) { 324 /* XXX check if swapping is necessary on BE */ 325 adev->wb.wb[ring->wptr_offs] = ring->wptr << 2; 326 WDOORBELL32(ring->doorbell_index, ring->wptr << 2); 327 } else { 328 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1; 329 330 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2); 331 } 332 } 333 334 static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 335 { 336 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); 337 int i; 338 339 for (i = 0; i < count; i++) 340 if (sdma && sdma->burst_nop && (i == 0)) 341 amdgpu_ring_write(ring, ring->nop | 342 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 343 else 344 amdgpu_ring_write(ring, ring->nop); 345 } 346 347 /** 348 * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine 349 * 350 * @ring: amdgpu ring pointer 351 * @ib: IB object to schedule 352 * 353 * Schedule an IB in the DMA ring (VI). 354 */ 355 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring, 356 struct amdgpu_ib *ib) 357 { 358 u32 vmid = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf; 359 u32 next_rptr = ring->wptr + 5; 360 361 while ((next_rptr & 7) != 2) 362 next_rptr++; 363 next_rptr += 6; 364 365 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 366 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 367 amdgpu_ring_write(ring, lower_32_bits(ring->next_rptr_gpu_addr) & 0xfffffffc); 368 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); 369 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); 370 amdgpu_ring_write(ring, next_rptr); 371 372 /* IB packet must end on a 8 DW boundary */ 373 sdma_v3_0_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8); 374 375 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 376 SDMA_PKT_INDIRECT_HEADER_VMID(vmid)); 377 /* base must be 32 byte aligned */ 378 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 379 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 380 amdgpu_ring_write(ring, ib->length_dw); 381 amdgpu_ring_write(ring, 0); 382 amdgpu_ring_write(ring, 0); 383 384 } 385 386 /** 387 * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 388 * 389 * @ring: amdgpu ring pointer 390 * 391 * Emit an hdp flush packet on the requested DMA ring. 392 */ 393 static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 394 { 395 u32 ref_and_mask = 0; 396 397 if (ring == &ring->adev->sdma.instance[0].ring) 398 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); 399 else 400 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); 401 402 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 403 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 404 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 405 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); 406 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); 407 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 408 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 409 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 410 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 411 } 412 413 /** 414 * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring 415 * 416 * @ring: amdgpu ring pointer 417 * @fence: amdgpu fence object 418 * 419 * Add a DMA fence packet to the ring to write 420 * the fence seq number and DMA trap packet to generate 421 * an interrupt if needed (VI). 422 */ 423 static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 424 unsigned flags) 425 { 426 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 427 /* write the fence */ 428 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 429 amdgpu_ring_write(ring, lower_32_bits(addr)); 430 amdgpu_ring_write(ring, upper_32_bits(addr)); 431 amdgpu_ring_write(ring, lower_32_bits(seq)); 432 433 /* optionally write high bits as well */ 434 if (write64bit) { 435 addr += 4; 436 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 437 amdgpu_ring_write(ring, lower_32_bits(addr)); 438 amdgpu_ring_write(ring, upper_32_bits(addr)); 439 amdgpu_ring_write(ring, upper_32_bits(seq)); 440 } 441 442 /* generate an interrupt */ 443 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 444 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 445 } 446 447 /** 448 * sdma_v3_0_gfx_stop - stop the gfx async dma engines 449 * 450 * @adev: amdgpu_device pointer 451 * 452 * Stop the gfx async dma ring buffers (VI). 453 */ 454 static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev) 455 { 456 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 457 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 458 u32 rb_cntl, ib_cntl; 459 int i; 460 461 if ((adev->mman.buffer_funcs_ring == sdma0) || 462 (adev->mman.buffer_funcs_ring == sdma1)) 463 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); 464 465 for (i = 0; i < adev->sdma.num_instances; i++) { 466 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 467 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 468 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 469 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 470 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 471 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 472 } 473 sdma0->ready = false; 474 sdma1->ready = false; 475 } 476 477 /** 478 * sdma_v3_0_rlc_stop - stop the compute async dma engines 479 * 480 * @adev: amdgpu_device pointer 481 * 482 * Stop the compute async dma queues (VI). 483 */ 484 static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev) 485 { 486 /* XXX todo */ 487 } 488 489 /** 490 * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch 491 * 492 * @adev: amdgpu_device pointer 493 * @enable: enable/disable the DMA MEs context switch. 494 * 495 * Halt or unhalt the async dma engines context switch (VI). 496 */ 497 static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 498 { 499 u32 f32_cntl; 500 int i; 501 502 for (i = 0; i < adev->sdma.num_instances; i++) { 503 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); 504 if (enable) 505 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 506 AUTO_CTXSW_ENABLE, 1); 507 else 508 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 509 AUTO_CTXSW_ENABLE, 0); 510 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); 511 } 512 } 513 514 /** 515 * sdma_v3_0_enable - stop the async dma engines 516 * 517 * @adev: amdgpu_device pointer 518 * @enable: enable/disable the DMA MEs. 519 * 520 * Halt or unhalt the async dma engines (VI). 521 */ 522 static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable) 523 { 524 u32 f32_cntl; 525 int i; 526 527 if (enable == false) { 528 sdma_v3_0_gfx_stop(adev); 529 sdma_v3_0_rlc_stop(adev); 530 } 531 532 for (i = 0; i < adev->sdma.num_instances; i++) { 533 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); 534 if (enable) 535 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); 536 else 537 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); 538 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); 539 } 540 } 541 542 /** 543 * sdma_v3_0_gfx_resume - setup and start the async dma engines 544 * 545 * @adev: amdgpu_device pointer 546 * 547 * Set up the gfx DMA ring buffers and enable them (VI). 548 * Returns 0 for success, error for failure. 549 */ 550 static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) 551 { 552 struct amdgpu_ring *ring; 553 u32 rb_cntl, ib_cntl; 554 u32 rb_bufsz; 555 u32 wb_offset; 556 u32 doorbell; 557 int i, j, r; 558 559 for (i = 0; i < adev->sdma.num_instances; i++) { 560 ring = &adev->sdma.instance[i].ring; 561 wb_offset = (ring->rptr_offs * 4); 562 563 mutex_lock(&adev->srbm_mutex); 564 for (j = 0; j < 16; j++) { 565 vi_srbm_select(adev, 0, 0, 0, j); 566 /* SDMA GFX */ 567 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); 568 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); 569 } 570 vi_srbm_select(adev, 0, 0, 0, 0); 571 mutex_unlock(&adev->srbm_mutex); 572 573 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); 574 575 /* Set ring buffer size in dwords */ 576 rb_bufsz = order_base_2(ring->ring_size / 4); 577 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 578 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 579 #ifdef __BIG_ENDIAN 580 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 581 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 582 RPTR_WRITEBACK_SWAP_ENABLE, 1); 583 #endif 584 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 585 586 /* Initialize the ring buffer's read and write pointers */ 587 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); 588 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); 589 590 /* set the wb address whether it's enabled or not */ 591 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], 592 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 593 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], 594 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 595 596 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 597 598 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); 599 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); 600 601 ring->wptr = 0; 602 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2); 603 604 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]); 605 606 if (ring->use_doorbell) { 607 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, 608 OFFSET, ring->doorbell_index); 609 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 610 } else { 611 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 612 } 613 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell); 614 615 /* enable DMA RB */ 616 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 617 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 618 619 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 620 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 621 #ifdef __BIG_ENDIAN 622 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 623 #endif 624 /* enable DMA IBs */ 625 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 626 627 ring->ready = true; 628 629 r = amdgpu_ring_test_ring(ring); 630 if (r) { 631 ring->ready = false; 632 return r; 633 } 634 635 if (adev->mman.buffer_funcs_ring == ring) 636 amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size); 637 } 638 639 return 0; 640 } 641 642 /** 643 * sdma_v3_0_rlc_resume - setup and start the async dma engines 644 * 645 * @adev: amdgpu_device pointer 646 * 647 * Set up the compute DMA queues and enable them (VI). 648 * Returns 0 for success, error for failure. 649 */ 650 static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev) 651 { 652 /* XXX todo */ 653 return 0; 654 } 655 656 /** 657 * sdma_v3_0_load_microcode - load the sDMA ME ucode 658 * 659 * @adev: amdgpu_device pointer 660 * 661 * Loads the sDMA0/1 ucode. 662 * Returns 0 for success, -EINVAL if the ucode is not available. 663 */ 664 static int sdma_v3_0_load_microcode(struct amdgpu_device *adev) 665 { 666 const struct sdma_firmware_header_v1_0 *hdr; 667 const __le32 *fw_data; 668 u32 fw_size; 669 int i, j; 670 671 /* halt the MEs */ 672 sdma_v3_0_enable(adev, false); 673 674 for (i = 0; i < adev->sdma.num_instances; i++) { 675 if (!adev->sdma.instance[i].fw) 676 return -EINVAL; 677 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 678 amdgpu_ucode_print_sdma_hdr(&hdr->header); 679 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 680 fw_data = (const __le32 *) 681 (adev->sdma.instance[i].fw->data + 682 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 683 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0); 684 for (j = 0; j < fw_size; j++) 685 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++)); 686 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version); 687 } 688 689 return 0; 690 } 691 692 /** 693 * sdma_v3_0_start - setup and start the async dma engines 694 * 695 * @adev: amdgpu_device pointer 696 * 697 * Set up the DMA engines and enable them (VI). 698 * Returns 0 for success, error for failure. 699 */ 700 static int sdma_v3_0_start(struct amdgpu_device *adev) 701 { 702 int r, i; 703 704 if (!adev->pp_enabled) { 705 if (!adev->firmware.smu_load) { 706 r = sdma_v3_0_load_microcode(adev); 707 if (r) 708 return r; 709 } else { 710 for (i = 0; i < adev->sdma.num_instances; i++) { 711 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, 712 (i == 0) ? 713 AMDGPU_UCODE_ID_SDMA0 : 714 AMDGPU_UCODE_ID_SDMA1); 715 if (r) 716 return -EINVAL; 717 } 718 } 719 } 720 721 /* unhalt the MEs */ 722 sdma_v3_0_enable(adev, true); 723 /* enable sdma ring preemption */ 724 sdma_v3_0_ctx_switch_enable(adev, true); 725 726 /* start the gfx rings and rlc compute queues */ 727 r = sdma_v3_0_gfx_resume(adev); 728 if (r) 729 return r; 730 r = sdma_v3_0_rlc_resume(adev); 731 if (r) 732 return r; 733 734 return 0; 735 } 736 737 /** 738 * sdma_v3_0_ring_test_ring - simple async dma engine test 739 * 740 * @ring: amdgpu_ring structure holding ring information 741 * 742 * Test the DMA engine by writing using it to write an 743 * value to memory. (VI). 744 * Returns 0 for success, error for failure. 745 */ 746 static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring) 747 { 748 struct amdgpu_device *adev = ring->adev; 749 unsigned i; 750 unsigned index; 751 int r; 752 u32 tmp; 753 u64 gpu_addr; 754 755 r = amdgpu_wb_get(adev, &index); 756 if (r) { 757 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 758 return r; 759 } 760 761 gpu_addr = adev->wb.gpu_addr + (index * 4); 762 tmp = 0xCAFEDEAD; 763 adev->wb.wb[index] = cpu_to_le32(tmp); 764 765 r = amdgpu_ring_alloc(ring, 5); 766 if (r) { 767 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 768 amdgpu_wb_free(adev, index); 769 return r; 770 } 771 772 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 773 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 774 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 775 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 776 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); 777 amdgpu_ring_write(ring, 0xDEADBEEF); 778 amdgpu_ring_commit(ring); 779 780 for (i = 0; i < adev->usec_timeout; i++) { 781 tmp = le32_to_cpu(adev->wb.wb[index]); 782 if (tmp == 0xDEADBEEF) 783 break; 784 DRM_UDELAY(1); 785 } 786 787 if (i < adev->usec_timeout) { 788 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 789 } else { 790 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 791 ring->idx, tmp); 792 r = -EINVAL; 793 } 794 amdgpu_wb_free(adev, index); 795 796 return r; 797 } 798 799 /** 800 * sdma_v3_0_ring_test_ib - test an IB on the DMA engine 801 * 802 * @ring: amdgpu_ring structure holding ring information 803 * 804 * Test a simple IB in the DMA ring (VI). 805 * Returns 0 on success, error on failure. 806 */ 807 static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring) 808 { 809 struct amdgpu_device *adev = ring->adev; 810 struct amdgpu_ib ib; 811 struct fence *f = NULL; 812 unsigned i; 813 unsigned index; 814 int r; 815 u32 tmp = 0; 816 u64 gpu_addr; 817 818 r = amdgpu_wb_get(adev, &index); 819 if (r) { 820 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 821 return r; 822 } 823 824 gpu_addr = adev->wb.gpu_addr + (index * 4); 825 tmp = 0xCAFEDEAD; 826 adev->wb.wb[index] = cpu_to_le32(tmp); 827 memset(&ib, 0, sizeof(ib)); 828 r = amdgpu_ib_get(adev, NULL, 256, &ib); 829 if (r) { 830 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r); 831 goto err0; 832 } 833 834 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 835 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 836 ib.ptr[1] = lower_32_bits(gpu_addr); 837 ib.ptr[2] = upper_32_bits(gpu_addr); 838 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1); 839 ib.ptr[4] = 0xDEADBEEF; 840 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 841 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 842 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 843 ib.length_dw = 8; 844 845 r = amdgpu_ib_schedule(ring, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED, 846 NULL, &f); 847 if (r) 848 goto err1; 849 850 r = fence_wait(f, false); 851 if (r) { 852 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); 853 goto err1; 854 } 855 for (i = 0; i < adev->usec_timeout; i++) { 856 tmp = le32_to_cpu(adev->wb.wb[index]); 857 if (tmp == 0xDEADBEEF) 858 break; 859 DRM_UDELAY(1); 860 } 861 if (i < adev->usec_timeout) { 862 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", 863 ring->idx, i); 864 goto err1; 865 } else { 866 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); 867 r = -EINVAL; 868 } 869 err1: 870 fence_put(f); 871 amdgpu_ib_free(adev, &ib); 872 err0: 873 amdgpu_wb_free(adev, index); 874 return r; 875 } 876 877 /** 878 * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART 879 * 880 * @ib: indirect buffer to fill with commands 881 * @pe: addr of the page entry 882 * @src: src addr to copy from 883 * @count: number of page entries to update 884 * 885 * Update PTEs by copying them from the GART using sDMA (CIK). 886 */ 887 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib, 888 uint64_t pe, uint64_t src, 889 unsigned count) 890 { 891 while (count) { 892 unsigned bytes = count * 8; 893 if (bytes > 0x1FFFF8) 894 bytes = 0x1FFFF8; 895 896 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 897 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 898 ib->ptr[ib->length_dw++] = bytes; 899 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 900 ib->ptr[ib->length_dw++] = lower_32_bits(src); 901 ib->ptr[ib->length_dw++] = upper_32_bits(src); 902 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 903 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 904 905 pe += bytes; 906 src += bytes; 907 count -= bytes / 8; 908 } 909 } 910 911 /** 912 * sdma_v3_0_vm_write_pte - update PTEs by writing them manually 913 * 914 * @ib: indirect buffer to fill with commands 915 * @pe: addr of the page entry 916 * @addr: dst addr to write into pe 917 * @count: number of page entries to update 918 * @incr: increase next addr by incr bytes 919 * @flags: access flags 920 * 921 * Update PTEs by writing them manually using sDMA (CIK). 922 */ 923 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, 924 const dma_addr_t *pages_addr, uint64_t pe, 925 uint64_t addr, unsigned count, 926 uint32_t incr, uint32_t flags) 927 { 928 uint64_t value; 929 unsigned ndw; 930 931 while (count) { 932 ndw = count * 2; 933 if (ndw > 0xFFFFE) 934 ndw = 0xFFFFE; 935 936 /* for non-physically contiguous pages (system) */ 937 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 938 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 939 ib->ptr[ib->length_dw++] = pe; 940 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 941 ib->ptr[ib->length_dw++] = ndw; 942 for (; ndw > 0; ndw -= 2, --count, pe += 8) { 943 value = amdgpu_vm_map_gart(pages_addr, addr); 944 addr += incr; 945 value |= flags; 946 ib->ptr[ib->length_dw++] = value; 947 ib->ptr[ib->length_dw++] = upper_32_bits(value); 948 } 949 } 950 } 951 952 /** 953 * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA 954 * 955 * @ib: indirect buffer to fill with commands 956 * @pe: addr of the page entry 957 * @addr: dst addr to write into pe 958 * @count: number of page entries to update 959 * @incr: increase next addr by incr bytes 960 * @flags: access flags 961 * 962 * Update the page tables using sDMA (CIK). 963 */ 964 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, 965 uint64_t pe, 966 uint64_t addr, unsigned count, 967 uint32_t incr, uint32_t flags) 968 { 969 uint64_t value; 970 unsigned ndw; 971 972 while (count) { 973 ndw = count; 974 if (ndw > 0x7FFFF) 975 ndw = 0x7FFFF; 976 977 if (flags & AMDGPU_PTE_VALID) 978 value = addr; 979 else 980 value = 0; 981 982 /* for physically contiguous pages (vram) */ 983 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE); 984 ib->ptr[ib->length_dw++] = pe; /* dst addr */ 985 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 986 ib->ptr[ib->length_dw++] = flags; /* mask */ 987 ib->ptr[ib->length_dw++] = 0; 988 ib->ptr[ib->length_dw++] = value; /* value */ 989 ib->ptr[ib->length_dw++] = upper_32_bits(value); 990 ib->ptr[ib->length_dw++] = incr; /* increment size */ 991 ib->ptr[ib->length_dw++] = 0; 992 ib->ptr[ib->length_dw++] = ndw; /* number of entries */ 993 994 pe += ndw * 8; 995 addr += ndw * incr; 996 count -= ndw; 997 } 998 } 999 1000 /** 1001 * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw 1002 * 1003 * @ib: indirect buffer to fill with padding 1004 * 1005 */ 1006 static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1007 { 1008 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); 1009 u32 pad_count; 1010 int i; 1011 1012 pad_count = (8 - (ib->length_dw & 0x7)) % 8; 1013 for (i = 0; i < pad_count; i++) 1014 if (sdma && sdma->burst_nop && (i == 0)) 1015 ib->ptr[ib->length_dw++] = 1016 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1017 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1018 else 1019 ib->ptr[ib->length_dw++] = 1020 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1021 } 1022 1023 /** 1024 * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA 1025 * 1026 * @ring: amdgpu_ring pointer 1027 * @vm: amdgpu_vm pointer 1028 * 1029 * Update the page table base and flush the VM TLB 1030 * using sDMA (VI). 1031 */ 1032 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1033 unsigned vm_id, uint64_t pd_addr) 1034 { 1035 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1036 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1037 if (vm_id < 8) { 1038 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id)); 1039 } else { 1040 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8)); 1041 } 1042 amdgpu_ring_write(ring, pd_addr >> 12); 1043 1044 /* flush TLB */ 1045 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1046 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1047 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 1048 amdgpu_ring_write(ring, 1 << vm_id); 1049 1050 /* wait for flush */ 1051 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1052 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1053 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */ 1054 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); 1055 amdgpu_ring_write(ring, 0); 1056 amdgpu_ring_write(ring, 0); /* reference */ 1057 amdgpu_ring_write(ring, 0); /* mask */ 1058 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1059 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 1060 } 1061 1062 static int sdma_v3_0_early_init(void *handle) 1063 { 1064 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1065 1066 switch (adev->asic_type) { 1067 case CHIP_STONEY: 1068 adev->sdma.num_instances = 1; 1069 break; 1070 default: 1071 adev->sdma.num_instances = SDMA_MAX_INSTANCE; 1072 break; 1073 } 1074 1075 sdma_v3_0_set_ring_funcs(adev); 1076 sdma_v3_0_set_buffer_funcs(adev); 1077 sdma_v3_0_set_vm_pte_funcs(adev); 1078 sdma_v3_0_set_irq_funcs(adev); 1079 1080 return 0; 1081 } 1082 1083 static int sdma_v3_0_sw_init(void *handle) 1084 { 1085 struct amdgpu_ring *ring; 1086 int r, i; 1087 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1088 1089 /* SDMA trap event */ 1090 r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq); 1091 if (r) 1092 return r; 1093 1094 /* SDMA Privileged inst */ 1095 r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq); 1096 if (r) 1097 return r; 1098 1099 /* SDMA Privileged inst */ 1100 r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq); 1101 if (r) 1102 return r; 1103 1104 r = sdma_v3_0_init_microcode(adev); 1105 if (r) { 1106 DRM_ERROR("Failed to load sdma firmware!\n"); 1107 return r; 1108 } 1109 1110 for (i = 0; i < adev->sdma.num_instances; i++) { 1111 ring = &adev->sdma.instance[i].ring; 1112 ring->ring_obj = NULL; 1113 ring->use_doorbell = true; 1114 ring->doorbell_index = (i == 0) ? 1115 AMDGPU_DOORBELL_sDMA_ENGINE0 : AMDGPU_DOORBELL_sDMA_ENGINE1; 1116 1117 sprintf(ring->name, "sdma%d", i); 1118 r = amdgpu_ring_init(adev, ring, 256 * 1024, 1119 SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, 1120 &adev->sdma.trap_irq, 1121 (i == 0) ? 1122 AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1, 1123 AMDGPU_RING_TYPE_SDMA); 1124 if (r) 1125 return r; 1126 } 1127 1128 return r; 1129 } 1130 1131 static int sdma_v3_0_sw_fini(void *handle) 1132 { 1133 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1134 int i; 1135 1136 for (i = 0; i < adev->sdma.num_instances; i++) 1137 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1138 1139 return 0; 1140 } 1141 1142 static int sdma_v3_0_hw_init(void *handle) 1143 { 1144 int r; 1145 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1146 1147 sdma_v3_0_init_golden_registers(adev); 1148 1149 r = sdma_v3_0_start(adev); 1150 if (r) 1151 return r; 1152 1153 return r; 1154 } 1155 1156 static int sdma_v3_0_hw_fini(void *handle) 1157 { 1158 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1159 1160 sdma_v3_0_ctx_switch_enable(adev, false); 1161 sdma_v3_0_enable(adev, false); 1162 1163 return 0; 1164 } 1165 1166 static int sdma_v3_0_suspend(void *handle) 1167 { 1168 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1169 1170 return sdma_v3_0_hw_fini(adev); 1171 } 1172 1173 static int sdma_v3_0_resume(void *handle) 1174 { 1175 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1176 1177 return sdma_v3_0_hw_init(adev); 1178 } 1179 1180 static bool sdma_v3_0_is_idle(void *handle) 1181 { 1182 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1183 u32 tmp = RREG32(mmSRBM_STATUS2); 1184 1185 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | 1186 SRBM_STATUS2__SDMA1_BUSY_MASK)) 1187 return false; 1188 1189 return true; 1190 } 1191 1192 static int sdma_v3_0_wait_for_idle(void *handle) 1193 { 1194 unsigned i; 1195 u32 tmp; 1196 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1197 1198 for (i = 0; i < adev->usec_timeout; i++) { 1199 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | 1200 SRBM_STATUS2__SDMA1_BUSY_MASK); 1201 1202 if (!tmp) 1203 return 0; 1204 udelay(1); 1205 } 1206 return -ETIMEDOUT; 1207 } 1208 1209 static void sdma_v3_0_print_status(void *handle) 1210 { 1211 int i, j; 1212 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1213 1214 dev_info(adev->dev, "VI SDMA registers\n"); 1215 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", 1216 RREG32(mmSRBM_STATUS2)); 1217 for (i = 0; i < adev->sdma.num_instances; i++) { 1218 dev_info(adev->dev, " SDMA%d_STATUS_REG=0x%08X\n", 1219 i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i])); 1220 dev_info(adev->dev, " SDMA%d_F32_CNTL=0x%08X\n", 1221 i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i])); 1222 dev_info(adev->dev, " SDMA%d_CNTL=0x%08X\n", 1223 i, RREG32(mmSDMA0_CNTL + sdma_offsets[i])); 1224 dev_info(adev->dev, " SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n", 1225 i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i])); 1226 dev_info(adev->dev, " SDMA%d_GFX_IB_CNTL=0x%08X\n", 1227 i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i])); 1228 dev_info(adev->dev, " SDMA%d_GFX_RB_CNTL=0x%08X\n", 1229 i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i])); 1230 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR=0x%08X\n", 1231 i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i])); 1232 dev_info(adev->dev, " SDMA%d_GFX_RB_WPTR=0x%08X\n", 1233 i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i])); 1234 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n", 1235 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i])); 1236 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n", 1237 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i])); 1238 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE=0x%08X\n", 1239 i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i])); 1240 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE_HI=0x%08X\n", 1241 i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i])); 1242 dev_info(adev->dev, " SDMA%d_GFX_DOORBELL=0x%08X\n", 1243 i, RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i])); 1244 mutex_lock(&adev->srbm_mutex); 1245 for (j = 0; j < 16; j++) { 1246 vi_srbm_select(adev, 0, 0, 0, j); 1247 dev_info(adev->dev, " VM %d:\n", j); 1248 dev_info(adev->dev, " SDMA%d_GFX_VIRTUAL_ADDR=0x%08X\n", 1249 i, RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i])); 1250 dev_info(adev->dev, " SDMA%d_GFX_APE1_CNTL=0x%08X\n", 1251 i, RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i])); 1252 } 1253 vi_srbm_select(adev, 0, 0, 0, 0); 1254 mutex_unlock(&adev->srbm_mutex); 1255 } 1256 } 1257 1258 static int sdma_v3_0_soft_reset(void *handle) 1259 { 1260 u32 srbm_soft_reset = 0; 1261 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1262 u32 tmp = RREG32(mmSRBM_STATUS2); 1263 1264 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) { 1265 /* sdma0 */ 1266 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); 1267 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); 1268 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); 1269 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK; 1270 } 1271 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) { 1272 /* sdma1 */ 1273 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); 1274 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); 1275 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); 1276 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK; 1277 } 1278 1279 if (srbm_soft_reset) { 1280 sdma_v3_0_print_status((void *)adev); 1281 1282 tmp = RREG32(mmSRBM_SOFT_RESET); 1283 tmp |= srbm_soft_reset; 1284 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1285 WREG32(mmSRBM_SOFT_RESET, tmp); 1286 tmp = RREG32(mmSRBM_SOFT_RESET); 1287 1288 udelay(50); 1289 1290 tmp &= ~srbm_soft_reset; 1291 WREG32(mmSRBM_SOFT_RESET, tmp); 1292 tmp = RREG32(mmSRBM_SOFT_RESET); 1293 1294 /* Wait a little for things to settle down */ 1295 udelay(50); 1296 1297 sdma_v3_0_print_status((void *)adev); 1298 } 1299 1300 return 0; 1301 } 1302 1303 static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev, 1304 struct amdgpu_irq_src *source, 1305 unsigned type, 1306 enum amdgpu_interrupt_state state) 1307 { 1308 u32 sdma_cntl; 1309 1310 switch (type) { 1311 case AMDGPU_SDMA_IRQ_TRAP0: 1312 switch (state) { 1313 case AMDGPU_IRQ_STATE_DISABLE: 1314 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1315 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1316 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1317 break; 1318 case AMDGPU_IRQ_STATE_ENABLE: 1319 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1320 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1321 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1322 break; 1323 default: 1324 break; 1325 } 1326 break; 1327 case AMDGPU_SDMA_IRQ_TRAP1: 1328 switch (state) { 1329 case AMDGPU_IRQ_STATE_DISABLE: 1330 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1331 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1332 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1333 break; 1334 case AMDGPU_IRQ_STATE_ENABLE: 1335 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1336 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1337 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1338 break; 1339 default: 1340 break; 1341 } 1342 break; 1343 default: 1344 break; 1345 } 1346 return 0; 1347 } 1348 1349 static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev, 1350 struct amdgpu_irq_src *source, 1351 struct amdgpu_iv_entry *entry) 1352 { 1353 u8 instance_id, queue_id; 1354 1355 instance_id = (entry->ring_id & 0x3) >> 0; 1356 queue_id = (entry->ring_id & 0xc) >> 2; 1357 DRM_DEBUG("IH: SDMA trap\n"); 1358 switch (instance_id) { 1359 case 0: 1360 switch (queue_id) { 1361 case 0: 1362 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1363 break; 1364 case 1: 1365 /* XXX compute */ 1366 break; 1367 case 2: 1368 /* XXX compute */ 1369 break; 1370 } 1371 break; 1372 case 1: 1373 switch (queue_id) { 1374 case 0: 1375 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1376 break; 1377 case 1: 1378 /* XXX compute */ 1379 break; 1380 case 2: 1381 /* XXX compute */ 1382 break; 1383 } 1384 break; 1385 } 1386 return 0; 1387 } 1388 1389 static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1390 struct amdgpu_irq_src *source, 1391 struct amdgpu_iv_entry *entry) 1392 { 1393 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1394 schedule_work(&adev->reset_work); 1395 return 0; 1396 } 1397 1398 static void fiji_update_sdma_medium_grain_clock_gating( 1399 struct amdgpu_device *adev, 1400 bool enable) 1401 { 1402 uint32_t temp, data; 1403 1404 if (enable) { 1405 temp = data = RREG32(mmSDMA0_CLK_CTRL); 1406 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1407 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1408 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1409 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1410 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1411 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1412 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1413 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1414 if (data != temp) 1415 WREG32(mmSDMA0_CLK_CTRL, data); 1416 1417 temp = data = RREG32(mmSDMA1_CLK_CTRL); 1418 data &= ~(SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1419 SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1420 SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1421 SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1422 SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1423 SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1424 SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1425 SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1426 1427 if (data != temp) 1428 WREG32(mmSDMA1_CLK_CTRL, data); 1429 } else { 1430 temp = data = RREG32(mmSDMA0_CLK_CTRL); 1431 data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1432 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1433 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1434 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1435 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1436 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1437 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1438 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK; 1439 1440 if (data != temp) 1441 WREG32(mmSDMA0_CLK_CTRL, data); 1442 1443 temp = data = RREG32(mmSDMA1_CLK_CTRL); 1444 data |= SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1445 SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1446 SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1447 SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1448 SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1449 SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1450 SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1451 SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK; 1452 1453 if (data != temp) 1454 WREG32(mmSDMA1_CLK_CTRL, data); 1455 } 1456 } 1457 1458 static void fiji_update_sdma_medium_grain_light_sleep( 1459 struct amdgpu_device *adev, 1460 bool enable) 1461 { 1462 uint32_t temp, data; 1463 1464 if (enable) { 1465 temp = data = RREG32(mmSDMA0_POWER_CNTL); 1466 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1467 1468 if (temp != data) 1469 WREG32(mmSDMA0_POWER_CNTL, data); 1470 1471 temp = data = RREG32(mmSDMA1_POWER_CNTL); 1472 data |= SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1473 1474 if (temp != data) 1475 WREG32(mmSDMA1_POWER_CNTL, data); 1476 } else { 1477 temp = data = RREG32(mmSDMA0_POWER_CNTL); 1478 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1479 1480 if (temp != data) 1481 WREG32(mmSDMA0_POWER_CNTL, data); 1482 1483 temp = data = RREG32(mmSDMA1_POWER_CNTL); 1484 data &= ~SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1485 1486 if (temp != data) 1487 WREG32(mmSDMA1_POWER_CNTL, data); 1488 } 1489 } 1490 1491 static int sdma_v3_0_set_clockgating_state(void *handle, 1492 enum amd_clockgating_state state) 1493 { 1494 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1495 1496 switch (adev->asic_type) { 1497 case CHIP_FIJI: 1498 fiji_update_sdma_medium_grain_clock_gating(adev, 1499 state == AMD_CG_STATE_GATE ? true : false); 1500 fiji_update_sdma_medium_grain_light_sleep(adev, 1501 state == AMD_CG_STATE_GATE ? true : false); 1502 break; 1503 default: 1504 break; 1505 } 1506 return 0; 1507 } 1508 1509 static int sdma_v3_0_set_powergating_state(void *handle, 1510 enum amd_powergating_state state) 1511 { 1512 return 0; 1513 } 1514 1515 const struct amd_ip_funcs sdma_v3_0_ip_funcs = { 1516 .early_init = sdma_v3_0_early_init, 1517 .late_init = NULL, 1518 .sw_init = sdma_v3_0_sw_init, 1519 .sw_fini = sdma_v3_0_sw_fini, 1520 .hw_init = sdma_v3_0_hw_init, 1521 .hw_fini = sdma_v3_0_hw_fini, 1522 .suspend = sdma_v3_0_suspend, 1523 .resume = sdma_v3_0_resume, 1524 .is_idle = sdma_v3_0_is_idle, 1525 .wait_for_idle = sdma_v3_0_wait_for_idle, 1526 .soft_reset = sdma_v3_0_soft_reset, 1527 .print_status = sdma_v3_0_print_status, 1528 .set_clockgating_state = sdma_v3_0_set_clockgating_state, 1529 .set_powergating_state = sdma_v3_0_set_powergating_state, 1530 }; 1531 1532 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { 1533 .get_rptr = sdma_v3_0_ring_get_rptr, 1534 .get_wptr = sdma_v3_0_ring_get_wptr, 1535 .set_wptr = sdma_v3_0_ring_set_wptr, 1536 .parse_cs = NULL, 1537 .emit_ib = sdma_v3_0_ring_emit_ib, 1538 .emit_fence = sdma_v3_0_ring_emit_fence, 1539 .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush, 1540 .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush, 1541 .test_ring = sdma_v3_0_ring_test_ring, 1542 .test_ib = sdma_v3_0_ring_test_ib, 1543 .insert_nop = sdma_v3_0_ring_insert_nop, 1544 .pad_ib = sdma_v3_0_ring_pad_ib, 1545 }; 1546 1547 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev) 1548 { 1549 int i; 1550 1551 for (i = 0; i < adev->sdma.num_instances; i++) 1552 adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs; 1553 } 1554 1555 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = { 1556 .set = sdma_v3_0_set_trap_irq_state, 1557 .process = sdma_v3_0_process_trap_irq, 1558 }; 1559 1560 static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = { 1561 .process = sdma_v3_0_process_illegal_inst_irq, 1562 }; 1563 1564 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev) 1565 { 1566 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 1567 adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs; 1568 adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs; 1569 } 1570 1571 /** 1572 * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine 1573 * 1574 * @ring: amdgpu_ring structure holding ring information 1575 * @src_offset: src GPU address 1576 * @dst_offset: dst GPU address 1577 * @byte_count: number of bytes to xfer 1578 * 1579 * Copy GPU buffers using the DMA engine (VI). 1580 * Used by the amdgpu ttm implementation to move pages if 1581 * registered as the asic copy callback. 1582 */ 1583 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib, 1584 uint64_t src_offset, 1585 uint64_t dst_offset, 1586 uint32_t byte_count) 1587 { 1588 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1589 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1590 ib->ptr[ib->length_dw++] = byte_count; 1591 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1592 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1593 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1594 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1595 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1596 } 1597 1598 /** 1599 * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine 1600 * 1601 * @ring: amdgpu_ring structure holding ring information 1602 * @src_data: value to write to buffer 1603 * @dst_offset: dst GPU address 1604 * @byte_count: number of bytes to xfer 1605 * 1606 * Fill GPU buffers using the DMA engine (VI). 1607 */ 1608 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib, 1609 uint32_t src_data, 1610 uint64_t dst_offset, 1611 uint32_t byte_count) 1612 { 1613 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1614 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1615 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1616 ib->ptr[ib->length_dw++] = src_data; 1617 ib->ptr[ib->length_dw++] = byte_count; 1618 } 1619 1620 static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = { 1621 .copy_max_bytes = 0x1fffff, 1622 .copy_num_dw = 7, 1623 .emit_copy_buffer = sdma_v3_0_emit_copy_buffer, 1624 1625 .fill_max_bytes = 0x1fffff, 1626 .fill_num_dw = 5, 1627 .emit_fill_buffer = sdma_v3_0_emit_fill_buffer, 1628 }; 1629 1630 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev) 1631 { 1632 if (adev->mman.buffer_funcs == NULL) { 1633 adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs; 1634 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1635 } 1636 } 1637 1638 static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = { 1639 .copy_pte = sdma_v3_0_vm_copy_pte, 1640 .write_pte = sdma_v3_0_vm_write_pte, 1641 .set_pte_pde = sdma_v3_0_vm_set_pte_pde, 1642 }; 1643 1644 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1645 { 1646 if (adev->vm_manager.vm_pte_funcs == NULL) { 1647 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs; 1648 adev->vm_manager.vm_pte_funcs_ring = &adev->sdma.instance[0].ring; 1649 adev->vm_manager.vm_pte_funcs_ring->is_pte_ring = true; 1650 } 1651 } 1652