1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_ucode.h" 28 #include "amdgpu_trace.h" 29 #include "vi.h" 30 #include "vid.h" 31 32 #include "oss/oss_3_0_d.h" 33 #include "oss/oss_3_0_sh_mask.h" 34 35 #include "gmc/gmc_8_1_d.h" 36 #include "gmc/gmc_8_1_sh_mask.h" 37 38 #include "gca/gfx_8_0_d.h" 39 #include "gca/gfx_8_0_enum.h" 40 #include "gca/gfx_8_0_sh_mask.h" 41 42 #include "bif/bif_5_0_d.h" 43 #include "bif/bif_5_0_sh_mask.h" 44 45 #include "tonga_sdma_pkt_open.h" 46 47 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev); 48 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev); 49 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev); 50 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev); 51 52 MODULE_FIRMWARE("amdgpu/tonga_sdma.bin"); 53 MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin"); 54 MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin"); 55 MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin"); 56 MODULE_FIRMWARE("amdgpu/fiji_sdma.bin"); 57 MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin"); 58 MODULE_FIRMWARE("amdgpu/stoney_sdma.bin"); 59 MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin"); 60 MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin"); 61 MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin"); 62 MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin"); 63 MODULE_FIRMWARE("amdgpu/polaris12_sdma.bin"); 64 MODULE_FIRMWARE("amdgpu/polaris12_sdma1.bin"); 65 MODULE_FIRMWARE("amdgpu/vegam_sdma.bin"); 66 MODULE_FIRMWARE("amdgpu/vegam_sdma1.bin"); 67 68 69 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = 70 { 71 SDMA0_REGISTER_OFFSET, 72 SDMA1_REGISTER_OFFSET 73 }; 74 75 static const u32 golden_settings_tonga_a11[] = 76 { 77 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 78 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 79 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 80 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 81 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 82 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 83 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 84 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 85 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 86 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 87 }; 88 89 static const u32 tonga_mgcg_cgcg_init[] = 90 { 91 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 92 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 93 }; 94 95 static const u32 golden_settings_fiji_a10[] = 96 { 97 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 98 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 99 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 100 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 101 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 102 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 103 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 104 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 105 }; 106 107 static const u32 fiji_mgcg_cgcg_init[] = 108 { 109 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 110 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 111 }; 112 113 static const u32 golden_settings_polaris11_a11[] = 114 { 115 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 116 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 117 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 118 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 119 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 120 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 121 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 122 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 123 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 124 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 125 }; 126 127 static const u32 golden_settings_polaris10_a11[] = 128 { 129 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 130 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 131 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 132 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 133 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 134 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 135 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 136 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 137 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 138 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 139 }; 140 141 static const u32 cz_golden_settings_a11[] = 142 { 143 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 144 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 145 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, 146 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, 147 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, 148 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, 149 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 150 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 151 mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100, 152 mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800, 153 mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100, 154 mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100, 155 }; 156 157 static const u32 cz_mgcg_cgcg_init[] = 158 { 159 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 160 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 161 }; 162 163 static const u32 stoney_golden_settings_a11[] = 164 { 165 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, 166 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, 167 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, 168 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, 169 }; 170 171 static const u32 stoney_mgcg_cgcg_init[] = 172 { 173 mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100, 174 }; 175 176 /* 177 * sDMA - System DMA 178 * Starting with CIK, the GPU has new asynchronous 179 * DMA engines. These engines are used for compute 180 * and gfx. There are two DMA engines (SDMA0, SDMA1) 181 * and each one supports 1 ring buffer used for gfx 182 * and 2 queues used for compute. 183 * 184 * The programming model is very similar to the CP 185 * (ring buffer, IBs, etc.), but sDMA has it's own 186 * packet format that is different from the PM4 format 187 * used by the CP. sDMA supports copying data, writing 188 * embedded data, solid fills, and a number of other 189 * things. It also has support for tiling/detiling of 190 * buffers. 191 */ 192 193 static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev) 194 { 195 switch (adev->asic_type) { 196 case CHIP_FIJI: 197 amdgpu_device_program_register_sequence(adev, 198 fiji_mgcg_cgcg_init, 199 ARRAY_SIZE(fiji_mgcg_cgcg_init)); 200 amdgpu_device_program_register_sequence(adev, 201 golden_settings_fiji_a10, 202 ARRAY_SIZE(golden_settings_fiji_a10)); 203 break; 204 case CHIP_TONGA: 205 amdgpu_device_program_register_sequence(adev, 206 tonga_mgcg_cgcg_init, 207 ARRAY_SIZE(tonga_mgcg_cgcg_init)); 208 amdgpu_device_program_register_sequence(adev, 209 golden_settings_tonga_a11, 210 ARRAY_SIZE(golden_settings_tonga_a11)); 211 break; 212 case CHIP_POLARIS11: 213 case CHIP_POLARIS12: 214 case CHIP_VEGAM: 215 amdgpu_device_program_register_sequence(adev, 216 golden_settings_polaris11_a11, 217 ARRAY_SIZE(golden_settings_polaris11_a11)); 218 break; 219 case CHIP_POLARIS10: 220 amdgpu_device_program_register_sequence(adev, 221 golden_settings_polaris10_a11, 222 ARRAY_SIZE(golden_settings_polaris10_a11)); 223 break; 224 case CHIP_CARRIZO: 225 amdgpu_device_program_register_sequence(adev, 226 cz_mgcg_cgcg_init, 227 ARRAY_SIZE(cz_mgcg_cgcg_init)); 228 amdgpu_device_program_register_sequence(adev, 229 cz_golden_settings_a11, 230 ARRAY_SIZE(cz_golden_settings_a11)); 231 break; 232 case CHIP_STONEY: 233 amdgpu_device_program_register_sequence(adev, 234 stoney_mgcg_cgcg_init, 235 ARRAY_SIZE(stoney_mgcg_cgcg_init)); 236 amdgpu_device_program_register_sequence(adev, 237 stoney_golden_settings_a11, 238 ARRAY_SIZE(stoney_golden_settings_a11)); 239 break; 240 default: 241 break; 242 } 243 } 244 245 static void sdma_v3_0_free_microcode(struct amdgpu_device *adev) 246 { 247 int i; 248 for (i = 0; i < adev->sdma.num_instances; i++) { 249 release_firmware(adev->sdma.instance[i].fw); 250 adev->sdma.instance[i].fw = NULL; 251 } 252 } 253 254 /** 255 * sdma_v3_0_init_microcode - load ucode images from disk 256 * 257 * @adev: amdgpu_device pointer 258 * 259 * Use the firmware interface to load the ucode images into 260 * the driver (not loaded into hw). 261 * Returns 0 on success, error on failure. 262 */ 263 static int sdma_v3_0_init_microcode(struct amdgpu_device *adev) 264 { 265 const char *chip_name; 266 char fw_name[30]; 267 int err = 0, i; 268 struct amdgpu_firmware_info *info = NULL; 269 const struct common_firmware_header *header = NULL; 270 const struct sdma_firmware_header_v1_0 *hdr; 271 272 DRM_DEBUG("\n"); 273 274 switch (adev->asic_type) { 275 case CHIP_TONGA: 276 chip_name = "tonga"; 277 break; 278 case CHIP_FIJI: 279 chip_name = "fiji"; 280 break; 281 case CHIP_POLARIS10: 282 chip_name = "polaris10"; 283 break; 284 case CHIP_POLARIS11: 285 chip_name = "polaris11"; 286 break; 287 case CHIP_POLARIS12: 288 chip_name = "polaris12"; 289 break; 290 case CHIP_VEGAM: 291 chip_name = "vegam"; 292 break; 293 case CHIP_CARRIZO: 294 chip_name = "carrizo"; 295 break; 296 case CHIP_STONEY: 297 chip_name = "stoney"; 298 break; 299 default: BUG(); 300 } 301 302 for (i = 0; i < adev->sdma.num_instances; i++) { 303 if (i == 0) 304 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 305 else 306 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); 307 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 308 if (err) 309 goto out; 310 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); 311 if (err) 312 goto out; 313 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 314 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 315 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 316 if (adev->sdma.instance[i].feature_version >= 20) 317 adev->sdma.instance[i].burst_nop = true; 318 319 if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) { 320 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 321 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 322 info->fw = adev->sdma.instance[i].fw; 323 header = (const struct common_firmware_header *)info->fw->data; 324 adev->firmware.fw_size += 325 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 326 } 327 } 328 out: 329 if (err) { 330 pr_err("sdma_v3_0: Failed to load firmware \"%s\"\n", fw_name); 331 for (i = 0; i < adev->sdma.num_instances; i++) { 332 release_firmware(adev->sdma.instance[i].fw); 333 adev->sdma.instance[i].fw = NULL; 334 } 335 } 336 return err; 337 } 338 339 /** 340 * sdma_v3_0_ring_get_rptr - get the current read pointer 341 * 342 * @ring: amdgpu ring pointer 343 * 344 * Get the current rptr from the hardware (VI+). 345 */ 346 static uint64_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring) 347 { 348 /* XXX check if swapping is necessary on BE */ 349 return ring->adev->wb.wb[ring->rptr_offs] >> 2; 350 } 351 352 /** 353 * sdma_v3_0_ring_get_wptr - get the current write pointer 354 * 355 * @ring: amdgpu ring pointer 356 * 357 * Get the current wptr from the hardware (VI+). 358 */ 359 static uint64_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring) 360 { 361 struct amdgpu_device *adev = ring->adev; 362 u32 wptr; 363 364 if (ring->use_doorbell || ring->use_pollmem) { 365 /* XXX check if swapping is necessary on BE */ 366 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2; 367 } else { 368 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1; 369 370 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2; 371 } 372 373 return wptr; 374 } 375 376 /** 377 * sdma_v3_0_ring_set_wptr - commit the write pointer 378 * 379 * @ring: amdgpu ring pointer 380 * 381 * Write the wptr back to the hardware (VI+). 382 */ 383 static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring) 384 { 385 struct amdgpu_device *adev = ring->adev; 386 387 if (ring->use_doorbell) { 388 u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs]; 389 /* XXX check if swapping is necessary on BE */ 390 WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2)); 391 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr) << 2); 392 } else if (ring->use_pollmem) { 393 u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs]; 394 395 WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2)); 396 } else { 397 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1; 398 399 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], lower_32_bits(ring->wptr) << 2); 400 } 401 } 402 403 static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 404 { 405 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); 406 int i; 407 408 for (i = 0; i < count; i++) 409 if (sdma && sdma->burst_nop && (i == 0)) 410 amdgpu_ring_write(ring, ring->funcs->nop | 411 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 412 else 413 amdgpu_ring_write(ring, ring->funcs->nop); 414 } 415 416 /** 417 * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine 418 * 419 * @ring: amdgpu ring pointer 420 * @ib: IB object to schedule 421 * 422 * Schedule an IB in the DMA ring (VI). 423 */ 424 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring, 425 struct amdgpu_ib *ib, 426 unsigned vmid, bool ctx_switch) 427 { 428 /* IB packet must end on a 8 DW boundary */ 429 sdma_v3_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8); 430 431 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 432 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 433 /* base must be 32 byte aligned */ 434 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 435 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 436 amdgpu_ring_write(ring, ib->length_dw); 437 amdgpu_ring_write(ring, 0); 438 amdgpu_ring_write(ring, 0); 439 440 } 441 442 /** 443 * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 444 * 445 * @ring: amdgpu ring pointer 446 * 447 * Emit an hdp flush packet on the requested DMA ring. 448 */ 449 static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 450 { 451 u32 ref_and_mask = 0; 452 453 if (ring == &ring->adev->sdma.instance[0].ring) 454 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); 455 else 456 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); 457 458 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 459 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 460 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 461 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); 462 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); 463 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 464 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 465 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 466 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 467 } 468 469 /** 470 * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring 471 * 472 * @ring: amdgpu ring pointer 473 * @fence: amdgpu fence object 474 * 475 * Add a DMA fence packet to the ring to write 476 * the fence seq number and DMA trap packet to generate 477 * an interrupt if needed (VI). 478 */ 479 static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 480 unsigned flags) 481 { 482 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 483 /* write the fence */ 484 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 485 amdgpu_ring_write(ring, lower_32_bits(addr)); 486 amdgpu_ring_write(ring, upper_32_bits(addr)); 487 amdgpu_ring_write(ring, lower_32_bits(seq)); 488 489 /* optionally write high bits as well */ 490 if (write64bit) { 491 addr += 4; 492 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 493 amdgpu_ring_write(ring, lower_32_bits(addr)); 494 amdgpu_ring_write(ring, upper_32_bits(addr)); 495 amdgpu_ring_write(ring, upper_32_bits(seq)); 496 } 497 498 /* generate an interrupt */ 499 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 500 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 501 } 502 503 /** 504 * sdma_v3_0_gfx_stop - stop the gfx async dma engines 505 * 506 * @adev: amdgpu_device pointer 507 * 508 * Stop the gfx async dma ring buffers (VI). 509 */ 510 static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev) 511 { 512 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 513 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 514 u32 rb_cntl, ib_cntl; 515 int i; 516 517 if ((adev->mman.buffer_funcs_ring == sdma0) || 518 (adev->mman.buffer_funcs_ring == sdma1)) 519 amdgpu_ttm_set_buffer_funcs_status(adev, false); 520 521 for (i = 0; i < adev->sdma.num_instances; i++) { 522 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 523 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 524 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 525 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 526 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 527 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 528 } 529 sdma0->ready = false; 530 sdma1->ready = false; 531 } 532 533 /** 534 * sdma_v3_0_rlc_stop - stop the compute async dma engines 535 * 536 * @adev: amdgpu_device pointer 537 * 538 * Stop the compute async dma queues (VI). 539 */ 540 static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev) 541 { 542 /* XXX todo */ 543 } 544 545 /** 546 * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch 547 * 548 * @adev: amdgpu_device pointer 549 * @enable: enable/disable the DMA MEs context switch. 550 * 551 * Halt or unhalt the async dma engines context switch (VI). 552 */ 553 static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 554 { 555 u32 f32_cntl, phase_quantum = 0; 556 int i; 557 558 if (amdgpu_sdma_phase_quantum) { 559 unsigned value = amdgpu_sdma_phase_quantum; 560 unsigned unit = 0; 561 562 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 563 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 564 value = (value + 1) >> 1; 565 unit++; 566 } 567 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 568 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 569 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 570 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 571 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 572 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 573 WARN_ONCE(1, 574 "clamping sdma_phase_quantum to %uK clock cycles\n", 575 value << unit); 576 } 577 phase_quantum = 578 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 579 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 580 } 581 582 for (i = 0; i < adev->sdma.num_instances; i++) { 583 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); 584 if (enable) { 585 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 586 AUTO_CTXSW_ENABLE, 1); 587 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 588 ATC_L1_ENABLE, 1); 589 if (amdgpu_sdma_phase_quantum) { 590 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i], 591 phase_quantum); 592 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i], 593 phase_quantum); 594 } 595 } else { 596 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 597 AUTO_CTXSW_ENABLE, 0); 598 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 599 ATC_L1_ENABLE, 1); 600 } 601 602 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); 603 } 604 } 605 606 /** 607 * sdma_v3_0_enable - stop the async dma engines 608 * 609 * @adev: amdgpu_device pointer 610 * @enable: enable/disable the DMA MEs. 611 * 612 * Halt or unhalt the async dma engines (VI). 613 */ 614 static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable) 615 { 616 u32 f32_cntl; 617 int i; 618 619 if (!enable) { 620 sdma_v3_0_gfx_stop(adev); 621 sdma_v3_0_rlc_stop(adev); 622 } 623 624 for (i = 0; i < adev->sdma.num_instances; i++) { 625 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); 626 if (enable) 627 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); 628 else 629 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); 630 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); 631 } 632 } 633 634 /** 635 * sdma_v3_0_gfx_resume - setup and start the async dma engines 636 * 637 * @adev: amdgpu_device pointer 638 * 639 * Set up the gfx DMA ring buffers and enable them (VI). 640 * Returns 0 for success, error for failure. 641 */ 642 static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) 643 { 644 struct amdgpu_ring *ring; 645 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 646 u32 rb_bufsz; 647 u32 wb_offset; 648 u32 doorbell; 649 u64 wptr_gpu_addr; 650 int i, j, r; 651 652 for (i = 0; i < adev->sdma.num_instances; i++) { 653 ring = &adev->sdma.instance[i].ring; 654 amdgpu_ring_clear_ring(ring); 655 wb_offset = (ring->rptr_offs * 4); 656 657 mutex_lock(&adev->srbm_mutex); 658 for (j = 0; j < 16; j++) { 659 vi_srbm_select(adev, 0, 0, 0, j); 660 /* SDMA GFX */ 661 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); 662 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); 663 } 664 vi_srbm_select(adev, 0, 0, 0, 0); 665 mutex_unlock(&adev->srbm_mutex); 666 667 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], 668 adev->gfx.config.gb_addr_config & 0x70); 669 670 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); 671 672 /* Set ring buffer size in dwords */ 673 rb_bufsz = order_base_2(ring->ring_size / 4); 674 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 675 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 676 #ifdef __BIG_ENDIAN 677 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 678 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 679 RPTR_WRITEBACK_SWAP_ENABLE, 1); 680 #endif 681 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 682 683 /* Initialize the ring buffer's read and write pointers */ 684 ring->wptr = 0; 685 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); 686 sdma_v3_0_ring_set_wptr(ring); 687 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); 688 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); 689 690 /* set the wb address whether it's enabled or not */ 691 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], 692 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 693 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], 694 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 695 696 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 697 698 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); 699 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); 700 701 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]); 702 703 if (ring->use_doorbell) { 704 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, 705 OFFSET, ring->doorbell_index); 706 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 707 } else { 708 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 709 } 710 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell); 711 712 /* setup the wptr shadow polling */ 713 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 714 715 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i], 716 lower_32_bits(wptr_gpu_addr)); 717 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i], 718 upper_32_bits(wptr_gpu_addr)); 719 wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]); 720 if (ring->use_pollmem) { 721 /*wptr polling is not enogh fast, directly clean the wptr register */ 722 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); 723 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 724 SDMA0_GFX_RB_WPTR_POLL_CNTL, 725 ENABLE, 1); 726 } else { 727 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 728 SDMA0_GFX_RB_WPTR_POLL_CNTL, 729 ENABLE, 0); 730 } 731 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i], wptr_poll_cntl); 732 733 /* enable DMA RB */ 734 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 735 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 736 737 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 738 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 739 #ifdef __BIG_ENDIAN 740 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 741 #endif 742 /* enable DMA IBs */ 743 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 744 745 ring->ready = true; 746 } 747 748 /* unhalt the MEs */ 749 sdma_v3_0_enable(adev, true); 750 /* enable sdma ring preemption */ 751 sdma_v3_0_ctx_switch_enable(adev, true); 752 753 for (i = 0; i < adev->sdma.num_instances; i++) { 754 ring = &adev->sdma.instance[i].ring; 755 r = amdgpu_ring_test_ring(ring); 756 if (r) { 757 ring->ready = false; 758 return r; 759 } 760 761 if (adev->mman.buffer_funcs_ring == ring) 762 amdgpu_ttm_set_buffer_funcs_status(adev, true); 763 } 764 765 return 0; 766 } 767 768 /** 769 * sdma_v3_0_rlc_resume - setup and start the async dma engines 770 * 771 * @adev: amdgpu_device pointer 772 * 773 * Set up the compute DMA queues and enable them (VI). 774 * Returns 0 for success, error for failure. 775 */ 776 static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev) 777 { 778 /* XXX todo */ 779 return 0; 780 } 781 782 /** 783 * sdma_v3_0_load_microcode - load the sDMA ME ucode 784 * 785 * @adev: amdgpu_device pointer 786 * 787 * Loads the sDMA0/1 ucode. 788 * Returns 0 for success, -EINVAL if the ucode is not available. 789 */ 790 static int sdma_v3_0_load_microcode(struct amdgpu_device *adev) 791 { 792 const struct sdma_firmware_header_v1_0 *hdr; 793 const __le32 *fw_data; 794 u32 fw_size; 795 int i, j; 796 797 /* halt the MEs */ 798 sdma_v3_0_enable(adev, false); 799 800 for (i = 0; i < adev->sdma.num_instances; i++) { 801 if (!adev->sdma.instance[i].fw) 802 return -EINVAL; 803 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 804 amdgpu_ucode_print_sdma_hdr(&hdr->header); 805 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 806 fw_data = (const __le32 *) 807 (adev->sdma.instance[i].fw->data + 808 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 809 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0); 810 for (j = 0; j < fw_size; j++) 811 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++)); 812 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version); 813 } 814 815 return 0; 816 } 817 818 /** 819 * sdma_v3_0_start - setup and start the async dma engines 820 * 821 * @adev: amdgpu_device pointer 822 * 823 * Set up the DMA engines and enable them (VI). 824 * Returns 0 for success, error for failure. 825 */ 826 static int sdma_v3_0_start(struct amdgpu_device *adev) 827 { 828 int r; 829 830 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 831 r = sdma_v3_0_load_microcode(adev); 832 if (r) 833 return r; 834 } 835 836 /* disable sdma engine before programing it */ 837 sdma_v3_0_ctx_switch_enable(adev, false); 838 sdma_v3_0_enable(adev, false); 839 840 /* start the gfx rings and rlc compute queues */ 841 r = sdma_v3_0_gfx_resume(adev); 842 if (r) 843 return r; 844 r = sdma_v3_0_rlc_resume(adev); 845 if (r) 846 return r; 847 848 return 0; 849 } 850 851 /** 852 * sdma_v3_0_ring_test_ring - simple async dma engine test 853 * 854 * @ring: amdgpu_ring structure holding ring information 855 * 856 * Test the DMA engine by writing using it to write an 857 * value to memory. (VI). 858 * Returns 0 for success, error for failure. 859 */ 860 static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring) 861 { 862 struct amdgpu_device *adev = ring->adev; 863 unsigned i; 864 unsigned index; 865 int r; 866 u32 tmp; 867 u64 gpu_addr; 868 869 r = amdgpu_device_wb_get(adev, &index); 870 if (r) { 871 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 872 return r; 873 } 874 875 gpu_addr = adev->wb.gpu_addr + (index * 4); 876 tmp = 0xCAFEDEAD; 877 adev->wb.wb[index] = cpu_to_le32(tmp); 878 879 r = amdgpu_ring_alloc(ring, 5); 880 if (r) { 881 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 882 amdgpu_device_wb_free(adev, index); 883 return r; 884 } 885 886 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 887 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 888 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 889 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 890 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); 891 amdgpu_ring_write(ring, 0xDEADBEEF); 892 amdgpu_ring_commit(ring); 893 894 for (i = 0; i < adev->usec_timeout; i++) { 895 tmp = le32_to_cpu(adev->wb.wb[index]); 896 if (tmp == 0xDEADBEEF) 897 break; 898 DRM_UDELAY(1); 899 } 900 901 if (i < adev->usec_timeout) { 902 DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); 903 } else { 904 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 905 ring->idx, tmp); 906 r = -EINVAL; 907 } 908 amdgpu_device_wb_free(adev, index); 909 910 return r; 911 } 912 913 /** 914 * sdma_v3_0_ring_test_ib - test an IB on the DMA engine 915 * 916 * @ring: amdgpu_ring structure holding ring information 917 * 918 * Test a simple IB in the DMA ring (VI). 919 * Returns 0 on success, error on failure. 920 */ 921 static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 922 { 923 struct amdgpu_device *adev = ring->adev; 924 struct amdgpu_ib ib; 925 struct dma_fence *f = NULL; 926 unsigned index; 927 u32 tmp = 0; 928 u64 gpu_addr; 929 long r; 930 931 r = amdgpu_device_wb_get(adev, &index); 932 if (r) { 933 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 934 return r; 935 } 936 937 gpu_addr = adev->wb.gpu_addr + (index * 4); 938 tmp = 0xCAFEDEAD; 939 adev->wb.wb[index] = cpu_to_le32(tmp); 940 memset(&ib, 0, sizeof(ib)); 941 r = amdgpu_ib_get(adev, NULL, 256, &ib); 942 if (r) { 943 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 944 goto err0; 945 } 946 947 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 948 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 949 ib.ptr[1] = lower_32_bits(gpu_addr); 950 ib.ptr[2] = upper_32_bits(gpu_addr); 951 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1); 952 ib.ptr[4] = 0xDEADBEEF; 953 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 954 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 955 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 956 ib.length_dw = 8; 957 958 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 959 if (r) 960 goto err1; 961 962 r = dma_fence_wait_timeout(f, false, timeout); 963 if (r == 0) { 964 DRM_ERROR("amdgpu: IB test timed out\n"); 965 r = -ETIMEDOUT; 966 goto err1; 967 } else if (r < 0) { 968 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 969 goto err1; 970 } 971 tmp = le32_to_cpu(adev->wb.wb[index]); 972 if (tmp == 0xDEADBEEF) { 973 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); 974 r = 0; 975 } else { 976 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); 977 r = -EINVAL; 978 } 979 err1: 980 amdgpu_ib_free(adev, &ib, NULL); 981 dma_fence_put(f); 982 err0: 983 amdgpu_device_wb_free(adev, index); 984 return r; 985 } 986 987 /** 988 * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART 989 * 990 * @ib: indirect buffer to fill with commands 991 * @pe: addr of the page entry 992 * @src: src addr to copy from 993 * @count: number of page entries to update 994 * 995 * Update PTEs by copying them from the GART using sDMA (CIK). 996 */ 997 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib, 998 uint64_t pe, uint64_t src, 999 unsigned count) 1000 { 1001 unsigned bytes = count * 8; 1002 1003 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1004 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1005 ib->ptr[ib->length_dw++] = bytes; 1006 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1007 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1008 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1009 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1010 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1011 } 1012 1013 /** 1014 * sdma_v3_0_vm_write_pte - update PTEs by writing them manually 1015 * 1016 * @ib: indirect buffer to fill with commands 1017 * @pe: addr of the page entry 1018 * @value: dst addr to write into pe 1019 * @count: number of page entries to update 1020 * @incr: increase next addr by incr bytes 1021 * 1022 * Update PTEs by writing them manually using sDMA (CIK). 1023 */ 1024 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1025 uint64_t value, unsigned count, 1026 uint32_t incr) 1027 { 1028 unsigned ndw = count * 2; 1029 1030 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1031 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1032 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1033 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1034 ib->ptr[ib->length_dw++] = ndw; 1035 for (; ndw > 0; ndw -= 2) { 1036 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1037 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1038 value += incr; 1039 } 1040 } 1041 1042 /** 1043 * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA 1044 * 1045 * @ib: indirect buffer to fill with commands 1046 * @pe: addr of the page entry 1047 * @addr: dst addr to write into pe 1048 * @count: number of page entries to update 1049 * @incr: increase next addr by incr bytes 1050 * @flags: access flags 1051 * 1052 * Update the page tables using sDMA (CIK). 1053 */ 1054 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe, 1055 uint64_t addr, unsigned count, 1056 uint32_t incr, uint64_t flags) 1057 { 1058 /* for physically contiguous pages (vram) */ 1059 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE); 1060 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1061 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1062 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1063 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1064 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1065 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1066 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1067 ib->ptr[ib->length_dw++] = 0; 1068 ib->ptr[ib->length_dw++] = count; /* number of entries */ 1069 } 1070 1071 /** 1072 * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw 1073 * 1074 * @ib: indirect buffer to fill with padding 1075 * 1076 */ 1077 static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1078 { 1079 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); 1080 u32 pad_count; 1081 int i; 1082 1083 pad_count = (8 - (ib->length_dw & 0x7)) % 8; 1084 for (i = 0; i < pad_count; i++) 1085 if (sdma && sdma->burst_nop && (i == 0)) 1086 ib->ptr[ib->length_dw++] = 1087 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1088 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1089 else 1090 ib->ptr[ib->length_dw++] = 1091 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1092 } 1093 1094 /** 1095 * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline 1096 * 1097 * @ring: amdgpu_ring pointer 1098 * 1099 * Make sure all previous operations are completed (CIK). 1100 */ 1101 static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1102 { 1103 uint32_t seq = ring->fence_drv.sync_seq; 1104 uint64_t addr = ring->fence_drv.gpu_addr; 1105 1106 /* wait for idle */ 1107 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1108 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1109 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1110 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1111 amdgpu_ring_write(ring, addr & 0xfffffffc); 1112 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1113 amdgpu_ring_write(ring, seq); /* reference */ 1114 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1115 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1116 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1117 } 1118 1119 /** 1120 * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA 1121 * 1122 * @ring: amdgpu_ring pointer 1123 * @vm: amdgpu_vm pointer 1124 * 1125 * Update the page table base and flush the VM TLB 1126 * using sDMA (VI). 1127 */ 1128 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1129 unsigned vmid, uint64_t pd_addr) 1130 { 1131 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1132 1133 /* wait for flush */ 1134 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1135 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1136 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */ 1137 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); 1138 amdgpu_ring_write(ring, 0); 1139 amdgpu_ring_write(ring, 0); /* reference */ 1140 amdgpu_ring_write(ring, 0); /* mask */ 1141 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1142 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 1143 } 1144 1145 static void sdma_v3_0_ring_emit_wreg(struct amdgpu_ring *ring, 1146 uint32_t reg, uint32_t val) 1147 { 1148 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1149 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1150 amdgpu_ring_write(ring, reg); 1151 amdgpu_ring_write(ring, val); 1152 } 1153 1154 static int sdma_v3_0_early_init(void *handle) 1155 { 1156 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1157 1158 switch (adev->asic_type) { 1159 case CHIP_STONEY: 1160 adev->sdma.num_instances = 1; 1161 break; 1162 default: 1163 adev->sdma.num_instances = SDMA_MAX_INSTANCE; 1164 break; 1165 } 1166 1167 sdma_v3_0_set_ring_funcs(adev); 1168 sdma_v3_0_set_buffer_funcs(adev); 1169 sdma_v3_0_set_vm_pte_funcs(adev); 1170 sdma_v3_0_set_irq_funcs(adev); 1171 1172 return 0; 1173 } 1174 1175 static int sdma_v3_0_sw_init(void *handle) 1176 { 1177 struct amdgpu_ring *ring; 1178 int r, i; 1179 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1180 1181 /* SDMA trap event */ 1182 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 224, 1183 &adev->sdma.trap_irq); 1184 if (r) 1185 return r; 1186 1187 /* SDMA Privileged inst */ 1188 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 241, 1189 &adev->sdma.illegal_inst_irq); 1190 if (r) 1191 return r; 1192 1193 /* SDMA Privileged inst */ 1194 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 247, 1195 &adev->sdma.illegal_inst_irq); 1196 if (r) 1197 return r; 1198 1199 r = sdma_v3_0_init_microcode(adev); 1200 if (r) { 1201 DRM_ERROR("Failed to load sdma firmware!\n"); 1202 return r; 1203 } 1204 1205 for (i = 0; i < adev->sdma.num_instances; i++) { 1206 ring = &adev->sdma.instance[i].ring; 1207 ring->ring_obj = NULL; 1208 if (!amdgpu_sriov_vf(adev)) { 1209 ring->use_doorbell = true; 1210 ring->doorbell_index = (i == 0) ? 1211 AMDGPU_DOORBELL_sDMA_ENGINE0 : AMDGPU_DOORBELL_sDMA_ENGINE1; 1212 } else { 1213 ring->use_pollmem = true; 1214 } 1215 1216 sprintf(ring->name, "sdma%d", i); 1217 r = amdgpu_ring_init(adev, ring, 1024, 1218 &adev->sdma.trap_irq, 1219 (i == 0) ? 1220 AMDGPU_SDMA_IRQ_TRAP0 : 1221 AMDGPU_SDMA_IRQ_TRAP1); 1222 if (r) 1223 return r; 1224 } 1225 1226 return r; 1227 } 1228 1229 static int sdma_v3_0_sw_fini(void *handle) 1230 { 1231 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1232 int i; 1233 1234 for (i = 0; i < adev->sdma.num_instances; i++) 1235 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1236 1237 sdma_v3_0_free_microcode(adev); 1238 return 0; 1239 } 1240 1241 static int sdma_v3_0_hw_init(void *handle) 1242 { 1243 int r; 1244 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1245 1246 sdma_v3_0_init_golden_registers(adev); 1247 1248 r = sdma_v3_0_start(adev); 1249 if (r) 1250 return r; 1251 1252 return r; 1253 } 1254 1255 static int sdma_v3_0_hw_fini(void *handle) 1256 { 1257 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1258 1259 sdma_v3_0_ctx_switch_enable(adev, false); 1260 sdma_v3_0_enable(adev, false); 1261 1262 return 0; 1263 } 1264 1265 static int sdma_v3_0_suspend(void *handle) 1266 { 1267 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1268 1269 return sdma_v3_0_hw_fini(adev); 1270 } 1271 1272 static int sdma_v3_0_resume(void *handle) 1273 { 1274 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1275 1276 return sdma_v3_0_hw_init(adev); 1277 } 1278 1279 static bool sdma_v3_0_is_idle(void *handle) 1280 { 1281 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1282 u32 tmp = RREG32(mmSRBM_STATUS2); 1283 1284 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | 1285 SRBM_STATUS2__SDMA1_BUSY_MASK)) 1286 return false; 1287 1288 return true; 1289 } 1290 1291 static int sdma_v3_0_wait_for_idle(void *handle) 1292 { 1293 unsigned i; 1294 u32 tmp; 1295 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1296 1297 for (i = 0; i < adev->usec_timeout; i++) { 1298 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | 1299 SRBM_STATUS2__SDMA1_BUSY_MASK); 1300 1301 if (!tmp) 1302 return 0; 1303 udelay(1); 1304 } 1305 return -ETIMEDOUT; 1306 } 1307 1308 static bool sdma_v3_0_check_soft_reset(void *handle) 1309 { 1310 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1311 u32 srbm_soft_reset = 0; 1312 u32 tmp = RREG32(mmSRBM_STATUS2); 1313 1314 if ((tmp & SRBM_STATUS2__SDMA_BUSY_MASK) || 1315 (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)) { 1316 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK; 1317 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK; 1318 } 1319 1320 if (srbm_soft_reset) { 1321 adev->sdma.srbm_soft_reset = srbm_soft_reset; 1322 return true; 1323 } else { 1324 adev->sdma.srbm_soft_reset = 0; 1325 return false; 1326 } 1327 } 1328 1329 static int sdma_v3_0_pre_soft_reset(void *handle) 1330 { 1331 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1332 u32 srbm_soft_reset = 0; 1333 1334 if (!adev->sdma.srbm_soft_reset) 1335 return 0; 1336 1337 srbm_soft_reset = adev->sdma.srbm_soft_reset; 1338 1339 if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) || 1340 REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) { 1341 sdma_v3_0_ctx_switch_enable(adev, false); 1342 sdma_v3_0_enable(adev, false); 1343 } 1344 1345 return 0; 1346 } 1347 1348 static int sdma_v3_0_post_soft_reset(void *handle) 1349 { 1350 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1351 u32 srbm_soft_reset = 0; 1352 1353 if (!adev->sdma.srbm_soft_reset) 1354 return 0; 1355 1356 srbm_soft_reset = adev->sdma.srbm_soft_reset; 1357 1358 if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) || 1359 REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) { 1360 sdma_v3_0_gfx_resume(adev); 1361 sdma_v3_0_rlc_resume(adev); 1362 } 1363 1364 return 0; 1365 } 1366 1367 static int sdma_v3_0_soft_reset(void *handle) 1368 { 1369 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1370 u32 srbm_soft_reset = 0; 1371 u32 tmp; 1372 1373 if (!adev->sdma.srbm_soft_reset) 1374 return 0; 1375 1376 srbm_soft_reset = adev->sdma.srbm_soft_reset; 1377 1378 if (srbm_soft_reset) { 1379 tmp = RREG32(mmSRBM_SOFT_RESET); 1380 tmp |= srbm_soft_reset; 1381 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1382 WREG32(mmSRBM_SOFT_RESET, tmp); 1383 tmp = RREG32(mmSRBM_SOFT_RESET); 1384 1385 udelay(50); 1386 1387 tmp &= ~srbm_soft_reset; 1388 WREG32(mmSRBM_SOFT_RESET, tmp); 1389 tmp = RREG32(mmSRBM_SOFT_RESET); 1390 1391 /* Wait a little for things to settle down */ 1392 udelay(50); 1393 } 1394 1395 return 0; 1396 } 1397 1398 static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev, 1399 struct amdgpu_irq_src *source, 1400 unsigned type, 1401 enum amdgpu_interrupt_state state) 1402 { 1403 u32 sdma_cntl; 1404 1405 switch (type) { 1406 case AMDGPU_SDMA_IRQ_TRAP0: 1407 switch (state) { 1408 case AMDGPU_IRQ_STATE_DISABLE: 1409 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1410 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1411 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1412 break; 1413 case AMDGPU_IRQ_STATE_ENABLE: 1414 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1415 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1416 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1417 break; 1418 default: 1419 break; 1420 } 1421 break; 1422 case AMDGPU_SDMA_IRQ_TRAP1: 1423 switch (state) { 1424 case AMDGPU_IRQ_STATE_DISABLE: 1425 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1426 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1427 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1428 break; 1429 case AMDGPU_IRQ_STATE_ENABLE: 1430 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1431 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1432 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1433 break; 1434 default: 1435 break; 1436 } 1437 break; 1438 default: 1439 break; 1440 } 1441 return 0; 1442 } 1443 1444 static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev, 1445 struct amdgpu_irq_src *source, 1446 struct amdgpu_iv_entry *entry) 1447 { 1448 u8 instance_id, queue_id; 1449 1450 instance_id = (entry->ring_id & 0x3) >> 0; 1451 queue_id = (entry->ring_id & 0xc) >> 2; 1452 DRM_DEBUG("IH: SDMA trap\n"); 1453 switch (instance_id) { 1454 case 0: 1455 switch (queue_id) { 1456 case 0: 1457 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1458 break; 1459 case 1: 1460 /* XXX compute */ 1461 break; 1462 case 2: 1463 /* XXX compute */ 1464 break; 1465 } 1466 break; 1467 case 1: 1468 switch (queue_id) { 1469 case 0: 1470 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1471 break; 1472 case 1: 1473 /* XXX compute */ 1474 break; 1475 case 2: 1476 /* XXX compute */ 1477 break; 1478 } 1479 break; 1480 } 1481 return 0; 1482 } 1483 1484 static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1485 struct amdgpu_irq_src *source, 1486 struct amdgpu_iv_entry *entry) 1487 { 1488 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1489 schedule_work(&adev->reset_work); 1490 return 0; 1491 } 1492 1493 static void sdma_v3_0_update_sdma_medium_grain_clock_gating( 1494 struct amdgpu_device *adev, 1495 bool enable) 1496 { 1497 uint32_t temp, data; 1498 int i; 1499 1500 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1501 for (i = 0; i < adev->sdma.num_instances; i++) { 1502 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]); 1503 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1504 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1505 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1506 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1507 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1508 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1509 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1510 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1511 if (data != temp) 1512 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); 1513 } 1514 } else { 1515 for (i = 0; i < adev->sdma.num_instances; i++) { 1516 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]); 1517 data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1518 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1519 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1520 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1521 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1522 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1523 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1524 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK; 1525 1526 if (data != temp) 1527 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); 1528 } 1529 } 1530 } 1531 1532 static void sdma_v3_0_update_sdma_medium_grain_light_sleep( 1533 struct amdgpu_device *adev, 1534 bool enable) 1535 { 1536 uint32_t temp, data; 1537 int i; 1538 1539 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1540 for (i = 0; i < adev->sdma.num_instances; i++) { 1541 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); 1542 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1543 1544 if (temp != data) 1545 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); 1546 } 1547 } else { 1548 for (i = 0; i < adev->sdma.num_instances; i++) { 1549 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); 1550 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1551 1552 if (temp != data) 1553 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); 1554 } 1555 } 1556 } 1557 1558 static int sdma_v3_0_set_clockgating_state(void *handle, 1559 enum amd_clockgating_state state) 1560 { 1561 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1562 1563 if (amdgpu_sriov_vf(adev)) 1564 return 0; 1565 1566 switch (adev->asic_type) { 1567 case CHIP_FIJI: 1568 case CHIP_CARRIZO: 1569 case CHIP_STONEY: 1570 sdma_v3_0_update_sdma_medium_grain_clock_gating(adev, 1571 state == AMD_CG_STATE_GATE); 1572 sdma_v3_0_update_sdma_medium_grain_light_sleep(adev, 1573 state == AMD_CG_STATE_GATE); 1574 break; 1575 default: 1576 break; 1577 } 1578 return 0; 1579 } 1580 1581 static int sdma_v3_0_set_powergating_state(void *handle, 1582 enum amd_powergating_state state) 1583 { 1584 return 0; 1585 } 1586 1587 static void sdma_v3_0_get_clockgating_state(void *handle, u32 *flags) 1588 { 1589 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1590 int data; 1591 1592 if (amdgpu_sriov_vf(adev)) 1593 *flags = 0; 1594 1595 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1596 data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[0]); 1597 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK)) 1598 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1599 1600 /* AMD_CG_SUPPORT_SDMA_LS */ 1601 data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[0]); 1602 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1603 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1604 } 1605 1606 static const struct amd_ip_funcs sdma_v3_0_ip_funcs = { 1607 .name = "sdma_v3_0", 1608 .early_init = sdma_v3_0_early_init, 1609 .late_init = NULL, 1610 .sw_init = sdma_v3_0_sw_init, 1611 .sw_fini = sdma_v3_0_sw_fini, 1612 .hw_init = sdma_v3_0_hw_init, 1613 .hw_fini = sdma_v3_0_hw_fini, 1614 .suspend = sdma_v3_0_suspend, 1615 .resume = sdma_v3_0_resume, 1616 .is_idle = sdma_v3_0_is_idle, 1617 .wait_for_idle = sdma_v3_0_wait_for_idle, 1618 .check_soft_reset = sdma_v3_0_check_soft_reset, 1619 .pre_soft_reset = sdma_v3_0_pre_soft_reset, 1620 .post_soft_reset = sdma_v3_0_post_soft_reset, 1621 .soft_reset = sdma_v3_0_soft_reset, 1622 .set_clockgating_state = sdma_v3_0_set_clockgating_state, 1623 .set_powergating_state = sdma_v3_0_set_powergating_state, 1624 .get_clockgating_state = sdma_v3_0_get_clockgating_state, 1625 }; 1626 1627 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { 1628 .type = AMDGPU_RING_TYPE_SDMA, 1629 .align_mask = 0xf, 1630 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1631 .support_64bit_ptrs = false, 1632 .get_rptr = sdma_v3_0_ring_get_rptr, 1633 .get_wptr = sdma_v3_0_ring_get_wptr, 1634 .set_wptr = sdma_v3_0_ring_set_wptr, 1635 .emit_frame_size = 1636 6 + /* sdma_v3_0_ring_emit_hdp_flush */ 1637 3 + /* hdp invalidate */ 1638 6 + /* sdma_v3_0_ring_emit_pipeline_sync */ 1639 VI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v3_0_ring_emit_vm_flush */ 1640 10 + 10 + 10, /* sdma_v3_0_ring_emit_fence x3 for user fence, vm fence */ 1641 .emit_ib_size = 7 + 6, /* sdma_v3_0_ring_emit_ib */ 1642 .emit_ib = sdma_v3_0_ring_emit_ib, 1643 .emit_fence = sdma_v3_0_ring_emit_fence, 1644 .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync, 1645 .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush, 1646 .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush, 1647 .test_ring = sdma_v3_0_ring_test_ring, 1648 .test_ib = sdma_v3_0_ring_test_ib, 1649 .insert_nop = sdma_v3_0_ring_insert_nop, 1650 .pad_ib = sdma_v3_0_ring_pad_ib, 1651 .emit_wreg = sdma_v3_0_ring_emit_wreg, 1652 }; 1653 1654 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev) 1655 { 1656 int i; 1657 1658 for (i = 0; i < adev->sdma.num_instances; i++) 1659 adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs; 1660 } 1661 1662 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = { 1663 .set = sdma_v3_0_set_trap_irq_state, 1664 .process = sdma_v3_0_process_trap_irq, 1665 }; 1666 1667 static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = { 1668 .process = sdma_v3_0_process_illegal_inst_irq, 1669 }; 1670 1671 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev) 1672 { 1673 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 1674 adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs; 1675 adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs; 1676 } 1677 1678 /** 1679 * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine 1680 * 1681 * @ring: amdgpu_ring structure holding ring information 1682 * @src_offset: src GPU address 1683 * @dst_offset: dst GPU address 1684 * @byte_count: number of bytes to xfer 1685 * 1686 * Copy GPU buffers using the DMA engine (VI). 1687 * Used by the amdgpu ttm implementation to move pages if 1688 * registered as the asic copy callback. 1689 */ 1690 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib, 1691 uint64_t src_offset, 1692 uint64_t dst_offset, 1693 uint32_t byte_count) 1694 { 1695 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1696 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1697 ib->ptr[ib->length_dw++] = byte_count; 1698 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1699 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1700 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1701 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1702 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1703 } 1704 1705 /** 1706 * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine 1707 * 1708 * @ring: amdgpu_ring structure holding ring information 1709 * @src_data: value to write to buffer 1710 * @dst_offset: dst GPU address 1711 * @byte_count: number of bytes to xfer 1712 * 1713 * Fill GPU buffers using the DMA engine (VI). 1714 */ 1715 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib, 1716 uint32_t src_data, 1717 uint64_t dst_offset, 1718 uint32_t byte_count) 1719 { 1720 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1721 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1722 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1723 ib->ptr[ib->length_dw++] = src_data; 1724 ib->ptr[ib->length_dw++] = byte_count; 1725 } 1726 1727 static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = { 1728 .copy_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */ 1729 .copy_num_dw = 7, 1730 .emit_copy_buffer = sdma_v3_0_emit_copy_buffer, 1731 1732 .fill_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */ 1733 .fill_num_dw = 5, 1734 .emit_fill_buffer = sdma_v3_0_emit_fill_buffer, 1735 }; 1736 1737 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev) 1738 { 1739 if (adev->mman.buffer_funcs == NULL) { 1740 adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs; 1741 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1742 } 1743 } 1744 1745 static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = { 1746 .copy_pte_num_dw = 7, 1747 .copy_pte = sdma_v3_0_vm_copy_pte, 1748 1749 .write_pte = sdma_v3_0_vm_write_pte, 1750 .set_pte_pde = sdma_v3_0_vm_set_pte_pde, 1751 }; 1752 1753 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1754 { 1755 unsigned i; 1756 1757 if (adev->vm_manager.vm_pte_funcs == NULL) { 1758 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs; 1759 for (i = 0; i < adev->sdma.num_instances; i++) 1760 adev->vm_manager.vm_pte_rings[i] = 1761 &adev->sdma.instance[i].ring; 1762 1763 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances; 1764 } 1765 } 1766 1767 const struct amdgpu_ip_block_version sdma_v3_0_ip_block = 1768 { 1769 .type = AMD_IP_BLOCK_TYPE_SDMA, 1770 .major = 3, 1771 .minor = 0, 1772 .rev = 0, 1773 .funcs = &sdma_v3_0_ip_funcs, 1774 }; 1775 1776 const struct amdgpu_ip_block_version sdma_v3_1_ip_block = 1777 { 1778 .type = AMD_IP_BLOCK_TYPE_SDMA, 1779 .major = 3, 1780 .minor = 1, 1781 .rev = 0, 1782 .funcs = &sdma_v3_0_ip_funcs, 1783 }; 1784