1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_ucode.h" 28 #include "amdgpu_trace.h" 29 #include "vi.h" 30 #include "vid.h" 31 32 #include "oss/oss_3_0_d.h" 33 #include "oss/oss_3_0_sh_mask.h" 34 35 #include "gmc/gmc_8_1_d.h" 36 #include "gmc/gmc_8_1_sh_mask.h" 37 38 #include "gca/gfx_8_0_d.h" 39 #include "gca/gfx_8_0_enum.h" 40 #include "gca/gfx_8_0_sh_mask.h" 41 42 #include "bif/bif_5_0_d.h" 43 #include "bif/bif_5_0_sh_mask.h" 44 45 #include "tonga_sdma_pkt_open.h" 46 47 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev); 48 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev); 49 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev); 50 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev); 51 52 MODULE_FIRMWARE("amdgpu/tonga_sdma.bin"); 53 MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin"); 54 MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin"); 55 MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin"); 56 MODULE_FIRMWARE("amdgpu/fiji_sdma.bin"); 57 MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin"); 58 MODULE_FIRMWARE("amdgpu/stoney_sdma.bin"); 59 MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin"); 60 MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin"); 61 MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin"); 62 MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin"); 63 MODULE_FIRMWARE("amdgpu/polaris12_sdma.bin"); 64 MODULE_FIRMWARE("amdgpu/polaris12_sdma1.bin"); 65 MODULE_FIRMWARE("amdgpu/vegam_sdma.bin"); 66 MODULE_FIRMWARE("amdgpu/vegam_sdma1.bin"); 67 68 69 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = 70 { 71 SDMA0_REGISTER_OFFSET, 72 SDMA1_REGISTER_OFFSET 73 }; 74 75 static const u32 golden_settings_tonga_a11[] = 76 { 77 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 78 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 79 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 80 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 81 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 82 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 83 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 84 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 85 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 86 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 87 }; 88 89 static const u32 tonga_mgcg_cgcg_init[] = 90 { 91 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 92 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 93 }; 94 95 static const u32 golden_settings_fiji_a10[] = 96 { 97 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 98 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 99 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 100 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 101 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 102 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 103 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 104 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 105 }; 106 107 static const u32 fiji_mgcg_cgcg_init[] = 108 { 109 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 110 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 111 }; 112 113 static const u32 golden_settings_polaris11_a11[] = 114 { 115 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 116 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 117 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 118 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 119 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 120 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 121 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 122 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 123 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 124 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 125 }; 126 127 static const u32 golden_settings_polaris10_a11[] = 128 { 129 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 130 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 131 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 132 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 133 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 134 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 135 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 136 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 137 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 138 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 139 }; 140 141 static const u32 cz_golden_settings_a11[] = 142 { 143 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 144 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 145 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, 146 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, 147 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, 148 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, 149 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 150 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 151 mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100, 152 mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800, 153 mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100, 154 mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100, 155 }; 156 157 static const u32 cz_mgcg_cgcg_init[] = 158 { 159 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 160 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 161 }; 162 163 static const u32 stoney_golden_settings_a11[] = 164 { 165 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, 166 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, 167 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, 168 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, 169 }; 170 171 static const u32 stoney_mgcg_cgcg_init[] = 172 { 173 mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100, 174 }; 175 176 /* 177 * sDMA - System DMA 178 * Starting with CIK, the GPU has new asynchronous 179 * DMA engines. These engines are used for compute 180 * and gfx. There are two DMA engines (SDMA0, SDMA1) 181 * and each one supports 1 ring buffer used for gfx 182 * and 2 queues used for compute. 183 * 184 * The programming model is very similar to the CP 185 * (ring buffer, IBs, etc.), but sDMA has it's own 186 * packet format that is different from the PM4 format 187 * used by the CP. sDMA supports copying data, writing 188 * embedded data, solid fills, and a number of other 189 * things. It also has support for tiling/detiling of 190 * buffers. 191 */ 192 193 static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev) 194 { 195 switch (adev->asic_type) { 196 case CHIP_FIJI: 197 amdgpu_device_program_register_sequence(adev, 198 fiji_mgcg_cgcg_init, 199 ARRAY_SIZE(fiji_mgcg_cgcg_init)); 200 amdgpu_device_program_register_sequence(adev, 201 golden_settings_fiji_a10, 202 ARRAY_SIZE(golden_settings_fiji_a10)); 203 break; 204 case CHIP_TONGA: 205 amdgpu_device_program_register_sequence(adev, 206 tonga_mgcg_cgcg_init, 207 ARRAY_SIZE(tonga_mgcg_cgcg_init)); 208 amdgpu_device_program_register_sequence(adev, 209 golden_settings_tonga_a11, 210 ARRAY_SIZE(golden_settings_tonga_a11)); 211 break; 212 case CHIP_POLARIS11: 213 case CHIP_POLARIS12: 214 case CHIP_VEGAM: 215 amdgpu_device_program_register_sequence(adev, 216 golden_settings_polaris11_a11, 217 ARRAY_SIZE(golden_settings_polaris11_a11)); 218 break; 219 case CHIP_POLARIS10: 220 amdgpu_device_program_register_sequence(adev, 221 golden_settings_polaris10_a11, 222 ARRAY_SIZE(golden_settings_polaris10_a11)); 223 break; 224 case CHIP_CARRIZO: 225 amdgpu_device_program_register_sequence(adev, 226 cz_mgcg_cgcg_init, 227 ARRAY_SIZE(cz_mgcg_cgcg_init)); 228 amdgpu_device_program_register_sequence(adev, 229 cz_golden_settings_a11, 230 ARRAY_SIZE(cz_golden_settings_a11)); 231 break; 232 case CHIP_STONEY: 233 amdgpu_device_program_register_sequence(adev, 234 stoney_mgcg_cgcg_init, 235 ARRAY_SIZE(stoney_mgcg_cgcg_init)); 236 amdgpu_device_program_register_sequence(adev, 237 stoney_golden_settings_a11, 238 ARRAY_SIZE(stoney_golden_settings_a11)); 239 break; 240 default: 241 break; 242 } 243 } 244 245 static void sdma_v3_0_free_microcode(struct amdgpu_device *adev) 246 { 247 int i; 248 for (i = 0; i < adev->sdma.num_instances; i++) { 249 release_firmware(adev->sdma.instance[i].fw); 250 adev->sdma.instance[i].fw = NULL; 251 } 252 } 253 254 /** 255 * sdma_v3_0_init_microcode - load ucode images from disk 256 * 257 * @adev: amdgpu_device pointer 258 * 259 * Use the firmware interface to load the ucode images into 260 * the driver (not loaded into hw). 261 * Returns 0 on success, error on failure. 262 */ 263 static int sdma_v3_0_init_microcode(struct amdgpu_device *adev) 264 { 265 const char *chip_name; 266 char fw_name[30]; 267 int err = 0, i; 268 struct amdgpu_firmware_info *info = NULL; 269 const struct common_firmware_header *header = NULL; 270 const struct sdma_firmware_header_v1_0 *hdr; 271 272 DRM_DEBUG("\n"); 273 274 switch (adev->asic_type) { 275 case CHIP_TONGA: 276 chip_name = "tonga"; 277 break; 278 case CHIP_FIJI: 279 chip_name = "fiji"; 280 break; 281 case CHIP_POLARIS10: 282 chip_name = "polaris10"; 283 break; 284 case CHIP_POLARIS11: 285 chip_name = "polaris11"; 286 break; 287 case CHIP_POLARIS12: 288 chip_name = "polaris12"; 289 break; 290 case CHIP_VEGAM: 291 chip_name = "vegam"; 292 break; 293 case CHIP_CARRIZO: 294 chip_name = "carrizo"; 295 break; 296 case CHIP_STONEY: 297 chip_name = "stoney"; 298 break; 299 default: BUG(); 300 } 301 302 for (i = 0; i < adev->sdma.num_instances; i++) { 303 if (i == 0) 304 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 305 else 306 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); 307 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 308 if (err) 309 goto out; 310 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); 311 if (err) 312 goto out; 313 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 314 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 315 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 316 if (adev->sdma.instance[i].feature_version >= 20) 317 adev->sdma.instance[i].burst_nop = true; 318 319 if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) { 320 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 321 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 322 info->fw = adev->sdma.instance[i].fw; 323 header = (const struct common_firmware_header *)info->fw->data; 324 adev->firmware.fw_size += 325 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 326 } 327 } 328 out: 329 if (err) { 330 pr_err("sdma_v3_0: Failed to load firmware \"%s\"\n", fw_name); 331 for (i = 0; i < adev->sdma.num_instances; i++) { 332 release_firmware(adev->sdma.instance[i].fw); 333 adev->sdma.instance[i].fw = NULL; 334 } 335 } 336 return err; 337 } 338 339 /** 340 * sdma_v3_0_ring_get_rptr - get the current read pointer 341 * 342 * @ring: amdgpu ring pointer 343 * 344 * Get the current rptr from the hardware (VI+). 345 */ 346 static uint64_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring) 347 { 348 /* XXX check if swapping is necessary on BE */ 349 return ring->adev->wb.wb[ring->rptr_offs] >> 2; 350 } 351 352 /** 353 * sdma_v3_0_ring_get_wptr - get the current write pointer 354 * 355 * @ring: amdgpu ring pointer 356 * 357 * Get the current wptr from the hardware (VI+). 358 */ 359 static uint64_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring) 360 { 361 struct amdgpu_device *adev = ring->adev; 362 u32 wptr; 363 364 if (ring->use_doorbell || ring->use_pollmem) { 365 /* XXX check if swapping is necessary on BE */ 366 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2; 367 } else { 368 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2; 369 } 370 371 return wptr; 372 } 373 374 /** 375 * sdma_v3_0_ring_set_wptr - commit the write pointer 376 * 377 * @ring: amdgpu ring pointer 378 * 379 * Write the wptr back to the hardware (VI+). 380 */ 381 static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring) 382 { 383 struct amdgpu_device *adev = ring->adev; 384 385 if (ring->use_doorbell) { 386 u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs]; 387 /* XXX check if swapping is necessary on BE */ 388 WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2)); 389 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr) << 2); 390 } else if (ring->use_pollmem) { 391 u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs]; 392 393 WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2)); 394 } else { 395 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2); 396 } 397 } 398 399 static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 400 { 401 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); 402 int i; 403 404 for (i = 0; i < count; i++) 405 if (sdma && sdma->burst_nop && (i == 0)) 406 amdgpu_ring_write(ring, ring->funcs->nop | 407 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 408 else 409 amdgpu_ring_write(ring, ring->funcs->nop); 410 } 411 412 /** 413 * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine 414 * 415 * @ring: amdgpu ring pointer 416 * @ib: IB object to schedule 417 * 418 * Schedule an IB in the DMA ring (VI). 419 */ 420 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring, 421 struct amdgpu_ib *ib, 422 unsigned vmid, bool ctx_switch) 423 { 424 /* IB packet must end on a 8 DW boundary */ 425 sdma_v3_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8); 426 427 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 428 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 429 /* base must be 32 byte aligned */ 430 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 431 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 432 amdgpu_ring_write(ring, ib->length_dw); 433 amdgpu_ring_write(ring, 0); 434 amdgpu_ring_write(ring, 0); 435 436 } 437 438 /** 439 * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 440 * 441 * @ring: amdgpu ring pointer 442 * 443 * Emit an hdp flush packet on the requested DMA ring. 444 */ 445 static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 446 { 447 u32 ref_and_mask = 0; 448 449 if (ring->me == 0) 450 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); 451 else 452 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); 453 454 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 455 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 456 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 457 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); 458 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); 459 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 460 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 461 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 462 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 463 } 464 465 /** 466 * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring 467 * 468 * @ring: amdgpu ring pointer 469 * @fence: amdgpu fence object 470 * 471 * Add a DMA fence packet to the ring to write 472 * the fence seq number and DMA trap packet to generate 473 * an interrupt if needed (VI). 474 */ 475 static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 476 unsigned flags) 477 { 478 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 479 /* write the fence */ 480 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 481 amdgpu_ring_write(ring, lower_32_bits(addr)); 482 amdgpu_ring_write(ring, upper_32_bits(addr)); 483 amdgpu_ring_write(ring, lower_32_bits(seq)); 484 485 /* optionally write high bits as well */ 486 if (write64bit) { 487 addr += 4; 488 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 489 amdgpu_ring_write(ring, lower_32_bits(addr)); 490 amdgpu_ring_write(ring, upper_32_bits(addr)); 491 amdgpu_ring_write(ring, upper_32_bits(seq)); 492 } 493 494 /* generate an interrupt */ 495 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 496 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 497 } 498 499 /** 500 * sdma_v3_0_gfx_stop - stop the gfx async dma engines 501 * 502 * @adev: amdgpu_device pointer 503 * 504 * Stop the gfx async dma ring buffers (VI). 505 */ 506 static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev) 507 { 508 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 509 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 510 u32 rb_cntl, ib_cntl; 511 int i; 512 513 if ((adev->mman.buffer_funcs_ring == sdma0) || 514 (adev->mman.buffer_funcs_ring == sdma1)) 515 amdgpu_ttm_set_buffer_funcs_status(adev, false); 516 517 for (i = 0; i < adev->sdma.num_instances; i++) { 518 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 519 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 520 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 521 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 522 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 523 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 524 } 525 sdma0->ready = false; 526 sdma1->ready = false; 527 } 528 529 /** 530 * sdma_v3_0_rlc_stop - stop the compute async dma engines 531 * 532 * @adev: amdgpu_device pointer 533 * 534 * Stop the compute async dma queues (VI). 535 */ 536 static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev) 537 { 538 /* XXX todo */ 539 } 540 541 /** 542 * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch 543 * 544 * @adev: amdgpu_device pointer 545 * @enable: enable/disable the DMA MEs context switch. 546 * 547 * Halt or unhalt the async dma engines context switch (VI). 548 */ 549 static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 550 { 551 u32 f32_cntl, phase_quantum = 0; 552 int i; 553 554 if (amdgpu_sdma_phase_quantum) { 555 unsigned value = amdgpu_sdma_phase_quantum; 556 unsigned unit = 0; 557 558 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 559 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 560 value = (value + 1) >> 1; 561 unit++; 562 } 563 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 564 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 565 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 566 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 567 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 568 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 569 WARN_ONCE(1, 570 "clamping sdma_phase_quantum to %uK clock cycles\n", 571 value << unit); 572 } 573 phase_quantum = 574 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 575 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 576 } 577 578 for (i = 0; i < adev->sdma.num_instances; i++) { 579 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); 580 if (enable) { 581 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 582 AUTO_CTXSW_ENABLE, 1); 583 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 584 ATC_L1_ENABLE, 1); 585 if (amdgpu_sdma_phase_quantum) { 586 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i], 587 phase_quantum); 588 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i], 589 phase_quantum); 590 } 591 } else { 592 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 593 AUTO_CTXSW_ENABLE, 0); 594 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 595 ATC_L1_ENABLE, 1); 596 } 597 598 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); 599 } 600 } 601 602 /** 603 * sdma_v3_0_enable - stop the async dma engines 604 * 605 * @adev: amdgpu_device pointer 606 * @enable: enable/disable the DMA MEs. 607 * 608 * Halt or unhalt the async dma engines (VI). 609 */ 610 static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable) 611 { 612 u32 f32_cntl; 613 int i; 614 615 if (!enable) { 616 sdma_v3_0_gfx_stop(adev); 617 sdma_v3_0_rlc_stop(adev); 618 } 619 620 for (i = 0; i < adev->sdma.num_instances; i++) { 621 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); 622 if (enable) 623 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); 624 else 625 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); 626 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); 627 } 628 } 629 630 /** 631 * sdma_v3_0_gfx_resume - setup and start the async dma engines 632 * 633 * @adev: amdgpu_device pointer 634 * 635 * Set up the gfx DMA ring buffers and enable them (VI). 636 * Returns 0 for success, error for failure. 637 */ 638 static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) 639 { 640 struct amdgpu_ring *ring; 641 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 642 u32 rb_bufsz; 643 u32 wb_offset; 644 u32 doorbell; 645 u64 wptr_gpu_addr; 646 int i, j, r; 647 648 for (i = 0; i < adev->sdma.num_instances; i++) { 649 ring = &adev->sdma.instance[i].ring; 650 amdgpu_ring_clear_ring(ring); 651 wb_offset = (ring->rptr_offs * 4); 652 653 mutex_lock(&adev->srbm_mutex); 654 for (j = 0; j < 16; j++) { 655 vi_srbm_select(adev, 0, 0, 0, j); 656 /* SDMA GFX */ 657 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); 658 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); 659 } 660 vi_srbm_select(adev, 0, 0, 0, 0); 661 mutex_unlock(&adev->srbm_mutex); 662 663 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], 664 adev->gfx.config.gb_addr_config & 0x70); 665 666 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); 667 668 /* Set ring buffer size in dwords */ 669 rb_bufsz = order_base_2(ring->ring_size / 4); 670 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 671 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 672 #ifdef __BIG_ENDIAN 673 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 674 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 675 RPTR_WRITEBACK_SWAP_ENABLE, 1); 676 #endif 677 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 678 679 /* Initialize the ring buffer's read and write pointers */ 680 ring->wptr = 0; 681 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); 682 sdma_v3_0_ring_set_wptr(ring); 683 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); 684 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); 685 686 /* set the wb address whether it's enabled or not */ 687 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], 688 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 689 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], 690 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 691 692 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 693 694 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); 695 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); 696 697 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]); 698 699 if (ring->use_doorbell) { 700 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, 701 OFFSET, ring->doorbell_index); 702 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 703 } else { 704 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 705 } 706 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell); 707 708 /* setup the wptr shadow polling */ 709 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 710 711 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i], 712 lower_32_bits(wptr_gpu_addr)); 713 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i], 714 upper_32_bits(wptr_gpu_addr)); 715 wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]); 716 if (ring->use_pollmem) { 717 /*wptr polling is not enogh fast, directly clean the wptr register */ 718 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); 719 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 720 SDMA0_GFX_RB_WPTR_POLL_CNTL, 721 ENABLE, 1); 722 } else { 723 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 724 SDMA0_GFX_RB_WPTR_POLL_CNTL, 725 ENABLE, 0); 726 } 727 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i], wptr_poll_cntl); 728 729 /* enable DMA RB */ 730 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 731 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 732 733 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 734 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 735 #ifdef __BIG_ENDIAN 736 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 737 #endif 738 /* enable DMA IBs */ 739 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 740 741 ring->ready = true; 742 } 743 744 /* unhalt the MEs */ 745 sdma_v3_0_enable(adev, true); 746 /* enable sdma ring preemption */ 747 sdma_v3_0_ctx_switch_enable(adev, true); 748 749 for (i = 0; i < adev->sdma.num_instances; i++) { 750 ring = &adev->sdma.instance[i].ring; 751 r = amdgpu_ring_test_ring(ring); 752 if (r) { 753 ring->ready = false; 754 return r; 755 } 756 757 if (adev->mman.buffer_funcs_ring == ring) 758 amdgpu_ttm_set_buffer_funcs_status(adev, true); 759 } 760 761 return 0; 762 } 763 764 /** 765 * sdma_v3_0_rlc_resume - setup and start the async dma engines 766 * 767 * @adev: amdgpu_device pointer 768 * 769 * Set up the compute DMA queues and enable them (VI). 770 * Returns 0 for success, error for failure. 771 */ 772 static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev) 773 { 774 /* XXX todo */ 775 return 0; 776 } 777 778 /** 779 * sdma_v3_0_load_microcode - load the sDMA ME ucode 780 * 781 * @adev: amdgpu_device pointer 782 * 783 * Loads the sDMA0/1 ucode. 784 * Returns 0 for success, -EINVAL if the ucode is not available. 785 */ 786 static int sdma_v3_0_load_microcode(struct amdgpu_device *adev) 787 { 788 const struct sdma_firmware_header_v1_0 *hdr; 789 const __le32 *fw_data; 790 u32 fw_size; 791 int i, j; 792 793 /* halt the MEs */ 794 sdma_v3_0_enable(adev, false); 795 796 for (i = 0; i < adev->sdma.num_instances; i++) { 797 if (!adev->sdma.instance[i].fw) 798 return -EINVAL; 799 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 800 amdgpu_ucode_print_sdma_hdr(&hdr->header); 801 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 802 fw_data = (const __le32 *) 803 (adev->sdma.instance[i].fw->data + 804 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 805 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0); 806 for (j = 0; j < fw_size; j++) 807 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++)); 808 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version); 809 } 810 811 return 0; 812 } 813 814 /** 815 * sdma_v3_0_start - setup and start the async dma engines 816 * 817 * @adev: amdgpu_device pointer 818 * 819 * Set up the DMA engines and enable them (VI). 820 * Returns 0 for success, error for failure. 821 */ 822 static int sdma_v3_0_start(struct amdgpu_device *adev) 823 { 824 int r; 825 826 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 827 r = sdma_v3_0_load_microcode(adev); 828 if (r) 829 return r; 830 } 831 832 /* disable sdma engine before programing it */ 833 sdma_v3_0_ctx_switch_enable(adev, false); 834 sdma_v3_0_enable(adev, false); 835 836 /* start the gfx rings and rlc compute queues */ 837 r = sdma_v3_0_gfx_resume(adev); 838 if (r) 839 return r; 840 r = sdma_v3_0_rlc_resume(adev); 841 if (r) 842 return r; 843 844 return 0; 845 } 846 847 /** 848 * sdma_v3_0_ring_test_ring - simple async dma engine test 849 * 850 * @ring: amdgpu_ring structure holding ring information 851 * 852 * Test the DMA engine by writing using it to write an 853 * value to memory. (VI). 854 * Returns 0 for success, error for failure. 855 */ 856 static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring) 857 { 858 struct amdgpu_device *adev = ring->adev; 859 unsigned i; 860 unsigned index; 861 int r; 862 u32 tmp; 863 u64 gpu_addr; 864 865 r = amdgpu_device_wb_get(adev, &index); 866 if (r) { 867 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 868 return r; 869 } 870 871 gpu_addr = adev->wb.gpu_addr + (index * 4); 872 tmp = 0xCAFEDEAD; 873 adev->wb.wb[index] = cpu_to_le32(tmp); 874 875 r = amdgpu_ring_alloc(ring, 5); 876 if (r) { 877 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 878 amdgpu_device_wb_free(adev, index); 879 return r; 880 } 881 882 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 883 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 884 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 885 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 886 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); 887 amdgpu_ring_write(ring, 0xDEADBEEF); 888 amdgpu_ring_commit(ring); 889 890 for (i = 0; i < adev->usec_timeout; i++) { 891 tmp = le32_to_cpu(adev->wb.wb[index]); 892 if (tmp == 0xDEADBEEF) 893 break; 894 DRM_UDELAY(1); 895 } 896 897 if (i < adev->usec_timeout) { 898 DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); 899 } else { 900 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 901 ring->idx, tmp); 902 r = -EINVAL; 903 } 904 amdgpu_device_wb_free(adev, index); 905 906 return r; 907 } 908 909 /** 910 * sdma_v3_0_ring_test_ib - test an IB on the DMA engine 911 * 912 * @ring: amdgpu_ring structure holding ring information 913 * 914 * Test a simple IB in the DMA ring (VI). 915 * Returns 0 on success, error on failure. 916 */ 917 static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 918 { 919 struct amdgpu_device *adev = ring->adev; 920 struct amdgpu_ib ib; 921 struct dma_fence *f = NULL; 922 unsigned index; 923 u32 tmp = 0; 924 u64 gpu_addr; 925 long r; 926 927 r = amdgpu_device_wb_get(adev, &index); 928 if (r) { 929 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 930 return r; 931 } 932 933 gpu_addr = adev->wb.gpu_addr + (index * 4); 934 tmp = 0xCAFEDEAD; 935 adev->wb.wb[index] = cpu_to_le32(tmp); 936 memset(&ib, 0, sizeof(ib)); 937 r = amdgpu_ib_get(adev, NULL, 256, &ib); 938 if (r) { 939 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 940 goto err0; 941 } 942 943 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 944 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 945 ib.ptr[1] = lower_32_bits(gpu_addr); 946 ib.ptr[2] = upper_32_bits(gpu_addr); 947 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1); 948 ib.ptr[4] = 0xDEADBEEF; 949 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 950 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 951 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 952 ib.length_dw = 8; 953 954 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 955 if (r) 956 goto err1; 957 958 r = dma_fence_wait_timeout(f, false, timeout); 959 if (r == 0) { 960 DRM_ERROR("amdgpu: IB test timed out\n"); 961 r = -ETIMEDOUT; 962 goto err1; 963 } else if (r < 0) { 964 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 965 goto err1; 966 } 967 tmp = le32_to_cpu(adev->wb.wb[index]); 968 if (tmp == 0xDEADBEEF) { 969 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); 970 r = 0; 971 } else { 972 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); 973 r = -EINVAL; 974 } 975 err1: 976 amdgpu_ib_free(adev, &ib, NULL); 977 dma_fence_put(f); 978 err0: 979 amdgpu_device_wb_free(adev, index); 980 return r; 981 } 982 983 /** 984 * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART 985 * 986 * @ib: indirect buffer to fill with commands 987 * @pe: addr of the page entry 988 * @src: src addr to copy from 989 * @count: number of page entries to update 990 * 991 * Update PTEs by copying them from the GART using sDMA (CIK). 992 */ 993 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib, 994 uint64_t pe, uint64_t src, 995 unsigned count) 996 { 997 unsigned bytes = count * 8; 998 999 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1000 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1001 ib->ptr[ib->length_dw++] = bytes; 1002 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1003 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1004 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1005 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1006 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1007 } 1008 1009 /** 1010 * sdma_v3_0_vm_write_pte - update PTEs by writing them manually 1011 * 1012 * @ib: indirect buffer to fill with commands 1013 * @pe: addr of the page entry 1014 * @value: dst addr to write into pe 1015 * @count: number of page entries to update 1016 * @incr: increase next addr by incr bytes 1017 * 1018 * Update PTEs by writing them manually using sDMA (CIK). 1019 */ 1020 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1021 uint64_t value, unsigned count, 1022 uint32_t incr) 1023 { 1024 unsigned ndw = count * 2; 1025 1026 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1027 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1028 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1029 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1030 ib->ptr[ib->length_dw++] = ndw; 1031 for (; ndw > 0; ndw -= 2) { 1032 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1033 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1034 value += incr; 1035 } 1036 } 1037 1038 /** 1039 * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA 1040 * 1041 * @ib: indirect buffer to fill with commands 1042 * @pe: addr of the page entry 1043 * @addr: dst addr to write into pe 1044 * @count: number of page entries to update 1045 * @incr: increase next addr by incr bytes 1046 * @flags: access flags 1047 * 1048 * Update the page tables using sDMA (CIK). 1049 */ 1050 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe, 1051 uint64_t addr, unsigned count, 1052 uint32_t incr, uint64_t flags) 1053 { 1054 /* for physically contiguous pages (vram) */ 1055 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE); 1056 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1057 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1058 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1059 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1060 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1061 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1062 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1063 ib->ptr[ib->length_dw++] = 0; 1064 ib->ptr[ib->length_dw++] = count; /* number of entries */ 1065 } 1066 1067 /** 1068 * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw 1069 * 1070 * @ib: indirect buffer to fill with padding 1071 * 1072 */ 1073 static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1074 { 1075 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); 1076 u32 pad_count; 1077 int i; 1078 1079 pad_count = (8 - (ib->length_dw & 0x7)) % 8; 1080 for (i = 0; i < pad_count; i++) 1081 if (sdma && sdma->burst_nop && (i == 0)) 1082 ib->ptr[ib->length_dw++] = 1083 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1084 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1085 else 1086 ib->ptr[ib->length_dw++] = 1087 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1088 } 1089 1090 /** 1091 * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline 1092 * 1093 * @ring: amdgpu_ring pointer 1094 * 1095 * Make sure all previous operations are completed (CIK). 1096 */ 1097 static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1098 { 1099 uint32_t seq = ring->fence_drv.sync_seq; 1100 uint64_t addr = ring->fence_drv.gpu_addr; 1101 1102 /* wait for idle */ 1103 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1104 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1105 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1106 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1107 amdgpu_ring_write(ring, addr & 0xfffffffc); 1108 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1109 amdgpu_ring_write(ring, seq); /* reference */ 1110 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1111 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1112 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1113 } 1114 1115 /** 1116 * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA 1117 * 1118 * @ring: amdgpu_ring pointer 1119 * @vm: amdgpu_vm pointer 1120 * 1121 * Update the page table base and flush the VM TLB 1122 * using sDMA (VI). 1123 */ 1124 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1125 unsigned vmid, uint64_t pd_addr) 1126 { 1127 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1128 1129 /* wait for flush */ 1130 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1131 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1132 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */ 1133 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); 1134 amdgpu_ring_write(ring, 0); 1135 amdgpu_ring_write(ring, 0); /* reference */ 1136 amdgpu_ring_write(ring, 0); /* mask */ 1137 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1138 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 1139 } 1140 1141 static void sdma_v3_0_ring_emit_wreg(struct amdgpu_ring *ring, 1142 uint32_t reg, uint32_t val) 1143 { 1144 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1145 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1146 amdgpu_ring_write(ring, reg); 1147 amdgpu_ring_write(ring, val); 1148 } 1149 1150 static int sdma_v3_0_early_init(void *handle) 1151 { 1152 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1153 1154 switch (adev->asic_type) { 1155 case CHIP_STONEY: 1156 adev->sdma.num_instances = 1; 1157 break; 1158 default: 1159 adev->sdma.num_instances = SDMA_MAX_INSTANCE; 1160 break; 1161 } 1162 1163 sdma_v3_0_set_ring_funcs(adev); 1164 sdma_v3_0_set_buffer_funcs(adev); 1165 sdma_v3_0_set_vm_pte_funcs(adev); 1166 sdma_v3_0_set_irq_funcs(adev); 1167 1168 return 0; 1169 } 1170 1171 static int sdma_v3_0_sw_init(void *handle) 1172 { 1173 struct amdgpu_ring *ring; 1174 int r, i; 1175 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1176 1177 /* SDMA trap event */ 1178 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 224, 1179 &adev->sdma.trap_irq); 1180 if (r) 1181 return r; 1182 1183 /* SDMA Privileged inst */ 1184 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 241, 1185 &adev->sdma.illegal_inst_irq); 1186 if (r) 1187 return r; 1188 1189 /* SDMA Privileged inst */ 1190 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 247, 1191 &adev->sdma.illegal_inst_irq); 1192 if (r) 1193 return r; 1194 1195 r = sdma_v3_0_init_microcode(adev); 1196 if (r) { 1197 DRM_ERROR("Failed to load sdma firmware!\n"); 1198 return r; 1199 } 1200 1201 for (i = 0; i < adev->sdma.num_instances; i++) { 1202 ring = &adev->sdma.instance[i].ring; 1203 ring->ring_obj = NULL; 1204 if (!amdgpu_sriov_vf(adev)) { 1205 ring->use_doorbell = true; 1206 ring->doorbell_index = (i == 0) ? 1207 AMDGPU_DOORBELL_sDMA_ENGINE0 : AMDGPU_DOORBELL_sDMA_ENGINE1; 1208 } else { 1209 ring->use_pollmem = true; 1210 } 1211 1212 sprintf(ring->name, "sdma%d", i); 1213 r = amdgpu_ring_init(adev, ring, 1024, 1214 &adev->sdma.trap_irq, 1215 (i == 0) ? 1216 AMDGPU_SDMA_IRQ_TRAP0 : 1217 AMDGPU_SDMA_IRQ_TRAP1); 1218 if (r) 1219 return r; 1220 } 1221 1222 return r; 1223 } 1224 1225 static int sdma_v3_0_sw_fini(void *handle) 1226 { 1227 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1228 int i; 1229 1230 for (i = 0; i < adev->sdma.num_instances; i++) 1231 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1232 1233 sdma_v3_0_free_microcode(adev); 1234 return 0; 1235 } 1236 1237 static int sdma_v3_0_hw_init(void *handle) 1238 { 1239 int r; 1240 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1241 1242 sdma_v3_0_init_golden_registers(adev); 1243 1244 r = sdma_v3_0_start(adev); 1245 if (r) 1246 return r; 1247 1248 return r; 1249 } 1250 1251 static int sdma_v3_0_hw_fini(void *handle) 1252 { 1253 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1254 1255 sdma_v3_0_ctx_switch_enable(adev, false); 1256 sdma_v3_0_enable(adev, false); 1257 1258 return 0; 1259 } 1260 1261 static int sdma_v3_0_suspend(void *handle) 1262 { 1263 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1264 1265 return sdma_v3_0_hw_fini(adev); 1266 } 1267 1268 static int sdma_v3_0_resume(void *handle) 1269 { 1270 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1271 1272 return sdma_v3_0_hw_init(adev); 1273 } 1274 1275 static bool sdma_v3_0_is_idle(void *handle) 1276 { 1277 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1278 u32 tmp = RREG32(mmSRBM_STATUS2); 1279 1280 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | 1281 SRBM_STATUS2__SDMA1_BUSY_MASK)) 1282 return false; 1283 1284 return true; 1285 } 1286 1287 static int sdma_v3_0_wait_for_idle(void *handle) 1288 { 1289 unsigned i; 1290 u32 tmp; 1291 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1292 1293 for (i = 0; i < adev->usec_timeout; i++) { 1294 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | 1295 SRBM_STATUS2__SDMA1_BUSY_MASK); 1296 1297 if (!tmp) 1298 return 0; 1299 udelay(1); 1300 } 1301 return -ETIMEDOUT; 1302 } 1303 1304 static bool sdma_v3_0_check_soft_reset(void *handle) 1305 { 1306 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1307 u32 srbm_soft_reset = 0; 1308 u32 tmp = RREG32(mmSRBM_STATUS2); 1309 1310 if ((tmp & SRBM_STATUS2__SDMA_BUSY_MASK) || 1311 (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)) { 1312 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK; 1313 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK; 1314 } 1315 1316 if (srbm_soft_reset) { 1317 adev->sdma.srbm_soft_reset = srbm_soft_reset; 1318 return true; 1319 } else { 1320 adev->sdma.srbm_soft_reset = 0; 1321 return false; 1322 } 1323 } 1324 1325 static int sdma_v3_0_pre_soft_reset(void *handle) 1326 { 1327 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1328 u32 srbm_soft_reset = 0; 1329 1330 if (!adev->sdma.srbm_soft_reset) 1331 return 0; 1332 1333 srbm_soft_reset = adev->sdma.srbm_soft_reset; 1334 1335 if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) || 1336 REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) { 1337 sdma_v3_0_ctx_switch_enable(adev, false); 1338 sdma_v3_0_enable(adev, false); 1339 } 1340 1341 return 0; 1342 } 1343 1344 static int sdma_v3_0_post_soft_reset(void *handle) 1345 { 1346 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1347 u32 srbm_soft_reset = 0; 1348 1349 if (!adev->sdma.srbm_soft_reset) 1350 return 0; 1351 1352 srbm_soft_reset = adev->sdma.srbm_soft_reset; 1353 1354 if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) || 1355 REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) { 1356 sdma_v3_0_gfx_resume(adev); 1357 sdma_v3_0_rlc_resume(adev); 1358 } 1359 1360 return 0; 1361 } 1362 1363 static int sdma_v3_0_soft_reset(void *handle) 1364 { 1365 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1366 u32 srbm_soft_reset = 0; 1367 u32 tmp; 1368 1369 if (!adev->sdma.srbm_soft_reset) 1370 return 0; 1371 1372 srbm_soft_reset = adev->sdma.srbm_soft_reset; 1373 1374 if (srbm_soft_reset) { 1375 tmp = RREG32(mmSRBM_SOFT_RESET); 1376 tmp |= srbm_soft_reset; 1377 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1378 WREG32(mmSRBM_SOFT_RESET, tmp); 1379 tmp = RREG32(mmSRBM_SOFT_RESET); 1380 1381 udelay(50); 1382 1383 tmp &= ~srbm_soft_reset; 1384 WREG32(mmSRBM_SOFT_RESET, tmp); 1385 tmp = RREG32(mmSRBM_SOFT_RESET); 1386 1387 /* Wait a little for things to settle down */ 1388 udelay(50); 1389 } 1390 1391 return 0; 1392 } 1393 1394 static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev, 1395 struct amdgpu_irq_src *source, 1396 unsigned type, 1397 enum amdgpu_interrupt_state state) 1398 { 1399 u32 sdma_cntl; 1400 1401 switch (type) { 1402 case AMDGPU_SDMA_IRQ_TRAP0: 1403 switch (state) { 1404 case AMDGPU_IRQ_STATE_DISABLE: 1405 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1406 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1407 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1408 break; 1409 case AMDGPU_IRQ_STATE_ENABLE: 1410 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1411 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1412 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1413 break; 1414 default: 1415 break; 1416 } 1417 break; 1418 case AMDGPU_SDMA_IRQ_TRAP1: 1419 switch (state) { 1420 case AMDGPU_IRQ_STATE_DISABLE: 1421 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1422 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1423 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1424 break; 1425 case AMDGPU_IRQ_STATE_ENABLE: 1426 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1427 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1428 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1429 break; 1430 default: 1431 break; 1432 } 1433 break; 1434 default: 1435 break; 1436 } 1437 return 0; 1438 } 1439 1440 static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev, 1441 struct amdgpu_irq_src *source, 1442 struct amdgpu_iv_entry *entry) 1443 { 1444 u8 instance_id, queue_id; 1445 1446 instance_id = (entry->ring_id & 0x3) >> 0; 1447 queue_id = (entry->ring_id & 0xc) >> 2; 1448 DRM_DEBUG("IH: SDMA trap\n"); 1449 switch (instance_id) { 1450 case 0: 1451 switch (queue_id) { 1452 case 0: 1453 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1454 break; 1455 case 1: 1456 /* XXX compute */ 1457 break; 1458 case 2: 1459 /* XXX compute */ 1460 break; 1461 } 1462 break; 1463 case 1: 1464 switch (queue_id) { 1465 case 0: 1466 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1467 break; 1468 case 1: 1469 /* XXX compute */ 1470 break; 1471 case 2: 1472 /* XXX compute */ 1473 break; 1474 } 1475 break; 1476 } 1477 return 0; 1478 } 1479 1480 static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1481 struct amdgpu_irq_src *source, 1482 struct amdgpu_iv_entry *entry) 1483 { 1484 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1485 schedule_work(&adev->reset_work); 1486 return 0; 1487 } 1488 1489 static void sdma_v3_0_update_sdma_medium_grain_clock_gating( 1490 struct amdgpu_device *adev, 1491 bool enable) 1492 { 1493 uint32_t temp, data; 1494 int i; 1495 1496 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1497 for (i = 0; i < adev->sdma.num_instances; i++) { 1498 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]); 1499 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1500 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1501 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1502 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1503 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1504 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1505 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1506 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1507 if (data != temp) 1508 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); 1509 } 1510 } else { 1511 for (i = 0; i < adev->sdma.num_instances; i++) { 1512 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]); 1513 data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1514 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1515 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1516 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1517 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1518 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1519 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1520 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK; 1521 1522 if (data != temp) 1523 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); 1524 } 1525 } 1526 } 1527 1528 static void sdma_v3_0_update_sdma_medium_grain_light_sleep( 1529 struct amdgpu_device *adev, 1530 bool enable) 1531 { 1532 uint32_t temp, data; 1533 int i; 1534 1535 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1536 for (i = 0; i < adev->sdma.num_instances; i++) { 1537 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); 1538 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1539 1540 if (temp != data) 1541 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); 1542 } 1543 } else { 1544 for (i = 0; i < adev->sdma.num_instances; i++) { 1545 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); 1546 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1547 1548 if (temp != data) 1549 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); 1550 } 1551 } 1552 } 1553 1554 static int sdma_v3_0_set_clockgating_state(void *handle, 1555 enum amd_clockgating_state state) 1556 { 1557 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1558 1559 if (amdgpu_sriov_vf(adev)) 1560 return 0; 1561 1562 switch (adev->asic_type) { 1563 case CHIP_FIJI: 1564 case CHIP_CARRIZO: 1565 case CHIP_STONEY: 1566 sdma_v3_0_update_sdma_medium_grain_clock_gating(adev, 1567 state == AMD_CG_STATE_GATE); 1568 sdma_v3_0_update_sdma_medium_grain_light_sleep(adev, 1569 state == AMD_CG_STATE_GATE); 1570 break; 1571 default: 1572 break; 1573 } 1574 return 0; 1575 } 1576 1577 static int sdma_v3_0_set_powergating_state(void *handle, 1578 enum amd_powergating_state state) 1579 { 1580 return 0; 1581 } 1582 1583 static void sdma_v3_0_get_clockgating_state(void *handle, u32 *flags) 1584 { 1585 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1586 int data; 1587 1588 if (amdgpu_sriov_vf(adev)) 1589 *flags = 0; 1590 1591 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1592 data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[0]); 1593 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK)) 1594 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1595 1596 /* AMD_CG_SUPPORT_SDMA_LS */ 1597 data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[0]); 1598 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1599 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1600 } 1601 1602 static const struct amd_ip_funcs sdma_v3_0_ip_funcs = { 1603 .name = "sdma_v3_0", 1604 .early_init = sdma_v3_0_early_init, 1605 .late_init = NULL, 1606 .sw_init = sdma_v3_0_sw_init, 1607 .sw_fini = sdma_v3_0_sw_fini, 1608 .hw_init = sdma_v3_0_hw_init, 1609 .hw_fini = sdma_v3_0_hw_fini, 1610 .suspend = sdma_v3_0_suspend, 1611 .resume = sdma_v3_0_resume, 1612 .is_idle = sdma_v3_0_is_idle, 1613 .wait_for_idle = sdma_v3_0_wait_for_idle, 1614 .check_soft_reset = sdma_v3_0_check_soft_reset, 1615 .pre_soft_reset = sdma_v3_0_pre_soft_reset, 1616 .post_soft_reset = sdma_v3_0_post_soft_reset, 1617 .soft_reset = sdma_v3_0_soft_reset, 1618 .set_clockgating_state = sdma_v3_0_set_clockgating_state, 1619 .set_powergating_state = sdma_v3_0_set_powergating_state, 1620 .get_clockgating_state = sdma_v3_0_get_clockgating_state, 1621 }; 1622 1623 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { 1624 .type = AMDGPU_RING_TYPE_SDMA, 1625 .align_mask = 0xf, 1626 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1627 .support_64bit_ptrs = false, 1628 .get_rptr = sdma_v3_0_ring_get_rptr, 1629 .get_wptr = sdma_v3_0_ring_get_wptr, 1630 .set_wptr = sdma_v3_0_ring_set_wptr, 1631 .emit_frame_size = 1632 6 + /* sdma_v3_0_ring_emit_hdp_flush */ 1633 3 + /* hdp invalidate */ 1634 6 + /* sdma_v3_0_ring_emit_pipeline_sync */ 1635 VI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v3_0_ring_emit_vm_flush */ 1636 10 + 10 + 10, /* sdma_v3_0_ring_emit_fence x3 for user fence, vm fence */ 1637 .emit_ib_size = 7 + 6, /* sdma_v3_0_ring_emit_ib */ 1638 .emit_ib = sdma_v3_0_ring_emit_ib, 1639 .emit_fence = sdma_v3_0_ring_emit_fence, 1640 .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync, 1641 .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush, 1642 .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush, 1643 .test_ring = sdma_v3_0_ring_test_ring, 1644 .test_ib = sdma_v3_0_ring_test_ib, 1645 .insert_nop = sdma_v3_0_ring_insert_nop, 1646 .pad_ib = sdma_v3_0_ring_pad_ib, 1647 .emit_wreg = sdma_v3_0_ring_emit_wreg, 1648 }; 1649 1650 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev) 1651 { 1652 int i; 1653 1654 for (i = 0; i < adev->sdma.num_instances; i++) { 1655 adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs; 1656 adev->sdma.instance[i].ring.me = i; 1657 } 1658 } 1659 1660 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = { 1661 .set = sdma_v3_0_set_trap_irq_state, 1662 .process = sdma_v3_0_process_trap_irq, 1663 }; 1664 1665 static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = { 1666 .process = sdma_v3_0_process_illegal_inst_irq, 1667 }; 1668 1669 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev) 1670 { 1671 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 1672 adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs; 1673 adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs; 1674 } 1675 1676 /** 1677 * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine 1678 * 1679 * @ring: amdgpu_ring structure holding ring information 1680 * @src_offset: src GPU address 1681 * @dst_offset: dst GPU address 1682 * @byte_count: number of bytes to xfer 1683 * 1684 * Copy GPU buffers using the DMA engine (VI). 1685 * Used by the amdgpu ttm implementation to move pages if 1686 * registered as the asic copy callback. 1687 */ 1688 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib, 1689 uint64_t src_offset, 1690 uint64_t dst_offset, 1691 uint32_t byte_count) 1692 { 1693 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1694 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1695 ib->ptr[ib->length_dw++] = byte_count; 1696 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1697 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1698 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1699 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1700 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1701 } 1702 1703 /** 1704 * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine 1705 * 1706 * @ring: amdgpu_ring structure holding ring information 1707 * @src_data: value to write to buffer 1708 * @dst_offset: dst GPU address 1709 * @byte_count: number of bytes to xfer 1710 * 1711 * Fill GPU buffers using the DMA engine (VI). 1712 */ 1713 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib, 1714 uint32_t src_data, 1715 uint64_t dst_offset, 1716 uint32_t byte_count) 1717 { 1718 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1719 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1720 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1721 ib->ptr[ib->length_dw++] = src_data; 1722 ib->ptr[ib->length_dw++] = byte_count; 1723 } 1724 1725 static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = { 1726 .copy_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */ 1727 .copy_num_dw = 7, 1728 .emit_copy_buffer = sdma_v3_0_emit_copy_buffer, 1729 1730 .fill_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */ 1731 .fill_num_dw = 5, 1732 .emit_fill_buffer = sdma_v3_0_emit_fill_buffer, 1733 }; 1734 1735 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev) 1736 { 1737 if (adev->mman.buffer_funcs == NULL) { 1738 adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs; 1739 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1740 } 1741 } 1742 1743 static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = { 1744 .copy_pte_num_dw = 7, 1745 .copy_pte = sdma_v3_0_vm_copy_pte, 1746 1747 .write_pte = sdma_v3_0_vm_write_pte, 1748 .set_pte_pde = sdma_v3_0_vm_set_pte_pde, 1749 }; 1750 1751 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1752 { 1753 unsigned i; 1754 1755 if (adev->vm_manager.vm_pte_funcs == NULL) { 1756 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs; 1757 for (i = 0; i < adev->sdma.num_instances; i++) 1758 adev->vm_manager.vm_pte_rings[i] = 1759 &adev->sdma.instance[i].ring; 1760 1761 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances; 1762 } 1763 } 1764 1765 const struct amdgpu_ip_block_version sdma_v3_0_ip_block = 1766 { 1767 .type = AMD_IP_BLOCK_TYPE_SDMA, 1768 .major = 3, 1769 .minor = 0, 1770 .rev = 0, 1771 .funcs = &sdma_v3_0_ip_funcs, 1772 }; 1773 1774 const struct amdgpu_ip_block_version sdma_v3_1_ip_block = 1775 { 1776 .type = AMD_IP_BLOCK_TYPE_SDMA, 1777 .major = 3, 1778 .minor = 1, 1779 .rev = 0, 1780 .funcs = &sdma_v3_0_ip_funcs, 1781 }; 1782