1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_ucode.h" 28 #include "amdgpu_trace.h" 29 #include "vi.h" 30 #include "vid.h" 31 32 #include "oss/oss_3_0_d.h" 33 #include "oss/oss_3_0_sh_mask.h" 34 35 #include "gmc/gmc_8_1_d.h" 36 #include "gmc/gmc_8_1_sh_mask.h" 37 38 #include "gca/gfx_8_0_d.h" 39 #include "gca/gfx_8_0_enum.h" 40 #include "gca/gfx_8_0_sh_mask.h" 41 42 #include "bif/bif_5_0_d.h" 43 #include "bif/bif_5_0_sh_mask.h" 44 45 #include "tonga_sdma_pkt_open.h" 46 47 #include "ivsrcid/ivsrcid_vislands30.h" 48 49 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev); 50 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev); 51 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev); 52 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev); 53 54 MODULE_FIRMWARE("amdgpu/tonga_sdma.bin"); 55 MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin"); 56 MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin"); 57 MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin"); 58 MODULE_FIRMWARE("amdgpu/fiji_sdma.bin"); 59 MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin"); 60 MODULE_FIRMWARE("amdgpu/stoney_sdma.bin"); 61 MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin"); 62 MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin"); 63 MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin"); 64 MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin"); 65 MODULE_FIRMWARE("amdgpu/polaris12_sdma.bin"); 66 MODULE_FIRMWARE("amdgpu/polaris12_sdma1.bin"); 67 MODULE_FIRMWARE("amdgpu/vegam_sdma.bin"); 68 MODULE_FIRMWARE("amdgpu/vegam_sdma1.bin"); 69 70 71 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = 72 { 73 SDMA0_REGISTER_OFFSET, 74 SDMA1_REGISTER_OFFSET 75 }; 76 77 static const u32 golden_settings_tonga_a11[] = 78 { 79 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 80 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 81 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 82 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 83 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 84 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 85 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 86 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 87 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 88 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 89 }; 90 91 static const u32 tonga_mgcg_cgcg_init[] = 92 { 93 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 94 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 95 }; 96 97 static const u32 golden_settings_fiji_a10[] = 98 { 99 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 100 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 101 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 102 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 103 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 104 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 105 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 106 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 107 }; 108 109 static const u32 fiji_mgcg_cgcg_init[] = 110 { 111 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 112 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 113 }; 114 115 static const u32 golden_settings_polaris11_a11[] = 116 { 117 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 118 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 119 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 120 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 121 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 122 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 123 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 124 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 125 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 126 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 127 }; 128 129 static const u32 golden_settings_polaris10_a11[] = 130 { 131 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 132 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 133 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 134 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 135 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 136 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 137 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 138 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 139 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 140 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 141 }; 142 143 static const u32 cz_golden_settings_a11[] = 144 { 145 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 146 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 147 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, 148 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, 149 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, 150 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, 151 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 152 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 153 mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100, 154 mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800, 155 mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100, 156 mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100, 157 }; 158 159 static const u32 cz_mgcg_cgcg_init[] = 160 { 161 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 162 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 163 }; 164 165 static const u32 stoney_golden_settings_a11[] = 166 { 167 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, 168 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, 169 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, 170 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, 171 }; 172 173 static const u32 stoney_mgcg_cgcg_init[] = 174 { 175 mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100, 176 }; 177 178 /* 179 * sDMA - System DMA 180 * Starting with CIK, the GPU has new asynchronous 181 * DMA engines. These engines are used for compute 182 * and gfx. There are two DMA engines (SDMA0, SDMA1) 183 * and each one supports 1 ring buffer used for gfx 184 * and 2 queues used for compute. 185 * 186 * The programming model is very similar to the CP 187 * (ring buffer, IBs, etc.), but sDMA has it's own 188 * packet format that is different from the PM4 format 189 * used by the CP. sDMA supports copying data, writing 190 * embedded data, solid fills, and a number of other 191 * things. It also has support for tiling/detiling of 192 * buffers. 193 */ 194 195 static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev) 196 { 197 switch (adev->asic_type) { 198 case CHIP_FIJI: 199 amdgpu_device_program_register_sequence(adev, 200 fiji_mgcg_cgcg_init, 201 ARRAY_SIZE(fiji_mgcg_cgcg_init)); 202 amdgpu_device_program_register_sequence(adev, 203 golden_settings_fiji_a10, 204 ARRAY_SIZE(golden_settings_fiji_a10)); 205 break; 206 case CHIP_TONGA: 207 amdgpu_device_program_register_sequence(adev, 208 tonga_mgcg_cgcg_init, 209 ARRAY_SIZE(tonga_mgcg_cgcg_init)); 210 amdgpu_device_program_register_sequence(adev, 211 golden_settings_tonga_a11, 212 ARRAY_SIZE(golden_settings_tonga_a11)); 213 break; 214 case CHIP_POLARIS11: 215 case CHIP_POLARIS12: 216 case CHIP_VEGAM: 217 amdgpu_device_program_register_sequence(adev, 218 golden_settings_polaris11_a11, 219 ARRAY_SIZE(golden_settings_polaris11_a11)); 220 break; 221 case CHIP_POLARIS10: 222 amdgpu_device_program_register_sequence(adev, 223 golden_settings_polaris10_a11, 224 ARRAY_SIZE(golden_settings_polaris10_a11)); 225 break; 226 case CHIP_CARRIZO: 227 amdgpu_device_program_register_sequence(adev, 228 cz_mgcg_cgcg_init, 229 ARRAY_SIZE(cz_mgcg_cgcg_init)); 230 amdgpu_device_program_register_sequence(adev, 231 cz_golden_settings_a11, 232 ARRAY_SIZE(cz_golden_settings_a11)); 233 break; 234 case CHIP_STONEY: 235 amdgpu_device_program_register_sequence(adev, 236 stoney_mgcg_cgcg_init, 237 ARRAY_SIZE(stoney_mgcg_cgcg_init)); 238 amdgpu_device_program_register_sequence(adev, 239 stoney_golden_settings_a11, 240 ARRAY_SIZE(stoney_golden_settings_a11)); 241 break; 242 default: 243 break; 244 } 245 } 246 247 static void sdma_v3_0_free_microcode(struct amdgpu_device *adev) 248 { 249 int i; 250 for (i = 0; i < adev->sdma.num_instances; i++) { 251 release_firmware(adev->sdma.instance[i].fw); 252 adev->sdma.instance[i].fw = NULL; 253 } 254 } 255 256 /** 257 * sdma_v3_0_init_microcode - load ucode images from disk 258 * 259 * @adev: amdgpu_device pointer 260 * 261 * Use the firmware interface to load the ucode images into 262 * the driver (not loaded into hw). 263 * Returns 0 on success, error on failure. 264 */ 265 static int sdma_v3_0_init_microcode(struct amdgpu_device *adev) 266 { 267 const char *chip_name; 268 char fw_name[30]; 269 int err = 0, i; 270 struct amdgpu_firmware_info *info = NULL; 271 const struct common_firmware_header *header = NULL; 272 const struct sdma_firmware_header_v1_0 *hdr; 273 274 DRM_DEBUG("\n"); 275 276 switch (adev->asic_type) { 277 case CHIP_TONGA: 278 chip_name = "tonga"; 279 break; 280 case CHIP_FIJI: 281 chip_name = "fiji"; 282 break; 283 case CHIP_POLARIS10: 284 chip_name = "polaris10"; 285 break; 286 case CHIP_POLARIS11: 287 chip_name = "polaris11"; 288 break; 289 case CHIP_POLARIS12: 290 chip_name = "polaris12"; 291 break; 292 case CHIP_VEGAM: 293 chip_name = "vegam"; 294 break; 295 case CHIP_CARRIZO: 296 chip_name = "carrizo"; 297 break; 298 case CHIP_STONEY: 299 chip_name = "stoney"; 300 break; 301 default: BUG(); 302 } 303 304 for (i = 0; i < adev->sdma.num_instances; i++) { 305 if (i == 0) 306 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 307 else 308 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); 309 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 310 if (err) 311 goto out; 312 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); 313 if (err) 314 goto out; 315 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 316 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 317 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 318 if (adev->sdma.instance[i].feature_version >= 20) 319 adev->sdma.instance[i].burst_nop = true; 320 321 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 322 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 323 info->fw = adev->sdma.instance[i].fw; 324 header = (const struct common_firmware_header *)info->fw->data; 325 adev->firmware.fw_size += 326 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 327 328 } 329 out: 330 if (err) { 331 pr_err("sdma_v3_0: Failed to load firmware \"%s\"\n", fw_name); 332 for (i = 0; i < adev->sdma.num_instances; i++) { 333 release_firmware(adev->sdma.instance[i].fw); 334 adev->sdma.instance[i].fw = NULL; 335 } 336 } 337 return err; 338 } 339 340 /** 341 * sdma_v3_0_ring_get_rptr - get the current read pointer 342 * 343 * @ring: amdgpu ring pointer 344 * 345 * Get the current rptr from the hardware (VI+). 346 */ 347 static uint64_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring) 348 { 349 /* XXX check if swapping is necessary on BE */ 350 return ring->adev->wb.wb[ring->rptr_offs] >> 2; 351 } 352 353 /** 354 * sdma_v3_0_ring_get_wptr - get the current write pointer 355 * 356 * @ring: amdgpu ring pointer 357 * 358 * Get the current wptr from the hardware (VI+). 359 */ 360 static uint64_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring) 361 { 362 struct amdgpu_device *adev = ring->adev; 363 u32 wptr; 364 365 if (ring->use_doorbell || ring->use_pollmem) { 366 /* XXX check if swapping is necessary on BE */ 367 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2; 368 } else { 369 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2; 370 } 371 372 return wptr; 373 } 374 375 /** 376 * sdma_v3_0_ring_set_wptr - commit the write pointer 377 * 378 * @ring: amdgpu ring pointer 379 * 380 * Write the wptr back to the hardware (VI+). 381 */ 382 static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring) 383 { 384 struct amdgpu_device *adev = ring->adev; 385 386 if (ring->use_doorbell) { 387 u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs]; 388 /* XXX check if swapping is necessary on BE */ 389 WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2)); 390 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr) << 2); 391 } else if (ring->use_pollmem) { 392 u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs]; 393 394 WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2)); 395 } else { 396 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2); 397 } 398 } 399 400 static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 401 { 402 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 403 int i; 404 405 for (i = 0; i < count; i++) 406 if (sdma && sdma->burst_nop && (i == 0)) 407 amdgpu_ring_write(ring, ring->funcs->nop | 408 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 409 else 410 amdgpu_ring_write(ring, ring->funcs->nop); 411 } 412 413 /** 414 * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine 415 * 416 * @ring: amdgpu ring pointer 417 * @ib: IB object to schedule 418 * 419 * Schedule an IB in the DMA ring (VI). 420 */ 421 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring, 422 struct amdgpu_job *job, 423 struct amdgpu_ib *ib, 424 uint32_t flags) 425 { 426 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 427 428 /* IB packet must end on a 8 DW boundary */ 429 sdma_v3_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8); 430 431 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 432 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 433 /* base must be 32 byte aligned */ 434 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 435 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 436 amdgpu_ring_write(ring, ib->length_dw); 437 amdgpu_ring_write(ring, 0); 438 amdgpu_ring_write(ring, 0); 439 440 } 441 442 /** 443 * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 444 * 445 * @ring: amdgpu ring pointer 446 * 447 * Emit an hdp flush packet on the requested DMA ring. 448 */ 449 static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 450 { 451 u32 ref_and_mask = 0; 452 453 if (ring->me == 0) 454 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); 455 else 456 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); 457 458 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 459 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 460 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 461 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); 462 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); 463 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 464 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 465 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 466 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 467 } 468 469 /** 470 * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring 471 * 472 * @ring: amdgpu ring pointer 473 * @fence: amdgpu fence object 474 * 475 * Add a DMA fence packet to the ring to write 476 * the fence seq number and DMA trap packet to generate 477 * an interrupt if needed (VI). 478 */ 479 static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 480 unsigned flags) 481 { 482 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 483 /* write the fence */ 484 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 485 amdgpu_ring_write(ring, lower_32_bits(addr)); 486 amdgpu_ring_write(ring, upper_32_bits(addr)); 487 amdgpu_ring_write(ring, lower_32_bits(seq)); 488 489 /* optionally write high bits as well */ 490 if (write64bit) { 491 addr += 4; 492 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 493 amdgpu_ring_write(ring, lower_32_bits(addr)); 494 amdgpu_ring_write(ring, upper_32_bits(addr)); 495 amdgpu_ring_write(ring, upper_32_bits(seq)); 496 } 497 498 /* generate an interrupt */ 499 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 500 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 501 } 502 503 /** 504 * sdma_v3_0_gfx_stop - stop the gfx async dma engines 505 * 506 * @adev: amdgpu_device pointer 507 * 508 * Stop the gfx async dma ring buffers (VI). 509 */ 510 static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev) 511 { 512 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 513 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 514 u32 rb_cntl, ib_cntl; 515 int i; 516 517 if ((adev->mman.buffer_funcs_ring == sdma0) || 518 (adev->mman.buffer_funcs_ring == sdma1)) 519 amdgpu_ttm_set_buffer_funcs_status(adev, false); 520 521 for (i = 0; i < adev->sdma.num_instances; i++) { 522 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 523 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 524 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 525 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 526 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 527 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 528 } 529 sdma0->sched.ready = false; 530 sdma1->sched.ready = false; 531 } 532 533 /** 534 * sdma_v3_0_rlc_stop - stop the compute async dma engines 535 * 536 * @adev: amdgpu_device pointer 537 * 538 * Stop the compute async dma queues (VI). 539 */ 540 static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev) 541 { 542 /* XXX todo */ 543 } 544 545 /** 546 * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch 547 * 548 * @adev: amdgpu_device pointer 549 * @enable: enable/disable the DMA MEs context switch. 550 * 551 * Halt or unhalt the async dma engines context switch (VI). 552 */ 553 static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 554 { 555 u32 f32_cntl, phase_quantum = 0; 556 int i; 557 558 if (amdgpu_sdma_phase_quantum) { 559 unsigned value = amdgpu_sdma_phase_quantum; 560 unsigned unit = 0; 561 562 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 563 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 564 value = (value + 1) >> 1; 565 unit++; 566 } 567 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 568 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 569 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 570 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 571 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 572 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 573 WARN_ONCE(1, 574 "clamping sdma_phase_quantum to %uK clock cycles\n", 575 value << unit); 576 } 577 phase_quantum = 578 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 579 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 580 } 581 582 for (i = 0; i < adev->sdma.num_instances; i++) { 583 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); 584 if (enable) { 585 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 586 AUTO_CTXSW_ENABLE, 1); 587 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 588 ATC_L1_ENABLE, 1); 589 if (amdgpu_sdma_phase_quantum) { 590 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i], 591 phase_quantum); 592 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i], 593 phase_quantum); 594 } 595 } else { 596 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 597 AUTO_CTXSW_ENABLE, 0); 598 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 599 ATC_L1_ENABLE, 1); 600 } 601 602 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); 603 } 604 } 605 606 /** 607 * sdma_v3_0_enable - stop the async dma engines 608 * 609 * @adev: amdgpu_device pointer 610 * @enable: enable/disable the DMA MEs. 611 * 612 * Halt or unhalt the async dma engines (VI). 613 */ 614 static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable) 615 { 616 u32 f32_cntl; 617 int i; 618 619 if (!enable) { 620 sdma_v3_0_gfx_stop(adev); 621 sdma_v3_0_rlc_stop(adev); 622 } 623 624 for (i = 0; i < adev->sdma.num_instances; i++) { 625 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); 626 if (enable) 627 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); 628 else 629 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); 630 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); 631 } 632 } 633 634 /** 635 * sdma_v3_0_gfx_resume - setup and start the async dma engines 636 * 637 * @adev: amdgpu_device pointer 638 * 639 * Set up the gfx DMA ring buffers and enable them (VI). 640 * Returns 0 for success, error for failure. 641 */ 642 static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) 643 { 644 struct amdgpu_ring *ring; 645 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 646 u32 rb_bufsz; 647 u32 wb_offset; 648 u32 doorbell; 649 u64 wptr_gpu_addr; 650 int i, j, r; 651 652 for (i = 0; i < adev->sdma.num_instances; i++) { 653 ring = &adev->sdma.instance[i].ring; 654 amdgpu_ring_clear_ring(ring); 655 wb_offset = (ring->rptr_offs * 4); 656 657 mutex_lock(&adev->srbm_mutex); 658 for (j = 0; j < 16; j++) { 659 vi_srbm_select(adev, 0, 0, 0, j); 660 /* SDMA GFX */ 661 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); 662 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); 663 } 664 vi_srbm_select(adev, 0, 0, 0, 0); 665 mutex_unlock(&adev->srbm_mutex); 666 667 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], 668 adev->gfx.config.gb_addr_config & 0x70); 669 670 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); 671 672 /* Set ring buffer size in dwords */ 673 rb_bufsz = order_base_2(ring->ring_size / 4); 674 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 675 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 676 #ifdef __BIG_ENDIAN 677 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 678 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 679 RPTR_WRITEBACK_SWAP_ENABLE, 1); 680 #endif 681 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 682 683 /* Initialize the ring buffer's read and write pointers */ 684 ring->wptr = 0; 685 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); 686 sdma_v3_0_ring_set_wptr(ring); 687 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); 688 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); 689 690 /* set the wb address whether it's enabled or not */ 691 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], 692 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 693 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], 694 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 695 696 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 697 698 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); 699 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); 700 701 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]); 702 703 if (ring->use_doorbell) { 704 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, 705 OFFSET, ring->doorbell_index); 706 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 707 } else { 708 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 709 } 710 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell); 711 712 /* setup the wptr shadow polling */ 713 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 714 715 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i], 716 lower_32_bits(wptr_gpu_addr)); 717 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i], 718 upper_32_bits(wptr_gpu_addr)); 719 wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]); 720 if (ring->use_pollmem) { 721 /*wptr polling is not enogh fast, directly clean the wptr register */ 722 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); 723 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 724 SDMA0_GFX_RB_WPTR_POLL_CNTL, 725 ENABLE, 1); 726 } else { 727 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 728 SDMA0_GFX_RB_WPTR_POLL_CNTL, 729 ENABLE, 0); 730 } 731 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i], wptr_poll_cntl); 732 733 /* enable DMA RB */ 734 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 735 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 736 737 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 738 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 739 #ifdef __BIG_ENDIAN 740 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 741 #endif 742 /* enable DMA IBs */ 743 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 744 745 ring->sched.ready = true; 746 } 747 748 /* unhalt the MEs */ 749 sdma_v3_0_enable(adev, true); 750 /* enable sdma ring preemption */ 751 sdma_v3_0_ctx_switch_enable(adev, true); 752 753 for (i = 0; i < adev->sdma.num_instances; i++) { 754 ring = &adev->sdma.instance[i].ring; 755 r = amdgpu_ring_test_helper(ring); 756 if (r) 757 return r; 758 759 if (adev->mman.buffer_funcs_ring == ring) 760 amdgpu_ttm_set_buffer_funcs_status(adev, true); 761 } 762 763 return 0; 764 } 765 766 /** 767 * sdma_v3_0_rlc_resume - setup and start the async dma engines 768 * 769 * @adev: amdgpu_device pointer 770 * 771 * Set up the compute DMA queues and enable them (VI). 772 * Returns 0 for success, error for failure. 773 */ 774 static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev) 775 { 776 /* XXX todo */ 777 return 0; 778 } 779 780 /** 781 * sdma_v3_0_start - setup and start the async dma engines 782 * 783 * @adev: amdgpu_device pointer 784 * 785 * Set up the DMA engines and enable them (VI). 786 * Returns 0 for success, error for failure. 787 */ 788 static int sdma_v3_0_start(struct amdgpu_device *adev) 789 { 790 int r; 791 792 /* disable sdma engine before programing it */ 793 sdma_v3_0_ctx_switch_enable(adev, false); 794 sdma_v3_0_enable(adev, false); 795 796 /* start the gfx rings and rlc compute queues */ 797 r = sdma_v3_0_gfx_resume(adev); 798 if (r) 799 return r; 800 r = sdma_v3_0_rlc_resume(adev); 801 if (r) 802 return r; 803 804 return 0; 805 } 806 807 /** 808 * sdma_v3_0_ring_test_ring - simple async dma engine test 809 * 810 * @ring: amdgpu_ring structure holding ring information 811 * 812 * Test the DMA engine by writing using it to write an 813 * value to memory. (VI). 814 * Returns 0 for success, error for failure. 815 */ 816 static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring) 817 { 818 struct amdgpu_device *adev = ring->adev; 819 unsigned i; 820 unsigned index; 821 int r; 822 u32 tmp; 823 u64 gpu_addr; 824 825 r = amdgpu_device_wb_get(adev, &index); 826 if (r) 827 return r; 828 829 gpu_addr = adev->wb.gpu_addr + (index * 4); 830 tmp = 0xCAFEDEAD; 831 adev->wb.wb[index] = cpu_to_le32(tmp); 832 833 r = amdgpu_ring_alloc(ring, 5); 834 if (r) 835 goto error_free_wb; 836 837 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 838 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 839 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 840 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 841 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); 842 amdgpu_ring_write(ring, 0xDEADBEEF); 843 amdgpu_ring_commit(ring); 844 845 for (i = 0; i < adev->usec_timeout; i++) { 846 tmp = le32_to_cpu(adev->wb.wb[index]); 847 if (tmp == 0xDEADBEEF) 848 break; 849 DRM_UDELAY(1); 850 } 851 852 if (i >= adev->usec_timeout) 853 r = -ETIMEDOUT; 854 855 error_free_wb: 856 amdgpu_device_wb_free(adev, index); 857 return r; 858 } 859 860 /** 861 * sdma_v3_0_ring_test_ib - test an IB on the DMA engine 862 * 863 * @ring: amdgpu_ring structure holding ring information 864 * 865 * Test a simple IB in the DMA ring (VI). 866 * Returns 0 on success, error on failure. 867 */ 868 static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 869 { 870 struct amdgpu_device *adev = ring->adev; 871 struct amdgpu_ib ib; 872 struct dma_fence *f = NULL; 873 unsigned index; 874 u32 tmp = 0; 875 u64 gpu_addr; 876 long r; 877 878 r = amdgpu_device_wb_get(adev, &index); 879 if (r) 880 return r; 881 882 gpu_addr = adev->wb.gpu_addr + (index * 4); 883 tmp = 0xCAFEDEAD; 884 adev->wb.wb[index] = cpu_to_le32(tmp); 885 memset(&ib, 0, sizeof(ib)); 886 r = amdgpu_ib_get(adev, NULL, 256, &ib); 887 if (r) 888 goto err0; 889 890 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 891 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 892 ib.ptr[1] = lower_32_bits(gpu_addr); 893 ib.ptr[2] = upper_32_bits(gpu_addr); 894 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1); 895 ib.ptr[4] = 0xDEADBEEF; 896 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 897 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 898 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 899 ib.length_dw = 8; 900 901 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 902 if (r) 903 goto err1; 904 905 r = dma_fence_wait_timeout(f, false, timeout); 906 if (r == 0) { 907 r = -ETIMEDOUT; 908 goto err1; 909 } else if (r < 0) { 910 goto err1; 911 } 912 tmp = le32_to_cpu(adev->wb.wb[index]); 913 if (tmp == 0xDEADBEEF) 914 r = 0; 915 else 916 r = -EINVAL; 917 err1: 918 amdgpu_ib_free(adev, &ib, NULL); 919 dma_fence_put(f); 920 err0: 921 amdgpu_device_wb_free(adev, index); 922 return r; 923 } 924 925 /** 926 * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART 927 * 928 * @ib: indirect buffer to fill with commands 929 * @pe: addr of the page entry 930 * @src: src addr to copy from 931 * @count: number of page entries to update 932 * 933 * Update PTEs by copying them from the GART using sDMA (CIK). 934 */ 935 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib, 936 uint64_t pe, uint64_t src, 937 unsigned count) 938 { 939 unsigned bytes = count * 8; 940 941 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 942 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 943 ib->ptr[ib->length_dw++] = bytes; 944 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 945 ib->ptr[ib->length_dw++] = lower_32_bits(src); 946 ib->ptr[ib->length_dw++] = upper_32_bits(src); 947 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 948 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 949 } 950 951 /** 952 * sdma_v3_0_vm_write_pte - update PTEs by writing them manually 953 * 954 * @ib: indirect buffer to fill with commands 955 * @pe: addr of the page entry 956 * @value: dst addr to write into pe 957 * @count: number of page entries to update 958 * @incr: increase next addr by incr bytes 959 * 960 * Update PTEs by writing them manually using sDMA (CIK). 961 */ 962 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 963 uint64_t value, unsigned count, 964 uint32_t incr) 965 { 966 unsigned ndw = count * 2; 967 968 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 969 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 970 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 971 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 972 ib->ptr[ib->length_dw++] = ndw; 973 for (; ndw > 0; ndw -= 2) { 974 ib->ptr[ib->length_dw++] = lower_32_bits(value); 975 ib->ptr[ib->length_dw++] = upper_32_bits(value); 976 value += incr; 977 } 978 } 979 980 /** 981 * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA 982 * 983 * @ib: indirect buffer to fill with commands 984 * @pe: addr of the page entry 985 * @addr: dst addr to write into pe 986 * @count: number of page entries to update 987 * @incr: increase next addr by incr bytes 988 * @flags: access flags 989 * 990 * Update the page tables using sDMA (CIK). 991 */ 992 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe, 993 uint64_t addr, unsigned count, 994 uint32_t incr, uint64_t flags) 995 { 996 /* for physically contiguous pages (vram) */ 997 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE); 998 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 999 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1000 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1001 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1002 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1003 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1004 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1005 ib->ptr[ib->length_dw++] = 0; 1006 ib->ptr[ib->length_dw++] = count; /* number of entries */ 1007 } 1008 1009 /** 1010 * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw 1011 * 1012 * @ib: indirect buffer to fill with padding 1013 * 1014 */ 1015 static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1016 { 1017 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1018 u32 pad_count; 1019 int i; 1020 1021 pad_count = (8 - (ib->length_dw & 0x7)) % 8; 1022 for (i = 0; i < pad_count; i++) 1023 if (sdma && sdma->burst_nop && (i == 0)) 1024 ib->ptr[ib->length_dw++] = 1025 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1026 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1027 else 1028 ib->ptr[ib->length_dw++] = 1029 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1030 } 1031 1032 /** 1033 * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline 1034 * 1035 * @ring: amdgpu_ring pointer 1036 * 1037 * Make sure all previous operations are completed (CIK). 1038 */ 1039 static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1040 { 1041 uint32_t seq = ring->fence_drv.sync_seq; 1042 uint64_t addr = ring->fence_drv.gpu_addr; 1043 1044 /* wait for idle */ 1045 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1046 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1047 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1048 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1049 amdgpu_ring_write(ring, addr & 0xfffffffc); 1050 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1051 amdgpu_ring_write(ring, seq); /* reference */ 1052 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1053 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1054 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1055 } 1056 1057 /** 1058 * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA 1059 * 1060 * @ring: amdgpu_ring pointer 1061 * @vm: amdgpu_vm pointer 1062 * 1063 * Update the page table base and flush the VM TLB 1064 * using sDMA (VI). 1065 */ 1066 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1067 unsigned vmid, uint64_t pd_addr) 1068 { 1069 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1070 1071 /* wait for flush */ 1072 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1073 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1074 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */ 1075 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); 1076 amdgpu_ring_write(ring, 0); 1077 amdgpu_ring_write(ring, 0); /* reference */ 1078 amdgpu_ring_write(ring, 0); /* mask */ 1079 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1080 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 1081 } 1082 1083 static void sdma_v3_0_ring_emit_wreg(struct amdgpu_ring *ring, 1084 uint32_t reg, uint32_t val) 1085 { 1086 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1087 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1088 amdgpu_ring_write(ring, reg); 1089 amdgpu_ring_write(ring, val); 1090 } 1091 1092 static int sdma_v3_0_early_init(void *handle) 1093 { 1094 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1095 1096 switch (adev->asic_type) { 1097 case CHIP_STONEY: 1098 adev->sdma.num_instances = 1; 1099 break; 1100 default: 1101 adev->sdma.num_instances = SDMA_MAX_INSTANCE; 1102 break; 1103 } 1104 1105 sdma_v3_0_set_ring_funcs(adev); 1106 sdma_v3_0_set_buffer_funcs(adev); 1107 sdma_v3_0_set_vm_pte_funcs(adev); 1108 sdma_v3_0_set_irq_funcs(adev); 1109 1110 return 0; 1111 } 1112 1113 static int sdma_v3_0_sw_init(void *handle) 1114 { 1115 struct amdgpu_ring *ring; 1116 int r, i; 1117 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1118 1119 /* SDMA trap event */ 1120 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP, 1121 &adev->sdma.trap_irq); 1122 if (r) 1123 return r; 1124 1125 /* SDMA Privileged inst */ 1126 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 241, 1127 &adev->sdma.illegal_inst_irq); 1128 if (r) 1129 return r; 1130 1131 /* SDMA Privileged inst */ 1132 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE, 1133 &adev->sdma.illegal_inst_irq); 1134 if (r) 1135 return r; 1136 1137 r = sdma_v3_0_init_microcode(adev); 1138 if (r) { 1139 DRM_ERROR("Failed to load sdma firmware!\n"); 1140 return r; 1141 } 1142 1143 for (i = 0; i < adev->sdma.num_instances; i++) { 1144 ring = &adev->sdma.instance[i].ring; 1145 ring->ring_obj = NULL; 1146 if (!amdgpu_sriov_vf(adev)) { 1147 ring->use_doorbell = true; 1148 ring->doorbell_index = adev->doorbell_index.sdma_engine[i]; 1149 } else { 1150 ring->use_pollmem = true; 1151 } 1152 1153 sprintf(ring->name, "sdma%d", i); 1154 r = amdgpu_ring_init(adev, ring, 1024, 1155 &adev->sdma.trap_irq, 1156 (i == 0) ? 1157 AMDGPU_SDMA_IRQ_INSTANCE0 : 1158 AMDGPU_SDMA_IRQ_INSTANCE1); 1159 if (r) 1160 return r; 1161 } 1162 1163 return r; 1164 } 1165 1166 static int sdma_v3_0_sw_fini(void *handle) 1167 { 1168 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1169 int i; 1170 1171 for (i = 0; i < adev->sdma.num_instances; i++) 1172 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1173 1174 sdma_v3_0_free_microcode(adev); 1175 return 0; 1176 } 1177 1178 static int sdma_v3_0_hw_init(void *handle) 1179 { 1180 int r; 1181 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1182 1183 sdma_v3_0_init_golden_registers(adev); 1184 1185 r = sdma_v3_0_start(adev); 1186 if (r) 1187 return r; 1188 1189 return r; 1190 } 1191 1192 static int sdma_v3_0_hw_fini(void *handle) 1193 { 1194 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1195 1196 sdma_v3_0_ctx_switch_enable(adev, false); 1197 sdma_v3_0_enable(adev, false); 1198 1199 return 0; 1200 } 1201 1202 static int sdma_v3_0_suspend(void *handle) 1203 { 1204 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1205 1206 return sdma_v3_0_hw_fini(adev); 1207 } 1208 1209 static int sdma_v3_0_resume(void *handle) 1210 { 1211 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1212 1213 return sdma_v3_0_hw_init(adev); 1214 } 1215 1216 static bool sdma_v3_0_is_idle(void *handle) 1217 { 1218 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1219 u32 tmp = RREG32(mmSRBM_STATUS2); 1220 1221 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | 1222 SRBM_STATUS2__SDMA1_BUSY_MASK)) 1223 return false; 1224 1225 return true; 1226 } 1227 1228 static int sdma_v3_0_wait_for_idle(void *handle) 1229 { 1230 unsigned i; 1231 u32 tmp; 1232 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1233 1234 for (i = 0; i < adev->usec_timeout; i++) { 1235 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | 1236 SRBM_STATUS2__SDMA1_BUSY_MASK); 1237 1238 if (!tmp) 1239 return 0; 1240 udelay(1); 1241 } 1242 return -ETIMEDOUT; 1243 } 1244 1245 static bool sdma_v3_0_check_soft_reset(void *handle) 1246 { 1247 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1248 u32 srbm_soft_reset = 0; 1249 u32 tmp = RREG32(mmSRBM_STATUS2); 1250 1251 if ((tmp & SRBM_STATUS2__SDMA_BUSY_MASK) || 1252 (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)) { 1253 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK; 1254 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK; 1255 } 1256 1257 if (srbm_soft_reset) { 1258 adev->sdma.srbm_soft_reset = srbm_soft_reset; 1259 return true; 1260 } else { 1261 adev->sdma.srbm_soft_reset = 0; 1262 return false; 1263 } 1264 } 1265 1266 static int sdma_v3_0_pre_soft_reset(void *handle) 1267 { 1268 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1269 u32 srbm_soft_reset = 0; 1270 1271 if (!adev->sdma.srbm_soft_reset) 1272 return 0; 1273 1274 srbm_soft_reset = adev->sdma.srbm_soft_reset; 1275 1276 if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) || 1277 REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) { 1278 sdma_v3_0_ctx_switch_enable(adev, false); 1279 sdma_v3_0_enable(adev, false); 1280 } 1281 1282 return 0; 1283 } 1284 1285 static int sdma_v3_0_post_soft_reset(void *handle) 1286 { 1287 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1288 u32 srbm_soft_reset = 0; 1289 1290 if (!adev->sdma.srbm_soft_reset) 1291 return 0; 1292 1293 srbm_soft_reset = adev->sdma.srbm_soft_reset; 1294 1295 if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) || 1296 REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) { 1297 sdma_v3_0_gfx_resume(adev); 1298 sdma_v3_0_rlc_resume(adev); 1299 } 1300 1301 return 0; 1302 } 1303 1304 static int sdma_v3_0_soft_reset(void *handle) 1305 { 1306 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1307 u32 srbm_soft_reset = 0; 1308 u32 tmp; 1309 1310 if (!adev->sdma.srbm_soft_reset) 1311 return 0; 1312 1313 srbm_soft_reset = adev->sdma.srbm_soft_reset; 1314 1315 if (srbm_soft_reset) { 1316 tmp = RREG32(mmSRBM_SOFT_RESET); 1317 tmp |= srbm_soft_reset; 1318 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1319 WREG32(mmSRBM_SOFT_RESET, tmp); 1320 tmp = RREG32(mmSRBM_SOFT_RESET); 1321 1322 udelay(50); 1323 1324 tmp &= ~srbm_soft_reset; 1325 WREG32(mmSRBM_SOFT_RESET, tmp); 1326 tmp = RREG32(mmSRBM_SOFT_RESET); 1327 1328 /* Wait a little for things to settle down */ 1329 udelay(50); 1330 } 1331 1332 return 0; 1333 } 1334 1335 static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev, 1336 struct amdgpu_irq_src *source, 1337 unsigned type, 1338 enum amdgpu_interrupt_state state) 1339 { 1340 u32 sdma_cntl; 1341 1342 switch (type) { 1343 case AMDGPU_SDMA_IRQ_INSTANCE0: 1344 switch (state) { 1345 case AMDGPU_IRQ_STATE_DISABLE: 1346 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1347 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1348 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1349 break; 1350 case AMDGPU_IRQ_STATE_ENABLE: 1351 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1352 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1353 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1354 break; 1355 default: 1356 break; 1357 } 1358 break; 1359 case AMDGPU_SDMA_IRQ_INSTANCE1: 1360 switch (state) { 1361 case AMDGPU_IRQ_STATE_DISABLE: 1362 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1363 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1364 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1365 break; 1366 case AMDGPU_IRQ_STATE_ENABLE: 1367 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1368 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1369 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1370 break; 1371 default: 1372 break; 1373 } 1374 break; 1375 default: 1376 break; 1377 } 1378 return 0; 1379 } 1380 1381 static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev, 1382 struct amdgpu_irq_src *source, 1383 struct amdgpu_iv_entry *entry) 1384 { 1385 u8 instance_id, queue_id; 1386 1387 instance_id = (entry->ring_id & 0x3) >> 0; 1388 queue_id = (entry->ring_id & 0xc) >> 2; 1389 DRM_DEBUG("IH: SDMA trap\n"); 1390 switch (instance_id) { 1391 case 0: 1392 switch (queue_id) { 1393 case 0: 1394 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1395 break; 1396 case 1: 1397 /* XXX compute */ 1398 break; 1399 case 2: 1400 /* XXX compute */ 1401 break; 1402 } 1403 break; 1404 case 1: 1405 switch (queue_id) { 1406 case 0: 1407 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1408 break; 1409 case 1: 1410 /* XXX compute */ 1411 break; 1412 case 2: 1413 /* XXX compute */ 1414 break; 1415 } 1416 break; 1417 } 1418 return 0; 1419 } 1420 1421 static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1422 struct amdgpu_irq_src *source, 1423 struct amdgpu_iv_entry *entry) 1424 { 1425 u8 instance_id, queue_id; 1426 1427 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1428 instance_id = (entry->ring_id & 0x3) >> 0; 1429 queue_id = (entry->ring_id & 0xc) >> 2; 1430 1431 if (instance_id <= 1 && queue_id == 0) 1432 drm_sched_fault(&adev->sdma.instance[instance_id].ring.sched); 1433 return 0; 1434 } 1435 1436 static void sdma_v3_0_update_sdma_medium_grain_clock_gating( 1437 struct amdgpu_device *adev, 1438 bool enable) 1439 { 1440 uint32_t temp, data; 1441 int i; 1442 1443 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1444 for (i = 0; i < adev->sdma.num_instances; i++) { 1445 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]); 1446 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1447 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1448 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1449 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1450 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1451 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1452 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1453 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1454 if (data != temp) 1455 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); 1456 } 1457 } else { 1458 for (i = 0; i < adev->sdma.num_instances; i++) { 1459 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]); 1460 data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1461 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1462 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1463 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1464 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1465 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1466 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1467 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK; 1468 1469 if (data != temp) 1470 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); 1471 } 1472 } 1473 } 1474 1475 static void sdma_v3_0_update_sdma_medium_grain_light_sleep( 1476 struct amdgpu_device *adev, 1477 bool enable) 1478 { 1479 uint32_t temp, data; 1480 int i; 1481 1482 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1483 for (i = 0; i < adev->sdma.num_instances; i++) { 1484 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); 1485 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1486 1487 if (temp != data) 1488 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); 1489 } 1490 } else { 1491 for (i = 0; i < adev->sdma.num_instances; i++) { 1492 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); 1493 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1494 1495 if (temp != data) 1496 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); 1497 } 1498 } 1499 } 1500 1501 static int sdma_v3_0_set_clockgating_state(void *handle, 1502 enum amd_clockgating_state state) 1503 { 1504 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1505 1506 if (amdgpu_sriov_vf(adev)) 1507 return 0; 1508 1509 switch (adev->asic_type) { 1510 case CHIP_FIJI: 1511 case CHIP_CARRIZO: 1512 case CHIP_STONEY: 1513 sdma_v3_0_update_sdma_medium_grain_clock_gating(adev, 1514 state == AMD_CG_STATE_GATE); 1515 sdma_v3_0_update_sdma_medium_grain_light_sleep(adev, 1516 state == AMD_CG_STATE_GATE); 1517 break; 1518 default: 1519 break; 1520 } 1521 return 0; 1522 } 1523 1524 static int sdma_v3_0_set_powergating_state(void *handle, 1525 enum amd_powergating_state state) 1526 { 1527 return 0; 1528 } 1529 1530 static void sdma_v3_0_get_clockgating_state(void *handle, u32 *flags) 1531 { 1532 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1533 int data; 1534 1535 if (amdgpu_sriov_vf(adev)) 1536 *flags = 0; 1537 1538 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1539 data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[0]); 1540 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK)) 1541 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1542 1543 /* AMD_CG_SUPPORT_SDMA_LS */ 1544 data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[0]); 1545 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1546 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1547 } 1548 1549 static const struct amd_ip_funcs sdma_v3_0_ip_funcs = { 1550 .name = "sdma_v3_0", 1551 .early_init = sdma_v3_0_early_init, 1552 .late_init = NULL, 1553 .sw_init = sdma_v3_0_sw_init, 1554 .sw_fini = sdma_v3_0_sw_fini, 1555 .hw_init = sdma_v3_0_hw_init, 1556 .hw_fini = sdma_v3_0_hw_fini, 1557 .suspend = sdma_v3_0_suspend, 1558 .resume = sdma_v3_0_resume, 1559 .is_idle = sdma_v3_0_is_idle, 1560 .wait_for_idle = sdma_v3_0_wait_for_idle, 1561 .check_soft_reset = sdma_v3_0_check_soft_reset, 1562 .pre_soft_reset = sdma_v3_0_pre_soft_reset, 1563 .post_soft_reset = sdma_v3_0_post_soft_reset, 1564 .soft_reset = sdma_v3_0_soft_reset, 1565 .set_clockgating_state = sdma_v3_0_set_clockgating_state, 1566 .set_powergating_state = sdma_v3_0_set_powergating_state, 1567 .get_clockgating_state = sdma_v3_0_get_clockgating_state, 1568 }; 1569 1570 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { 1571 .type = AMDGPU_RING_TYPE_SDMA, 1572 .align_mask = 0xf, 1573 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1574 .support_64bit_ptrs = false, 1575 .get_rptr = sdma_v3_0_ring_get_rptr, 1576 .get_wptr = sdma_v3_0_ring_get_wptr, 1577 .set_wptr = sdma_v3_0_ring_set_wptr, 1578 .emit_frame_size = 1579 6 + /* sdma_v3_0_ring_emit_hdp_flush */ 1580 3 + /* hdp invalidate */ 1581 6 + /* sdma_v3_0_ring_emit_pipeline_sync */ 1582 VI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v3_0_ring_emit_vm_flush */ 1583 10 + 10 + 10, /* sdma_v3_0_ring_emit_fence x3 for user fence, vm fence */ 1584 .emit_ib_size = 7 + 6, /* sdma_v3_0_ring_emit_ib */ 1585 .emit_ib = sdma_v3_0_ring_emit_ib, 1586 .emit_fence = sdma_v3_0_ring_emit_fence, 1587 .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync, 1588 .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush, 1589 .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush, 1590 .test_ring = sdma_v3_0_ring_test_ring, 1591 .test_ib = sdma_v3_0_ring_test_ib, 1592 .insert_nop = sdma_v3_0_ring_insert_nop, 1593 .pad_ib = sdma_v3_0_ring_pad_ib, 1594 .emit_wreg = sdma_v3_0_ring_emit_wreg, 1595 }; 1596 1597 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev) 1598 { 1599 int i; 1600 1601 for (i = 0; i < adev->sdma.num_instances; i++) { 1602 adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs; 1603 adev->sdma.instance[i].ring.me = i; 1604 } 1605 } 1606 1607 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = { 1608 .set = sdma_v3_0_set_trap_irq_state, 1609 .process = sdma_v3_0_process_trap_irq, 1610 }; 1611 1612 static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = { 1613 .process = sdma_v3_0_process_illegal_inst_irq, 1614 }; 1615 1616 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev) 1617 { 1618 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 1619 adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs; 1620 adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs; 1621 } 1622 1623 /** 1624 * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine 1625 * 1626 * @ring: amdgpu_ring structure holding ring information 1627 * @src_offset: src GPU address 1628 * @dst_offset: dst GPU address 1629 * @byte_count: number of bytes to xfer 1630 * 1631 * Copy GPU buffers using the DMA engine (VI). 1632 * Used by the amdgpu ttm implementation to move pages if 1633 * registered as the asic copy callback. 1634 */ 1635 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib, 1636 uint64_t src_offset, 1637 uint64_t dst_offset, 1638 uint32_t byte_count) 1639 { 1640 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1641 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1642 ib->ptr[ib->length_dw++] = byte_count; 1643 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1644 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1645 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1646 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1647 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1648 } 1649 1650 /** 1651 * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine 1652 * 1653 * @ring: amdgpu_ring structure holding ring information 1654 * @src_data: value to write to buffer 1655 * @dst_offset: dst GPU address 1656 * @byte_count: number of bytes to xfer 1657 * 1658 * Fill GPU buffers using the DMA engine (VI). 1659 */ 1660 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib, 1661 uint32_t src_data, 1662 uint64_t dst_offset, 1663 uint32_t byte_count) 1664 { 1665 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1666 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1667 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1668 ib->ptr[ib->length_dw++] = src_data; 1669 ib->ptr[ib->length_dw++] = byte_count; 1670 } 1671 1672 static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = { 1673 .copy_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */ 1674 .copy_num_dw = 7, 1675 .emit_copy_buffer = sdma_v3_0_emit_copy_buffer, 1676 1677 .fill_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */ 1678 .fill_num_dw = 5, 1679 .emit_fill_buffer = sdma_v3_0_emit_fill_buffer, 1680 }; 1681 1682 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev) 1683 { 1684 adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs; 1685 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1686 } 1687 1688 static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = { 1689 .copy_pte_num_dw = 7, 1690 .copy_pte = sdma_v3_0_vm_copy_pte, 1691 1692 .write_pte = sdma_v3_0_vm_write_pte, 1693 .set_pte_pde = sdma_v3_0_vm_set_pte_pde, 1694 }; 1695 1696 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1697 { 1698 struct drm_gpu_scheduler *sched; 1699 unsigned i; 1700 1701 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs; 1702 for (i = 0; i < adev->sdma.num_instances; i++) { 1703 sched = &adev->sdma.instance[i].ring.sched; 1704 adev->vm_manager.vm_pte_rqs[i] = 1705 &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL]; 1706 } 1707 adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances; 1708 } 1709 1710 const struct amdgpu_ip_block_version sdma_v3_0_ip_block = 1711 { 1712 .type = AMD_IP_BLOCK_TYPE_SDMA, 1713 .major = 3, 1714 .minor = 0, 1715 .rev = 0, 1716 .funcs = &sdma_v3_0_ip_funcs, 1717 }; 1718 1719 const struct amdgpu_ip_block_version sdma_v3_1_ip_block = 1720 { 1721 .type = AMD_IP_BLOCK_TYPE_SDMA, 1722 .major = 3, 1723 .minor = 1, 1724 .rev = 0, 1725 .funcs = &sdma_v3_0_ip_funcs, 1726 }; 1727