1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_ucode.h" 28 #include "amdgpu_trace.h" 29 #include "vi.h" 30 #include "vid.h" 31 32 #include "oss/oss_2_4_d.h" 33 #include "oss/oss_2_4_sh_mask.h" 34 35 #include "gmc/gmc_7_1_d.h" 36 #include "gmc/gmc_7_1_sh_mask.h" 37 38 #include "gca/gfx_8_0_d.h" 39 #include "gca/gfx_8_0_enum.h" 40 #include "gca/gfx_8_0_sh_mask.h" 41 42 #include "bif/bif_5_0_d.h" 43 #include "bif/bif_5_0_sh_mask.h" 44 45 #include "iceland_sdma_pkt_open.h" 46 47 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev); 48 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev); 49 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev); 50 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev); 51 52 MODULE_FIRMWARE("amdgpu/topaz_sdma.bin"); 53 MODULE_FIRMWARE("amdgpu/topaz_sdma1.bin"); 54 55 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = 56 { 57 SDMA0_REGISTER_OFFSET, 58 SDMA1_REGISTER_OFFSET 59 }; 60 61 static const u32 golden_settings_iceland_a11[] = 62 { 63 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 64 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 65 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 66 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 67 }; 68 69 static const u32 iceland_mgcg_cgcg_init[] = 70 { 71 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 72 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 73 }; 74 75 /* 76 * sDMA - System DMA 77 * Starting with CIK, the GPU has new asynchronous 78 * DMA engines. These engines are used for compute 79 * and gfx. There are two DMA engines (SDMA0, SDMA1) 80 * and each one supports 1 ring buffer used for gfx 81 * and 2 queues used for compute. 82 * 83 * The programming model is very similar to the CP 84 * (ring buffer, IBs, etc.), but sDMA has it's own 85 * packet format that is different from the PM4 format 86 * used by the CP. sDMA supports copying data, writing 87 * embedded data, solid fills, and a number of other 88 * things. It also has support for tiling/detiling of 89 * buffers. 90 */ 91 92 static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev) 93 { 94 switch (adev->asic_type) { 95 case CHIP_TOPAZ: 96 amdgpu_program_register_sequence(adev, 97 iceland_mgcg_cgcg_init, 98 ARRAY_SIZE(iceland_mgcg_cgcg_init)); 99 amdgpu_program_register_sequence(adev, 100 golden_settings_iceland_a11, 101 ARRAY_SIZE(golden_settings_iceland_a11)); 102 break; 103 default: 104 break; 105 } 106 } 107 108 static void sdma_v2_4_free_microcode(struct amdgpu_device *adev) 109 { 110 int i; 111 for (i = 0; i < adev->sdma.num_instances; i++) { 112 release_firmware(adev->sdma.instance[i].fw); 113 adev->sdma.instance[i].fw = NULL; 114 } 115 } 116 117 /** 118 * sdma_v2_4_init_microcode - load ucode images from disk 119 * 120 * @adev: amdgpu_device pointer 121 * 122 * Use the firmware interface to load the ucode images into 123 * the driver (not loaded into hw). 124 * Returns 0 on success, error on failure. 125 */ 126 static int sdma_v2_4_init_microcode(struct amdgpu_device *adev) 127 { 128 const char *chip_name; 129 char fw_name[30]; 130 int err = 0, i; 131 struct amdgpu_firmware_info *info = NULL; 132 const struct common_firmware_header *header = NULL; 133 const struct sdma_firmware_header_v1_0 *hdr; 134 135 DRM_DEBUG("\n"); 136 137 switch (adev->asic_type) { 138 case CHIP_TOPAZ: 139 chip_name = "topaz"; 140 break; 141 default: BUG(); 142 } 143 144 for (i = 0; i < adev->sdma.num_instances; i++) { 145 if (i == 0) 146 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 147 else 148 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); 149 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 150 if (err) 151 goto out; 152 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); 153 if (err) 154 goto out; 155 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 156 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 157 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 158 if (adev->sdma.instance[i].feature_version >= 20) 159 adev->sdma.instance[i].burst_nop = true; 160 161 if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) { 162 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 163 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 164 info->fw = adev->sdma.instance[i].fw; 165 header = (const struct common_firmware_header *)info->fw->data; 166 adev->firmware.fw_size += 167 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 168 } 169 } 170 171 out: 172 if (err) { 173 pr_err("sdma_v2_4: Failed to load firmware \"%s\"\n", fw_name); 174 for (i = 0; i < adev->sdma.num_instances; i++) { 175 release_firmware(adev->sdma.instance[i].fw); 176 adev->sdma.instance[i].fw = NULL; 177 } 178 } 179 return err; 180 } 181 182 /** 183 * sdma_v2_4_ring_get_rptr - get the current read pointer 184 * 185 * @ring: amdgpu ring pointer 186 * 187 * Get the current rptr from the hardware (VI+). 188 */ 189 static uint64_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring) 190 { 191 /* XXX check if swapping is necessary on BE */ 192 return ring->adev->wb.wb[ring->rptr_offs] >> 2; 193 } 194 195 /** 196 * sdma_v2_4_ring_get_wptr - get the current write pointer 197 * 198 * @ring: amdgpu ring pointer 199 * 200 * Get the current wptr from the hardware (VI+). 201 */ 202 static uint64_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring) 203 { 204 struct amdgpu_device *adev = ring->adev; 205 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1; 206 u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2; 207 208 return wptr; 209 } 210 211 /** 212 * sdma_v2_4_ring_set_wptr - commit the write pointer 213 * 214 * @ring: amdgpu ring pointer 215 * 216 * Write the wptr back to the hardware (VI+). 217 */ 218 static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring) 219 { 220 struct amdgpu_device *adev = ring->adev; 221 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1; 222 223 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], lower_32_bits(ring->wptr) << 2); 224 } 225 226 static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 227 { 228 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); 229 int i; 230 231 for (i = 0; i < count; i++) 232 if (sdma && sdma->burst_nop && (i == 0)) 233 amdgpu_ring_write(ring, ring->funcs->nop | 234 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 235 else 236 amdgpu_ring_write(ring, ring->funcs->nop); 237 } 238 239 /** 240 * sdma_v2_4_ring_emit_ib - Schedule an IB on the DMA engine 241 * 242 * @ring: amdgpu ring pointer 243 * @ib: IB object to schedule 244 * 245 * Schedule an IB in the DMA ring (VI). 246 */ 247 static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring, 248 struct amdgpu_ib *ib, 249 unsigned vm_id, bool ctx_switch) 250 { 251 u32 vmid = vm_id & 0xf; 252 253 /* IB packet must end on a 8 DW boundary */ 254 sdma_v2_4_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8); 255 256 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 257 SDMA_PKT_INDIRECT_HEADER_VMID(vmid)); 258 /* base must be 32 byte aligned */ 259 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 260 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 261 amdgpu_ring_write(ring, ib->length_dw); 262 amdgpu_ring_write(ring, 0); 263 amdgpu_ring_write(ring, 0); 264 265 } 266 267 /** 268 * sdma_v2_4_hdp_flush_ring_emit - emit an hdp flush on the DMA ring 269 * 270 * @ring: amdgpu ring pointer 271 * 272 * Emit an hdp flush packet on the requested DMA ring. 273 */ 274 static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring) 275 { 276 u32 ref_and_mask = 0; 277 278 if (ring == &ring->adev->sdma.instance[0].ring) 279 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); 280 else 281 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); 282 283 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 284 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 285 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 286 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); 287 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); 288 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 289 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 290 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 291 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 292 } 293 294 static void sdma_v2_4_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) 295 { 296 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 297 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 298 amdgpu_ring_write(ring, mmHDP_DEBUG0); 299 amdgpu_ring_write(ring, 1); 300 } 301 /** 302 * sdma_v2_4_ring_emit_fence - emit a fence on the DMA ring 303 * 304 * @ring: amdgpu ring pointer 305 * @fence: amdgpu fence object 306 * 307 * Add a DMA fence packet to the ring to write 308 * the fence seq number and DMA trap packet to generate 309 * an interrupt if needed (VI). 310 */ 311 static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 312 unsigned flags) 313 { 314 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 315 /* write the fence */ 316 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 317 amdgpu_ring_write(ring, lower_32_bits(addr)); 318 amdgpu_ring_write(ring, upper_32_bits(addr)); 319 amdgpu_ring_write(ring, lower_32_bits(seq)); 320 321 /* optionally write high bits as well */ 322 if (write64bit) { 323 addr += 4; 324 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 325 amdgpu_ring_write(ring, lower_32_bits(addr)); 326 amdgpu_ring_write(ring, upper_32_bits(addr)); 327 amdgpu_ring_write(ring, upper_32_bits(seq)); 328 } 329 330 /* generate an interrupt */ 331 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 332 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 333 } 334 335 /** 336 * sdma_v2_4_gfx_stop - stop the gfx async dma engines 337 * 338 * @adev: amdgpu_device pointer 339 * 340 * Stop the gfx async dma ring buffers (VI). 341 */ 342 static void sdma_v2_4_gfx_stop(struct amdgpu_device *adev) 343 { 344 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 345 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 346 u32 rb_cntl, ib_cntl; 347 int i; 348 349 if ((adev->mman.buffer_funcs_ring == sdma0) || 350 (adev->mman.buffer_funcs_ring == sdma1)) 351 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); 352 353 for (i = 0; i < adev->sdma.num_instances; i++) { 354 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 355 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 356 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 357 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 358 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 359 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 360 } 361 sdma0->ready = false; 362 sdma1->ready = false; 363 } 364 365 /** 366 * sdma_v2_4_rlc_stop - stop the compute async dma engines 367 * 368 * @adev: amdgpu_device pointer 369 * 370 * Stop the compute async dma queues (VI). 371 */ 372 static void sdma_v2_4_rlc_stop(struct amdgpu_device *adev) 373 { 374 /* XXX todo */ 375 } 376 377 /** 378 * sdma_v2_4_enable - stop the async dma engines 379 * 380 * @adev: amdgpu_device pointer 381 * @enable: enable/disable the DMA MEs. 382 * 383 * Halt or unhalt the async dma engines (VI). 384 */ 385 static void sdma_v2_4_enable(struct amdgpu_device *adev, bool enable) 386 { 387 u32 f32_cntl; 388 int i; 389 390 if (!enable) { 391 sdma_v2_4_gfx_stop(adev); 392 sdma_v2_4_rlc_stop(adev); 393 } 394 395 for (i = 0; i < adev->sdma.num_instances; i++) { 396 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); 397 if (enable) 398 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); 399 else 400 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); 401 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); 402 } 403 } 404 405 /** 406 * sdma_v2_4_gfx_resume - setup and start the async dma engines 407 * 408 * @adev: amdgpu_device pointer 409 * 410 * Set up the gfx DMA ring buffers and enable them (VI). 411 * Returns 0 for success, error for failure. 412 */ 413 static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev) 414 { 415 struct amdgpu_ring *ring; 416 u32 rb_cntl, ib_cntl; 417 u32 rb_bufsz; 418 u32 wb_offset; 419 int i, j, r; 420 421 for (i = 0; i < adev->sdma.num_instances; i++) { 422 ring = &adev->sdma.instance[i].ring; 423 wb_offset = (ring->rptr_offs * 4); 424 425 mutex_lock(&adev->srbm_mutex); 426 for (j = 0; j < 16; j++) { 427 vi_srbm_select(adev, 0, 0, 0, j); 428 /* SDMA GFX */ 429 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); 430 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); 431 } 432 vi_srbm_select(adev, 0, 0, 0, 0); 433 mutex_unlock(&adev->srbm_mutex); 434 435 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], 436 adev->gfx.config.gb_addr_config & 0x70); 437 438 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); 439 440 /* Set ring buffer size in dwords */ 441 rb_bufsz = order_base_2(ring->ring_size / 4); 442 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 443 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 444 #ifdef __BIG_ENDIAN 445 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 446 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 447 RPTR_WRITEBACK_SWAP_ENABLE, 1); 448 #endif 449 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 450 451 /* Initialize the ring buffer's read and write pointers */ 452 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); 453 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); 454 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); 455 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); 456 457 /* set the wb address whether it's enabled or not */ 458 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], 459 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 460 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], 461 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 462 463 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 464 465 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); 466 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); 467 468 ring->wptr = 0; 469 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2); 470 471 /* enable DMA RB */ 472 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 473 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 474 475 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 476 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 477 #ifdef __BIG_ENDIAN 478 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 479 #endif 480 /* enable DMA IBs */ 481 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 482 483 ring->ready = true; 484 } 485 486 sdma_v2_4_enable(adev, true); 487 for (i = 0; i < adev->sdma.num_instances; i++) { 488 ring = &adev->sdma.instance[i].ring; 489 r = amdgpu_ring_test_ring(ring); 490 if (r) { 491 ring->ready = false; 492 return r; 493 } 494 495 if (adev->mman.buffer_funcs_ring == ring) 496 amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size); 497 } 498 499 return 0; 500 } 501 502 /** 503 * sdma_v2_4_rlc_resume - setup and start the async dma engines 504 * 505 * @adev: amdgpu_device pointer 506 * 507 * Set up the compute DMA queues and enable them (VI). 508 * Returns 0 for success, error for failure. 509 */ 510 static int sdma_v2_4_rlc_resume(struct amdgpu_device *adev) 511 { 512 /* XXX todo */ 513 return 0; 514 } 515 516 /** 517 * sdma_v2_4_load_microcode - load the sDMA ME ucode 518 * 519 * @adev: amdgpu_device pointer 520 * 521 * Loads the sDMA0/1 ucode. 522 * Returns 0 for success, -EINVAL if the ucode is not available. 523 */ 524 static int sdma_v2_4_load_microcode(struct amdgpu_device *adev) 525 { 526 const struct sdma_firmware_header_v1_0 *hdr; 527 const __le32 *fw_data; 528 u32 fw_size; 529 int i, j; 530 531 /* halt the MEs */ 532 sdma_v2_4_enable(adev, false); 533 534 for (i = 0; i < adev->sdma.num_instances; i++) { 535 if (!adev->sdma.instance[i].fw) 536 return -EINVAL; 537 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 538 amdgpu_ucode_print_sdma_hdr(&hdr->header); 539 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 540 fw_data = (const __le32 *) 541 (adev->sdma.instance[i].fw->data + 542 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 543 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0); 544 for (j = 0; j < fw_size; j++) 545 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++)); 546 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version); 547 } 548 549 return 0; 550 } 551 552 /** 553 * sdma_v2_4_start - setup and start the async dma engines 554 * 555 * @adev: amdgpu_device pointer 556 * 557 * Set up the DMA engines and enable them (VI). 558 * Returns 0 for success, error for failure. 559 */ 560 static int sdma_v2_4_start(struct amdgpu_device *adev) 561 { 562 int r; 563 564 565 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 566 r = sdma_v2_4_load_microcode(adev); 567 if (r) 568 return r; 569 } 570 571 /* halt the engine before programing */ 572 sdma_v2_4_enable(adev, false); 573 574 /* start the gfx rings and rlc compute queues */ 575 r = sdma_v2_4_gfx_resume(adev); 576 if (r) 577 return r; 578 r = sdma_v2_4_rlc_resume(adev); 579 if (r) 580 return r; 581 582 return 0; 583 } 584 585 /** 586 * sdma_v2_4_ring_test_ring - simple async dma engine test 587 * 588 * @ring: amdgpu_ring structure holding ring information 589 * 590 * Test the DMA engine by writing using it to write an 591 * value to memory. (VI). 592 * Returns 0 for success, error for failure. 593 */ 594 static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring) 595 { 596 struct amdgpu_device *adev = ring->adev; 597 unsigned i; 598 unsigned index; 599 int r; 600 u32 tmp; 601 u64 gpu_addr; 602 603 r = amdgpu_wb_get(adev, &index); 604 if (r) { 605 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 606 return r; 607 } 608 609 gpu_addr = adev->wb.gpu_addr + (index * 4); 610 tmp = 0xCAFEDEAD; 611 adev->wb.wb[index] = cpu_to_le32(tmp); 612 613 r = amdgpu_ring_alloc(ring, 5); 614 if (r) { 615 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 616 amdgpu_wb_free(adev, index); 617 return r; 618 } 619 620 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 621 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 622 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 623 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 624 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); 625 amdgpu_ring_write(ring, 0xDEADBEEF); 626 amdgpu_ring_commit(ring); 627 628 for (i = 0; i < adev->usec_timeout; i++) { 629 tmp = le32_to_cpu(adev->wb.wb[index]); 630 if (tmp == 0xDEADBEEF) 631 break; 632 DRM_UDELAY(1); 633 } 634 635 if (i < adev->usec_timeout) { 636 DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); 637 } else { 638 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 639 ring->idx, tmp); 640 r = -EINVAL; 641 } 642 amdgpu_wb_free(adev, index); 643 644 return r; 645 } 646 647 /** 648 * sdma_v2_4_ring_test_ib - test an IB on the DMA engine 649 * 650 * @ring: amdgpu_ring structure holding ring information 651 * 652 * Test a simple IB in the DMA ring (VI). 653 * Returns 0 on success, error on failure. 654 */ 655 static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring, long timeout) 656 { 657 struct amdgpu_device *adev = ring->adev; 658 struct amdgpu_ib ib; 659 struct dma_fence *f = NULL; 660 unsigned index; 661 u32 tmp = 0; 662 u64 gpu_addr; 663 long r; 664 665 r = amdgpu_wb_get(adev, &index); 666 if (r) { 667 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 668 return r; 669 } 670 671 gpu_addr = adev->wb.gpu_addr + (index * 4); 672 tmp = 0xCAFEDEAD; 673 adev->wb.wb[index] = cpu_to_le32(tmp); 674 memset(&ib, 0, sizeof(ib)); 675 r = amdgpu_ib_get(adev, NULL, 256, &ib); 676 if (r) { 677 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 678 goto err0; 679 } 680 681 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 682 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 683 ib.ptr[1] = lower_32_bits(gpu_addr); 684 ib.ptr[2] = upper_32_bits(gpu_addr); 685 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1); 686 ib.ptr[4] = 0xDEADBEEF; 687 ib.ptr[5] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 688 ib.ptr[6] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 689 ib.ptr[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 690 ib.length_dw = 8; 691 692 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 693 if (r) 694 goto err1; 695 696 r = dma_fence_wait_timeout(f, false, timeout); 697 if (r == 0) { 698 DRM_ERROR("amdgpu: IB test timed out\n"); 699 r = -ETIMEDOUT; 700 goto err1; 701 } else if (r < 0) { 702 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 703 goto err1; 704 } 705 tmp = le32_to_cpu(adev->wb.wb[index]); 706 if (tmp == 0xDEADBEEF) { 707 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); 708 r = 0; 709 } else { 710 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); 711 r = -EINVAL; 712 } 713 714 err1: 715 amdgpu_ib_free(adev, &ib, NULL); 716 dma_fence_put(f); 717 err0: 718 amdgpu_wb_free(adev, index); 719 return r; 720 } 721 722 /** 723 * sdma_v2_4_vm_copy_pte - update PTEs by copying them from the GART 724 * 725 * @ib: indirect buffer to fill with commands 726 * @pe: addr of the page entry 727 * @src: src addr to copy from 728 * @count: number of page entries to update 729 * 730 * Update PTEs by copying them from the GART using sDMA (CIK). 731 */ 732 static void sdma_v2_4_vm_copy_pte(struct amdgpu_ib *ib, 733 uint64_t pe, uint64_t src, 734 unsigned count) 735 { 736 unsigned bytes = count * 8; 737 738 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 739 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 740 ib->ptr[ib->length_dw++] = bytes; 741 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 742 ib->ptr[ib->length_dw++] = lower_32_bits(src); 743 ib->ptr[ib->length_dw++] = upper_32_bits(src); 744 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 745 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 746 } 747 748 /** 749 * sdma_v2_4_vm_write_pte - update PTEs by writing them manually 750 * 751 * @ib: indirect buffer to fill with commands 752 * @pe: addr of the page entry 753 * @value: dst addr to write into pe 754 * @count: number of page entries to update 755 * @incr: increase next addr by incr bytes 756 * 757 * Update PTEs by writing them manually using sDMA (CIK). 758 */ 759 static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 760 uint64_t value, unsigned count, 761 uint32_t incr) 762 { 763 unsigned ndw = count * 2; 764 765 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 766 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 767 ib->ptr[ib->length_dw++] = pe; 768 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 769 ib->ptr[ib->length_dw++] = ndw; 770 for (; ndw > 0; ndw -= 2) { 771 ib->ptr[ib->length_dw++] = lower_32_bits(value); 772 ib->ptr[ib->length_dw++] = upper_32_bits(value); 773 value += incr; 774 } 775 } 776 777 /** 778 * sdma_v2_4_vm_set_pte_pde - update the page tables using sDMA 779 * 780 * @ib: indirect buffer to fill with commands 781 * @pe: addr of the page entry 782 * @addr: dst addr to write into pe 783 * @count: number of page entries to update 784 * @incr: increase next addr by incr bytes 785 * @flags: access flags 786 * 787 * Update the page tables using sDMA (CIK). 788 */ 789 static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe, 790 uint64_t addr, unsigned count, 791 uint32_t incr, uint64_t flags) 792 { 793 /* for physically contiguous pages (vram) */ 794 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE); 795 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 796 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 797 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 798 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 799 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 800 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 801 ib->ptr[ib->length_dw++] = incr; /* increment size */ 802 ib->ptr[ib->length_dw++] = 0; 803 ib->ptr[ib->length_dw++] = count; /* number of entries */ 804 } 805 806 /** 807 * sdma_v2_4_ring_pad_ib - pad the IB to the required number of dw 808 * 809 * @ib: indirect buffer to fill with padding 810 * 811 */ 812 static void sdma_v2_4_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 813 { 814 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); 815 u32 pad_count; 816 int i; 817 818 pad_count = (8 - (ib->length_dw & 0x7)) % 8; 819 for (i = 0; i < pad_count; i++) 820 if (sdma && sdma->burst_nop && (i == 0)) 821 ib->ptr[ib->length_dw++] = 822 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 823 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 824 else 825 ib->ptr[ib->length_dw++] = 826 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 827 } 828 829 /** 830 * sdma_v2_4_ring_emit_pipeline_sync - sync the pipeline 831 * 832 * @ring: amdgpu_ring pointer 833 * 834 * Make sure all previous operations are completed (CIK). 835 */ 836 static void sdma_v2_4_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 837 { 838 uint32_t seq = ring->fence_drv.sync_seq; 839 uint64_t addr = ring->fence_drv.gpu_addr; 840 841 /* wait for idle */ 842 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 843 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 844 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 845 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 846 amdgpu_ring_write(ring, addr & 0xfffffffc); 847 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 848 amdgpu_ring_write(ring, seq); /* reference */ 849 amdgpu_ring_write(ring, 0xfffffff); /* mask */ 850 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 851 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 852 } 853 854 /** 855 * sdma_v2_4_ring_emit_vm_flush - cik vm flush using sDMA 856 * 857 * @ring: amdgpu_ring pointer 858 * @vm: amdgpu_vm pointer 859 * 860 * Update the page table base and flush the VM TLB 861 * using sDMA (VI). 862 */ 863 static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring, 864 unsigned vm_id, uint64_t pd_addr) 865 { 866 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 867 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 868 if (vm_id < 8) { 869 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id)); 870 } else { 871 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8)); 872 } 873 amdgpu_ring_write(ring, pd_addr >> 12); 874 875 /* flush TLB */ 876 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 877 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 878 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 879 amdgpu_ring_write(ring, 1 << vm_id); 880 881 /* wait for flush */ 882 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 883 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 884 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */ 885 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); 886 amdgpu_ring_write(ring, 0); 887 amdgpu_ring_write(ring, 0); /* reference */ 888 amdgpu_ring_write(ring, 0); /* mask */ 889 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 890 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 891 } 892 893 static int sdma_v2_4_early_init(void *handle) 894 { 895 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 896 897 adev->sdma.num_instances = SDMA_MAX_INSTANCE; 898 899 sdma_v2_4_set_ring_funcs(adev); 900 sdma_v2_4_set_buffer_funcs(adev); 901 sdma_v2_4_set_vm_pte_funcs(adev); 902 sdma_v2_4_set_irq_funcs(adev); 903 904 return 0; 905 } 906 907 static int sdma_v2_4_sw_init(void *handle) 908 { 909 struct amdgpu_ring *ring; 910 int r, i; 911 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 912 913 /* SDMA trap event */ 914 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 224, 915 &adev->sdma.trap_irq); 916 if (r) 917 return r; 918 919 /* SDMA Privileged inst */ 920 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 241, 921 &adev->sdma.illegal_inst_irq); 922 if (r) 923 return r; 924 925 /* SDMA Privileged inst */ 926 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 247, 927 &adev->sdma.illegal_inst_irq); 928 if (r) 929 return r; 930 931 r = sdma_v2_4_init_microcode(adev); 932 if (r) { 933 DRM_ERROR("Failed to load sdma firmware!\n"); 934 return r; 935 } 936 937 for (i = 0; i < adev->sdma.num_instances; i++) { 938 ring = &adev->sdma.instance[i].ring; 939 ring->ring_obj = NULL; 940 ring->use_doorbell = false; 941 sprintf(ring->name, "sdma%d", i); 942 r = amdgpu_ring_init(adev, ring, 1024, 943 &adev->sdma.trap_irq, 944 (i == 0) ? 945 AMDGPU_SDMA_IRQ_TRAP0 : 946 AMDGPU_SDMA_IRQ_TRAP1); 947 if (r) 948 return r; 949 } 950 951 return r; 952 } 953 954 static int sdma_v2_4_sw_fini(void *handle) 955 { 956 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 957 int i; 958 959 for (i = 0; i < adev->sdma.num_instances; i++) 960 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 961 962 sdma_v2_4_free_microcode(adev); 963 return 0; 964 } 965 966 static int sdma_v2_4_hw_init(void *handle) 967 { 968 int r; 969 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 970 971 sdma_v2_4_init_golden_registers(adev); 972 973 r = sdma_v2_4_start(adev); 974 if (r) 975 return r; 976 977 return r; 978 } 979 980 static int sdma_v2_4_hw_fini(void *handle) 981 { 982 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 983 984 sdma_v2_4_enable(adev, false); 985 986 return 0; 987 } 988 989 static int sdma_v2_4_suspend(void *handle) 990 { 991 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 992 993 return sdma_v2_4_hw_fini(adev); 994 } 995 996 static int sdma_v2_4_resume(void *handle) 997 { 998 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 999 1000 return sdma_v2_4_hw_init(adev); 1001 } 1002 1003 static bool sdma_v2_4_is_idle(void *handle) 1004 { 1005 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1006 u32 tmp = RREG32(mmSRBM_STATUS2); 1007 1008 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | 1009 SRBM_STATUS2__SDMA1_BUSY_MASK)) 1010 return false; 1011 1012 return true; 1013 } 1014 1015 static int sdma_v2_4_wait_for_idle(void *handle) 1016 { 1017 unsigned i; 1018 u32 tmp; 1019 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1020 1021 for (i = 0; i < adev->usec_timeout; i++) { 1022 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | 1023 SRBM_STATUS2__SDMA1_BUSY_MASK); 1024 1025 if (!tmp) 1026 return 0; 1027 udelay(1); 1028 } 1029 return -ETIMEDOUT; 1030 } 1031 1032 static int sdma_v2_4_soft_reset(void *handle) 1033 { 1034 u32 srbm_soft_reset = 0; 1035 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1036 u32 tmp = RREG32(mmSRBM_STATUS2); 1037 1038 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) { 1039 /* sdma0 */ 1040 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); 1041 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); 1042 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); 1043 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK; 1044 } 1045 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) { 1046 /* sdma1 */ 1047 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); 1048 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); 1049 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); 1050 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK; 1051 } 1052 1053 if (srbm_soft_reset) { 1054 tmp = RREG32(mmSRBM_SOFT_RESET); 1055 tmp |= srbm_soft_reset; 1056 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1057 WREG32(mmSRBM_SOFT_RESET, tmp); 1058 tmp = RREG32(mmSRBM_SOFT_RESET); 1059 1060 udelay(50); 1061 1062 tmp &= ~srbm_soft_reset; 1063 WREG32(mmSRBM_SOFT_RESET, tmp); 1064 tmp = RREG32(mmSRBM_SOFT_RESET); 1065 1066 /* Wait a little for things to settle down */ 1067 udelay(50); 1068 } 1069 1070 return 0; 1071 } 1072 1073 static int sdma_v2_4_set_trap_irq_state(struct amdgpu_device *adev, 1074 struct amdgpu_irq_src *src, 1075 unsigned type, 1076 enum amdgpu_interrupt_state state) 1077 { 1078 u32 sdma_cntl; 1079 1080 switch (type) { 1081 case AMDGPU_SDMA_IRQ_TRAP0: 1082 switch (state) { 1083 case AMDGPU_IRQ_STATE_DISABLE: 1084 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1085 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1086 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1087 break; 1088 case AMDGPU_IRQ_STATE_ENABLE: 1089 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1090 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1091 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1092 break; 1093 default: 1094 break; 1095 } 1096 break; 1097 case AMDGPU_SDMA_IRQ_TRAP1: 1098 switch (state) { 1099 case AMDGPU_IRQ_STATE_DISABLE: 1100 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1101 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1102 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1103 break; 1104 case AMDGPU_IRQ_STATE_ENABLE: 1105 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1106 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1107 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1108 break; 1109 default: 1110 break; 1111 } 1112 break; 1113 default: 1114 break; 1115 } 1116 return 0; 1117 } 1118 1119 static int sdma_v2_4_process_trap_irq(struct amdgpu_device *adev, 1120 struct amdgpu_irq_src *source, 1121 struct amdgpu_iv_entry *entry) 1122 { 1123 u8 instance_id, queue_id; 1124 1125 instance_id = (entry->ring_id & 0x3) >> 0; 1126 queue_id = (entry->ring_id & 0xc) >> 2; 1127 DRM_DEBUG("IH: SDMA trap\n"); 1128 switch (instance_id) { 1129 case 0: 1130 switch (queue_id) { 1131 case 0: 1132 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1133 break; 1134 case 1: 1135 /* XXX compute */ 1136 break; 1137 case 2: 1138 /* XXX compute */ 1139 break; 1140 } 1141 break; 1142 case 1: 1143 switch (queue_id) { 1144 case 0: 1145 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1146 break; 1147 case 1: 1148 /* XXX compute */ 1149 break; 1150 case 2: 1151 /* XXX compute */ 1152 break; 1153 } 1154 break; 1155 } 1156 return 0; 1157 } 1158 1159 static int sdma_v2_4_process_illegal_inst_irq(struct amdgpu_device *adev, 1160 struct amdgpu_irq_src *source, 1161 struct amdgpu_iv_entry *entry) 1162 { 1163 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1164 schedule_work(&adev->reset_work); 1165 return 0; 1166 } 1167 1168 static int sdma_v2_4_set_clockgating_state(void *handle, 1169 enum amd_clockgating_state state) 1170 { 1171 /* XXX handled via the smc on VI */ 1172 return 0; 1173 } 1174 1175 static int sdma_v2_4_set_powergating_state(void *handle, 1176 enum amd_powergating_state state) 1177 { 1178 return 0; 1179 } 1180 1181 static const struct amd_ip_funcs sdma_v2_4_ip_funcs = { 1182 .name = "sdma_v2_4", 1183 .early_init = sdma_v2_4_early_init, 1184 .late_init = NULL, 1185 .sw_init = sdma_v2_4_sw_init, 1186 .sw_fini = sdma_v2_4_sw_fini, 1187 .hw_init = sdma_v2_4_hw_init, 1188 .hw_fini = sdma_v2_4_hw_fini, 1189 .suspend = sdma_v2_4_suspend, 1190 .resume = sdma_v2_4_resume, 1191 .is_idle = sdma_v2_4_is_idle, 1192 .wait_for_idle = sdma_v2_4_wait_for_idle, 1193 .soft_reset = sdma_v2_4_soft_reset, 1194 .set_clockgating_state = sdma_v2_4_set_clockgating_state, 1195 .set_powergating_state = sdma_v2_4_set_powergating_state, 1196 }; 1197 1198 static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = { 1199 .type = AMDGPU_RING_TYPE_SDMA, 1200 .align_mask = 0xf, 1201 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1202 .support_64bit_ptrs = false, 1203 .get_rptr = sdma_v2_4_ring_get_rptr, 1204 .get_wptr = sdma_v2_4_ring_get_wptr, 1205 .set_wptr = sdma_v2_4_ring_set_wptr, 1206 .emit_frame_size = 1207 6 + /* sdma_v2_4_ring_emit_hdp_flush */ 1208 3 + /* sdma_v2_4_ring_emit_hdp_invalidate */ 1209 6 + /* sdma_v2_4_ring_emit_pipeline_sync */ 1210 12 + /* sdma_v2_4_ring_emit_vm_flush */ 1211 10 + 10 + 10, /* sdma_v2_4_ring_emit_fence x3 for user fence, vm fence */ 1212 .emit_ib_size = 7 + 6, /* sdma_v2_4_ring_emit_ib */ 1213 .emit_ib = sdma_v2_4_ring_emit_ib, 1214 .emit_fence = sdma_v2_4_ring_emit_fence, 1215 .emit_pipeline_sync = sdma_v2_4_ring_emit_pipeline_sync, 1216 .emit_vm_flush = sdma_v2_4_ring_emit_vm_flush, 1217 .emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush, 1218 .emit_hdp_invalidate = sdma_v2_4_ring_emit_hdp_invalidate, 1219 .test_ring = sdma_v2_4_ring_test_ring, 1220 .test_ib = sdma_v2_4_ring_test_ib, 1221 .insert_nop = sdma_v2_4_ring_insert_nop, 1222 .pad_ib = sdma_v2_4_ring_pad_ib, 1223 }; 1224 1225 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev) 1226 { 1227 int i; 1228 1229 for (i = 0; i < adev->sdma.num_instances; i++) 1230 adev->sdma.instance[i].ring.funcs = &sdma_v2_4_ring_funcs; 1231 } 1232 1233 static const struct amdgpu_irq_src_funcs sdma_v2_4_trap_irq_funcs = { 1234 .set = sdma_v2_4_set_trap_irq_state, 1235 .process = sdma_v2_4_process_trap_irq, 1236 }; 1237 1238 static const struct amdgpu_irq_src_funcs sdma_v2_4_illegal_inst_irq_funcs = { 1239 .process = sdma_v2_4_process_illegal_inst_irq, 1240 }; 1241 1242 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev) 1243 { 1244 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 1245 adev->sdma.trap_irq.funcs = &sdma_v2_4_trap_irq_funcs; 1246 adev->sdma.illegal_inst_irq.funcs = &sdma_v2_4_illegal_inst_irq_funcs; 1247 } 1248 1249 /** 1250 * sdma_v2_4_emit_copy_buffer - copy buffer using the sDMA engine 1251 * 1252 * @ring: amdgpu_ring structure holding ring information 1253 * @src_offset: src GPU address 1254 * @dst_offset: dst GPU address 1255 * @byte_count: number of bytes to xfer 1256 * 1257 * Copy GPU buffers using the DMA engine (VI). 1258 * Used by the amdgpu ttm implementation to move pages if 1259 * registered as the asic copy callback. 1260 */ 1261 static void sdma_v2_4_emit_copy_buffer(struct amdgpu_ib *ib, 1262 uint64_t src_offset, 1263 uint64_t dst_offset, 1264 uint32_t byte_count) 1265 { 1266 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1267 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1268 ib->ptr[ib->length_dw++] = byte_count; 1269 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1270 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1271 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1272 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1273 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1274 } 1275 1276 /** 1277 * sdma_v2_4_emit_fill_buffer - fill buffer using the sDMA engine 1278 * 1279 * @ring: amdgpu_ring structure holding ring information 1280 * @src_data: value to write to buffer 1281 * @dst_offset: dst GPU address 1282 * @byte_count: number of bytes to xfer 1283 * 1284 * Fill GPU buffers using the DMA engine (VI). 1285 */ 1286 static void sdma_v2_4_emit_fill_buffer(struct amdgpu_ib *ib, 1287 uint32_t src_data, 1288 uint64_t dst_offset, 1289 uint32_t byte_count) 1290 { 1291 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1292 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1293 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1294 ib->ptr[ib->length_dw++] = src_data; 1295 ib->ptr[ib->length_dw++] = byte_count; 1296 } 1297 1298 static const struct amdgpu_buffer_funcs sdma_v2_4_buffer_funcs = { 1299 .copy_max_bytes = 0x1fffff, 1300 .copy_num_dw = 7, 1301 .emit_copy_buffer = sdma_v2_4_emit_copy_buffer, 1302 1303 .fill_max_bytes = 0x1fffff, 1304 .fill_num_dw = 7, 1305 .emit_fill_buffer = sdma_v2_4_emit_fill_buffer, 1306 }; 1307 1308 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev) 1309 { 1310 if (adev->mman.buffer_funcs == NULL) { 1311 adev->mman.buffer_funcs = &sdma_v2_4_buffer_funcs; 1312 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1313 } 1314 } 1315 1316 static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = { 1317 .copy_pte_num_dw = 7, 1318 .copy_pte = sdma_v2_4_vm_copy_pte, 1319 1320 .write_pte = sdma_v2_4_vm_write_pte, 1321 1322 .set_max_nums_pte_pde = 0x1fffff >> 3, 1323 .set_pte_pde_num_dw = 10, 1324 .set_pte_pde = sdma_v2_4_vm_set_pte_pde, 1325 }; 1326 1327 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev) 1328 { 1329 unsigned i; 1330 1331 if (adev->vm_manager.vm_pte_funcs == NULL) { 1332 adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs; 1333 for (i = 0; i < adev->sdma.num_instances; i++) 1334 adev->vm_manager.vm_pte_rings[i] = 1335 &adev->sdma.instance[i].ring; 1336 1337 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances; 1338 } 1339 } 1340 1341 const struct amdgpu_ip_block_version sdma_v2_4_ip_block = 1342 { 1343 .type = AMD_IP_BLOCK_TYPE_SDMA, 1344 .major = 2, 1345 .minor = 4, 1346 .rev = 0, 1347 .funcs = &sdma_v2_4_ip_funcs, 1348 }; 1349