1 /*
2  * Copyright 2014 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Alex Deucher
23  */
24 #include <linux/firmware.h>
25 #include <drm/drmP.h>
26 #include "amdgpu.h"
27 #include "amdgpu_ucode.h"
28 #include "amdgpu_trace.h"
29 #include "vi.h"
30 #include "vid.h"
31 
32 #include "oss/oss_2_4_d.h"
33 #include "oss/oss_2_4_sh_mask.h"
34 
35 #include "gmc/gmc_7_1_d.h"
36 #include "gmc/gmc_7_1_sh_mask.h"
37 
38 #include "gca/gfx_8_0_d.h"
39 #include "gca/gfx_8_0_enum.h"
40 #include "gca/gfx_8_0_sh_mask.h"
41 
42 #include "bif/bif_5_0_d.h"
43 #include "bif/bif_5_0_sh_mask.h"
44 
45 #include "iceland_sdma_pkt_open.h"
46 
47 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev);
48 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev);
49 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev);
50 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev);
51 
52 MODULE_FIRMWARE("amdgpu/topaz_sdma.bin");
53 MODULE_FIRMWARE("amdgpu/topaz_sdma1.bin");
54 
55 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
56 {
57 	SDMA0_REGISTER_OFFSET,
58 	SDMA1_REGISTER_OFFSET
59 };
60 
61 static const u32 golden_settings_iceland_a11[] =
62 {
63 	mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
64 	mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
65 	mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
66 	mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
67 };
68 
69 static const u32 iceland_mgcg_cgcg_init[] =
70 {
71 	mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
72 	mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
73 };
74 
75 /*
76  * sDMA - System DMA
77  * Starting with CIK, the GPU has new asynchronous
78  * DMA engines.  These engines are used for compute
79  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
80  * and each one supports 1 ring buffer used for gfx
81  * and 2 queues used for compute.
82  *
83  * The programming model is very similar to the CP
84  * (ring buffer, IBs, etc.), but sDMA has it's own
85  * packet format that is different from the PM4 format
86  * used by the CP. sDMA supports copying data, writing
87  * embedded data, solid fills, and a number of other
88  * things.  It also has support for tiling/detiling of
89  * buffers.
90  */
91 
92 static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev)
93 {
94 	switch (adev->asic_type) {
95 	case CHIP_TOPAZ:
96 		amdgpu_device_program_register_sequence(adev,
97 							iceland_mgcg_cgcg_init,
98 							ARRAY_SIZE(iceland_mgcg_cgcg_init));
99 		amdgpu_device_program_register_sequence(adev,
100 							golden_settings_iceland_a11,
101 							ARRAY_SIZE(golden_settings_iceland_a11));
102 		break;
103 	default:
104 		break;
105 	}
106 }
107 
108 static void sdma_v2_4_free_microcode(struct amdgpu_device *adev)
109 {
110 	int i;
111 	for (i = 0; i < adev->sdma.num_instances; i++) {
112 		release_firmware(adev->sdma.instance[i].fw);
113 		adev->sdma.instance[i].fw = NULL;
114 	}
115 }
116 
117 /**
118  * sdma_v2_4_init_microcode - load ucode images from disk
119  *
120  * @adev: amdgpu_device pointer
121  *
122  * Use the firmware interface to load the ucode images into
123  * the driver (not loaded into hw).
124  * Returns 0 on success, error on failure.
125  */
126 static int sdma_v2_4_init_microcode(struct amdgpu_device *adev)
127 {
128 	const char *chip_name;
129 	char fw_name[30];
130 	int err = 0, i;
131 	struct amdgpu_firmware_info *info = NULL;
132 	const struct common_firmware_header *header = NULL;
133 	const struct sdma_firmware_header_v1_0 *hdr;
134 
135 	DRM_DEBUG("\n");
136 
137 	switch (adev->asic_type) {
138 	case CHIP_TOPAZ:
139 		chip_name = "topaz";
140 		break;
141 	default: BUG();
142 	}
143 
144 	for (i = 0; i < adev->sdma.num_instances; i++) {
145 		if (i == 0)
146 			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
147 		else
148 			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
149 		err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
150 		if (err)
151 			goto out;
152 		err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
153 		if (err)
154 			goto out;
155 		hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
156 		adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
157 		adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
158 		if (adev->sdma.instance[i].feature_version >= 20)
159 			adev->sdma.instance[i].burst_nop = true;
160 
161 		if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) {
162 			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
163 			info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
164 			info->fw = adev->sdma.instance[i].fw;
165 			header = (const struct common_firmware_header *)info->fw->data;
166 			adev->firmware.fw_size +=
167 				ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
168 		}
169 	}
170 
171 out:
172 	if (err) {
173 		pr_err("sdma_v2_4: Failed to load firmware \"%s\"\n", fw_name);
174 		for (i = 0; i < adev->sdma.num_instances; i++) {
175 			release_firmware(adev->sdma.instance[i].fw);
176 			adev->sdma.instance[i].fw = NULL;
177 		}
178 	}
179 	return err;
180 }
181 
182 /**
183  * sdma_v2_4_ring_get_rptr - get the current read pointer
184  *
185  * @ring: amdgpu ring pointer
186  *
187  * Get the current rptr from the hardware (VI+).
188  */
189 static uint64_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring)
190 {
191 	/* XXX check if swapping is necessary on BE */
192 	return ring->adev->wb.wb[ring->rptr_offs] >> 2;
193 }
194 
195 /**
196  * sdma_v2_4_ring_get_wptr - get the current write pointer
197  *
198  * @ring: amdgpu ring pointer
199  *
200  * Get the current wptr from the hardware (VI+).
201  */
202 static uint64_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring)
203 {
204 	struct amdgpu_device *adev = ring->adev;
205 	int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
206 	u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
207 
208 	return wptr;
209 }
210 
211 /**
212  * sdma_v2_4_ring_set_wptr - commit the write pointer
213  *
214  * @ring: amdgpu ring pointer
215  *
216  * Write the wptr back to the hardware (VI+).
217  */
218 static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring)
219 {
220 	struct amdgpu_device *adev = ring->adev;
221 	int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
222 
223 	WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], lower_32_bits(ring->wptr) << 2);
224 }
225 
226 static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
227 {
228 	struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
229 	int i;
230 
231 	for (i = 0; i < count; i++)
232 		if (sdma && sdma->burst_nop && (i == 0))
233 			amdgpu_ring_write(ring, ring->funcs->nop |
234 				SDMA_PKT_NOP_HEADER_COUNT(count - 1));
235 		else
236 			amdgpu_ring_write(ring, ring->funcs->nop);
237 }
238 
239 /**
240  * sdma_v2_4_ring_emit_ib - Schedule an IB on the DMA engine
241  *
242  * @ring: amdgpu ring pointer
243  * @ib: IB object to schedule
244  *
245  * Schedule an IB in the DMA ring (VI).
246  */
247 static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring,
248 				   struct amdgpu_ib *ib,
249 				   unsigned vmid, bool ctx_switch)
250 {
251 	/* IB packet must end on a 8 DW boundary */
252 	sdma_v2_4_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8);
253 
254 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
255 			  SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
256 	/* base must be 32 byte aligned */
257 	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
258 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
259 	amdgpu_ring_write(ring, ib->length_dw);
260 	amdgpu_ring_write(ring, 0);
261 	amdgpu_ring_write(ring, 0);
262 
263 }
264 
265 /**
266  * sdma_v2_4_hdp_flush_ring_emit - emit an hdp flush on the DMA ring
267  *
268  * @ring: amdgpu ring pointer
269  *
270  * Emit an hdp flush packet on the requested DMA ring.
271  */
272 static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring)
273 {
274 	u32 ref_and_mask = 0;
275 
276 	if (ring == &ring->adev->sdma.instance[0].ring)
277 		ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
278 	else
279 		ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
280 
281 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
282 			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
283 			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
284 	amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
285 	amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
286 	amdgpu_ring_write(ring, ref_and_mask); /* reference */
287 	amdgpu_ring_write(ring, ref_and_mask); /* mask */
288 	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
289 			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
290 }
291 
292 static void sdma_v2_4_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
293 {
294 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
295 			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
296 	amdgpu_ring_write(ring, mmHDP_DEBUG0);
297 	amdgpu_ring_write(ring, 1);
298 }
299 /**
300  * sdma_v2_4_ring_emit_fence - emit a fence on the DMA ring
301  *
302  * @ring: amdgpu ring pointer
303  * @fence: amdgpu fence object
304  *
305  * Add a DMA fence packet to the ring to write
306  * the fence seq number and DMA trap packet to generate
307  * an interrupt if needed (VI).
308  */
309 static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
310 				      unsigned flags)
311 {
312 	bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
313 	/* write the fence */
314 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
315 	amdgpu_ring_write(ring, lower_32_bits(addr));
316 	amdgpu_ring_write(ring, upper_32_bits(addr));
317 	amdgpu_ring_write(ring, lower_32_bits(seq));
318 
319 	/* optionally write high bits as well */
320 	if (write64bit) {
321 		addr += 4;
322 		amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
323 		amdgpu_ring_write(ring, lower_32_bits(addr));
324 		amdgpu_ring_write(ring, upper_32_bits(addr));
325 		amdgpu_ring_write(ring, upper_32_bits(seq));
326 	}
327 
328 	/* generate an interrupt */
329 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
330 	amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
331 }
332 
333 /**
334  * sdma_v2_4_gfx_stop - stop the gfx async dma engines
335  *
336  * @adev: amdgpu_device pointer
337  *
338  * Stop the gfx async dma ring buffers (VI).
339  */
340 static void sdma_v2_4_gfx_stop(struct amdgpu_device *adev)
341 {
342 	struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
343 	struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
344 	u32 rb_cntl, ib_cntl;
345 	int i;
346 
347 	if ((adev->mman.buffer_funcs_ring == sdma0) ||
348 	    (adev->mman.buffer_funcs_ring == sdma1))
349 		amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
350 
351 	for (i = 0; i < adev->sdma.num_instances; i++) {
352 		rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
353 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
354 		WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
355 		ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
356 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
357 		WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
358 	}
359 	sdma0->ready = false;
360 	sdma1->ready = false;
361 }
362 
363 /**
364  * sdma_v2_4_rlc_stop - stop the compute async dma engines
365  *
366  * @adev: amdgpu_device pointer
367  *
368  * Stop the compute async dma queues (VI).
369  */
370 static void sdma_v2_4_rlc_stop(struct amdgpu_device *adev)
371 {
372 	/* XXX todo */
373 }
374 
375 /**
376  * sdma_v2_4_enable - stop the async dma engines
377  *
378  * @adev: amdgpu_device pointer
379  * @enable: enable/disable the DMA MEs.
380  *
381  * Halt or unhalt the async dma engines (VI).
382  */
383 static void sdma_v2_4_enable(struct amdgpu_device *adev, bool enable)
384 {
385 	u32 f32_cntl;
386 	int i;
387 
388 	if (!enable) {
389 		sdma_v2_4_gfx_stop(adev);
390 		sdma_v2_4_rlc_stop(adev);
391 	}
392 
393 	for (i = 0; i < adev->sdma.num_instances; i++) {
394 		f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
395 		if (enable)
396 			f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
397 		else
398 			f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
399 		WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
400 	}
401 }
402 
403 /**
404  * sdma_v2_4_gfx_resume - setup and start the async dma engines
405  *
406  * @adev: amdgpu_device pointer
407  *
408  * Set up the gfx DMA ring buffers and enable them (VI).
409  * Returns 0 for success, error for failure.
410  */
411 static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev)
412 {
413 	struct amdgpu_ring *ring;
414 	u32 rb_cntl, ib_cntl;
415 	u32 rb_bufsz;
416 	u32 wb_offset;
417 	int i, j, r;
418 
419 	for (i = 0; i < adev->sdma.num_instances; i++) {
420 		ring = &adev->sdma.instance[i].ring;
421 		wb_offset = (ring->rptr_offs * 4);
422 
423 		mutex_lock(&adev->srbm_mutex);
424 		for (j = 0; j < 16; j++) {
425 			vi_srbm_select(adev, 0, 0, 0, j);
426 			/* SDMA GFX */
427 			WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
428 			WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
429 		}
430 		vi_srbm_select(adev, 0, 0, 0, 0);
431 		mutex_unlock(&adev->srbm_mutex);
432 
433 		WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
434 		       adev->gfx.config.gb_addr_config & 0x70);
435 
436 		WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
437 
438 		/* Set ring buffer size in dwords */
439 		rb_bufsz = order_base_2(ring->ring_size / 4);
440 		rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
441 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
442 #ifdef __BIG_ENDIAN
443 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
444 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
445 					RPTR_WRITEBACK_SWAP_ENABLE, 1);
446 #endif
447 		WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
448 
449 		/* Initialize the ring buffer's read and write pointers */
450 		WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
451 		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
452 		WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
453 		WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
454 
455 		/* set the wb address whether it's enabled or not */
456 		WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
457 		       upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
458 		WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
459 		       lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
460 
461 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
462 
463 		WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
464 		WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
465 
466 		ring->wptr = 0;
467 		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2);
468 
469 		/* enable DMA RB */
470 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
471 		WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
472 
473 		ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
474 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
475 #ifdef __BIG_ENDIAN
476 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
477 #endif
478 		/* enable DMA IBs */
479 		WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
480 
481 		ring->ready = true;
482 	}
483 
484 	sdma_v2_4_enable(adev, true);
485 	for (i = 0; i < adev->sdma.num_instances; i++) {
486 		ring = &adev->sdma.instance[i].ring;
487 		r = amdgpu_ring_test_ring(ring);
488 		if (r) {
489 			ring->ready = false;
490 			return r;
491 		}
492 
493 		if (adev->mman.buffer_funcs_ring == ring)
494 			amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
495 	}
496 
497 	return 0;
498 }
499 
500 /**
501  * sdma_v2_4_rlc_resume - setup and start the async dma engines
502  *
503  * @adev: amdgpu_device pointer
504  *
505  * Set up the compute DMA queues and enable them (VI).
506  * Returns 0 for success, error for failure.
507  */
508 static int sdma_v2_4_rlc_resume(struct amdgpu_device *adev)
509 {
510 	/* XXX todo */
511 	return 0;
512 }
513 
514 /**
515  * sdma_v2_4_load_microcode - load the sDMA ME ucode
516  *
517  * @adev: amdgpu_device pointer
518  *
519  * Loads the sDMA0/1 ucode.
520  * Returns 0 for success, -EINVAL if the ucode is not available.
521  */
522 static int sdma_v2_4_load_microcode(struct amdgpu_device *adev)
523 {
524 	const struct sdma_firmware_header_v1_0 *hdr;
525 	const __le32 *fw_data;
526 	u32 fw_size;
527 	int i, j;
528 
529 	/* halt the MEs */
530 	sdma_v2_4_enable(adev, false);
531 
532 	for (i = 0; i < adev->sdma.num_instances; i++) {
533 		if (!adev->sdma.instance[i].fw)
534 			return -EINVAL;
535 		hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
536 		amdgpu_ucode_print_sdma_hdr(&hdr->header);
537 		fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
538 		fw_data = (const __le32 *)
539 			(adev->sdma.instance[i].fw->data +
540 			 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
541 		WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
542 		for (j = 0; j < fw_size; j++)
543 			WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
544 		WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
545 	}
546 
547 	return 0;
548 }
549 
550 /**
551  * sdma_v2_4_start - setup and start the async dma engines
552  *
553  * @adev: amdgpu_device pointer
554  *
555  * Set up the DMA engines and enable them (VI).
556  * Returns 0 for success, error for failure.
557  */
558 static int sdma_v2_4_start(struct amdgpu_device *adev)
559 {
560 	int r;
561 
562 
563 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
564 		r = sdma_v2_4_load_microcode(adev);
565 		if (r)
566 			return r;
567 	}
568 
569 	/* halt the engine before programing */
570 	sdma_v2_4_enable(adev, false);
571 
572 	/* start the gfx rings and rlc compute queues */
573 	r = sdma_v2_4_gfx_resume(adev);
574 	if (r)
575 		return r;
576 	r = sdma_v2_4_rlc_resume(adev);
577 	if (r)
578 		return r;
579 
580 	return 0;
581 }
582 
583 /**
584  * sdma_v2_4_ring_test_ring - simple async dma engine test
585  *
586  * @ring: amdgpu_ring structure holding ring information
587  *
588  * Test the DMA engine by writing using it to write an
589  * value to memory. (VI).
590  * Returns 0 for success, error for failure.
591  */
592 static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring)
593 {
594 	struct amdgpu_device *adev = ring->adev;
595 	unsigned i;
596 	unsigned index;
597 	int r;
598 	u32 tmp;
599 	u64 gpu_addr;
600 
601 	r = amdgpu_device_wb_get(adev, &index);
602 	if (r) {
603 		dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
604 		return r;
605 	}
606 
607 	gpu_addr = adev->wb.gpu_addr + (index * 4);
608 	tmp = 0xCAFEDEAD;
609 	adev->wb.wb[index] = cpu_to_le32(tmp);
610 
611 	r = amdgpu_ring_alloc(ring, 5);
612 	if (r) {
613 		DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
614 		amdgpu_device_wb_free(adev, index);
615 		return r;
616 	}
617 
618 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
619 			  SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
620 	amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
621 	amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
622 	amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
623 	amdgpu_ring_write(ring, 0xDEADBEEF);
624 	amdgpu_ring_commit(ring);
625 
626 	for (i = 0; i < adev->usec_timeout; i++) {
627 		tmp = le32_to_cpu(adev->wb.wb[index]);
628 		if (tmp == 0xDEADBEEF)
629 			break;
630 		DRM_UDELAY(1);
631 	}
632 
633 	if (i < adev->usec_timeout) {
634 		DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i);
635 	} else {
636 		DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
637 			  ring->idx, tmp);
638 		r = -EINVAL;
639 	}
640 	amdgpu_device_wb_free(adev, index);
641 
642 	return r;
643 }
644 
645 /**
646  * sdma_v2_4_ring_test_ib - test an IB on the DMA engine
647  *
648  * @ring: amdgpu_ring structure holding ring information
649  *
650  * Test a simple IB in the DMA ring (VI).
651  * Returns 0 on success, error on failure.
652  */
653 static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring, long timeout)
654 {
655 	struct amdgpu_device *adev = ring->adev;
656 	struct amdgpu_ib ib;
657 	struct dma_fence *f = NULL;
658 	unsigned index;
659 	u32 tmp = 0;
660 	u64 gpu_addr;
661 	long r;
662 
663 	r = amdgpu_device_wb_get(adev, &index);
664 	if (r) {
665 		dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
666 		return r;
667 	}
668 
669 	gpu_addr = adev->wb.gpu_addr + (index * 4);
670 	tmp = 0xCAFEDEAD;
671 	adev->wb.wb[index] = cpu_to_le32(tmp);
672 	memset(&ib, 0, sizeof(ib));
673 	r = amdgpu_ib_get(adev, NULL, 256, &ib);
674 	if (r) {
675 		DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
676 		goto err0;
677 	}
678 
679 	ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
680 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
681 	ib.ptr[1] = lower_32_bits(gpu_addr);
682 	ib.ptr[2] = upper_32_bits(gpu_addr);
683 	ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
684 	ib.ptr[4] = 0xDEADBEEF;
685 	ib.ptr[5] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
686 	ib.ptr[6] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
687 	ib.ptr[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
688 	ib.length_dw = 8;
689 
690 	r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
691 	if (r)
692 		goto err1;
693 
694 	r = dma_fence_wait_timeout(f, false, timeout);
695 	if (r == 0) {
696 		DRM_ERROR("amdgpu: IB test timed out\n");
697 		r = -ETIMEDOUT;
698 		goto err1;
699 	} else if (r < 0) {
700 		DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
701 		goto err1;
702 	}
703 	tmp = le32_to_cpu(adev->wb.wb[index]);
704 	if (tmp == 0xDEADBEEF) {
705 		DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
706 		r = 0;
707 	} else {
708 		DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
709 		r = -EINVAL;
710 	}
711 
712 err1:
713 	amdgpu_ib_free(adev, &ib, NULL);
714 	dma_fence_put(f);
715 err0:
716 	amdgpu_device_wb_free(adev, index);
717 	return r;
718 }
719 
720 /**
721  * sdma_v2_4_vm_copy_pte - update PTEs by copying them from the GART
722  *
723  * @ib: indirect buffer to fill with commands
724  * @pe: addr of the page entry
725  * @src: src addr to copy from
726  * @count: number of page entries to update
727  *
728  * Update PTEs by copying them from the GART using sDMA (CIK).
729  */
730 static void sdma_v2_4_vm_copy_pte(struct amdgpu_ib *ib,
731 				  uint64_t pe, uint64_t src,
732 				  unsigned count)
733 {
734 	unsigned bytes = count * 8;
735 
736 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
737 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
738 	ib->ptr[ib->length_dw++] = bytes;
739 	ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
740 	ib->ptr[ib->length_dw++] = lower_32_bits(src);
741 	ib->ptr[ib->length_dw++] = upper_32_bits(src);
742 	ib->ptr[ib->length_dw++] = lower_32_bits(pe);
743 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
744 }
745 
746 /**
747  * sdma_v2_4_vm_write_pte - update PTEs by writing them manually
748  *
749  * @ib: indirect buffer to fill with commands
750  * @pe: addr of the page entry
751  * @value: dst addr to write into pe
752  * @count: number of page entries to update
753  * @incr: increase next addr by incr bytes
754  *
755  * Update PTEs by writing them manually using sDMA (CIK).
756  */
757 static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
758 				   uint64_t value, unsigned count,
759 				   uint32_t incr)
760 {
761 	unsigned ndw = count * 2;
762 
763 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
764 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
765 	ib->ptr[ib->length_dw++] = pe;
766 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
767 	ib->ptr[ib->length_dw++] = ndw;
768 	for (; ndw > 0; ndw -= 2) {
769 		ib->ptr[ib->length_dw++] = lower_32_bits(value);
770 		ib->ptr[ib->length_dw++] = upper_32_bits(value);
771 		value += incr;
772 	}
773 }
774 
775 /**
776  * sdma_v2_4_vm_set_pte_pde - update the page tables using sDMA
777  *
778  * @ib: indirect buffer to fill with commands
779  * @pe: addr of the page entry
780  * @addr: dst addr to write into pe
781  * @count: number of page entries to update
782  * @incr: increase next addr by incr bytes
783  * @flags: access flags
784  *
785  * Update the page tables using sDMA (CIK).
786  */
787 static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
788 				     uint64_t addr, unsigned count,
789 				     uint32_t incr, uint64_t flags)
790 {
791 	/* for physically contiguous pages (vram) */
792 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
793 	ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
794 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
795 	ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
796 	ib->ptr[ib->length_dw++] = upper_32_bits(flags);
797 	ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
798 	ib->ptr[ib->length_dw++] = upper_32_bits(addr);
799 	ib->ptr[ib->length_dw++] = incr; /* increment size */
800 	ib->ptr[ib->length_dw++] = 0;
801 	ib->ptr[ib->length_dw++] = count; /* number of entries */
802 }
803 
804 /**
805  * sdma_v2_4_ring_pad_ib - pad the IB to the required number of dw
806  *
807  * @ib: indirect buffer to fill with padding
808  *
809  */
810 static void sdma_v2_4_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
811 {
812 	struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
813 	u32 pad_count;
814 	int i;
815 
816 	pad_count = (8 - (ib->length_dw & 0x7)) % 8;
817 	for (i = 0; i < pad_count; i++)
818 		if (sdma && sdma->burst_nop && (i == 0))
819 			ib->ptr[ib->length_dw++] =
820 				SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
821 				SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
822 		else
823 			ib->ptr[ib->length_dw++] =
824 				SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
825 }
826 
827 /**
828  * sdma_v2_4_ring_emit_pipeline_sync - sync the pipeline
829  *
830  * @ring: amdgpu_ring pointer
831  *
832  * Make sure all previous operations are completed (CIK).
833  */
834 static void sdma_v2_4_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
835 {
836 	uint32_t seq = ring->fence_drv.sync_seq;
837 	uint64_t addr = ring->fence_drv.gpu_addr;
838 
839 	/* wait for idle */
840 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
841 			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
842 			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
843 			  SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
844 	amdgpu_ring_write(ring, addr & 0xfffffffc);
845 	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
846 	amdgpu_ring_write(ring, seq); /* reference */
847 	amdgpu_ring_write(ring, 0xfffffff); /* mask */
848 	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
849 			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
850 }
851 
852 /**
853  * sdma_v2_4_ring_emit_vm_flush - cik vm flush using sDMA
854  *
855  * @ring: amdgpu_ring pointer
856  * @vm: amdgpu_vm pointer
857  *
858  * Update the page table base and flush the VM TLB
859  * using sDMA (VI).
860  */
861 static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
862 					 unsigned vmid, uint64_t pd_addr)
863 {
864 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
865 			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
866 	if (vmid < 8) {
867 		amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid));
868 	} else {
869 		amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8));
870 	}
871 	amdgpu_ring_write(ring, pd_addr >> 12);
872 
873 	/* flush TLB */
874 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
875 			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
876 	amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
877 	amdgpu_ring_write(ring, 1 << vmid);
878 
879 	/* wait for flush */
880 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
881 			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
882 			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
883 	amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
884 	amdgpu_ring_write(ring, 0);
885 	amdgpu_ring_write(ring, 0); /* reference */
886 	amdgpu_ring_write(ring, 0); /* mask */
887 	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
888 			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
889 }
890 
891 static int sdma_v2_4_early_init(void *handle)
892 {
893 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
894 
895 	adev->sdma.num_instances = SDMA_MAX_INSTANCE;
896 
897 	sdma_v2_4_set_ring_funcs(adev);
898 	sdma_v2_4_set_buffer_funcs(adev);
899 	sdma_v2_4_set_vm_pte_funcs(adev);
900 	sdma_v2_4_set_irq_funcs(adev);
901 
902 	return 0;
903 }
904 
905 static int sdma_v2_4_sw_init(void *handle)
906 {
907 	struct amdgpu_ring *ring;
908 	int r, i;
909 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
910 
911 	/* SDMA trap event */
912 	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 224,
913 			      &adev->sdma.trap_irq);
914 	if (r)
915 		return r;
916 
917 	/* SDMA Privileged inst */
918 	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 241,
919 			      &adev->sdma.illegal_inst_irq);
920 	if (r)
921 		return r;
922 
923 	/* SDMA Privileged inst */
924 	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 247,
925 			      &adev->sdma.illegal_inst_irq);
926 	if (r)
927 		return r;
928 
929 	r = sdma_v2_4_init_microcode(adev);
930 	if (r) {
931 		DRM_ERROR("Failed to load sdma firmware!\n");
932 		return r;
933 	}
934 
935 	for (i = 0; i < adev->sdma.num_instances; i++) {
936 		ring = &adev->sdma.instance[i].ring;
937 		ring->ring_obj = NULL;
938 		ring->use_doorbell = false;
939 		sprintf(ring->name, "sdma%d", i);
940 		r = amdgpu_ring_init(adev, ring, 1024,
941 				     &adev->sdma.trap_irq,
942 				     (i == 0) ?
943 				     AMDGPU_SDMA_IRQ_TRAP0 :
944 				     AMDGPU_SDMA_IRQ_TRAP1);
945 		if (r)
946 			return r;
947 	}
948 
949 	return r;
950 }
951 
952 static int sdma_v2_4_sw_fini(void *handle)
953 {
954 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
955 	int i;
956 
957 	for (i = 0; i < adev->sdma.num_instances; i++)
958 		amdgpu_ring_fini(&adev->sdma.instance[i].ring);
959 
960 	sdma_v2_4_free_microcode(adev);
961 	return 0;
962 }
963 
964 static int sdma_v2_4_hw_init(void *handle)
965 {
966 	int r;
967 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
968 
969 	sdma_v2_4_init_golden_registers(adev);
970 
971 	r = sdma_v2_4_start(adev);
972 	if (r)
973 		return r;
974 
975 	return r;
976 }
977 
978 static int sdma_v2_4_hw_fini(void *handle)
979 {
980 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
981 
982 	sdma_v2_4_enable(adev, false);
983 
984 	return 0;
985 }
986 
987 static int sdma_v2_4_suspend(void *handle)
988 {
989 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
990 
991 	return sdma_v2_4_hw_fini(adev);
992 }
993 
994 static int sdma_v2_4_resume(void *handle)
995 {
996 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
997 
998 	return sdma_v2_4_hw_init(adev);
999 }
1000 
1001 static bool sdma_v2_4_is_idle(void *handle)
1002 {
1003 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1004 	u32 tmp = RREG32(mmSRBM_STATUS2);
1005 
1006 	if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1007 		   SRBM_STATUS2__SDMA1_BUSY_MASK))
1008 	    return false;
1009 
1010 	return true;
1011 }
1012 
1013 static int sdma_v2_4_wait_for_idle(void *handle)
1014 {
1015 	unsigned i;
1016 	u32 tmp;
1017 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1018 
1019 	for (i = 0; i < adev->usec_timeout; i++) {
1020 		tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1021 				SRBM_STATUS2__SDMA1_BUSY_MASK);
1022 
1023 		if (!tmp)
1024 			return 0;
1025 		udelay(1);
1026 	}
1027 	return -ETIMEDOUT;
1028 }
1029 
1030 static int sdma_v2_4_soft_reset(void *handle)
1031 {
1032 	u32 srbm_soft_reset = 0;
1033 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1034 	u32 tmp = RREG32(mmSRBM_STATUS2);
1035 
1036 	if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
1037 		/* sdma0 */
1038 		tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1039 		tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1040 		WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1041 		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1042 	}
1043 	if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
1044 		/* sdma1 */
1045 		tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1046 		tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1047 		WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1048 		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1049 	}
1050 
1051 	if (srbm_soft_reset) {
1052 		tmp = RREG32(mmSRBM_SOFT_RESET);
1053 		tmp |= srbm_soft_reset;
1054 		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1055 		WREG32(mmSRBM_SOFT_RESET, tmp);
1056 		tmp = RREG32(mmSRBM_SOFT_RESET);
1057 
1058 		udelay(50);
1059 
1060 		tmp &= ~srbm_soft_reset;
1061 		WREG32(mmSRBM_SOFT_RESET, tmp);
1062 		tmp = RREG32(mmSRBM_SOFT_RESET);
1063 
1064 		/* Wait a little for things to settle down */
1065 		udelay(50);
1066 	}
1067 
1068 	return 0;
1069 }
1070 
1071 static int sdma_v2_4_set_trap_irq_state(struct amdgpu_device *adev,
1072 					struct amdgpu_irq_src *src,
1073 					unsigned type,
1074 					enum amdgpu_interrupt_state state)
1075 {
1076 	u32 sdma_cntl;
1077 
1078 	switch (type) {
1079 	case AMDGPU_SDMA_IRQ_TRAP0:
1080 		switch (state) {
1081 		case AMDGPU_IRQ_STATE_DISABLE:
1082 			sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1083 			sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1084 			WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1085 			break;
1086 		case AMDGPU_IRQ_STATE_ENABLE:
1087 			sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1088 			sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1089 			WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1090 			break;
1091 		default:
1092 			break;
1093 		}
1094 		break;
1095 	case AMDGPU_SDMA_IRQ_TRAP1:
1096 		switch (state) {
1097 		case AMDGPU_IRQ_STATE_DISABLE:
1098 			sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1099 			sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1100 			WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1101 			break;
1102 		case AMDGPU_IRQ_STATE_ENABLE:
1103 			sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1104 			sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1105 			WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1106 			break;
1107 		default:
1108 			break;
1109 		}
1110 		break;
1111 	default:
1112 		break;
1113 	}
1114 	return 0;
1115 }
1116 
1117 static int sdma_v2_4_process_trap_irq(struct amdgpu_device *adev,
1118 				      struct amdgpu_irq_src *source,
1119 				      struct amdgpu_iv_entry *entry)
1120 {
1121 	u8 instance_id, queue_id;
1122 
1123 	instance_id = (entry->ring_id & 0x3) >> 0;
1124 	queue_id = (entry->ring_id & 0xc) >> 2;
1125 	DRM_DEBUG("IH: SDMA trap\n");
1126 	switch (instance_id) {
1127 	case 0:
1128 		switch (queue_id) {
1129 		case 0:
1130 			amdgpu_fence_process(&adev->sdma.instance[0].ring);
1131 			break;
1132 		case 1:
1133 			/* XXX compute */
1134 			break;
1135 		case 2:
1136 			/* XXX compute */
1137 			break;
1138 		}
1139 		break;
1140 	case 1:
1141 		switch (queue_id) {
1142 		case 0:
1143 			amdgpu_fence_process(&adev->sdma.instance[1].ring);
1144 			break;
1145 		case 1:
1146 			/* XXX compute */
1147 			break;
1148 		case 2:
1149 			/* XXX compute */
1150 			break;
1151 		}
1152 		break;
1153 	}
1154 	return 0;
1155 }
1156 
1157 static int sdma_v2_4_process_illegal_inst_irq(struct amdgpu_device *adev,
1158 					      struct amdgpu_irq_src *source,
1159 					      struct amdgpu_iv_entry *entry)
1160 {
1161 	DRM_ERROR("Illegal instruction in SDMA command stream\n");
1162 	schedule_work(&adev->reset_work);
1163 	return 0;
1164 }
1165 
1166 static int sdma_v2_4_set_clockgating_state(void *handle,
1167 					  enum amd_clockgating_state state)
1168 {
1169 	/* XXX handled via the smc on VI */
1170 	return 0;
1171 }
1172 
1173 static int sdma_v2_4_set_powergating_state(void *handle,
1174 					  enum amd_powergating_state state)
1175 {
1176 	return 0;
1177 }
1178 
1179 static const struct amd_ip_funcs sdma_v2_4_ip_funcs = {
1180 	.name = "sdma_v2_4",
1181 	.early_init = sdma_v2_4_early_init,
1182 	.late_init = NULL,
1183 	.sw_init = sdma_v2_4_sw_init,
1184 	.sw_fini = sdma_v2_4_sw_fini,
1185 	.hw_init = sdma_v2_4_hw_init,
1186 	.hw_fini = sdma_v2_4_hw_fini,
1187 	.suspend = sdma_v2_4_suspend,
1188 	.resume = sdma_v2_4_resume,
1189 	.is_idle = sdma_v2_4_is_idle,
1190 	.wait_for_idle = sdma_v2_4_wait_for_idle,
1191 	.soft_reset = sdma_v2_4_soft_reset,
1192 	.set_clockgating_state = sdma_v2_4_set_clockgating_state,
1193 	.set_powergating_state = sdma_v2_4_set_powergating_state,
1194 };
1195 
1196 static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
1197 	.type = AMDGPU_RING_TYPE_SDMA,
1198 	.align_mask = 0xf,
1199 	.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1200 	.support_64bit_ptrs = false,
1201 	.get_rptr = sdma_v2_4_ring_get_rptr,
1202 	.get_wptr = sdma_v2_4_ring_get_wptr,
1203 	.set_wptr = sdma_v2_4_ring_set_wptr,
1204 	.emit_frame_size =
1205 		6 + /* sdma_v2_4_ring_emit_hdp_flush */
1206 		3 + /* sdma_v2_4_ring_emit_hdp_invalidate */
1207 		6 + /* sdma_v2_4_ring_emit_pipeline_sync */
1208 		12 + /* sdma_v2_4_ring_emit_vm_flush */
1209 		10 + 10 + 10, /* sdma_v2_4_ring_emit_fence x3 for user fence, vm fence */
1210 	.emit_ib_size = 7 + 6, /* sdma_v2_4_ring_emit_ib */
1211 	.emit_ib = sdma_v2_4_ring_emit_ib,
1212 	.emit_fence = sdma_v2_4_ring_emit_fence,
1213 	.emit_pipeline_sync = sdma_v2_4_ring_emit_pipeline_sync,
1214 	.emit_vm_flush = sdma_v2_4_ring_emit_vm_flush,
1215 	.emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush,
1216 	.emit_hdp_invalidate = sdma_v2_4_ring_emit_hdp_invalidate,
1217 	.test_ring = sdma_v2_4_ring_test_ring,
1218 	.test_ib = sdma_v2_4_ring_test_ib,
1219 	.insert_nop = sdma_v2_4_ring_insert_nop,
1220 	.pad_ib = sdma_v2_4_ring_pad_ib,
1221 };
1222 
1223 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev)
1224 {
1225 	int i;
1226 
1227 	for (i = 0; i < adev->sdma.num_instances; i++)
1228 		adev->sdma.instance[i].ring.funcs = &sdma_v2_4_ring_funcs;
1229 }
1230 
1231 static const struct amdgpu_irq_src_funcs sdma_v2_4_trap_irq_funcs = {
1232 	.set = sdma_v2_4_set_trap_irq_state,
1233 	.process = sdma_v2_4_process_trap_irq,
1234 };
1235 
1236 static const struct amdgpu_irq_src_funcs sdma_v2_4_illegal_inst_irq_funcs = {
1237 	.process = sdma_v2_4_process_illegal_inst_irq,
1238 };
1239 
1240 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev)
1241 {
1242 	adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1243 	adev->sdma.trap_irq.funcs = &sdma_v2_4_trap_irq_funcs;
1244 	adev->sdma.illegal_inst_irq.funcs = &sdma_v2_4_illegal_inst_irq_funcs;
1245 }
1246 
1247 /**
1248  * sdma_v2_4_emit_copy_buffer - copy buffer using the sDMA engine
1249  *
1250  * @ring: amdgpu_ring structure holding ring information
1251  * @src_offset: src GPU address
1252  * @dst_offset: dst GPU address
1253  * @byte_count: number of bytes to xfer
1254  *
1255  * Copy GPU buffers using the DMA engine (VI).
1256  * Used by the amdgpu ttm implementation to move pages if
1257  * registered as the asic copy callback.
1258  */
1259 static void sdma_v2_4_emit_copy_buffer(struct amdgpu_ib *ib,
1260 				       uint64_t src_offset,
1261 				       uint64_t dst_offset,
1262 				       uint32_t byte_count)
1263 {
1264 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1265 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1266 	ib->ptr[ib->length_dw++] = byte_count;
1267 	ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1268 	ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1269 	ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1270 	ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1271 	ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1272 }
1273 
1274 /**
1275  * sdma_v2_4_emit_fill_buffer - fill buffer using the sDMA engine
1276  *
1277  * @ring: amdgpu_ring structure holding ring information
1278  * @src_data: value to write to buffer
1279  * @dst_offset: dst GPU address
1280  * @byte_count: number of bytes to xfer
1281  *
1282  * Fill GPU buffers using the DMA engine (VI).
1283  */
1284 static void sdma_v2_4_emit_fill_buffer(struct amdgpu_ib *ib,
1285 				       uint32_t src_data,
1286 				       uint64_t dst_offset,
1287 				       uint32_t byte_count)
1288 {
1289 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1290 	ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1291 	ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1292 	ib->ptr[ib->length_dw++] = src_data;
1293 	ib->ptr[ib->length_dw++] = byte_count;
1294 }
1295 
1296 static const struct amdgpu_buffer_funcs sdma_v2_4_buffer_funcs = {
1297 	.copy_max_bytes = 0x1fffff,
1298 	.copy_num_dw = 7,
1299 	.emit_copy_buffer = sdma_v2_4_emit_copy_buffer,
1300 
1301 	.fill_max_bytes = 0x1fffff,
1302 	.fill_num_dw = 7,
1303 	.emit_fill_buffer = sdma_v2_4_emit_fill_buffer,
1304 };
1305 
1306 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev)
1307 {
1308 	if (adev->mman.buffer_funcs == NULL) {
1309 		adev->mman.buffer_funcs = &sdma_v2_4_buffer_funcs;
1310 		adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1311 	}
1312 }
1313 
1314 static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = {
1315 	.copy_pte_num_dw = 7,
1316 	.copy_pte = sdma_v2_4_vm_copy_pte,
1317 
1318 	.write_pte = sdma_v2_4_vm_write_pte,
1319 
1320 	.set_max_nums_pte_pde = 0x1fffff >> 3,
1321 	.set_pte_pde_num_dw = 10,
1322 	.set_pte_pde = sdma_v2_4_vm_set_pte_pde,
1323 };
1324 
1325 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev)
1326 {
1327 	unsigned i;
1328 
1329 	if (adev->vm_manager.vm_pte_funcs == NULL) {
1330 		adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs;
1331 		for (i = 0; i < adev->sdma.num_instances; i++)
1332 			adev->vm_manager.vm_pte_rings[i] =
1333 				&adev->sdma.instance[i].ring;
1334 
1335 		adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
1336 	}
1337 }
1338 
1339 const struct amdgpu_ip_block_version sdma_v2_4_ip_block =
1340 {
1341 	.type = AMD_IP_BLOCK_TYPE_SDMA,
1342 	.major = 2,
1343 	.minor = 4,
1344 	.rev = 0,
1345 	.funcs = &sdma_v2_4_ip_funcs,
1346 };
1347