1 /*
2  * Copyright 2014 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Alex Deucher
23  */
24 
25 #include <linux/delay.h>
26 #include <linux/firmware.h>
27 #include <linux/module.h>
28 
29 #include "amdgpu.h"
30 #include "amdgpu_ucode.h"
31 #include "amdgpu_trace.h"
32 #include "vi.h"
33 #include "vid.h"
34 
35 #include "oss/oss_2_4_d.h"
36 #include "oss/oss_2_4_sh_mask.h"
37 
38 #include "gmc/gmc_7_1_d.h"
39 #include "gmc/gmc_7_1_sh_mask.h"
40 
41 #include "gca/gfx_8_0_d.h"
42 #include "gca/gfx_8_0_enum.h"
43 #include "gca/gfx_8_0_sh_mask.h"
44 
45 #include "bif/bif_5_0_d.h"
46 #include "bif/bif_5_0_sh_mask.h"
47 
48 #include "iceland_sdma_pkt_open.h"
49 
50 #include "ivsrcid/ivsrcid_vislands30.h"
51 
52 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev);
53 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev);
54 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev);
55 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev);
56 
57 MODULE_FIRMWARE("amdgpu/topaz_sdma.bin");
58 MODULE_FIRMWARE("amdgpu/topaz_sdma1.bin");
59 
60 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
61 {
62 	SDMA0_REGISTER_OFFSET,
63 	SDMA1_REGISTER_OFFSET
64 };
65 
66 static const u32 golden_settings_iceland_a11[] =
67 {
68 	mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
69 	mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
70 	mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
71 	mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
72 };
73 
74 static const u32 iceland_mgcg_cgcg_init[] =
75 {
76 	mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
77 	mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
78 };
79 
80 /*
81  * sDMA - System DMA
82  * Starting with CIK, the GPU has new asynchronous
83  * DMA engines.  These engines are used for compute
84  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
85  * and each one supports 1 ring buffer used for gfx
86  * and 2 queues used for compute.
87  *
88  * The programming model is very similar to the CP
89  * (ring buffer, IBs, etc.), but sDMA has it's own
90  * packet format that is different from the PM4 format
91  * used by the CP. sDMA supports copying data, writing
92  * embedded data, solid fills, and a number of other
93  * things.  It also has support for tiling/detiling of
94  * buffers.
95  */
96 
97 static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev)
98 {
99 	switch (adev->asic_type) {
100 	case CHIP_TOPAZ:
101 		amdgpu_device_program_register_sequence(adev,
102 							iceland_mgcg_cgcg_init,
103 							ARRAY_SIZE(iceland_mgcg_cgcg_init));
104 		amdgpu_device_program_register_sequence(adev,
105 							golden_settings_iceland_a11,
106 							ARRAY_SIZE(golden_settings_iceland_a11));
107 		break;
108 	default:
109 		break;
110 	}
111 }
112 
113 static void sdma_v2_4_free_microcode(struct amdgpu_device *adev)
114 {
115 	int i;
116 
117 	for (i = 0; i < adev->sdma.num_instances; i++)
118 		amdgpu_ucode_release(&adev->sdma.instance[i].fw);
119 }
120 
121 /**
122  * sdma_v2_4_init_microcode - load ucode images from disk
123  *
124  * @adev: amdgpu_device pointer
125  *
126  * Use the firmware interface to load the ucode images into
127  * the driver (not loaded into hw).
128  * Returns 0 on success, error on failure.
129  */
130 static int sdma_v2_4_init_microcode(struct amdgpu_device *adev)
131 {
132 	const char *chip_name;
133 	char fw_name[30];
134 	int err = 0, i;
135 	struct amdgpu_firmware_info *info = NULL;
136 	const struct common_firmware_header *header = NULL;
137 	const struct sdma_firmware_header_v1_0 *hdr;
138 
139 	DRM_DEBUG("\n");
140 
141 	switch (adev->asic_type) {
142 	case CHIP_TOPAZ:
143 		chip_name = "topaz";
144 		break;
145 	default: BUG();
146 	}
147 
148 	for (i = 0; i < adev->sdma.num_instances; i++) {
149 		if (i == 0)
150 			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
151 		else
152 			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
153 		err = amdgpu_ucode_request(adev, &adev->sdma.instance[i].fw, fw_name);
154 		if (err)
155 			goto out;
156 		hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
157 		adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
158 		adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
159 		if (adev->sdma.instance[i].feature_version >= 20)
160 			adev->sdma.instance[i].burst_nop = true;
161 
162 		if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) {
163 			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
164 			info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
165 			info->fw = adev->sdma.instance[i].fw;
166 			header = (const struct common_firmware_header *)info->fw->data;
167 			adev->firmware.fw_size +=
168 				ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
169 		}
170 	}
171 
172 out:
173 	if (err) {
174 		pr_err("sdma_v2_4: Failed to load firmware \"%s\"\n", fw_name);
175 		for (i = 0; i < adev->sdma.num_instances; i++)
176 			amdgpu_ucode_release(&adev->sdma.instance[i].fw);
177 	}
178 	return err;
179 }
180 
181 /**
182  * sdma_v2_4_ring_get_rptr - get the current read pointer
183  *
184  * @ring: amdgpu ring pointer
185  *
186  * Get the current rptr from the hardware (VI+).
187  */
188 static uint64_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring)
189 {
190 	/* XXX check if swapping is necessary on BE */
191 	return *ring->rptr_cpu_addr >> 2;
192 }
193 
194 /**
195  * sdma_v2_4_ring_get_wptr - get the current write pointer
196  *
197  * @ring: amdgpu ring pointer
198  *
199  * Get the current wptr from the hardware (VI+).
200  */
201 static uint64_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring)
202 {
203 	struct amdgpu_device *adev = ring->adev;
204 	u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;
205 
206 	return wptr;
207 }
208 
209 /**
210  * sdma_v2_4_ring_set_wptr - commit the write pointer
211  *
212  * @ring: amdgpu ring pointer
213  *
214  * Write the wptr back to the hardware (VI+).
215  */
216 static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring)
217 {
218 	struct amdgpu_device *adev = ring->adev;
219 
220 	WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], ring->wptr << 2);
221 }
222 
223 static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
224 {
225 	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
226 	int i;
227 
228 	for (i = 0; i < count; i++)
229 		if (sdma && sdma->burst_nop && (i == 0))
230 			amdgpu_ring_write(ring, ring->funcs->nop |
231 				SDMA_PKT_NOP_HEADER_COUNT(count - 1));
232 		else
233 			amdgpu_ring_write(ring, ring->funcs->nop);
234 }
235 
236 /**
237  * sdma_v2_4_ring_emit_ib - Schedule an IB on the DMA engine
238  *
239  * @ring: amdgpu ring pointer
240  * @job: job to retrieve vmid from
241  * @ib: IB object to schedule
242  * @flags: unused
243  *
244  * Schedule an IB in the DMA ring (VI).
245  */
246 static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring,
247 				   struct amdgpu_job *job,
248 				   struct amdgpu_ib *ib,
249 				   uint32_t flags)
250 {
251 	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
252 
253 	/* IB packet must end on a 8 DW boundary */
254 	sdma_v2_4_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
255 
256 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
257 			  SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
258 	/* base must be 32 byte aligned */
259 	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
260 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
261 	amdgpu_ring_write(ring, ib->length_dw);
262 	amdgpu_ring_write(ring, 0);
263 	amdgpu_ring_write(ring, 0);
264 
265 }
266 
267 /**
268  * sdma_v2_4_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
269  *
270  * @ring: amdgpu ring pointer
271  *
272  * Emit an hdp flush packet on the requested DMA ring.
273  */
274 static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring)
275 {
276 	u32 ref_and_mask = 0;
277 
278 	if (ring->me == 0)
279 		ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
280 	else
281 		ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
282 
283 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
284 			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
285 			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
286 	amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
287 	amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
288 	amdgpu_ring_write(ring, ref_and_mask); /* reference */
289 	amdgpu_ring_write(ring, ref_and_mask); /* mask */
290 	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
291 			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
292 }
293 
294 /**
295  * sdma_v2_4_ring_emit_fence - emit a fence on the DMA ring
296  *
297  * @ring: amdgpu ring pointer
298  * @addr: address
299  * @seq: sequence number
300  * @flags: fence related flags
301  *
302  * Add a DMA fence packet to the ring to write
303  * the fence seq number and DMA trap packet to generate
304  * an interrupt if needed (VI).
305  */
306 static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
307 				      unsigned flags)
308 {
309 	bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
310 	/* write the fence */
311 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
312 	amdgpu_ring_write(ring, lower_32_bits(addr));
313 	amdgpu_ring_write(ring, upper_32_bits(addr));
314 	amdgpu_ring_write(ring, lower_32_bits(seq));
315 
316 	/* optionally write high bits as well */
317 	if (write64bit) {
318 		addr += 4;
319 		amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
320 		amdgpu_ring_write(ring, lower_32_bits(addr));
321 		amdgpu_ring_write(ring, upper_32_bits(addr));
322 		amdgpu_ring_write(ring, upper_32_bits(seq));
323 	}
324 
325 	/* generate an interrupt */
326 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
327 	amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
328 }
329 
330 /**
331  * sdma_v2_4_gfx_stop - stop the gfx async dma engines
332  *
333  * @adev: amdgpu_device pointer
334  *
335  * Stop the gfx async dma ring buffers (VI).
336  */
337 static void sdma_v2_4_gfx_stop(struct amdgpu_device *adev)
338 {
339 	u32 rb_cntl, ib_cntl;
340 	int i;
341 
342 	amdgpu_sdma_unset_buffer_funcs_helper(adev);
343 
344 	for (i = 0; i < adev->sdma.num_instances; i++) {
345 		rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
346 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
347 		WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
348 		ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
349 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
350 		WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
351 	}
352 }
353 
354 /**
355  * sdma_v2_4_rlc_stop - stop the compute async dma engines
356  *
357  * @adev: amdgpu_device pointer
358  *
359  * Stop the compute async dma queues (VI).
360  */
361 static void sdma_v2_4_rlc_stop(struct amdgpu_device *adev)
362 {
363 	/* XXX todo */
364 }
365 
366 /**
367  * sdma_v2_4_enable - stop the async dma engines
368  *
369  * @adev: amdgpu_device pointer
370  * @enable: enable/disable the DMA MEs.
371  *
372  * Halt or unhalt the async dma engines (VI).
373  */
374 static void sdma_v2_4_enable(struct amdgpu_device *adev, bool enable)
375 {
376 	u32 f32_cntl;
377 	int i;
378 
379 	if (!enable) {
380 		sdma_v2_4_gfx_stop(adev);
381 		sdma_v2_4_rlc_stop(adev);
382 	}
383 
384 	for (i = 0; i < adev->sdma.num_instances; i++) {
385 		f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
386 		if (enable)
387 			f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
388 		else
389 			f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
390 		WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
391 	}
392 }
393 
394 /**
395  * sdma_v2_4_gfx_resume - setup and start the async dma engines
396  *
397  * @adev: amdgpu_device pointer
398  *
399  * Set up the gfx DMA ring buffers and enable them (VI).
400  * Returns 0 for success, error for failure.
401  */
402 static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev)
403 {
404 	struct amdgpu_ring *ring;
405 	u32 rb_cntl, ib_cntl;
406 	u32 rb_bufsz;
407 	int i, j, r;
408 
409 	for (i = 0; i < adev->sdma.num_instances; i++) {
410 		ring = &adev->sdma.instance[i].ring;
411 
412 		mutex_lock(&adev->srbm_mutex);
413 		for (j = 0; j < 16; j++) {
414 			vi_srbm_select(adev, 0, 0, 0, j);
415 			/* SDMA GFX */
416 			WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
417 			WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
418 		}
419 		vi_srbm_select(adev, 0, 0, 0, 0);
420 		mutex_unlock(&adev->srbm_mutex);
421 
422 		WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
423 		       adev->gfx.config.gb_addr_config & 0x70);
424 
425 		WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
426 
427 		/* Set ring buffer size in dwords */
428 		rb_bufsz = order_base_2(ring->ring_size / 4);
429 		rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
430 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
431 #ifdef __BIG_ENDIAN
432 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
433 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
434 					RPTR_WRITEBACK_SWAP_ENABLE, 1);
435 #endif
436 		WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
437 
438 		/* Initialize the ring buffer's read and write pointers */
439 		WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
440 		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
441 		WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
442 		WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
443 
444 		/* set the wb address whether it's enabled or not */
445 		WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
446 		       upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
447 		WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
448 		       lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
449 
450 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
451 
452 		WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
453 		WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
454 
455 		ring->wptr = 0;
456 		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
457 
458 		/* enable DMA RB */
459 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
460 		WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
461 
462 		ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
463 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
464 #ifdef __BIG_ENDIAN
465 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
466 #endif
467 		/* enable DMA IBs */
468 		WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
469 
470 		ring->sched.ready = true;
471 	}
472 
473 	sdma_v2_4_enable(adev, true);
474 	for (i = 0; i < adev->sdma.num_instances; i++) {
475 		ring = &adev->sdma.instance[i].ring;
476 		r = amdgpu_ring_test_helper(ring);
477 		if (r)
478 			return r;
479 
480 		if (adev->mman.buffer_funcs_ring == ring)
481 			amdgpu_ttm_set_buffer_funcs_status(adev, true);
482 	}
483 
484 	return 0;
485 }
486 
487 /**
488  * sdma_v2_4_rlc_resume - setup and start the async dma engines
489  *
490  * @adev: amdgpu_device pointer
491  *
492  * Set up the compute DMA queues and enable them (VI).
493  * Returns 0 for success, error for failure.
494  */
495 static int sdma_v2_4_rlc_resume(struct amdgpu_device *adev)
496 {
497 	/* XXX todo */
498 	return 0;
499 }
500 
501 
502 /**
503  * sdma_v2_4_start - setup and start the async dma engines
504  *
505  * @adev: amdgpu_device pointer
506  *
507  * Set up the DMA engines and enable them (VI).
508  * Returns 0 for success, error for failure.
509  */
510 static int sdma_v2_4_start(struct amdgpu_device *adev)
511 {
512 	int r;
513 
514 	/* halt the engine before programing */
515 	sdma_v2_4_enable(adev, false);
516 
517 	/* start the gfx rings and rlc compute queues */
518 	r = sdma_v2_4_gfx_resume(adev);
519 	if (r)
520 		return r;
521 	r = sdma_v2_4_rlc_resume(adev);
522 	if (r)
523 		return r;
524 
525 	return 0;
526 }
527 
528 /**
529  * sdma_v2_4_ring_test_ring - simple async dma engine test
530  *
531  * @ring: amdgpu_ring structure holding ring information
532  *
533  * Test the DMA engine by writing using it to write an
534  * value to memory. (VI).
535  * Returns 0 for success, error for failure.
536  */
537 static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring)
538 {
539 	struct amdgpu_device *adev = ring->adev;
540 	unsigned i;
541 	unsigned index;
542 	int r;
543 	u32 tmp;
544 	u64 gpu_addr;
545 
546 	r = amdgpu_device_wb_get(adev, &index);
547 	if (r)
548 		return r;
549 
550 	gpu_addr = adev->wb.gpu_addr + (index * 4);
551 	tmp = 0xCAFEDEAD;
552 	adev->wb.wb[index] = cpu_to_le32(tmp);
553 
554 	r = amdgpu_ring_alloc(ring, 5);
555 	if (r)
556 		goto error_free_wb;
557 
558 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
559 			  SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
560 	amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
561 	amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
562 	amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
563 	amdgpu_ring_write(ring, 0xDEADBEEF);
564 	amdgpu_ring_commit(ring);
565 
566 	for (i = 0; i < adev->usec_timeout; i++) {
567 		tmp = le32_to_cpu(adev->wb.wb[index]);
568 		if (tmp == 0xDEADBEEF)
569 			break;
570 		udelay(1);
571 	}
572 
573 	if (i >= adev->usec_timeout)
574 		r = -ETIMEDOUT;
575 
576 error_free_wb:
577 	amdgpu_device_wb_free(adev, index);
578 	return r;
579 }
580 
581 /**
582  * sdma_v2_4_ring_test_ib - test an IB on the DMA engine
583  *
584  * @ring: amdgpu_ring structure holding ring information
585  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
586  *
587  * Test a simple IB in the DMA ring (VI).
588  * Returns 0 on success, error on failure.
589  */
590 static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring, long timeout)
591 {
592 	struct amdgpu_device *adev = ring->adev;
593 	struct amdgpu_ib ib;
594 	struct dma_fence *f = NULL;
595 	unsigned index;
596 	u32 tmp = 0;
597 	u64 gpu_addr;
598 	long r;
599 
600 	r = amdgpu_device_wb_get(adev, &index);
601 	if (r)
602 		return r;
603 
604 	gpu_addr = adev->wb.gpu_addr + (index * 4);
605 	tmp = 0xCAFEDEAD;
606 	adev->wb.wb[index] = cpu_to_le32(tmp);
607 	memset(&ib, 0, sizeof(ib));
608 	r = amdgpu_ib_get(adev, NULL, 256,
609 					AMDGPU_IB_POOL_DIRECT, &ib);
610 	if (r)
611 		goto err0;
612 
613 	ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
614 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
615 	ib.ptr[1] = lower_32_bits(gpu_addr);
616 	ib.ptr[2] = upper_32_bits(gpu_addr);
617 	ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
618 	ib.ptr[4] = 0xDEADBEEF;
619 	ib.ptr[5] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
620 	ib.ptr[6] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
621 	ib.ptr[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
622 	ib.length_dw = 8;
623 
624 	r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
625 	if (r)
626 		goto err1;
627 
628 	r = dma_fence_wait_timeout(f, false, timeout);
629 	if (r == 0) {
630 		r = -ETIMEDOUT;
631 		goto err1;
632 	} else if (r < 0) {
633 		goto err1;
634 	}
635 	tmp = le32_to_cpu(adev->wb.wb[index]);
636 	if (tmp == 0xDEADBEEF)
637 		r = 0;
638 	else
639 		r = -EINVAL;
640 
641 err1:
642 	amdgpu_ib_free(adev, &ib, NULL);
643 	dma_fence_put(f);
644 err0:
645 	amdgpu_device_wb_free(adev, index);
646 	return r;
647 }
648 
649 /**
650  * sdma_v2_4_vm_copy_pte - update PTEs by copying them from the GART
651  *
652  * @ib: indirect buffer to fill with commands
653  * @pe: addr of the page entry
654  * @src: src addr to copy from
655  * @count: number of page entries to update
656  *
657  * Update PTEs by copying them from the GART using sDMA (CIK).
658  */
659 static void sdma_v2_4_vm_copy_pte(struct amdgpu_ib *ib,
660 				  uint64_t pe, uint64_t src,
661 				  unsigned count)
662 {
663 	unsigned bytes = count * 8;
664 
665 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
666 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
667 	ib->ptr[ib->length_dw++] = bytes;
668 	ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
669 	ib->ptr[ib->length_dw++] = lower_32_bits(src);
670 	ib->ptr[ib->length_dw++] = upper_32_bits(src);
671 	ib->ptr[ib->length_dw++] = lower_32_bits(pe);
672 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
673 }
674 
675 /**
676  * sdma_v2_4_vm_write_pte - update PTEs by writing them manually
677  *
678  * @ib: indirect buffer to fill with commands
679  * @pe: addr of the page entry
680  * @value: dst addr to write into pe
681  * @count: number of page entries to update
682  * @incr: increase next addr by incr bytes
683  *
684  * Update PTEs by writing them manually using sDMA (CIK).
685  */
686 static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
687 				   uint64_t value, unsigned count,
688 				   uint32_t incr)
689 {
690 	unsigned ndw = count * 2;
691 
692 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
693 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
694 	ib->ptr[ib->length_dw++] = pe;
695 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
696 	ib->ptr[ib->length_dw++] = ndw;
697 	for (; ndw > 0; ndw -= 2) {
698 		ib->ptr[ib->length_dw++] = lower_32_bits(value);
699 		ib->ptr[ib->length_dw++] = upper_32_bits(value);
700 		value += incr;
701 	}
702 }
703 
704 /**
705  * sdma_v2_4_vm_set_pte_pde - update the page tables using sDMA
706  *
707  * @ib: indirect buffer to fill with commands
708  * @pe: addr of the page entry
709  * @addr: dst addr to write into pe
710  * @count: number of page entries to update
711  * @incr: increase next addr by incr bytes
712  * @flags: access flags
713  *
714  * Update the page tables using sDMA (CIK).
715  */
716 static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
717 				     uint64_t addr, unsigned count,
718 				     uint32_t incr, uint64_t flags)
719 {
720 	/* for physically contiguous pages (vram) */
721 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
722 	ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
723 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
724 	ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
725 	ib->ptr[ib->length_dw++] = upper_32_bits(flags);
726 	ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
727 	ib->ptr[ib->length_dw++] = upper_32_bits(addr);
728 	ib->ptr[ib->length_dw++] = incr; /* increment size */
729 	ib->ptr[ib->length_dw++] = 0;
730 	ib->ptr[ib->length_dw++] = count; /* number of entries */
731 }
732 
733 /**
734  * sdma_v2_4_ring_pad_ib - pad the IB to the required number of dw
735  *
736  * @ring: amdgpu_ring structure holding ring information
737  * @ib: indirect buffer to fill with padding
738  *
739  */
740 static void sdma_v2_4_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
741 {
742 	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
743 	u32 pad_count;
744 	int i;
745 
746 	pad_count = (-ib->length_dw) & 7;
747 	for (i = 0; i < pad_count; i++)
748 		if (sdma && sdma->burst_nop && (i == 0))
749 			ib->ptr[ib->length_dw++] =
750 				SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
751 				SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
752 		else
753 			ib->ptr[ib->length_dw++] =
754 				SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
755 }
756 
757 /**
758  * sdma_v2_4_ring_emit_pipeline_sync - sync the pipeline
759  *
760  * @ring: amdgpu_ring pointer
761  *
762  * Make sure all previous operations are completed (CIK).
763  */
764 static void sdma_v2_4_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
765 {
766 	uint32_t seq = ring->fence_drv.sync_seq;
767 	uint64_t addr = ring->fence_drv.gpu_addr;
768 
769 	/* wait for idle */
770 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
771 			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
772 			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
773 			  SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
774 	amdgpu_ring_write(ring, addr & 0xfffffffc);
775 	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
776 	amdgpu_ring_write(ring, seq); /* reference */
777 	amdgpu_ring_write(ring, 0xffffffff); /* mask */
778 	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
779 			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
780 }
781 
782 /**
783  * sdma_v2_4_ring_emit_vm_flush - cik vm flush using sDMA
784  *
785  * @ring: amdgpu_ring pointer
786  * @vmid: vmid number to use
787  * @pd_addr: address
788  *
789  * Update the page table base and flush the VM TLB
790  * using sDMA (VI).
791  */
792 static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
793 					 unsigned vmid, uint64_t pd_addr)
794 {
795 	amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
796 
797 	/* wait for flush */
798 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
799 			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
800 			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
801 	amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
802 	amdgpu_ring_write(ring, 0);
803 	amdgpu_ring_write(ring, 0); /* reference */
804 	amdgpu_ring_write(ring, 0); /* mask */
805 	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
806 			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
807 }
808 
809 static void sdma_v2_4_ring_emit_wreg(struct amdgpu_ring *ring,
810 				     uint32_t reg, uint32_t val)
811 {
812 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
813 			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
814 	amdgpu_ring_write(ring, reg);
815 	amdgpu_ring_write(ring, val);
816 }
817 
818 static int sdma_v2_4_early_init(void *handle)
819 {
820 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
821 
822 	adev->sdma.num_instances = SDMA_MAX_INSTANCE;
823 
824 	sdma_v2_4_set_ring_funcs(adev);
825 	sdma_v2_4_set_buffer_funcs(adev);
826 	sdma_v2_4_set_vm_pte_funcs(adev);
827 	sdma_v2_4_set_irq_funcs(adev);
828 
829 	return 0;
830 }
831 
832 static int sdma_v2_4_sw_init(void *handle)
833 {
834 	struct amdgpu_ring *ring;
835 	int r, i;
836 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
837 
838 	/* SDMA trap event */
839 	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP,
840 			      &adev->sdma.trap_irq);
841 	if (r)
842 		return r;
843 
844 	/* SDMA Privileged inst */
845 	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 241,
846 			      &adev->sdma.illegal_inst_irq);
847 	if (r)
848 		return r;
849 
850 	/* SDMA Privileged inst */
851 	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE,
852 			      &adev->sdma.illegal_inst_irq);
853 	if (r)
854 		return r;
855 
856 	r = sdma_v2_4_init_microcode(adev);
857 	if (r) {
858 		DRM_ERROR("Failed to load sdma firmware!\n");
859 		return r;
860 	}
861 
862 	for (i = 0; i < adev->sdma.num_instances; i++) {
863 		ring = &adev->sdma.instance[i].ring;
864 		ring->ring_obj = NULL;
865 		ring->use_doorbell = false;
866 		sprintf(ring->name, "sdma%d", i);
867 		r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
868 				     (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 :
869 				     AMDGPU_SDMA_IRQ_INSTANCE1,
870 				     AMDGPU_RING_PRIO_DEFAULT, NULL);
871 		if (r)
872 			return r;
873 	}
874 
875 	return r;
876 }
877 
878 static int sdma_v2_4_sw_fini(void *handle)
879 {
880 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
881 	int i;
882 
883 	for (i = 0; i < adev->sdma.num_instances; i++)
884 		amdgpu_ring_fini(&adev->sdma.instance[i].ring);
885 
886 	sdma_v2_4_free_microcode(adev);
887 	return 0;
888 }
889 
890 static int sdma_v2_4_hw_init(void *handle)
891 {
892 	int r;
893 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
894 
895 	sdma_v2_4_init_golden_registers(adev);
896 
897 	r = sdma_v2_4_start(adev);
898 	if (r)
899 		return r;
900 
901 	return r;
902 }
903 
904 static int sdma_v2_4_hw_fini(void *handle)
905 {
906 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
907 
908 	sdma_v2_4_enable(adev, false);
909 
910 	return 0;
911 }
912 
913 static int sdma_v2_4_suspend(void *handle)
914 {
915 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
916 
917 	return sdma_v2_4_hw_fini(adev);
918 }
919 
920 static int sdma_v2_4_resume(void *handle)
921 {
922 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
923 
924 	return sdma_v2_4_hw_init(adev);
925 }
926 
927 static bool sdma_v2_4_is_idle(void *handle)
928 {
929 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
930 	u32 tmp = RREG32(mmSRBM_STATUS2);
931 
932 	if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
933 		   SRBM_STATUS2__SDMA1_BUSY_MASK))
934 	    return false;
935 
936 	return true;
937 }
938 
939 static int sdma_v2_4_wait_for_idle(void *handle)
940 {
941 	unsigned i;
942 	u32 tmp;
943 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
944 
945 	for (i = 0; i < adev->usec_timeout; i++) {
946 		tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
947 				SRBM_STATUS2__SDMA1_BUSY_MASK);
948 
949 		if (!tmp)
950 			return 0;
951 		udelay(1);
952 	}
953 	return -ETIMEDOUT;
954 }
955 
956 static int sdma_v2_4_soft_reset(void *handle)
957 {
958 	u32 srbm_soft_reset = 0;
959 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
960 	u32 tmp = RREG32(mmSRBM_STATUS2);
961 
962 	if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
963 		/* sdma0 */
964 		tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
965 		tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
966 		WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
967 		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
968 	}
969 	if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
970 		/* sdma1 */
971 		tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
972 		tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
973 		WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
974 		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
975 	}
976 
977 	if (srbm_soft_reset) {
978 		tmp = RREG32(mmSRBM_SOFT_RESET);
979 		tmp |= srbm_soft_reset;
980 		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
981 		WREG32(mmSRBM_SOFT_RESET, tmp);
982 		tmp = RREG32(mmSRBM_SOFT_RESET);
983 
984 		udelay(50);
985 
986 		tmp &= ~srbm_soft_reset;
987 		WREG32(mmSRBM_SOFT_RESET, tmp);
988 		tmp = RREG32(mmSRBM_SOFT_RESET);
989 
990 		/* Wait a little for things to settle down */
991 		udelay(50);
992 	}
993 
994 	return 0;
995 }
996 
997 static int sdma_v2_4_set_trap_irq_state(struct amdgpu_device *adev,
998 					struct amdgpu_irq_src *src,
999 					unsigned type,
1000 					enum amdgpu_interrupt_state state)
1001 {
1002 	u32 sdma_cntl;
1003 
1004 	switch (type) {
1005 	case AMDGPU_SDMA_IRQ_INSTANCE0:
1006 		switch (state) {
1007 		case AMDGPU_IRQ_STATE_DISABLE:
1008 			sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1009 			sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1010 			WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1011 			break;
1012 		case AMDGPU_IRQ_STATE_ENABLE:
1013 			sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1014 			sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1015 			WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1016 			break;
1017 		default:
1018 			break;
1019 		}
1020 		break;
1021 	case AMDGPU_SDMA_IRQ_INSTANCE1:
1022 		switch (state) {
1023 		case AMDGPU_IRQ_STATE_DISABLE:
1024 			sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1025 			sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1026 			WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1027 			break;
1028 		case AMDGPU_IRQ_STATE_ENABLE:
1029 			sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1030 			sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1031 			WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1032 			break;
1033 		default:
1034 			break;
1035 		}
1036 		break;
1037 	default:
1038 		break;
1039 	}
1040 	return 0;
1041 }
1042 
1043 static int sdma_v2_4_process_trap_irq(struct amdgpu_device *adev,
1044 				      struct amdgpu_irq_src *source,
1045 				      struct amdgpu_iv_entry *entry)
1046 {
1047 	u8 instance_id, queue_id;
1048 
1049 	instance_id = (entry->ring_id & 0x3) >> 0;
1050 	queue_id = (entry->ring_id & 0xc) >> 2;
1051 	DRM_DEBUG("IH: SDMA trap\n");
1052 	switch (instance_id) {
1053 	case 0:
1054 		switch (queue_id) {
1055 		case 0:
1056 			amdgpu_fence_process(&adev->sdma.instance[0].ring);
1057 			break;
1058 		case 1:
1059 			/* XXX compute */
1060 			break;
1061 		case 2:
1062 			/* XXX compute */
1063 			break;
1064 		}
1065 		break;
1066 	case 1:
1067 		switch (queue_id) {
1068 		case 0:
1069 			amdgpu_fence_process(&adev->sdma.instance[1].ring);
1070 			break;
1071 		case 1:
1072 			/* XXX compute */
1073 			break;
1074 		case 2:
1075 			/* XXX compute */
1076 			break;
1077 		}
1078 		break;
1079 	}
1080 	return 0;
1081 }
1082 
1083 static int sdma_v2_4_process_illegal_inst_irq(struct amdgpu_device *adev,
1084 					      struct amdgpu_irq_src *source,
1085 					      struct amdgpu_iv_entry *entry)
1086 {
1087 	u8 instance_id, queue_id;
1088 
1089 	DRM_ERROR("Illegal instruction in SDMA command stream\n");
1090 	instance_id = (entry->ring_id & 0x3) >> 0;
1091 	queue_id = (entry->ring_id & 0xc) >> 2;
1092 
1093 	if (instance_id <= 1 && queue_id == 0)
1094 		drm_sched_fault(&adev->sdma.instance[instance_id].ring.sched);
1095 	return 0;
1096 }
1097 
1098 static int sdma_v2_4_set_clockgating_state(void *handle,
1099 					  enum amd_clockgating_state state)
1100 {
1101 	/* XXX handled via the smc on VI */
1102 	return 0;
1103 }
1104 
1105 static int sdma_v2_4_set_powergating_state(void *handle,
1106 					  enum amd_powergating_state state)
1107 {
1108 	return 0;
1109 }
1110 
1111 static const struct amd_ip_funcs sdma_v2_4_ip_funcs = {
1112 	.name = "sdma_v2_4",
1113 	.early_init = sdma_v2_4_early_init,
1114 	.late_init = NULL,
1115 	.sw_init = sdma_v2_4_sw_init,
1116 	.sw_fini = sdma_v2_4_sw_fini,
1117 	.hw_init = sdma_v2_4_hw_init,
1118 	.hw_fini = sdma_v2_4_hw_fini,
1119 	.suspend = sdma_v2_4_suspend,
1120 	.resume = sdma_v2_4_resume,
1121 	.is_idle = sdma_v2_4_is_idle,
1122 	.wait_for_idle = sdma_v2_4_wait_for_idle,
1123 	.soft_reset = sdma_v2_4_soft_reset,
1124 	.set_clockgating_state = sdma_v2_4_set_clockgating_state,
1125 	.set_powergating_state = sdma_v2_4_set_powergating_state,
1126 };
1127 
1128 static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
1129 	.type = AMDGPU_RING_TYPE_SDMA,
1130 	.align_mask = 0xf,
1131 	.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1132 	.support_64bit_ptrs = false,
1133 	.secure_submission_supported = true,
1134 	.get_rptr = sdma_v2_4_ring_get_rptr,
1135 	.get_wptr = sdma_v2_4_ring_get_wptr,
1136 	.set_wptr = sdma_v2_4_ring_set_wptr,
1137 	.emit_frame_size =
1138 		6 + /* sdma_v2_4_ring_emit_hdp_flush */
1139 		3 + /* hdp invalidate */
1140 		6 + /* sdma_v2_4_ring_emit_pipeline_sync */
1141 		VI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v2_4_ring_emit_vm_flush */
1142 		10 + 10 + 10, /* sdma_v2_4_ring_emit_fence x3 for user fence, vm fence */
1143 	.emit_ib_size = 7 + 6, /* sdma_v2_4_ring_emit_ib */
1144 	.emit_ib = sdma_v2_4_ring_emit_ib,
1145 	.emit_fence = sdma_v2_4_ring_emit_fence,
1146 	.emit_pipeline_sync = sdma_v2_4_ring_emit_pipeline_sync,
1147 	.emit_vm_flush = sdma_v2_4_ring_emit_vm_flush,
1148 	.emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush,
1149 	.test_ring = sdma_v2_4_ring_test_ring,
1150 	.test_ib = sdma_v2_4_ring_test_ib,
1151 	.insert_nop = sdma_v2_4_ring_insert_nop,
1152 	.pad_ib = sdma_v2_4_ring_pad_ib,
1153 	.emit_wreg = sdma_v2_4_ring_emit_wreg,
1154 };
1155 
1156 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev)
1157 {
1158 	int i;
1159 
1160 	for (i = 0; i < adev->sdma.num_instances; i++) {
1161 		adev->sdma.instance[i].ring.funcs = &sdma_v2_4_ring_funcs;
1162 		adev->sdma.instance[i].ring.me = i;
1163 	}
1164 }
1165 
1166 static const struct amdgpu_irq_src_funcs sdma_v2_4_trap_irq_funcs = {
1167 	.set = sdma_v2_4_set_trap_irq_state,
1168 	.process = sdma_v2_4_process_trap_irq,
1169 };
1170 
1171 static const struct amdgpu_irq_src_funcs sdma_v2_4_illegal_inst_irq_funcs = {
1172 	.process = sdma_v2_4_process_illegal_inst_irq,
1173 };
1174 
1175 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev)
1176 {
1177 	adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1178 	adev->sdma.trap_irq.funcs = &sdma_v2_4_trap_irq_funcs;
1179 	adev->sdma.illegal_inst_irq.funcs = &sdma_v2_4_illegal_inst_irq_funcs;
1180 }
1181 
1182 /**
1183  * sdma_v2_4_emit_copy_buffer - copy buffer using the sDMA engine
1184  *
1185  * @ib: indirect buffer to copy to
1186  * @src_offset: src GPU address
1187  * @dst_offset: dst GPU address
1188  * @byte_count: number of bytes to xfer
1189  * @tmz: unused
1190  *
1191  * Copy GPU buffers using the DMA engine (VI).
1192  * Used by the amdgpu ttm implementation to move pages if
1193  * registered as the asic copy callback.
1194  */
1195 static void sdma_v2_4_emit_copy_buffer(struct amdgpu_ib *ib,
1196 				       uint64_t src_offset,
1197 				       uint64_t dst_offset,
1198 				       uint32_t byte_count,
1199 				       bool tmz)
1200 {
1201 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1202 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1203 	ib->ptr[ib->length_dw++] = byte_count;
1204 	ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1205 	ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1206 	ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1207 	ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1208 	ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1209 }
1210 
1211 /**
1212  * sdma_v2_4_emit_fill_buffer - fill buffer using the sDMA engine
1213  *
1214  * @ib: indirect buffer to copy to
1215  * @src_data: value to write to buffer
1216  * @dst_offset: dst GPU address
1217  * @byte_count: number of bytes to xfer
1218  *
1219  * Fill GPU buffers using the DMA engine (VI).
1220  */
1221 static void sdma_v2_4_emit_fill_buffer(struct amdgpu_ib *ib,
1222 				       uint32_t src_data,
1223 				       uint64_t dst_offset,
1224 				       uint32_t byte_count)
1225 {
1226 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1227 	ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1228 	ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1229 	ib->ptr[ib->length_dw++] = src_data;
1230 	ib->ptr[ib->length_dw++] = byte_count;
1231 }
1232 
1233 static const struct amdgpu_buffer_funcs sdma_v2_4_buffer_funcs = {
1234 	.copy_max_bytes = 0x1fffff,
1235 	.copy_num_dw = 7,
1236 	.emit_copy_buffer = sdma_v2_4_emit_copy_buffer,
1237 
1238 	.fill_max_bytes = 0x1fffff,
1239 	.fill_num_dw = 7,
1240 	.emit_fill_buffer = sdma_v2_4_emit_fill_buffer,
1241 };
1242 
1243 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev)
1244 {
1245 	adev->mman.buffer_funcs = &sdma_v2_4_buffer_funcs;
1246 	adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1247 }
1248 
1249 static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = {
1250 	.copy_pte_num_dw = 7,
1251 	.copy_pte = sdma_v2_4_vm_copy_pte,
1252 
1253 	.write_pte = sdma_v2_4_vm_write_pte,
1254 	.set_pte_pde = sdma_v2_4_vm_set_pte_pde,
1255 };
1256 
1257 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev)
1258 {
1259 	unsigned i;
1260 
1261 	adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs;
1262 	for (i = 0; i < adev->sdma.num_instances; i++) {
1263 		adev->vm_manager.vm_pte_scheds[i] =
1264 			&adev->sdma.instance[i].ring.sched;
1265 	}
1266 	adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1267 }
1268 
1269 const struct amdgpu_ip_block_version sdma_v2_4_ip_block =
1270 {
1271 	.type = AMD_IP_BLOCK_TYPE_SDMA,
1272 	.major = 2,
1273 	.minor = 4,
1274 	.rev = 0,
1275 	.funcs = &sdma_v2_4_ip_funcs,
1276 };
1277