1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_ucode.h" 28 #include "amdgpu_trace.h" 29 #include "vi.h" 30 #include "vid.h" 31 32 #include "oss/oss_2_4_d.h" 33 #include "oss/oss_2_4_sh_mask.h" 34 35 #include "gmc/gmc_7_1_d.h" 36 #include "gmc/gmc_7_1_sh_mask.h" 37 38 #include "gca/gfx_8_0_d.h" 39 #include "gca/gfx_8_0_enum.h" 40 #include "gca/gfx_8_0_sh_mask.h" 41 42 #include "bif/bif_5_0_d.h" 43 #include "bif/bif_5_0_sh_mask.h" 44 45 #include "iceland_sdma_pkt_open.h" 46 47 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev); 48 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev); 49 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev); 50 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev); 51 52 MODULE_FIRMWARE("amdgpu/topaz_sdma.bin"); 53 MODULE_FIRMWARE("amdgpu/topaz_sdma1.bin"); 54 55 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = 56 { 57 SDMA0_REGISTER_OFFSET, 58 SDMA1_REGISTER_OFFSET 59 }; 60 61 static const u32 golden_settings_iceland_a11[] = 62 { 63 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 64 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 65 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 66 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 67 }; 68 69 static const u32 iceland_mgcg_cgcg_init[] = 70 { 71 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 72 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 73 }; 74 75 /* 76 * sDMA - System DMA 77 * Starting with CIK, the GPU has new asynchronous 78 * DMA engines. These engines are used for compute 79 * and gfx. There are two DMA engines (SDMA0, SDMA1) 80 * and each one supports 1 ring buffer used for gfx 81 * and 2 queues used for compute. 82 * 83 * The programming model is very similar to the CP 84 * (ring buffer, IBs, etc.), but sDMA has it's own 85 * packet format that is different from the PM4 format 86 * used by the CP. sDMA supports copying data, writing 87 * embedded data, solid fills, and a number of other 88 * things. It also has support for tiling/detiling of 89 * buffers. 90 */ 91 92 static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev) 93 { 94 switch (adev->asic_type) { 95 case CHIP_TOPAZ: 96 amdgpu_device_program_register_sequence(adev, 97 iceland_mgcg_cgcg_init, 98 ARRAY_SIZE(iceland_mgcg_cgcg_init)); 99 amdgpu_device_program_register_sequence(adev, 100 golden_settings_iceland_a11, 101 ARRAY_SIZE(golden_settings_iceland_a11)); 102 break; 103 default: 104 break; 105 } 106 } 107 108 static void sdma_v2_4_free_microcode(struct amdgpu_device *adev) 109 { 110 int i; 111 for (i = 0; i < adev->sdma.num_instances; i++) { 112 release_firmware(adev->sdma.instance[i].fw); 113 adev->sdma.instance[i].fw = NULL; 114 } 115 } 116 117 /** 118 * sdma_v2_4_init_microcode - load ucode images from disk 119 * 120 * @adev: amdgpu_device pointer 121 * 122 * Use the firmware interface to load the ucode images into 123 * the driver (not loaded into hw). 124 * Returns 0 on success, error on failure. 125 */ 126 static int sdma_v2_4_init_microcode(struct amdgpu_device *adev) 127 { 128 const char *chip_name; 129 char fw_name[30]; 130 int err = 0, i; 131 struct amdgpu_firmware_info *info = NULL; 132 const struct common_firmware_header *header = NULL; 133 const struct sdma_firmware_header_v1_0 *hdr; 134 135 DRM_DEBUG("\n"); 136 137 switch (adev->asic_type) { 138 case CHIP_TOPAZ: 139 chip_name = "topaz"; 140 break; 141 default: BUG(); 142 } 143 144 for (i = 0; i < adev->sdma.num_instances; i++) { 145 if (i == 0) 146 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 147 else 148 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); 149 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 150 if (err) 151 goto out; 152 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); 153 if (err) 154 goto out; 155 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 156 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 157 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 158 if (adev->sdma.instance[i].feature_version >= 20) 159 adev->sdma.instance[i].burst_nop = true; 160 161 if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) { 162 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 163 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 164 info->fw = adev->sdma.instance[i].fw; 165 header = (const struct common_firmware_header *)info->fw->data; 166 adev->firmware.fw_size += 167 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 168 } 169 } 170 171 out: 172 if (err) { 173 pr_err("sdma_v2_4: Failed to load firmware \"%s\"\n", fw_name); 174 for (i = 0; i < adev->sdma.num_instances; i++) { 175 release_firmware(adev->sdma.instance[i].fw); 176 adev->sdma.instance[i].fw = NULL; 177 } 178 } 179 return err; 180 } 181 182 /** 183 * sdma_v2_4_ring_get_rptr - get the current read pointer 184 * 185 * @ring: amdgpu ring pointer 186 * 187 * Get the current rptr from the hardware (VI+). 188 */ 189 static uint64_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring) 190 { 191 /* XXX check if swapping is necessary on BE */ 192 return ring->adev->wb.wb[ring->rptr_offs] >> 2; 193 } 194 195 /** 196 * sdma_v2_4_ring_get_wptr - get the current write pointer 197 * 198 * @ring: amdgpu ring pointer 199 * 200 * Get the current wptr from the hardware (VI+). 201 */ 202 static uint64_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring) 203 { 204 struct amdgpu_device *adev = ring->adev; 205 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1; 206 u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2; 207 208 return wptr; 209 } 210 211 /** 212 * sdma_v2_4_ring_set_wptr - commit the write pointer 213 * 214 * @ring: amdgpu ring pointer 215 * 216 * Write the wptr back to the hardware (VI+). 217 */ 218 static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring) 219 { 220 struct amdgpu_device *adev = ring->adev; 221 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1; 222 223 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], lower_32_bits(ring->wptr) << 2); 224 } 225 226 static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 227 { 228 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); 229 int i; 230 231 for (i = 0; i < count; i++) 232 if (sdma && sdma->burst_nop && (i == 0)) 233 amdgpu_ring_write(ring, ring->funcs->nop | 234 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 235 else 236 amdgpu_ring_write(ring, ring->funcs->nop); 237 } 238 239 /** 240 * sdma_v2_4_ring_emit_ib - Schedule an IB on the DMA engine 241 * 242 * @ring: amdgpu ring pointer 243 * @ib: IB object to schedule 244 * 245 * Schedule an IB in the DMA ring (VI). 246 */ 247 static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring, 248 struct amdgpu_ib *ib, 249 unsigned vmid, bool ctx_switch) 250 { 251 /* IB packet must end on a 8 DW boundary */ 252 sdma_v2_4_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8); 253 254 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 255 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 256 /* base must be 32 byte aligned */ 257 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 258 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 259 amdgpu_ring_write(ring, ib->length_dw); 260 amdgpu_ring_write(ring, 0); 261 amdgpu_ring_write(ring, 0); 262 263 } 264 265 /** 266 * sdma_v2_4_hdp_flush_ring_emit - emit an hdp flush on the DMA ring 267 * 268 * @ring: amdgpu ring pointer 269 * 270 * Emit an hdp flush packet on the requested DMA ring. 271 */ 272 static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring) 273 { 274 u32 ref_and_mask = 0; 275 276 if (ring == &ring->adev->sdma.instance[0].ring) 277 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); 278 else 279 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); 280 281 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 282 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 283 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 284 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); 285 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); 286 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 287 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 288 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 289 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 290 } 291 292 static void sdma_v2_4_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) 293 { 294 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 295 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 296 amdgpu_ring_write(ring, mmHDP_DEBUG0); 297 amdgpu_ring_write(ring, 1); 298 } 299 /** 300 * sdma_v2_4_ring_emit_fence - emit a fence on the DMA ring 301 * 302 * @ring: amdgpu ring pointer 303 * @fence: amdgpu fence object 304 * 305 * Add a DMA fence packet to the ring to write 306 * the fence seq number and DMA trap packet to generate 307 * an interrupt if needed (VI). 308 */ 309 static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 310 unsigned flags) 311 { 312 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 313 /* write the fence */ 314 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 315 amdgpu_ring_write(ring, lower_32_bits(addr)); 316 amdgpu_ring_write(ring, upper_32_bits(addr)); 317 amdgpu_ring_write(ring, lower_32_bits(seq)); 318 319 /* optionally write high bits as well */ 320 if (write64bit) { 321 addr += 4; 322 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 323 amdgpu_ring_write(ring, lower_32_bits(addr)); 324 amdgpu_ring_write(ring, upper_32_bits(addr)); 325 amdgpu_ring_write(ring, upper_32_bits(seq)); 326 } 327 328 /* generate an interrupt */ 329 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 330 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 331 } 332 333 /** 334 * sdma_v2_4_gfx_stop - stop the gfx async dma engines 335 * 336 * @adev: amdgpu_device pointer 337 * 338 * Stop the gfx async dma ring buffers (VI). 339 */ 340 static void sdma_v2_4_gfx_stop(struct amdgpu_device *adev) 341 { 342 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 343 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 344 u32 rb_cntl, ib_cntl; 345 int i; 346 347 if ((adev->mman.buffer_funcs_ring == sdma0) || 348 (adev->mman.buffer_funcs_ring == sdma1)) 349 amdgpu_ttm_set_active_vram_size(adev, adev->gmc.visible_vram_size); 350 351 for (i = 0; i < adev->sdma.num_instances; i++) { 352 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 353 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 354 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 355 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 356 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 357 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 358 } 359 sdma0->ready = false; 360 sdma1->ready = false; 361 } 362 363 /** 364 * sdma_v2_4_rlc_stop - stop the compute async dma engines 365 * 366 * @adev: amdgpu_device pointer 367 * 368 * Stop the compute async dma queues (VI). 369 */ 370 static void sdma_v2_4_rlc_stop(struct amdgpu_device *adev) 371 { 372 /* XXX todo */ 373 } 374 375 /** 376 * sdma_v2_4_enable - stop the async dma engines 377 * 378 * @adev: amdgpu_device pointer 379 * @enable: enable/disable the DMA MEs. 380 * 381 * Halt or unhalt the async dma engines (VI). 382 */ 383 static void sdma_v2_4_enable(struct amdgpu_device *adev, bool enable) 384 { 385 u32 f32_cntl; 386 int i; 387 388 if (!enable) { 389 sdma_v2_4_gfx_stop(adev); 390 sdma_v2_4_rlc_stop(adev); 391 } 392 393 for (i = 0; i < adev->sdma.num_instances; i++) { 394 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); 395 if (enable) 396 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); 397 else 398 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); 399 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); 400 } 401 } 402 403 /** 404 * sdma_v2_4_gfx_resume - setup and start the async dma engines 405 * 406 * @adev: amdgpu_device pointer 407 * 408 * Set up the gfx DMA ring buffers and enable them (VI). 409 * Returns 0 for success, error for failure. 410 */ 411 static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev) 412 { 413 struct amdgpu_ring *ring; 414 u32 rb_cntl, ib_cntl; 415 u32 rb_bufsz; 416 u32 wb_offset; 417 int i, j, r; 418 419 for (i = 0; i < adev->sdma.num_instances; i++) { 420 ring = &adev->sdma.instance[i].ring; 421 wb_offset = (ring->rptr_offs * 4); 422 423 mutex_lock(&adev->srbm_mutex); 424 for (j = 0; j < 16; j++) { 425 vi_srbm_select(adev, 0, 0, 0, j); 426 /* SDMA GFX */ 427 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); 428 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); 429 } 430 vi_srbm_select(adev, 0, 0, 0, 0); 431 mutex_unlock(&adev->srbm_mutex); 432 433 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], 434 adev->gfx.config.gb_addr_config & 0x70); 435 436 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); 437 438 /* Set ring buffer size in dwords */ 439 rb_bufsz = order_base_2(ring->ring_size / 4); 440 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 441 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 442 #ifdef __BIG_ENDIAN 443 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 444 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 445 RPTR_WRITEBACK_SWAP_ENABLE, 1); 446 #endif 447 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 448 449 /* Initialize the ring buffer's read and write pointers */ 450 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); 451 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); 452 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); 453 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); 454 455 /* set the wb address whether it's enabled or not */ 456 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], 457 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 458 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], 459 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 460 461 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 462 463 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); 464 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); 465 466 ring->wptr = 0; 467 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2); 468 469 /* enable DMA RB */ 470 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 471 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 472 473 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 474 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 475 #ifdef __BIG_ENDIAN 476 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 477 #endif 478 /* enable DMA IBs */ 479 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 480 481 ring->ready = true; 482 } 483 484 sdma_v2_4_enable(adev, true); 485 for (i = 0; i < adev->sdma.num_instances; i++) { 486 ring = &adev->sdma.instance[i].ring; 487 r = amdgpu_ring_test_ring(ring); 488 if (r) { 489 ring->ready = false; 490 return r; 491 } 492 493 if (adev->mman.buffer_funcs_ring == ring) 494 amdgpu_ttm_set_active_vram_size(adev, adev->gmc.real_vram_size); 495 } 496 497 return 0; 498 } 499 500 /** 501 * sdma_v2_4_rlc_resume - setup and start the async dma engines 502 * 503 * @adev: amdgpu_device pointer 504 * 505 * Set up the compute DMA queues and enable them (VI). 506 * Returns 0 for success, error for failure. 507 */ 508 static int sdma_v2_4_rlc_resume(struct amdgpu_device *adev) 509 { 510 /* XXX todo */ 511 return 0; 512 } 513 514 /** 515 * sdma_v2_4_load_microcode - load the sDMA ME ucode 516 * 517 * @adev: amdgpu_device pointer 518 * 519 * Loads the sDMA0/1 ucode. 520 * Returns 0 for success, -EINVAL if the ucode is not available. 521 */ 522 static int sdma_v2_4_load_microcode(struct amdgpu_device *adev) 523 { 524 const struct sdma_firmware_header_v1_0 *hdr; 525 const __le32 *fw_data; 526 u32 fw_size; 527 int i, j; 528 529 /* halt the MEs */ 530 sdma_v2_4_enable(adev, false); 531 532 for (i = 0; i < adev->sdma.num_instances; i++) { 533 if (!adev->sdma.instance[i].fw) 534 return -EINVAL; 535 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 536 amdgpu_ucode_print_sdma_hdr(&hdr->header); 537 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 538 fw_data = (const __le32 *) 539 (adev->sdma.instance[i].fw->data + 540 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 541 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0); 542 for (j = 0; j < fw_size; j++) 543 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++)); 544 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version); 545 } 546 547 return 0; 548 } 549 550 /** 551 * sdma_v2_4_start - setup and start the async dma engines 552 * 553 * @adev: amdgpu_device pointer 554 * 555 * Set up the DMA engines and enable them (VI). 556 * Returns 0 for success, error for failure. 557 */ 558 static int sdma_v2_4_start(struct amdgpu_device *adev) 559 { 560 int r; 561 562 563 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 564 r = sdma_v2_4_load_microcode(adev); 565 if (r) 566 return r; 567 } 568 569 /* halt the engine before programing */ 570 sdma_v2_4_enable(adev, false); 571 572 /* start the gfx rings and rlc compute queues */ 573 r = sdma_v2_4_gfx_resume(adev); 574 if (r) 575 return r; 576 r = sdma_v2_4_rlc_resume(adev); 577 if (r) 578 return r; 579 580 return 0; 581 } 582 583 /** 584 * sdma_v2_4_ring_test_ring - simple async dma engine test 585 * 586 * @ring: amdgpu_ring structure holding ring information 587 * 588 * Test the DMA engine by writing using it to write an 589 * value to memory. (VI). 590 * Returns 0 for success, error for failure. 591 */ 592 static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring) 593 { 594 struct amdgpu_device *adev = ring->adev; 595 unsigned i; 596 unsigned index; 597 int r; 598 u32 tmp; 599 u64 gpu_addr; 600 601 r = amdgpu_device_wb_get(adev, &index); 602 if (r) { 603 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 604 return r; 605 } 606 607 gpu_addr = adev->wb.gpu_addr + (index * 4); 608 tmp = 0xCAFEDEAD; 609 adev->wb.wb[index] = cpu_to_le32(tmp); 610 611 r = amdgpu_ring_alloc(ring, 5); 612 if (r) { 613 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 614 amdgpu_device_wb_free(adev, index); 615 return r; 616 } 617 618 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 619 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 620 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 621 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 622 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); 623 amdgpu_ring_write(ring, 0xDEADBEEF); 624 amdgpu_ring_commit(ring); 625 626 for (i = 0; i < adev->usec_timeout; i++) { 627 tmp = le32_to_cpu(adev->wb.wb[index]); 628 if (tmp == 0xDEADBEEF) 629 break; 630 DRM_UDELAY(1); 631 } 632 633 if (i < adev->usec_timeout) { 634 DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); 635 } else { 636 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 637 ring->idx, tmp); 638 r = -EINVAL; 639 } 640 amdgpu_device_wb_free(adev, index); 641 642 return r; 643 } 644 645 /** 646 * sdma_v2_4_ring_test_ib - test an IB on the DMA engine 647 * 648 * @ring: amdgpu_ring structure holding ring information 649 * 650 * Test a simple IB in the DMA ring (VI). 651 * Returns 0 on success, error on failure. 652 */ 653 static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring, long timeout) 654 { 655 struct amdgpu_device *adev = ring->adev; 656 struct amdgpu_ib ib; 657 struct dma_fence *f = NULL; 658 unsigned index; 659 u32 tmp = 0; 660 u64 gpu_addr; 661 long r; 662 663 r = amdgpu_device_wb_get(adev, &index); 664 if (r) { 665 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 666 return r; 667 } 668 669 gpu_addr = adev->wb.gpu_addr + (index * 4); 670 tmp = 0xCAFEDEAD; 671 adev->wb.wb[index] = cpu_to_le32(tmp); 672 memset(&ib, 0, sizeof(ib)); 673 r = amdgpu_ib_get(adev, NULL, 256, &ib); 674 if (r) { 675 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 676 goto err0; 677 } 678 679 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 680 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 681 ib.ptr[1] = lower_32_bits(gpu_addr); 682 ib.ptr[2] = upper_32_bits(gpu_addr); 683 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1); 684 ib.ptr[4] = 0xDEADBEEF; 685 ib.ptr[5] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 686 ib.ptr[6] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 687 ib.ptr[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 688 ib.length_dw = 8; 689 690 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 691 if (r) 692 goto err1; 693 694 r = dma_fence_wait_timeout(f, false, timeout); 695 if (r == 0) { 696 DRM_ERROR("amdgpu: IB test timed out\n"); 697 r = -ETIMEDOUT; 698 goto err1; 699 } else if (r < 0) { 700 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 701 goto err1; 702 } 703 tmp = le32_to_cpu(adev->wb.wb[index]); 704 if (tmp == 0xDEADBEEF) { 705 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); 706 r = 0; 707 } else { 708 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); 709 r = -EINVAL; 710 } 711 712 err1: 713 amdgpu_ib_free(adev, &ib, NULL); 714 dma_fence_put(f); 715 err0: 716 amdgpu_device_wb_free(adev, index); 717 return r; 718 } 719 720 /** 721 * sdma_v2_4_vm_copy_pte - update PTEs by copying them from the GART 722 * 723 * @ib: indirect buffer to fill with commands 724 * @pe: addr of the page entry 725 * @src: src addr to copy from 726 * @count: number of page entries to update 727 * 728 * Update PTEs by copying them from the GART using sDMA (CIK). 729 */ 730 static void sdma_v2_4_vm_copy_pte(struct amdgpu_ib *ib, 731 uint64_t pe, uint64_t src, 732 unsigned count) 733 { 734 unsigned bytes = count * 8; 735 736 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 737 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 738 ib->ptr[ib->length_dw++] = bytes; 739 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 740 ib->ptr[ib->length_dw++] = lower_32_bits(src); 741 ib->ptr[ib->length_dw++] = upper_32_bits(src); 742 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 743 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 744 } 745 746 /** 747 * sdma_v2_4_vm_write_pte - update PTEs by writing them manually 748 * 749 * @ib: indirect buffer to fill with commands 750 * @pe: addr of the page entry 751 * @value: dst addr to write into pe 752 * @count: number of page entries to update 753 * @incr: increase next addr by incr bytes 754 * 755 * Update PTEs by writing them manually using sDMA (CIK). 756 */ 757 static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 758 uint64_t value, unsigned count, 759 uint32_t incr) 760 { 761 unsigned ndw = count * 2; 762 763 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 764 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 765 ib->ptr[ib->length_dw++] = pe; 766 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 767 ib->ptr[ib->length_dw++] = ndw; 768 for (; ndw > 0; ndw -= 2) { 769 ib->ptr[ib->length_dw++] = lower_32_bits(value); 770 ib->ptr[ib->length_dw++] = upper_32_bits(value); 771 value += incr; 772 } 773 } 774 775 /** 776 * sdma_v2_4_vm_set_pte_pde - update the page tables using sDMA 777 * 778 * @ib: indirect buffer to fill with commands 779 * @pe: addr of the page entry 780 * @addr: dst addr to write into pe 781 * @count: number of page entries to update 782 * @incr: increase next addr by incr bytes 783 * @flags: access flags 784 * 785 * Update the page tables using sDMA (CIK). 786 */ 787 static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe, 788 uint64_t addr, unsigned count, 789 uint32_t incr, uint64_t flags) 790 { 791 /* for physically contiguous pages (vram) */ 792 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE); 793 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 794 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 795 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 796 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 797 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 798 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 799 ib->ptr[ib->length_dw++] = incr; /* increment size */ 800 ib->ptr[ib->length_dw++] = 0; 801 ib->ptr[ib->length_dw++] = count; /* number of entries */ 802 } 803 804 /** 805 * sdma_v2_4_ring_pad_ib - pad the IB to the required number of dw 806 * 807 * @ib: indirect buffer to fill with padding 808 * 809 */ 810 static void sdma_v2_4_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 811 { 812 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); 813 u32 pad_count; 814 int i; 815 816 pad_count = (8 - (ib->length_dw & 0x7)) % 8; 817 for (i = 0; i < pad_count; i++) 818 if (sdma && sdma->burst_nop && (i == 0)) 819 ib->ptr[ib->length_dw++] = 820 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 821 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 822 else 823 ib->ptr[ib->length_dw++] = 824 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 825 } 826 827 /** 828 * sdma_v2_4_ring_emit_pipeline_sync - sync the pipeline 829 * 830 * @ring: amdgpu_ring pointer 831 * 832 * Make sure all previous operations are completed (CIK). 833 */ 834 static void sdma_v2_4_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 835 { 836 uint32_t seq = ring->fence_drv.sync_seq; 837 uint64_t addr = ring->fence_drv.gpu_addr; 838 839 /* wait for idle */ 840 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 841 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 842 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 843 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 844 amdgpu_ring_write(ring, addr & 0xfffffffc); 845 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 846 amdgpu_ring_write(ring, seq); /* reference */ 847 amdgpu_ring_write(ring, 0xfffffff); /* mask */ 848 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 849 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 850 } 851 852 /** 853 * sdma_v2_4_ring_emit_vm_flush - cik vm flush using sDMA 854 * 855 * @ring: amdgpu_ring pointer 856 * @vm: amdgpu_vm pointer 857 * 858 * Update the page table base and flush the VM TLB 859 * using sDMA (VI). 860 */ 861 static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring, 862 unsigned vmid, unsigned pasid, 863 uint64_t pd_addr) 864 { 865 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr); 866 867 /* wait for flush */ 868 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 869 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 870 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */ 871 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); 872 amdgpu_ring_write(ring, 0); 873 amdgpu_ring_write(ring, 0); /* reference */ 874 amdgpu_ring_write(ring, 0); /* mask */ 875 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 876 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 877 } 878 879 static void sdma_v2_4_ring_emit_wreg(struct amdgpu_ring *ring, 880 uint32_t reg, uint32_t val) 881 { 882 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 883 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 884 amdgpu_ring_write(ring, reg); 885 amdgpu_ring_write(ring, val); 886 } 887 888 static int sdma_v2_4_early_init(void *handle) 889 { 890 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 891 892 adev->sdma.num_instances = SDMA_MAX_INSTANCE; 893 894 sdma_v2_4_set_ring_funcs(adev); 895 sdma_v2_4_set_buffer_funcs(adev); 896 sdma_v2_4_set_vm_pte_funcs(adev); 897 sdma_v2_4_set_irq_funcs(adev); 898 899 return 0; 900 } 901 902 static int sdma_v2_4_sw_init(void *handle) 903 { 904 struct amdgpu_ring *ring; 905 int r, i; 906 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 907 908 /* SDMA trap event */ 909 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 224, 910 &adev->sdma.trap_irq); 911 if (r) 912 return r; 913 914 /* SDMA Privileged inst */ 915 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 241, 916 &adev->sdma.illegal_inst_irq); 917 if (r) 918 return r; 919 920 /* SDMA Privileged inst */ 921 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 247, 922 &adev->sdma.illegal_inst_irq); 923 if (r) 924 return r; 925 926 r = sdma_v2_4_init_microcode(adev); 927 if (r) { 928 DRM_ERROR("Failed to load sdma firmware!\n"); 929 return r; 930 } 931 932 for (i = 0; i < adev->sdma.num_instances; i++) { 933 ring = &adev->sdma.instance[i].ring; 934 ring->ring_obj = NULL; 935 ring->use_doorbell = false; 936 sprintf(ring->name, "sdma%d", i); 937 r = amdgpu_ring_init(adev, ring, 1024, 938 &adev->sdma.trap_irq, 939 (i == 0) ? 940 AMDGPU_SDMA_IRQ_TRAP0 : 941 AMDGPU_SDMA_IRQ_TRAP1); 942 if (r) 943 return r; 944 } 945 946 return r; 947 } 948 949 static int sdma_v2_4_sw_fini(void *handle) 950 { 951 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 952 int i; 953 954 for (i = 0; i < adev->sdma.num_instances; i++) 955 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 956 957 sdma_v2_4_free_microcode(adev); 958 return 0; 959 } 960 961 static int sdma_v2_4_hw_init(void *handle) 962 { 963 int r; 964 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 965 966 sdma_v2_4_init_golden_registers(adev); 967 968 r = sdma_v2_4_start(adev); 969 if (r) 970 return r; 971 972 return r; 973 } 974 975 static int sdma_v2_4_hw_fini(void *handle) 976 { 977 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 978 979 sdma_v2_4_enable(adev, false); 980 981 return 0; 982 } 983 984 static int sdma_v2_4_suspend(void *handle) 985 { 986 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 987 988 return sdma_v2_4_hw_fini(adev); 989 } 990 991 static int sdma_v2_4_resume(void *handle) 992 { 993 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 994 995 return sdma_v2_4_hw_init(adev); 996 } 997 998 static bool sdma_v2_4_is_idle(void *handle) 999 { 1000 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1001 u32 tmp = RREG32(mmSRBM_STATUS2); 1002 1003 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | 1004 SRBM_STATUS2__SDMA1_BUSY_MASK)) 1005 return false; 1006 1007 return true; 1008 } 1009 1010 static int sdma_v2_4_wait_for_idle(void *handle) 1011 { 1012 unsigned i; 1013 u32 tmp; 1014 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1015 1016 for (i = 0; i < adev->usec_timeout; i++) { 1017 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | 1018 SRBM_STATUS2__SDMA1_BUSY_MASK); 1019 1020 if (!tmp) 1021 return 0; 1022 udelay(1); 1023 } 1024 return -ETIMEDOUT; 1025 } 1026 1027 static int sdma_v2_4_soft_reset(void *handle) 1028 { 1029 u32 srbm_soft_reset = 0; 1030 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1031 u32 tmp = RREG32(mmSRBM_STATUS2); 1032 1033 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) { 1034 /* sdma0 */ 1035 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); 1036 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); 1037 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); 1038 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK; 1039 } 1040 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) { 1041 /* sdma1 */ 1042 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); 1043 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); 1044 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); 1045 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK; 1046 } 1047 1048 if (srbm_soft_reset) { 1049 tmp = RREG32(mmSRBM_SOFT_RESET); 1050 tmp |= srbm_soft_reset; 1051 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1052 WREG32(mmSRBM_SOFT_RESET, tmp); 1053 tmp = RREG32(mmSRBM_SOFT_RESET); 1054 1055 udelay(50); 1056 1057 tmp &= ~srbm_soft_reset; 1058 WREG32(mmSRBM_SOFT_RESET, tmp); 1059 tmp = RREG32(mmSRBM_SOFT_RESET); 1060 1061 /* Wait a little for things to settle down */ 1062 udelay(50); 1063 } 1064 1065 return 0; 1066 } 1067 1068 static int sdma_v2_4_set_trap_irq_state(struct amdgpu_device *adev, 1069 struct amdgpu_irq_src *src, 1070 unsigned type, 1071 enum amdgpu_interrupt_state state) 1072 { 1073 u32 sdma_cntl; 1074 1075 switch (type) { 1076 case AMDGPU_SDMA_IRQ_TRAP0: 1077 switch (state) { 1078 case AMDGPU_IRQ_STATE_DISABLE: 1079 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1080 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1081 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1082 break; 1083 case AMDGPU_IRQ_STATE_ENABLE: 1084 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1085 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1086 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1087 break; 1088 default: 1089 break; 1090 } 1091 break; 1092 case AMDGPU_SDMA_IRQ_TRAP1: 1093 switch (state) { 1094 case AMDGPU_IRQ_STATE_DISABLE: 1095 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1096 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1097 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1098 break; 1099 case AMDGPU_IRQ_STATE_ENABLE: 1100 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1101 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1102 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1103 break; 1104 default: 1105 break; 1106 } 1107 break; 1108 default: 1109 break; 1110 } 1111 return 0; 1112 } 1113 1114 static int sdma_v2_4_process_trap_irq(struct amdgpu_device *adev, 1115 struct amdgpu_irq_src *source, 1116 struct amdgpu_iv_entry *entry) 1117 { 1118 u8 instance_id, queue_id; 1119 1120 instance_id = (entry->ring_id & 0x3) >> 0; 1121 queue_id = (entry->ring_id & 0xc) >> 2; 1122 DRM_DEBUG("IH: SDMA trap\n"); 1123 switch (instance_id) { 1124 case 0: 1125 switch (queue_id) { 1126 case 0: 1127 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1128 break; 1129 case 1: 1130 /* XXX compute */ 1131 break; 1132 case 2: 1133 /* XXX compute */ 1134 break; 1135 } 1136 break; 1137 case 1: 1138 switch (queue_id) { 1139 case 0: 1140 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1141 break; 1142 case 1: 1143 /* XXX compute */ 1144 break; 1145 case 2: 1146 /* XXX compute */ 1147 break; 1148 } 1149 break; 1150 } 1151 return 0; 1152 } 1153 1154 static int sdma_v2_4_process_illegal_inst_irq(struct amdgpu_device *adev, 1155 struct amdgpu_irq_src *source, 1156 struct amdgpu_iv_entry *entry) 1157 { 1158 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1159 schedule_work(&adev->reset_work); 1160 return 0; 1161 } 1162 1163 static int sdma_v2_4_set_clockgating_state(void *handle, 1164 enum amd_clockgating_state state) 1165 { 1166 /* XXX handled via the smc on VI */ 1167 return 0; 1168 } 1169 1170 static int sdma_v2_4_set_powergating_state(void *handle, 1171 enum amd_powergating_state state) 1172 { 1173 return 0; 1174 } 1175 1176 static const struct amd_ip_funcs sdma_v2_4_ip_funcs = { 1177 .name = "sdma_v2_4", 1178 .early_init = sdma_v2_4_early_init, 1179 .late_init = NULL, 1180 .sw_init = sdma_v2_4_sw_init, 1181 .sw_fini = sdma_v2_4_sw_fini, 1182 .hw_init = sdma_v2_4_hw_init, 1183 .hw_fini = sdma_v2_4_hw_fini, 1184 .suspend = sdma_v2_4_suspend, 1185 .resume = sdma_v2_4_resume, 1186 .is_idle = sdma_v2_4_is_idle, 1187 .wait_for_idle = sdma_v2_4_wait_for_idle, 1188 .soft_reset = sdma_v2_4_soft_reset, 1189 .set_clockgating_state = sdma_v2_4_set_clockgating_state, 1190 .set_powergating_state = sdma_v2_4_set_powergating_state, 1191 }; 1192 1193 static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = { 1194 .type = AMDGPU_RING_TYPE_SDMA, 1195 .align_mask = 0xf, 1196 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1197 .support_64bit_ptrs = false, 1198 .get_rptr = sdma_v2_4_ring_get_rptr, 1199 .get_wptr = sdma_v2_4_ring_get_wptr, 1200 .set_wptr = sdma_v2_4_ring_set_wptr, 1201 .emit_frame_size = 1202 6 + /* sdma_v2_4_ring_emit_hdp_flush */ 1203 3 + /* sdma_v2_4_ring_emit_hdp_invalidate */ 1204 6 + /* sdma_v2_4_ring_emit_pipeline_sync */ 1205 VI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v2_4_ring_emit_vm_flush */ 1206 10 + 10 + 10, /* sdma_v2_4_ring_emit_fence x3 for user fence, vm fence */ 1207 .emit_ib_size = 7 + 6, /* sdma_v2_4_ring_emit_ib */ 1208 .emit_ib = sdma_v2_4_ring_emit_ib, 1209 .emit_fence = sdma_v2_4_ring_emit_fence, 1210 .emit_pipeline_sync = sdma_v2_4_ring_emit_pipeline_sync, 1211 .emit_vm_flush = sdma_v2_4_ring_emit_vm_flush, 1212 .emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush, 1213 .emit_hdp_invalidate = sdma_v2_4_ring_emit_hdp_invalidate, 1214 .test_ring = sdma_v2_4_ring_test_ring, 1215 .test_ib = sdma_v2_4_ring_test_ib, 1216 .insert_nop = sdma_v2_4_ring_insert_nop, 1217 .pad_ib = sdma_v2_4_ring_pad_ib, 1218 .emit_wreg = sdma_v2_4_ring_emit_wreg, 1219 }; 1220 1221 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev) 1222 { 1223 int i; 1224 1225 for (i = 0; i < adev->sdma.num_instances; i++) 1226 adev->sdma.instance[i].ring.funcs = &sdma_v2_4_ring_funcs; 1227 } 1228 1229 static const struct amdgpu_irq_src_funcs sdma_v2_4_trap_irq_funcs = { 1230 .set = sdma_v2_4_set_trap_irq_state, 1231 .process = sdma_v2_4_process_trap_irq, 1232 }; 1233 1234 static const struct amdgpu_irq_src_funcs sdma_v2_4_illegal_inst_irq_funcs = { 1235 .process = sdma_v2_4_process_illegal_inst_irq, 1236 }; 1237 1238 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev) 1239 { 1240 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 1241 adev->sdma.trap_irq.funcs = &sdma_v2_4_trap_irq_funcs; 1242 adev->sdma.illegal_inst_irq.funcs = &sdma_v2_4_illegal_inst_irq_funcs; 1243 } 1244 1245 /** 1246 * sdma_v2_4_emit_copy_buffer - copy buffer using the sDMA engine 1247 * 1248 * @ring: amdgpu_ring structure holding ring information 1249 * @src_offset: src GPU address 1250 * @dst_offset: dst GPU address 1251 * @byte_count: number of bytes to xfer 1252 * 1253 * Copy GPU buffers using the DMA engine (VI). 1254 * Used by the amdgpu ttm implementation to move pages if 1255 * registered as the asic copy callback. 1256 */ 1257 static void sdma_v2_4_emit_copy_buffer(struct amdgpu_ib *ib, 1258 uint64_t src_offset, 1259 uint64_t dst_offset, 1260 uint32_t byte_count) 1261 { 1262 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1263 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1264 ib->ptr[ib->length_dw++] = byte_count; 1265 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1266 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1267 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1268 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1269 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1270 } 1271 1272 /** 1273 * sdma_v2_4_emit_fill_buffer - fill buffer using the sDMA engine 1274 * 1275 * @ring: amdgpu_ring structure holding ring information 1276 * @src_data: value to write to buffer 1277 * @dst_offset: dst GPU address 1278 * @byte_count: number of bytes to xfer 1279 * 1280 * Fill GPU buffers using the DMA engine (VI). 1281 */ 1282 static void sdma_v2_4_emit_fill_buffer(struct amdgpu_ib *ib, 1283 uint32_t src_data, 1284 uint64_t dst_offset, 1285 uint32_t byte_count) 1286 { 1287 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1288 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1289 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1290 ib->ptr[ib->length_dw++] = src_data; 1291 ib->ptr[ib->length_dw++] = byte_count; 1292 } 1293 1294 static const struct amdgpu_buffer_funcs sdma_v2_4_buffer_funcs = { 1295 .copy_max_bytes = 0x1fffff, 1296 .copy_num_dw = 7, 1297 .emit_copy_buffer = sdma_v2_4_emit_copy_buffer, 1298 1299 .fill_max_bytes = 0x1fffff, 1300 .fill_num_dw = 7, 1301 .emit_fill_buffer = sdma_v2_4_emit_fill_buffer, 1302 }; 1303 1304 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev) 1305 { 1306 if (adev->mman.buffer_funcs == NULL) { 1307 adev->mman.buffer_funcs = &sdma_v2_4_buffer_funcs; 1308 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1309 } 1310 } 1311 1312 static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = { 1313 .copy_pte_num_dw = 7, 1314 .copy_pte = sdma_v2_4_vm_copy_pte, 1315 1316 .write_pte = sdma_v2_4_vm_write_pte, 1317 1318 .set_max_nums_pte_pde = 0x1fffff >> 3, 1319 .set_pte_pde_num_dw = 10, 1320 .set_pte_pde = sdma_v2_4_vm_set_pte_pde, 1321 }; 1322 1323 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev) 1324 { 1325 unsigned i; 1326 1327 if (adev->vm_manager.vm_pte_funcs == NULL) { 1328 adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs; 1329 for (i = 0; i < adev->sdma.num_instances; i++) 1330 adev->vm_manager.vm_pte_rings[i] = 1331 &adev->sdma.instance[i].ring; 1332 1333 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances; 1334 } 1335 } 1336 1337 const struct amdgpu_ip_block_version sdma_v2_4_ip_block = 1338 { 1339 .type = AMD_IP_BLOCK_TYPE_SDMA, 1340 .major = 2, 1341 .minor = 4, 1342 .rev = 0, 1343 .funcs = &sdma_v2_4_ip_funcs, 1344 }; 1345