1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drmP.h> 28 #include "amdgpu.h" 29 #include "amdgpu_psp.h" 30 #include "amdgpu_ucode.h" 31 #include "soc15_common.h" 32 #include "psp_v3_1.h" 33 34 #include "mp/mp_9_0_offset.h" 35 #include "mp/mp_9_0_sh_mask.h" 36 #include "gc/gc_9_0_offset.h" 37 #include "sdma0/sdma0_4_0_offset.h" 38 #include "nbio/nbio_6_1_offset.h" 39 40 #include "oss/osssys_4_0_offset.h" 41 #include "oss/osssys_4_0_sh_mask.h" 42 43 MODULE_FIRMWARE("amdgpu/vega10_sos.bin"); 44 MODULE_FIRMWARE("amdgpu/vega10_asd.bin"); 45 MODULE_FIRMWARE("amdgpu/vega12_sos.bin"); 46 MODULE_FIRMWARE("amdgpu/vega12_asd.bin"); 47 48 49 #define smnMP1_FIRMWARE_FLAGS 0x3010028 50 51 static uint32_t sos_old_versions[] = {1517616, 1510592, 1448594, 1446554}; 52 53 static bool psp_v3_1_support_vmr_ring(struct psp_context *psp); 54 static int psp_v3_1_ring_stop(struct psp_context *psp, 55 enum psp_ring_type ring_type); 56 57 static int psp_v3_1_init_microcode(struct psp_context *psp) 58 { 59 struct amdgpu_device *adev = psp->adev; 60 const char *chip_name; 61 char fw_name[30]; 62 int err = 0; 63 const struct psp_firmware_header_v1_0 *hdr; 64 65 DRM_DEBUG("\n"); 66 67 switch (adev->asic_type) { 68 case CHIP_VEGA10: 69 chip_name = "vega10"; 70 break; 71 case CHIP_VEGA12: 72 chip_name = "vega12"; 73 break; 74 default: BUG(); 75 } 76 77 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 78 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 79 if (err) 80 goto out; 81 82 err = amdgpu_ucode_validate(adev->psp.sos_fw); 83 if (err) 84 goto out; 85 86 hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 87 adev->psp.sos_fw_version = le32_to_cpu(hdr->header.ucode_version); 88 adev->psp.sos_feature_version = le32_to_cpu(hdr->ucode_feature_version); 89 adev->psp.sos_bin_size = le32_to_cpu(hdr->sos_size_bytes); 90 adev->psp.sys_bin_size = le32_to_cpu(hdr->header.ucode_size_bytes) - 91 le32_to_cpu(hdr->sos_size_bytes); 92 adev->psp.sys_start_addr = (uint8_t *)hdr + 93 le32_to_cpu(hdr->header.ucode_array_offset_bytes); 94 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr + 95 le32_to_cpu(hdr->sos_offset_bytes); 96 97 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 98 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 99 if (err) 100 goto out; 101 102 err = amdgpu_ucode_validate(adev->psp.asd_fw); 103 if (err) 104 goto out; 105 106 hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 107 adev->psp.asd_fw_version = le32_to_cpu(hdr->header.ucode_version); 108 adev->psp.asd_feature_version = le32_to_cpu(hdr->ucode_feature_version); 109 adev->psp.asd_ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes); 110 adev->psp.asd_start_addr = (uint8_t *)hdr + 111 le32_to_cpu(hdr->header.ucode_array_offset_bytes); 112 113 return 0; 114 out: 115 if (err) { 116 dev_err(adev->dev, 117 "psp v3.1: Failed to load firmware \"%s\"\n", 118 fw_name); 119 release_firmware(adev->psp.sos_fw); 120 adev->psp.sos_fw = NULL; 121 release_firmware(adev->psp.asd_fw); 122 adev->psp.asd_fw = NULL; 123 } 124 125 return err; 126 } 127 128 static int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp) 129 { 130 int ret; 131 uint32_t psp_gfxdrv_command_reg = 0; 132 struct amdgpu_device *adev = psp->adev; 133 uint32_t sol_reg; 134 135 /* Check sOS sign of life register to confirm sys driver and sOS 136 * are already been loaded. 137 */ 138 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 139 if (sol_reg) 140 return 0; 141 142 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 143 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 144 0x80000000, 0x80000000, false); 145 if (ret) 146 return ret; 147 148 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 149 150 /* Copy PSP System Driver binary to memory */ 151 memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size); 152 153 /* Provide the sys driver to bootloader */ 154 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 155 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 156 psp_gfxdrv_command_reg = 1 << 16; 157 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 158 psp_gfxdrv_command_reg); 159 160 /* there might be handshake issue with hardware which needs delay */ 161 mdelay(20); 162 163 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 164 0x80000000, 0x80000000, false); 165 166 return ret; 167 } 168 169 static bool psp_v3_1_match_version(struct amdgpu_device *adev, uint32_t ver) 170 { 171 int i; 172 173 if (ver == adev->psp.sos_fw_version) 174 return true; 175 176 /* 177 * Double check if the latest four legacy versions. 178 * If yes, it is still the right version. 179 */ 180 for (i = 0; i < sizeof(sos_old_versions) / sizeof(uint32_t); i++) { 181 if (sos_old_versions[i] == adev->psp.sos_fw_version) 182 return true; 183 } 184 185 return false; 186 } 187 188 static int psp_v3_1_bootloader_load_sos(struct psp_context *psp) 189 { 190 int ret; 191 unsigned int psp_gfxdrv_command_reg = 0; 192 struct amdgpu_device *adev = psp->adev; 193 uint32_t sol_reg, ver; 194 195 /* Check sOS sign of life register to confirm sys driver and sOS 196 * are already been loaded. 197 */ 198 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 199 if (sol_reg) { 200 psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58); 201 printk("sos fw version = 0x%x.\n", psp->sos_fw_version); 202 return 0; 203 } 204 205 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 206 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 207 0x80000000, 0x80000000, false); 208 if (ret) 209 return ret; 210 211 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 212 213 /* Copy Secure OS binary to PSP memory */ 214 memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size); 215 216 /* Provide the PSP secure OS to bootloader */ 217 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 218 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 219 psp_gfxdrv_command_reg = 2 << 16; 220 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 221 psp_gfxdrv_command_reg); 222 223 /* there might be handshake issue with hardware which needs delay */ 224 mdelay(20); 225 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), 226 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 227 0, true); 228 229 ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58); 230 if (!psp_v3_1_match_version(adev, ver)) 231 DRM_WARN("SOS version doesn't match\n"); 232 233 return ret; 234 } 235 236 static int psp_v3_1_ring_init(struct psp_context *psp, 237 enum psp_ring_type ring_type) 238 { 239 int ret = 0; 240 struct psp_ring *ring; 241 struct amdgpu_device *adev = psp->adev; 242 243 ring = &psp->km_ring; 244 245 ring->ring_type = ring_type; 246 247 /* allocate 4k Page of Local Frame Buffer memory for ring */ 248 ring->ring_size = 0x1000; 249 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 250 AMDGPU_GEM_DOMAIN_VRAM, 251 &adev->firmware.rbuf, 252 &ring->ring_mem_mc_addr, 253 (void **)&ring->ring_mem); 254 if (ret) { 255 ring->ring_size = 0; 256 return ret; 257 } 258 259 return 0; 260 } 261 262 static void psp_v3_1_reroute_ih(struct psp_context *psp) 263 { 264 struct amdgpu_device *adev = psp->adev; 265 uint32_t tmp; 266 267 /* Change IH ring for VMC */ 268 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b); 269 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1); 270 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 271 272 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3); 273 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); 274 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); 275 276 mdelay(20); 277 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 278 0x80000000, 0x8000FFFF, false); 279 280 /* Change IH ring for UMC */ 281 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b); 282 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 283 284 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4); 285 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); 286 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); 287 288 mdelay(20); 289 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 290 0x80000000, 0x8000FFFF, false); 291 } 292 293 static int psp_v3_1_ring_create(struct psp_context *psp, 294 enum psp_ring_type ring_type) 295 { 296 int ret = 0; 297 unsigned int psp_ring_reg = 0; 298 struct psp_ring *ring = &psp->km_ring; 299 struct amdgpu_device *adev = psp->adev; 300 301 psp_v3_1_reroute_ih(psp); 302 303 if (psp_v3_1_support_vmr_ring(psp)) { 304 ret = psp_v3_1_ring_stop(psp, ring_type); 305 if (ret) { 306 DRM_ERROR("psp_v3_1_ring_stop_sriov failed!\n"); 307 return ret; 308 } 309 310 /* Write low address of the ring to C2PMSG_102 */ 311 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 312 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg); 313 /* Write high address of the ring to C2PMSG_103 */ 314 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 315 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg); 316 /* No size initialization for sriov */ 317 /* Write the ring initialization command to C2PMSG_101 */ 318 psp_ring_reg = ring_type; 319 psp_ring_reg = psp_ring_reg << 16; 320 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, psp_ring_reg); 321 322 /* there might be hardware handshake issue which needs delay */ 323 mdelay(20); 324 325 /* Wait for response flag (bit 31) in C2PMSG_101 */ 326 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, 327 mmMP0_SMN_C2PMSG_101), 0x80000000, 328 0x8000FFFF, false); 329 } else { 330 331 /* Write low address of the ring to C2PMSG_69 */ 332 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 333 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); 334 /* Write high address of the ring to C2PMSG_70 */ 335 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 336 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); 337 /* Write size of ring to C2PMSG_71 */ 338 psp_ring_reg = ring->ring_size; 339 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); 340 /* Write the ring initialization command to C2PMSG_64 */ 341 psp_ring_reg = ring_type; 342 psp_ring_reg = psp_ring_reg << 16; 343 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 344 345 /* there might be hardware handshake issue which needs delay */ 346 mdelay(20); 347 348 /* Wait for response flag (bit 31) in C2PMSG_64 */ 349 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, 350 mmMP0_SMN_C2PMSG_64), 0x80000000, 351 0x8000FFFF, false); 352 353 } 354 return ret; 355 } 356 357 static int psp_v3_1_ring_stop(struct psp_context *psp, 358 enum psp_ring_type ring_type) 359 { 360 int ret = 0; 361 unsigned int psp_ring_reg = 0; 362 struct amdgpu_device *adev = psp->adev; 363 364 if (psp_v3_1_support_vmr_ring(psp)) { 365 /* Write the Destroy GPCOM ring command to C2PMSG_101 */ 366 psp_ring_reg = GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING; 367 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, psp_ring_reg); 368 369 /* there might be handshake issue which needs delay */ 370 mdelay(20); 371 372 /* Wait for response flag (bit 31) in C2PMSG_101 */ 373 ret = psp_wait_for(psp, 374 SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 375 0x80000000, 0x80000000, false); 376 } else { 377 /* Write the ring destroy command to C2PMSG_64 */ 378 psp_ring_reg = 3 << 16; 379 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 380 381 /* there might be handshake issue which needs delay */ 382 mdelay(20); 383 384 /* Wait for response flag (bit 31) in C2PMSG_64 */ 385 ret = psp_wait_for(psp, 386 SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 387 0x80000000, 0x80000000, false); 388 } 389 390 return ret; 391 } 392 393 static int psp_v3_1_ring_destroy(struct psp_context *psp, 394 enum psp_ring_type ring_type) 395 { 396 int ret = 0; 397 struct psp_ring *ring = &psp->km_ring; 398 struct amdgpu_device *adev = psp->adev; 399 400 ret = psp_v3_1_ring_stop(psp, ring_type); 401 if (ret) 402 DRM_ERROR("Fail to stop psp ring\n"); 403 404 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 405 &ring->ring_mem_mc_addr, 406 (void **)&ring->ring_mem); 407 408 return ret; 409 } 410 411 static int psp_v3_1_cmd_submit(struct psp_context *psp, 412 struct amdgpu_firmware_info *ucode, 413 uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, 414 int index) 415 { 416 unsigned int psp_write_ptr_reg = 0; 417 struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem; 418 struct psp_ring *ring = &psp->km_ring; 419 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 420 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 421 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 422 struct amdgpu_device *adev = psp->adev; 423 uint32_t ring_size_dw = ring->ring_size / 4; 424 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 425 426 /* KM (GPCOM) prepare write pointer */ 427 if (psp_v3_1_support_vmr_ring(psp)) 428 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102); 429 else 430 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); 431 432 /* Update KM RB frame pointer to new frame */ 433 /* write_frame ptr increments by size of rb_frame in bytes */ 434 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 435 if ((psp_write_ptr_reg % ring_size_dw) == 0) 436 write_frame = ring_buffer_start; 437 else 438 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 439 /* Check invalid write_frame ptr address */ 440 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 441 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 442 ring_buffer_start, ring_buffer_end, write_frame); 443 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 444 return -EINVAL; 445 } 446 447 /* Initialize KM RB frame */ 448 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 449 450 /* Update KM RB frame */ 451 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 452 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 453 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 454 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 455 write_frame->fence_value = index; 456 457 /* Update the write Pointer in DWORDs */ 458 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 459 if (psp_v3_1_support_vmr_ring(psp)) { 460 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_write_ptr_reg); 461 /* send interrupt to PSP for SRIOV ring write pointer update */ 462 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 463 GFX_CTRL_CMD_ID_CONSUME_CMD); 464 } else 465 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg); 466 467 return 0; 468 } 469 470 static int 471 psp_v3_1_sram_map(struct amdgpu_device *adev, 472 unsigned int *sram_offset, unsigned int *sram_addr_reg_offset, 473 unsigned int *sram_data_reg_offset, 474 enum AMDGPU_UCODE_ID ucode_id) 475 { 476 int ret = 0; 477 478 switch(ucode_id) { 479 /* TODO: needs to confirm */ 480 #if 0 481 case AMDGPU_UCODE_ID_SMC: 482 *sram_offset = 0; 483 *sram_addr_reg_offset = 0; 484 *sram_data_reg_offset = 0; 485 break; 486 #endif 487 488 case AMDGPU_UCODE_ID_CP_CE: 489 *sram_offset = 0x0; 490 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR); 491 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA); 492 break; 493 494 case AMDGPU_UCODE_ID_CP_PFP: 495 *sram_offset = 0x0; 496 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR); 497 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA); 498 break; 499 500 case AMDGPU_UCODE_ID_CP_ME: 501 *sram_offset = 0x0; 502 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR); 503 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA); 504 break; 505 506 case AMDGPU_UCODE_ID_CP_MEC1: 507 *sram_offset = 0x10000; 508 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR); 509 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); 510 break; 511 512 case AMDGPU_UCODE_ID_CP_MEC2: 513 *sram_offset = 0x10000; 514 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR); 515 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA); 516 break; 517 518 case AMDGPU_UCODE_ID_RLC_G: 519 *sram_offset = 0x2000; 520 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR); 521 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA); 522 break; 523 524 case AMDGPU_UCODE_ID_SDMA0: 525 *sram_offset = 0x0; 526 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR); 527 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA); 528 break; 529 530 /* TODO: needs to confirm */ 531 #if 0 532 case AMDGPU_UCODE_ID_SDMA1: 533 *sram_offset = ; 534 *sram_addr_reg_offset = ; 535 break; 536 537 case AMDGPU_UCODE_ID_UVD: 538 *sram_offset = ; 539 *sram_addr_reg_offset = ; 540 break; 541 542 case AMDGPU_UCODE_ID_VCE: 543 *sram_offset = ; 544 *sram_addr_reg_offset = ; 545 break; 546 #endif 547 548 case AMDGPU_UCODE_ID_MAXIMUM: 549 default: 550 ret = -EINVAL; 551 break; 552 } 553 554 return ret; 555 } 556 557 static bool psp_v3_1_compare_sram_data(struct psp_context *psp, 558 struct amdgpu_firmware_info *ucode, 559 enum AMDGPU_UCODE_ID ucode_type) 560 { 561 int err = 0; 562 unsigned int fw_sram_reg_val = 0; 563 unsigned int fw_sram_addr_reg_offset = 0; 564 unsigned int fw_sram_data_reg_offset = 0; 565 unsigned int ucode_size; 566 uint32_t *ucode_mem = NULL; 567 struct amdgpu_device *adev = psp->adev; 568 569 err = psp_v3_1_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset, 570 &fw_sram_data_reg_offset, ucode_type); 571 if (err) 572 return false; 573 574 WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val); 575 576 ucode_size = ucode->ucode_size; 577 ucode_mem = (uint32_t *)ucode->kaddr; 578 while (ucode_size) { 579 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset); 580 581 if (*ucode_mem != fw_sram_reg_val) 582 return false; 583 584 ucode_mem++; 585 /* 4 bytes */ 586 ucode_size -= 4; 587 } 588 589 return true; 590 } 591 592 static bool psp_v3_1_smu_reload_quirk(struct psp_context *psp) 593 { 594 struct amdgpu_device *adev = psp->adev; 595 uint32_t reg; 596 597 reg = RREG32_PCIE(smnMP1_FIRMWARE_FLAGS | 0x03b00000); 598 return (reg & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) ? true : false; 599 } 600 601 static int psp_v3_1_mode1_reset(struct psp_context *psp) 602 { 603 int ret; 604 uint32_t offset; 605 struct amdgpu_device *adev = psp->adev; 606 607 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); 608 609 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false); 610 611 if (ret) { 612 DRM_INFO("psp is not working correctly before mode1 reset!\n"); 613 return -EINVAL; 614 } 615 616 /*send the mode 1 reset command*/ 617 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST); 618 619 msleep(500); 620 621 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); 622 623 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false); 624 625 if (ret) { 626 DRM_INFO("psp mode 1 reset failed!\n"); 627 return -EINVAL; 628 } 629 630 DRM_INFO("psp mode1 reset succeed \n"); 631 632 return 0; 633 } 634 635 static bool psp_v3_1_support_vmr_ring(struct psp_context *psp) 636 { 637 if (amdgpu_sriov_vf(psp->adev) && psp->sos_fw_version >= 0x80455) 638 return true; 639 640 return false; 641 } 642 643 static const struct psp_funcs psp_v3_1_funcs = { 644 .init_microcode = psp_v3_1_init_microcode, 645 .bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv, 646 .bootloader_load_sos = psp_v3_1_bootloader_load_sos, 647 .ring_init = psp_v3_1_ring_init, 648 .ring_create = psp_v3_1_ring_create, 649 .ring_stop = psp_v3_1_ring_stop, 650 .ring_destroy = psp_v3_1_ring_destroy, 651 .cmd_submit = psp_v3_1_cmd_submit, 652 .compare_sram_data = psp_v3_1_compare_sram_data, 653 .smu_reload_quirk = psp_v3_1_smu_reload_quirk, 654 .mode1_reset = psp_v3_1_mode1_reset, 655 .support_vmr_ring = psp_v3_1_support_vmr_ring, 656 }; 657 658 void psp_v3_1_set_psp_funcs(struct psp_context *psp) 659 { 660 psp->funcs = &psp_v3_1_funcs; 661 } 662