1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include "drmP.h" 28 #include "amdgpu.h" 29 #include "amdgpu_psp.h" 30 #include "amdgpu_ucode.h" 31 #include "soc15_common.h" 32 #include "psp_v3_1.h" 33 34 #include "vega10/soc15ip.h" 35 #include "vega10/MP/mp_9_0_offset.h" 36 #include "vega10/MP/mp_9_0_sh_mask.h" 37 #include "vega10/GC/gc_9_0_offset.h" 38 #include "vega10/SDMA0/sdma0_4_0_offset.h" 39 #include "vega10/NBIO/nbio_6_1_offset.h" 40 41 MODULE_FIRMWARE("amdgpu/vega10_sos.bin"); 42 MODULE_FIRMWARE("amdgpu/vega10_asd.bin"); 43 44 #define smnMP1_FIRMWARE_FLAGS 0x3010028 45 46 static int 47 psp_v3_1_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type) 48 { 49 switch(ucode->ucode_id) { 50 case AMDGPU_UCODE_ID_SDMA0: 51 *type = GFX_FW_TYPE_SDMA0; 52 break; 53 case AMDGPU_UCODE_ID_SDMA1: 54 *type = GFX_FW_TYPE_SDMA1; 55 break; 56 case AMDGPU_UCODE_ID_CP_CE: 57 *type = GFX_FW_TYPE_CP_CE; 58 break; 59 case AMDGPU_UCODE_ID_CP_PFP: 60 *type = GFX_FW_TYPE_CP_PFP; 61 break; 62 case AMDGPU_UCODE_ID_CP_ME: 63 *type = GFX_FW_TYPE_CP_ME; 64 break; 65 case AMDGPU_UCODE_ID_CP_MEC1: 66 *type = GFX_FW_TYPE_CP_MEC; 67 break; 68 case AMDGPU_UCODE_ID_CP_MEC1_JT: 69 *type = GFX_FW_TYPE_CP_MEC_ME1; 70 break; 71 case AMDGPU_UCODE_ID_CP_MEC2: 72 *type = GFX_FW_TYPE_CP_MEC; 73 break; 74 case AMDGPU_UCODE_ID_CP_MEC2_JT: 75 *type = GFX_FW_TYPE_CP_MEC_ME2; 76 break; 77 case AMDGPU_UCODE_ID_RLC_G: 78 *type = GFX_FW_TYPE_RLC_G; 79 break; 80 case AMDGPU_UCODE_ID_SMC: 81 *type = GFX_FW_TYPE_SMU; 82 break; 83 case AMDGPU_UCODE_ID_UVD: 84 *type = GFX_FW_TYPE_UVD; 85 break; 86 case AMDGPU_UCODE_ID_VCE: 87 *type = GFX_FW_TYPE_VCE; 88 break; 89 case AMDGPU_UCODE_ID_MAXIMUM: 90 default: 91 return -EINVAL; 92 } 93 94 return 0; 95 } 96 97 int psp_v3_1_init_microcode(struct psp_context *psp) 98 { 99 struct amdgpu_device *adev = psp->adev; 100 const char *chip_name; 101 char fw_name[30]; 102 int err = 0; 103 const struct psp_firmware_header_v1_0 *hdr; 104 105 DRM_DEBUG("\n"); 106 107 switch (adev->asic_type) { 108 case CHIP_VEGA10: 109 chip_name = "vega10"; 110 break; 111 default: BUG(); 112 } 113 114 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 115 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 116 if (err) 117 goto out; 118 119 err = amdgpu_ucode_validate(adev->psp.sos_fw); 120 if (err) 121 goto out; 122 123 hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 124 adev->psp.sos_fw_version = le32_to_cpu(hdr->header.ucode_version); 125 adev->psp.sos_feature_version = le32_to_cpu(hdr->ucode_feature_version); 126 adev->psp.sos_bin_size = le32_to_cpu(hdr->sos_size_bytes); 127 adev->psp.sys_bin_size = le32_to_cpu(hdr->header.ucode_size_bytes) - 128 le32_to_cpu(hdr->sos_size_bytes); 129 adev->psp.sys_start_addr = (uint8_t *)hdr + 130 le32_to_cpu(hdr->header.ucode_array_offset_bytes); 131 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr + 132 le32_to_cpu(hdr->sos_offset_bytes); 133 134 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 135 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 136 if (err) 137 goto out; 138 139 err = amdgpu_ucode_validate(adev->psp.asd_fw); 140 if (err) 141 goto out; 142 143 hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 144 adev->psp.asd_fw_version = le32_to_cpu(hdr->header.ucode_version); 145 adev->psp.asd_feature_version = le32_to_cpu(hdr->ucode_feature_version); 146 adev->psp.asd_ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes); 147 adev->psp.asd_start_addr = (uint8_t *)hdr + 148 le32_to_cpu(hdr->header.ucode_array_offset_bytes); 149 150 return 0; 151 out: 152 if (err) { 153 dev_err(adev->dev, 154 "psp v3.1: Failed to load firmware \"%s\"\n", 155 fw_name); 156 release_firmware(adev->psp.sos_fw); 157 adev->psp.sos_fw = NULL; 158 release_firmware(adev->psp.asd_fw); 159 adev->psp.asd_fw = NULL; 160 } 161 162 return err; 163 } 164 165 int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp) 166 { 167 int ret; 168 uint32_t psp_gfxdrv_command_reg = 0; 169 struct amdgpu_device *adev = psp->adev; 170 uint32_t sol_reg; 171 172 /* Check sOS sign of life register to confirm sys driver and sOS 173 * are already been loaded. 174 */ 175 sol_reg = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81)); 176 if (sol_reg) 177 return 0; 178 179 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 180 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 181 0x80000000, 0x80000000, false); 182 if (ret) 183 return ret; 184 185 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 186 187 /* Copy PSP System Driver binary to memory */ 188 memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size); 189 190 /* Provide the sys driver to bootrom */ 191 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_36), 192 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 193 psp_gfxdrv_command_reg = 1 << 16; 194 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 195 psp_gfxdrv_command_reg); 196 197 /* there might be handshake issue with hardware which needs delay */ 198 mdelay(20); 199 200 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 201 0x80000000, 0x80000000, false); 202 203 return ret; 204 } 205 206 int psp_v3_1_bootloader_load_sos(struct psp_context *psp) 207 { 208 int ret; 209 unsigned int psp_gfxdrv_command_reg = 0; 210 struct amdgpu_device *adev = psp->adev; 211 uint32_t sol_reg; 212 213 /* Check sOS sign of life register to confirm sys driver and sOS 214 * are already been loaded. 215 */ 216 sol_reg = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81)); 217 if (sol_reg) 218 return 0; 219 220 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 221 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 222 0x80000000, 0x80000000, false); 223 if (ret) 224 return ret; 225 226 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 227 228 /* Copy Secure OS binary to PSP memory */ 229 memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size); 230 231 /* Provide the PSP secure OS to bootrom */ 232 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_36), 233 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 234 psp_gfxdrv_command_reg = 2 << 16; 235 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 236 psp_gfxdrv_command_reg); 237 238 /* there might be handshake issue with hardware which needs delay */ 239 mdelay(20); 240 #if 0 241 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), 242 RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81)), 243 0, true); 244 #endif 245 246 return ret; 247 } 248 249 int psp_v3_1_prep_cmd_buf(struct amdgpu_firmware_info *ucode, struct psp_gfx_cmd_resp *cmd) 250 { 251 int ret; 252 uint64_t fw_mem_mc_addr = ucode->mc_addr; 253 254 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 255 256 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 257 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = (uint32_t)fw_mem_mc_addr; 258 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = (uint32_t)((uint64_t)fw_mem_mc_addr >> 32); 259 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 260 261 ret = psp_v3_1_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 262 if (ret) 263 DRM_ERROR("Unknown firmware type\n"); 264 265 return ret; 266 } 267 268 int psp_v3_1_ring_init(struct psp_context *psp, enum psp_ring_type ring_type) 269 { 270 int ret = 0; 271 struct psp_ring *ring; 272 struct amdgpu_device *adev = psp->adev; 273 274 ring = &psp->km_ring; 275 276 ring->ring_type = ring_type; 277 278 /* allocate 4k Page of Local Frame Buffer memory for ring */ 279 ring->ring_size = 0x1000; 280 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 281 AMDGPU_GEM_DOMAIN_VRAM, 282 &adev->firmware.rbuf, 283 &ring->ring_mem_mc_addr, 284 (void **)&ring->ring_mem); 285 if (ret) { 286 ring->ring_size = 0; 287 return ret; 288 } 289 290 return 0; 291 } 292 293 int psp_v3_1_ring_create(struct psp_context *psp, enum psp_ring_type ring_type) 294 { 295 int ret = 0; 296 unsigned int psp_ring_reg = 0; 297 struct psp_ring *ring = &psp->km_ring; 298 struct amdgpu_device *adev = psp->adev; 299 300 /* Write low address of the ring to C2PMSG_69 */ 301 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 302 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_69), psp_ring_reg); 303 /* Write high address of the ring to C2PMSG_70 */ 304 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 305 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_70), psp_ring_reg); 306 /* Write size of ring to C2PMSG_71 */ 307 psp_ring_reg = ring->ring_size; 308 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_71), psp_ring_reg); 309 /* Write the ring initialization command to C2PMSG_64 */ 310 psp_ring_reg = ring_type; 311 psp_ring_reg = psp_ring_reg << 16; 312 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), psp_ring_reg); 313 314 /* there might be handshake issue with hardware which needs delay */ 315 mdelay(20); 316 317 /* Wait for response flag (bit 31) in C2PMSG_64 */ 318 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 319 0x80000000, 0x8000FFFF, false); 320 321 return ret; 322 } 323 324 int psp_v3_1_ring_destroy(struct psp_context *psp, enum psp_ring_type ring_type) 325 { 326 int ret = 0; 327 struct psp_ring *ring; 328 unsigned int psp_ring_reg = 0; 329 struct amdgpu_device *adev = psp->adev; 330 331 ring = &psp->km_ring; 332 333 /* Write the ring destroy command to C2PMSG_64 */ 334 psp_ring_reg = 3 << 16; 335 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), psp_ring_reg); 336 337 /* there might be handshake issue with hardware which needs delay */ 338 mdelay(20); 339 340 /* Wait for response flag (bit 31) in C2PMSG_64 */ 341 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 342 0x80000000, 0x80000000, false); 343 344 if (ring->ring_mem) 345 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 346 &ring->ring_mem_mc_addr, 347 (void **)&ring->ring_mem); 348 return ret; 349 } 350 351 int psp_v3_1_cmd_submit(struct psp_context *psp, 352 struct amdgpu_firmware_info *ucode, 353 uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, 354 int index) 355 { 356 unsigned int psp_write_ptr_reg = 0; 357 struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem; 358 struct psp_ring *ring = &psp->km_ring; 359 struct amdgpu_device *adev = psp->adev; 360 uint32_t ring_size_dw = ring->ring_size / 4; 361 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 362 363 /* KM (GPCOM) prepare write pointer */ 364 psp_write_ptr_reg = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_67)); 365 366 /* Update KM RB frame pointer to new frame */ 367 /* write_frame ptr increments by size of rb_frame in bytes */ 368 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 369 if ((psp_write_ptr_reg % ring_size_dw) == 0) 370 write_frame = ring->ring_mem; 371 else 372 write_frame = ring->ring_mem + (psp_write_ptr_reg / rb_frame_size_dw); 373 374 /* Initialize KM RB frame */ 375 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 376 377 /* Update KM RB frame */ 378 write_frame->cmd_buf_addr_hi = (unsigned int)(cmd_buf_mc_addr >> 32); 379 write_frame->cmd_buf_addr_lo = (unsigned int)(cmd_buf_mc_addr); 380 write_frame->fence_addr_hi = (unsigned int)(fence_mc_addr >> 32); 381 write_frame->fence_addr_lo = (unsigned int)(fence_mc_addr); 382 write_frame->fence_value = index; 383 384 /* Update the write Pointer in DWORDs */ 385 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 386 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_67), psp_write_ptr_reg); 387 388 return 0; 389 } 390 391 static int 392 psp_v3_1_sram_map(unsigned int *sram_offset, unsigned int *sram_addr_reg_offset, 393 unsigned int *sram_data_reg_offset, 394 enum AMDGPU_UCODE_ID ucode_id) 395 { 396 int ret = 0; 397 398 switch(ucode_id) { 399 /* TODO: needs to confirm */ 400 #if 0 401 case AMDGPU_UCODE_ID_SMC: 402 *sram_offset = 0; 403 *sram_addr_reg_offset = 0; 404 *sram_data_reg_offset = 0; 405 break; 406 #endif 407 408 case AMDGPU_UCODE_ID_CP_CE: 409 *sram_offset = 0x0; 410 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR); 411 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA); 412 break; 413 414 case AMDGPU_UCODE_ID_CP_PFP: 415 *sram_offset = 0x0; 416 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR); 417 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA); 418 break; 419 420 case AMDGPU_UCODE_ID_CP_ME: 421 *sram_offset = 0x0; 422 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR); 423 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA); 424 break; 425 426 case AMDGPU_UCODE_ID_CP_MEC1: 427 *sram_offset = 0x10000; 428 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR); 429 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); 430 break; 431 432 case AMDGPU_UCODE_ID_CP_MEC2: 433 *sram_offset = 0x10000; 434 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR); 435 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA); 436 break; 437 438 case AMDGPU_UCODE_ID_RLC_G: 439 *sram_offset = 0x2000; 440 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR); 441 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA); 442 break; 443 444 case AMDGPU_UCODE_ID_SDMA0: 445 *sram_offset = 0x0; 446 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR); 447 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA); 448 break; 449 450 /* TODO: needs to confirm */ 451 #if 0 452 case AMDGPU_UCODE_ID_SDMA1: 453 *sram_offset = ; 454 *sram_addr_reg_offset = ; 455 break; 456 457 case AMDGPU_UCODE_ID_UVD: 458 *sram_offset = ; 459 *sram_addr_reg_offset = ; 460 break; 461 462 case AMDGPU_UCODE_ID_VCE: 463 *sram_offset = ; 464 *sram_addr_reg_offset = ; 465 break; 466 #endif 467 468 case AMDGPU_UCODE_ID_MAXIMUM: 469 default: 470 ret = -EINVAL; 471 break; 472 } 473 474 return ret; 475 } 476 477 bool psp_v3_1_compare_sram_data(struct psp_context *psp, 478 struct amdgpu_firmware_info *ucode, 479 enum AMDGPU_UCODE_ID ucode_type) 480 { 481 int err = 0; 482 unsigned int fw_sram_reg_val = 0; 483 unsigned int fw_sram_addr_reg_offset = 0; 484 unsigned int fw_sram_data_reg_offset = 0; 485 unsigned int ucode_size; 486 uint32_t *ucode_mem = NULL; 487 struct amdgpu_device *adev = psp->adev; 488 489 err = psp_v3_1_sram_map(&fw_sram_reg_val, &fw_sram_addr_reg_offset, 490 &fw_sram_data_reg_offset, ucode_type); 491 if (err) 492 return false; 493 494 WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val); 495 496 ucode_size = ucode->ucode_size; 497 ucode_mem = (uint32_t *)ucode->kaddr; 498 while (ucode_size) { 499 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset); 500 501 if (*ucode_mem != fw_sram_reg_val) 502 return false; 503 504 ucode_mem++; 505 /* 4 bytes */ 506 ucode_size -= 4; 507 } 508 509 return true; 510 } 511 512 bool psp_v3_1_smu_reload_quirk(struct psp_context *psp) 513 { 514 struct amdgpu_device *adev = psp->adev; 515 uint32_t reg; 516 517 reg = smnMP1_FIRMWARE_FLAGS | 0x03b00000; 518 WREG32(SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2), reg); 519 reg = RREG32(SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2)); 520 return (reg & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) ? true : false; 521 } 522