1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include "drmP.h" 28 #include "amdgpu.h" 29 #include "amdgpu_psp.h" 30 #include "amdgpu_ucode.h" 31 #include "soc15_common.h" 32 #include "psp_v3_1.h" 33 34 #include "vega10/soc15ip.h" 35 #include "vega10/MP/mp_9_0_offset.h" 36 #include "vega10/MP/mp_9_0_sh_mask.h" 37 #include "vega10/GC/gc_9_0_offset.h" 38 #include "vega10/SDMA0/sdma0_4_0_offset.h" 39 #include "vega10/NBIO/nbio_6_1_offset.h" 40 41 MODULE_FIRMWARE("amdgpu/vega10_sos.bin"); 42 MODULE_FIRMWARE("amdgpu/vega10_asd.bin"); 43 44 #define smnMP1_FIRMWARE_FLAGS 0x3010028 45 46 static int 47 psp_v3_1_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type) 48 { 49 switch(ucode->ucode_id) { 50 case AMDGPU_UCODE_ID_SDMA0: 51 *type = GFX_FW_TYPE_SDMA0; 52 break; 53 case AMDGPU_UCODE_ID_SDMA1: 54 *type = GFX_FW_TYPE_SDMA1; 55 break; 56 case AMDGPU_UCODE_ID_CP_CE: 57 *type = GFX_FW_TYPE_CP_CE; 58 break; 59 case AMDGPU_UCODE_ID_CP_PFP: 60 *type = GFX_FW_TYPE_CP_PFP; 61 break; 62 case AMDGPU_UCODE_ID_CP_ME: 63 *type = GFX_FW_TYPE_CP_ME; 64 break; 65 case AMDGPU_UCODE_ID_CP_MEC1: 66 *type = GFX_FW_TYPE_CP_MEC; 67 break; 68 case AMDGPU_UCODE_ID_CP_MEC1_JT: 69 *type = GFX_FW_TYPE_CP_MEC_ME1; 70 break; 71 case AMDGPU_UCODE_ID_CP_MEC2: 72 *type = GFX_FW_TYPE_CP_MEC; 73 break; 74 case AMDGPU_UCODE_ID_CP_MEC2_JT: 75 *type = GFX_FW_TYPE_CP_MEC_ME2; 76 break; 77 case AMDGPU_UCODE_ID_RLC_G: 78 *type = GFX_FW_TYPE_RLC_G; 79 break; 80 case AMDGPU_UCODE_ID_SMC: 81 *type = GFX_FW_TYPE_SMU; 82 break; 83 case AMDGPU_UCODE_ID_UVD: 84 *type = GFX_FW_TYPE_UVD; 85 break; 86 case AMDGPU_UCODE_ID_VCE: 87 *type = GFX_FW_TYPE_VCE; 88 break; 89 case AMDGPU_UCODE_ID_MAXIMUM: 90 default: 91 return -EINVAL; 92 } 93 94 return 0; 95 } 96 97 int psp_v3_1_init_microcode(struct psp_context *psp) 98 { 99 struct amdgpu_device *adev = psp->adev; 100 const char *chip_name; 101 char fw_name[30]; 102 int err = 0; 103 const struct psp_firmware_header_v1_0 *hdr; 104 105 DRM_DEBUG("\n"); 106 107 switch (adev->asic_type) { 108 case CHIP_VEGA10: 109 chip_name = "vega10"; 110 break; 111 default: BUG(); 112 } 113 114 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 115 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 116 if (err) 117 goto out; 118 119 err = amdgpu_ucode_validate(adev->psp.sos_fw); 120 if (err) 121 goto out; 122 123 hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 124 adev->psp.sos_fw_version = le32_to_cpu(hdr->header.ucode_version); 125 adev->psp.sos_feature_version = le32_to_cpu(hdr->ucode_feature_version); 126 adev->psp.sos_bin_size = le32_to_cpu(hdr->sos_size_bytes); 127 adev->psp.sys_bin_size = le32_to_cpu(hdr->header.ucode_size_bytes) - 128 le32_to_cpu(hdr->sos_size_bytes); 129 adev->psp.sys_start_addr = (uint8_t *)hdr + 130 le32_to_cpu(hdr->header.ucode_array_offset_bytes); 131 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr + 132 le32_to_cpu(hdr->sos_offset_bytes); 133 134 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 135 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 136 if (err) 137 goto out; 138 139 err = amdgpu_ucode_validate(adev->psp.asd_fw); 140 if (err) 141 goto out; 142 143 hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 144 adev->psp.asd_fw_version = le32_to_cpu(hdr->header.ucode_version); 145 adev->psp.asd_feature_version = le32_to_cpu(hdr->ucode_feature_version); 146 adev->psp.asd_ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes); 147 adev->psp.asd_start_addr = (uint8_t *)hdr + 148 le32_to_cpu(hdr->header.ucode_array_offset_bytes); 149 150 return 0; 151 out: 152 if (err) { 153 dev_err(adev->dev, 154 "psp v3.1: Failed to load firmware \"%s\"\n", 155 fw_name); 156 release_firmware(adev->psp.sos_fw); 157 adev->psp.sos_fw = NULL; 158 release_firmware(adev->psp.asd_fw); 159 adev->psp.asd_fw = NULL; 160 } 161 162 return err; 163 } 164 165 int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp) 166 { 167 int ret; 168 uint32_t psp_gfxdrv_command_reg = 0; 169 struct amdgpu_bo *psp_sysdrv; 170 void *psp_sysdrv_virt = NULL; 171 uint64_t psp_sysdrv_mem; 172 struct amdgpu_device *adev = psp->adev; 173 uint32_t size; 174 175 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 176 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 177 0x80000000, 0x80000000, false); 178 if (ret) 179 return ret; 180 181 /* 182 * Create a 1 meg GART memory to store the psp sys driver 183 * binary with a 1 meg aligned address 184 */ 185 size = (psp->sys_bin_size + (PSP_BOOTLOADER_1_MEG_ALIGNMENT - 1)) & 186 (~(PSP_BOOTLOADER_1_MEG_ALIGNMENT - 1)); 187 188 ret = amdgpu_bo_create_kernel(adev, size, PSP_BOOTLOADER_1_MEG_ALIGNMENT, 189 AMDGPU_GEM_DOMAIN_GTT, 190 &psp_sysdrv, 191 &psp_sysdrv_mem, 192 &psp_sysdrv_virt); 193 if (ret) 194 return ret; 195 196 /* Copy PSP System Driver binary to memory */ 197 memcpy(psp_sysdrv_virt, psp->sys_start_addr, psp->sys_bin_size); 198 199 /* Provide the sys driver to bootrom */ 200 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_36), 201 (uint32_t)(psp_sysdrv_mem >> 20)); 202 psp_gfxdrv_command_reg = 1 << 16; 203 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 204 psp_gfxdrv_command_reg); 205 206 /* there might be handshake issue with hardware which needs delay */ 207 mdelay(20); 208 209 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 210 0x80000000, 0x80000000, false); 211 212 amdgpu_bo_free_kernel(&psp_sysdrv, &psp_sysdrv_mem, &psp_sysdrv_virt); 213 214 return ret; 215 } 216 217 int psp_v3_1_bootloader_load_sos(struct psp_context *psp) 218 { 219 int ret; 220 unsigned int psp_gfxdrv_command_reg = 0; 221 struct amdgpu_bo *psp_sos; 222 void *psp_sos_virt = NULL; 223 uint64_t psp_sos_mem; 224 struct amdgpu_device *adev = psp->adev; 225 uint32_t size; 226 227 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 228 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 229 0x80000000, 0x80000000, false); 230 if (ret) 231 return ret; 232 233 size = (psp->sos_bin_size + (PSP_BOOTLOADER_1_MEG_ALIGNMENT - 1)) & 234 (~((uint64_t)PSP_BOOTLOADER_1_MEG_ALIGNMENT - 1)); 235 236 ret = amdgpu_bo_create_kernel(adev, size, PSP_BOOTLOADER_1_MEG_ALIGNMENT, 237 AMDGPU_GEM_DOMAIN_GTT, 238 &psp_sos, 239 &psp_sos_mem, 240 &psp_sos_virt); 241 if (ret) 242 return ret; 243 244 /* Copy Secure OS binary to PSP memory */ 245 memcpy(psp_sos_virt, psp->sos_start_addr, psp->sos_bin_size); 246 247 /* Provide the PSP secure OS to bootrom */ 248 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_36), 249 (uint32_t)(psp_sos_mem >> 20)); 250 psp_gfxdrv_command_reg = 2 << 16; 251 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 252 psp_gfxdrv_command_reg); 253 254 /* there might be handshake issue with hardware which needs delay */ 255 mdelay(20); 256 #if 0 257 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), 258 RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81)), 259 0, true); 260 #endif 261 262 amdgpu_bo_free_kernel(&psp_sos, &psp_sos_mem, &psp_sos_virt); 263 264 return ret; 265 } 266 267 int psp_v3_1_prep_cmd_buf(struct amdgpu_firmware_info *ucode, struct psp_gfx_cmd_resp *cmd) 268 { 269 int ret; 270 uint64_t fw_mem_mc_addr = ucode->mc_addr; 271 272 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 273 274 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 275 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = (uint32_t)fw_mem_mc_addr; 276 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = (uint32_t)((uint64_t)fw_mem_mc_addr >> 32); 277 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 278 279 ret = psp_v3_1_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 280 if (ret) 281 DRM_ERROR("Unknown firmware type\n"); 282 283 return ret; 284 } 285 286 int psp_v3_1_ring_init(struct psp_context *psp, enum psp_ring_type ring_type) 287 { 288 int ret = 0; 289 unsigned int psp_ring_reg = 0; 290 struct psp_ring *ring; 291 struct amdgpu_device *adev = psp->adev; 292 293 ring = &psp->km_ring; 294 295 ring->ring_type = ring_type; 296 297 /* allocate 4k Page of Local Frame Buffer memory for ring */ 298 ring->ring_size = 0x1000; 299 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 300 AMDGPU_GEM_DOMAIN_VRAM, 301 &adev->firmware.rbuf, 302 &ring->ring_mem_mc_addr, 303 (void **)&ring->ring_mem); 304 if (ret) { 305 ring->ring_size = 0; 306 return ret; 307 } 308 309 /* Write low address of the ring to C2PMSG_69 */ 310 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 311 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_69), psp_ring_reg); 312 /* Write high address of the ring to C2PMSG_70 */ 313 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 314 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_70), psp_ring_reg); 315 /* Write size of ring to C2PMSG_71 */ 316 psp_ring_reg = ring->ring_size; 317 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_71), psp_ring_reg); 318 /* Write the ring initialization command to C2PMSG_64 */ 319 psp_ring_reg = ring_type; 320 psp_ring_reg = psp_ring_reg << 16; 321 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), psp_ring_reg); 322 323 /* there might be handshake issue with hardware which needs delay */ 324 mdelay(20); 325 326 /* Wait for response flag (bit 31) in C2PMSG_64 */ 327 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 328 0x80000000, 0x8000FFFF, false); 329 330 return ret; 331 } 332 333 int psp_v3_1_cmd_submit(struct psp_context *psp, 334 struct amdgpu_firmware_info *ucode, 335 uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, 336 int index) 337 { 338 unsigned int psp_write_ptr_reg = 0; 339 struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem; 340 struct psp_ring *ring = &psp->km_ring; 341 struct amdgpu_device *adev = psp->adev; 342 uint32_t ring_size_dw = ring->ring_size / 4; 343 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 344 345 /* KM (GPCOM) prepare write pointer */ 346 psp_write_ptr_reg = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_67)); 347 348 /* Update KM RB frame pointer to new frame */ 349 /* write_frame ptr increments by size of rb_frame in bytes */ 350 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 351 if ((psp_write_ptr_reg % ring_size_dw) == 0) 352 write_frame = ring->ring_mem; 353 else 354 write_frame = ring->ring_mem + (psp_write_ptr_reg / rb_frame_size_dw); 355 356 /* Initialize KM RB frame */ 357 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 358 359 /* Update KM RB frame */ 360 write_frame->cmd_buf_addr_hi = (unsigned int)(cmd_buf_mc_addr >> 32); 361 write_frame->cmd_buf_addr_lo = (unsigned int)(cmd_buf_mc_addr); 362 write_frame->fence_addr_hi = (unsigned int)(fence_mc_addr >> 32); 363 write_frame->fence_addr_lo = (unsigned int)(fence_mc_addr); 364 write_frame->fence_value = index; 365 366 /* Update the write Pointer in DWORDs */ 367 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 368 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_67), psp_write_ptr_reg); 369 370 return 0; 371 } 372 373 static int 374 psp_v3_1_sram_map(unsigned int *sram_offset, unsigned int *sram_addr_reg_offset, 375 unsigned int *sram_data_reg_offset, 376 enum AMDGPU_UCODE_ID ucode_id) 377 { 378 int ret = 0; 379 380 switch(ucode_id) { 381 /* TODO: needs to confirm */ 382 #if 0 383 case AMDGPU_UCODE_ID_SMC: 384 *sram_offset = 0; 385 *sram_addr_reg_offset = 0; 386 *sram_data_reg_offset = 0; 387 break; 388 #endif 389 390 case AMDGPU_UCODE_ID_CP_CE: 391 *sram_offset = 0x0; 392 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR); 393 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA); 394 break; 395 396 case AMDGPU_UCODE_ID_CP_PFP: 397 *sram_offset = 0x0; 398 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR); 399 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA); 400 break; 401 402 case AMDGPU_UCODE_ID_CP_ME: 403 *sram_offset = 0x0; 404 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR); 405 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA); 406 break; 407 408 case AMDGPU_UCODE_ID_CP_MEC1: 409 *sram_offset = 0x10000; 410 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR); 411 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); 412 break; 413 414 case AMDGPU_UCODE_ID_CP_MEC2: 415 *sram_offset = 0x10000; 416 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR); 417 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA); 418 break; 419 420 case AMDGPU_UCODE_ID_RLC_G: 421 *sram_offset = 0x2000; 422 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR); 423 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA); 424 break; 425 426 case AMDGPU_UCODE_ID_SDMA0: 427 *sram_offset = 0x0; 428 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR); 429 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA); 430 break; 431 432 /* TODO: needs to confirm */ 433 #if 0 434 case AMDGPU_UCODE_ID_SDMA1: 435 *sram_offset = ; 436 *sram_addr_reg_offset = ; 437 break; 438 439 case AMDGPU_UCODE_ID_UVD: 440 *sram_offset = ; 441 *sram_addr_reg_offset = ; 442 break; 443 444 case AMDGPU_UCODE_ID_VCE: 445 *sram_offset = ; 446 *sram_addr_reg_offset = ; 447 break; 448 #endif 449 450 case AMDGPU_UCODE_ID_MAXIMUM: 451 default: 452 ret = -EINVAL; 453 break; 454 } 455 456 return ret; 457 } 458 459 bool psp_v3_1_compare_sram_data(struct psp_context *psp, 460 struct amdgpu_firmware_info *ucode, 461 enum AMDGPU_UCODE_ID ucode_type) 462 { 463 int err = 0; 464 unsigned int fw_sram_reg_val = 0; 465 unsigned int fw_sram_addr_reg_offset = 0; 466 unsigned int fw_sram_data_reg_offset = 0; 467 unsigned int ucode_size; 468 uint32_t *ucode_mem = NULL; 469 struct amdgpu_device *adev = psp->adev; 470 471 err = psp_v3_1_sram_map(&fw_sram_reg_val, &fw_sram_addr_reg_offset, 472 &fw_sram_data_reg_offset, ucode_type); 473 if (err) 474 return false; 475 476 WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val); 477 478 ucode_size = ucode->ucode_size; 479 ucode_mem = (uint32_t *)ucode->kaddr; 480 while (!ucode_size) { 481 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset); 482 483 if (*ucode_mem != fw_sram_reg_val) 484 return false; 485 486 ucode_mem++; 487 /* 4 bytes */ 488 ucode_size -= 4; 489 } 490 491 return true; 492 } 493 494 bool psp_v3_1_smu_reload_quirk(struct psp_context *psp) 495 { 496 struct amdgpu_device *adev = psp->adev; 497 uint32_t reg, reg_val; 498 499 reg_val = (smnMP1_FIRMWARE_FLAGS & 0xffffffff) | 0x03b00000; 500 WREG32(SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2), reg_val); 501 reg = RREG32(SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2)); 502 if ((reg & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> 503 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT) 504 return true; 505 506 return false; 507 } 508