1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drmP.h> 28 #include "amdgpu.h" 29 #include "amdgpu_psp.h" 30 #include "amdgpu_ucode.h" 31 #include "soc15_common.h" 32 #include "psp_v3_1.h" 33 34 #include "mp/mp_9_0_offset.h" 35 #include "mp/mp_9_0_sh_mask.h" 36 #include "gc/gc_9_0_offset.h" 37 #include "sdma0/sdma0_4_0_offset.h" 38 #include "nbio/nbio_6_1_offset.h" 39 40 MODULE_FIRMWARE("amdgpu/vega10_sos.bin"); 41 MODULE_FIRMWARE("amdgpu/vega10_asd.bin"); 42 MODULE_FIRMWARE("amdgpu/vega12_sos.bin"); 43 MODULE_FIRMWARE("amdgpu/vega12_asd.bin"); 44 45 46 #define smnMP1_FIRMWARE_FLAGS 0x3010028 47 48 static uint32_t sos_old_versions[] = {1517616, 1510592, 1448594, 1446554}; 49 50 static int psp_v3_1_init_microcode(struct psp_context *psp) 51 { 52 struct amdgpu_device *adev = psp->adev; 53 const char *chip_name; 54 char fw_name[30]; 55 int err = 0; 56 const struct psp_firmware_header_v1_0 *hdr; 57 58 DRM_DEBUG("\n"); 59 60 switch (adev->asic_type) { 61 case CHIP_VEGA10: 62 chip_name = "vega10"; 63 break; 64 case CHIP_VEGA12: 65 chip_name = "vega12"; 66 break; 67 default: BUG(); 68 } 69 70 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 71 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 72 if (err) 73 goto out; 74 75 err = amdgpu_ucode_validate(adev->psp.sos_fw); 76 if (err) 77 goto out; 78 79 hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 80 adev->psp.sos_fw_version = le32_to_cpu(hdr->header.ucode_version); 81 adev->psp.sos_feature_version = le32_to_cpu(hdr->ucode_feature_version); 82 adev->psp.sos_bin_size = le32_to_cpu(hdr->sos_size_bytes); 83 adev->psp.sys_bin_size = le32_to_cpu(hdr->header.ucode_size_bytes) - 84 le32_to_cpu(hdr->sos_size_bytes); 85 adev->psp.sys_start_addr = (uint8_t *)hdr + 86 le32_to_cpu(hdr->header.ucode_array_offset_bytes); 87 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr + 88 le32_to_cpu(hdr->sos_offset_bytes); 89 90 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 91 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 92 if (err) 93 goto out; 94 95 err = amdgpu_ucode_validate(adev->psp.asd_fw); 96 if (err) 97 goto out; 98 99 hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 100 adev->psp.asd_fw_version = le32_to_cpu(hdr->header.ucode_version); 101 adev->psp.asd_feature_version = le32_to_cpu(hdr->ucode_feature_version); 102 adev->psp.asd_ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes); 103 adev->psp.asd_start_addr = (uint8_t *)hdr + 104 le32_to_cpu(hdr->header.ucode_array_offset_bytes); 105 106 return 0; 107 out: 108 if (err) { 109 dev_err(adev->dev, 110 "psp v3.1: Failed to load firmware \"%s\"\n", 111 fw_name); 112 release_firmware(adev->psp.sos_fw); 113 adev->psp.sos_fw = NULL; 114 release_firmware(adev->psp.asd_fw); 115 adev->psp.asd_fw = NULL; 116 } 117 118 return err; 119 } 120 121 static int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp) 122 { 123 int ret; 124 uint32_t psp_gfxdrv_command_reg = 0; 125 struct amdgpu_device *adev = psp->adev; 126 uint32_t sol_reg; 127 128 /* Check sOS sign of life register to confirm sys driver and sOS 129 * are already been loaded. 130 */ 131 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 132 if (sol_reg) 133 return 0; 134 135 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 136 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 137 0x80000000, 0x80000000, false); 138 if (ret) 139 return ret; 140 141 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 142 143 /* Copy PSP System Driver binary to memory */ 144 memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size); 145 146 /* Provide the sys driver to bootloader */ 147 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 148 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 149 psp_gfxdrv_command_reg = 1 << 16; 150 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 151 psp_gfxdrv_command_reg); 152 153 /* there might be handshake issue with hardware which needs delay */ 154 mdelay(20); 155 156 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 157 0x80000000, 0x80000000, false); 158 159 return ret; 160 } 161 162 static bool psp_v3_1_match_version(struct amdgpu_device *adev, uint32_t ver) 163 { 164 int i; 165 166 if (ver == adev->psp.sos_fw_version) 167 return true; 168 169 /* 170 * Double check if the latest four legacy versions. 171 * If yes, it is still the right version. 172 */ 173 for (i = 0; i < sizeof(sos_old_versions) / sizeof(uint32_t); i++) { 174 if (sos_old_versions[i] == adev->psp.sos_fw_version) 175 return true; 176 } 177 178 return false; 179 } 180 181 static int psp_v3_1_bootloader_load_sos(struct psp_context *psp) 182 { 183 int ret; 184 unsigned int psp_gfxdrv_command_reg = 0; 185 struct amdgpu_device *adev = psp->adev; 186 uint32_t sol_reg, ver; 187 188 /* Check sOS sign of life register to confirm sys driver and sOS 189 * are already been loaded. 190 */ 191 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 192 if (sol_reg) { 193 psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58); 194 printk("sos fw version = 0x%x.\n", psp->sos_fw_version); 195 return 0; 196 } 197 198 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 199 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 200 0x80000000, 0x80000000, false); 201 if (ret) 202 return ret; 203 204 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 205 206 /* Copy Secure OS binary to PSP memory */ 207 memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size); 208 209 /* Provide the PSP secure OS to bootloader */ 210 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 211 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 212 psp_gfxdrv_command_reg = 2 << 16; 213 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 214 psp_gfxdrv_command_reg); 215 216 /* there might be handshake issue with hardware which needs delay */ 217 mdelay(20); 218 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), 219 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 220 0, true); 221 222 ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58); 223 if (!psp_v3_1_match_version(adev, ver)) 224 DRM_WARN("SOS version doesn't match\n"); 225 226 return ret; 227 } 228 229 static int psp_v3_1_ring_init(struct psp_context *psp, 230 enum psp_ring_type ring_type) 231 { 232 int ret = 0; 233 struct psp_ring *ring; 234 struct amdgpu_device *adev = psp->adev; 235 236 ring = &psp->km_ring; 237 238 ring->ring_type = ring_type; 239 240 /* allocate 4k Page of Local Frame Buffer memory for ring */ 241 ring->ring_size = 0x1000; 242 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 243 AMDGPU_GEM_DOMAIN_VRAM, 244 &adev->firmware.rbuf, 245 &ring->ring_mem_mc_addr, 246 (void **)&ring->ring_mem); 247 if (ret) { 248 ring->ring_size = 0; 249 return ret; 250 } 251 252 return 0; 253 } 254 255 static int psp_v3_1_ring_create(struct psp_context *psp, 256 enum psp_ring_type ring_type) 257 { 258 int ret = 0; 259 unsigned int psp_ring_reg = 0; 260 struct psp_ring *ring = &psp->km_ring; 261 struct amdgpu_device *adev = psp->adev; 262 263 /* Write low address of the ring to C2PMSG_69 */ 264 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 265 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); 266 /* Write high address of the ring to C2PMSG_70 */ 267 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 268 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); 269 /* Write size of ring to C2PMSG_71 */ 270 psp_ring_reg = ring->ring_size; 271 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); 272 /* Write the ring initialization command to C2PMSG_64 */ 273 psp_ring_reg = ring_type; 274 psp_ring_reg = psp_ring_reg << 16; 275 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 276 277 /* there might be handshake issue with hardware which needs delay */ 278 mdelay(20); 279 280 /* Wait for response flag (bit 31) in C2PMSG_64 */ 281 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 282 0x80000000, 0x8000FFFF, false); 283 284 return ret; 285 } 286 287 static int psp_v3_1_ring_stop(struct psp_context *psp, 288 enum psp_ring_type ring_type) 289 { 290 int ret = 0; 291 unsigned int psp_ring_reg = 0; 292 struct amdgpu_device *adev = psp->adev; 293 294 /* Write the ring destroy command to C2PMSG_64 */ 295 psp_ring_reg = 3 << 16; 296 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 297 298 /* there might be handshake issue with hardware which needs delay */ 299 mdelay(20); 300 301 /* Wait for response flag (bit 31) in C2PMSG_64 */ 302 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 303 0x80000000, 0x80000000, false); 304 305 return ret; 306 } 307 308 static int psp_v3_1_ring_destroy(struct psp_context *psp, 309 enum psp_ring_type ring_type) 310 { 311 int ret = 0; 312 struct psp_ring *ring = &psp->km_ring; 313 struct amdgpu_device *adev = psp->adev; 314 315 ret = psp_v3_1_ring_stop(psp, ring_type); 316 if (ret) 317 DRM_ERROR("Fail to stop psp ring\n"); 318 319 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 320 &ring->ring_mem_mc_addr, 321 (void **)&ring->ring_mem); 322 323 return ret; 324 } 325 326 static int psp_v3_1_cmd_submit(struct psp_context *psp, 327 struct amdgpu_firmware_info *ucode, 328 uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, 329 int index) 330 { 331 unsigned int psp_write_ptr_reg = 0; 332 struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem; 333 struct psp_ring *ring = &psp->km_ring; 334 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 335 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 336 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 337 struct amdgpu_device *adev = psp->adev; 338 uint32_t ring_size_dw = ring->ring_size / 4; 339 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 340 341 /* KM (GPCOM) prepare write pointer */ 342 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); 343 344 /* Update KM RB frame pointer to new frame */ 345 /* write_frame ptr increments by size of rb_frame in bytes */ 346 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 347 if ((psp_write_ptr_reg % ring_size_dw) == 0) 348 write_frame = ring_buffer_start; 349 else 350 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 351 /* Check invalid write_frame ptr address */ 352 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 353 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 354 ring_buffer_start, ring_buffer_end, write_frame); 355 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 356 return -EINVAL; 357 } 358 359 /* Initialize KM RB frame */ 360 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 361 362 /* Update KM RB frame */ 363 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 364 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 365 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 366 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 367 write_frame->fence_value = index; 368 369 /* Update the write Pointer in DWORDs */ 370 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 371 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg); 372 373 return 0; 374 } 375 376 static int 377 psp_v3_1_sram_map(struct amdgpu_device *adev, 378 unsigned int *sram_offset, unsigned int *sram_addr_reg_offset, 379 unsigned int *sram_data_reg_offset, 380 enum AMDGPU_UCODE_ID ucode_id) 381 { 382 int ret = 0; 383 384 switch(ucode_id) { 385 /* TODO: needs to confirm */ 386 #if 0 387 case AMDGPU_UCODE_ID_SMC: 388 *sram_offset = 0; 389 *sram_addr_reg_offset = 0; 390 *sram_data_reg_offset = 0; 391 break; 392 #endif 393 394 case AMDGPU_UCODE_ID_CP_CE: 395 *sram_offset = 0x0; 396 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR); 397 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA); 398 break; 399 400 case AMDGPU_UCODE_ID_CP_PFP: 401 *sram_offset = 0x0; 402 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR); 403 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA); 404 break; 405 406 case AMDGPU_UCODE_ID_CP_ME: 407 *sram_offset = 0x0; 408 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR); 409 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA); 410 break; 411 412 case AMDGPU_UCODE_ID_CP_MEC1: 413 *sram_offset = 0x10000; 414 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR); 415 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); 416 break; 417 418 case AMDGPU_UCODE_ID_CP_MEC2: 419 *sram_offset = 0x10000; 420 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR); 421 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA); 422 break; 423 424 case AMDGPU_UCODE_ID_RLC_G: 425 *sram_offset = 0x2000; 426 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR); 427 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA); 428 break; 429 430 case AMDGPU_UCODE_ID_SDMA0: 431 *sram_offset = 0x0; 432 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR); 433 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA); 434 break; 435 436 /* TODO: needs to confirm */ 437 #if 0 438 case AMDGPU_UCODE_ID_SDMA1: 439 *sram_offset = ; 440 *sram_addr_reg_offset = ; 441 break; 442 443 case AMDGPU_UCODE_ID_UVD: 444 *sram_offset = ; 445 *sram_addr_reg_offset = ; 446 break; 447 448 case AMDGPU_UCODE_ID_VCE: 449 *sram_offset = ; 450 *sram_addr_reg_offset = ; 451 break; 452 #endif 453 454 case AMDGPU_UCODE_ID_MAXIMUM: 455 default: 456 ret = -EINVAL; 457 break; 458 } 459 460 return ret; 461 } 462 463 static bool psp_v3_1_compare_sram_data(struct psp_context *psp, 464 struct amdgpu_firmware_info *ucode, 465 enum AMDGPU_UCODE_ID ucode_type) 466 { 467 int err = 0; 468 unsigned int fw_sram_reg_val = 0; 469 unsigned int fw_sram_addr_reg_offset = 0; 470 unsigned int fw_sram_data_reg_offset = 0; 471 unsigned int ucode_size; 472 uint32_t *ucode_mem = NULL; 473 struct amdgpu_device *adev = psp->adev; 474 475 err = psp_v3_1_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset, 476 &fw_sram_data_reg_offset, ucode_type); 477 if (err) 478 return false; 479 480 WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val); 481 482 ucode_size = ucode->ucode_size; 483 ucode_mem = (uint32_t *)ucode->kaddr; 484 while (ucode_size) { 485 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset); 486 487 if (*ucode_mem != fw_sram_reg_val) 488 return false; 489 490 ucode_mem++; 491 /* 4 bytes */ 492 ucode_size -= 4; 493 } 494 495 return true; 496 } 497 498 static bool psp_v3_1_smu_reload_quirk(struct psp_context *psp) 499 { 500 struct amdgpu_device *adev = psp->adev; 501 uint32_t reg; 502 503 reg = RREG32_PCIE(smnMP1_FIRMWARE_FLAGS | 0x03b00000); 504 return (reg & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) ? true : false; 505 } 506 507 static int psp_v3_1_mode1_reset(struct psp_context *psp) 508 { 509 int ret; 510 uint32_t offset; 511 struct amdgpu_device *adev = psp->adev; 512 513 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); 514 515 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false); 516 517 if (ret) { 518 DRM_INFO("psp is not working correctly before mode1 reset!\n"); 519 return -EINVAL; 520 } 521 522 /*send the mode 1 reset command*/ 523 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST); 524 525 msleep(500); 526 527 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); 528 529 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false); 530 531 if (ret) { 532 DRM_INFO("psp mode 1 reset failed!\n"); 533 return -EINVAL; 534 } 535 536 DRM_INFO("psp mode1 reset succeed \n"); 537 538 return 0; 539 } 540 541 static const struct psp_funcs psp_v3_1_funcs = { 542 .init_microcode = psp_v3_1_init_microcode, 543 .bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv, 544 .bootloader_load_sos = psp_v3_1_bootloader_load_sos, 545 .ring_init = psp_v3_1_ring_init, 546 .ring_create = psp_v3_1_ring_create, 547 .ring_stop = psp_v3_1_ring_stop, 548 .ring_destroy = psp_v3_1_ring_destroy, 549 .cmd_submit = psp_v3_1_cmd_submit, 550 .compare_sram_data = psp_v3_1_compare_sram_data, 551 .smu_reload_quirk = psp_v3_1_smu_reload_quirk, 552 .mode1_reset = psp_v3_1_mode1_reset, 553 }; 554 555 void psp_v3_1_set_psp_funcs(struct psp_context *psp) 556 { 557 psp->funcs = &psp_v3_1_funcs; 558 } 559