1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drmP.h> 28 #include "amdgpu.h" 29 #include "amdgpu_psp.h" 30 #include "amdgpu_ucode.h" 31 #include "soc15_common.h" 32 #include "psp_v3_1.h" 33 34 #include "mp/mp_9_0_offset.h" 35 #include "mp/mp_9_0_sh_mask.h" 36 #include "gc/gc_9_0_offset.h" 37 #include "sdma0/sdma0_4_0_offset.h" 38 #include "nbio/nbio_6_1_offset.h" 39 40 MODULE_FIRMWARE("amdgpu/vega10_sos.bin"); 41 MODULE_FIRMWARE("amdgpu/vega10_asd.bin"); 42 MODULE_FIRMWARE("amdgpu/vega12_sos.bin"); 43 MODULE_FIRMWARE("amdgpu/vega12_asd.bin"); 44 MODULE_FIRMWARE("amdgpu/vega20_sos.bin"); 45 MODULE_FIRMWARE("amdgpu/vega20_asd.bin"); 46 47 48 #define smnMP1_FIRMWARE_FLAGS 0x3010028 49 50 static int 51 psp_v3_1_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type) 52 { 53 switch(ucode->ucode_id) { 54 case AMDGPU_UCODE_ID_SDMA0: 55 *type = GFX_FW_TYPE_SDMA0; 56 break; 57 case AMDGPU_UCODE_ID_SDMA1: 58 *type = GFX_FW_TYPE_SDMA1; 59 break; 60 case AMDGPU_UCODE_ID_CP_CE: 61 *type = GFX_FW_TYPE_CP_CE; 62 break; 63 case AMDGPU_UCODE_ID_CP_PFP: 64 *type = GFX_FW_TYPE_CP_PFP; 65 break; 66 case AMDGPU_UCODE_ID_CP_ME: 67 *type = GFX_FW_TYPE_CP_ME; 68 break; 69 case AMDGPU_UCODE_ID_CP_MEC1: 70 *type = GFX_FW_TYPE_CP_MEC; 71 break; 72 case AMDGPU_UCODE_ID_CP_MEC1_JT: 73 *type = GFX_FW_TYPE_CP_MEC_ME1; 74 break; 75 case AMDGPU_UCODE_ID_CP_MEC2: 76 *type = GFX_FW_TYPE_CP_MEC; 77 break; 78 case AMDGPU_UCODE_ID_CP_MEC2_JT: 79 *type = GFX_FW_TYPE_CP_MEC_ME2; 80 break; 81 case AMDGPU_UCODE_ID_RLC_G: 82 *type = GFX_FW_TYPE_RLC_G; 83 break; 84 case AMDGPU_UCODE_ID_SMC: 85 *type = GFX_FW_TYPE_SMU; 86 break; 87 case AMDGPU_UCODE_ID_UVD: 88 *type = GFX_FW_TYPE_UVD; 89 break; 90 case AMDGPU_UCODE_ID_VCE: 91 *type = GFX_FW_TYPE_VCE; 92 break; 93 case AMDGPU_UCODE_ID_MAXIMUM: 94 default: 95 return -EINVAL; 96 } 97 98 return 0; 99 } 100 101 static int psp_v3_1_init_microcode(struct psp_context *psp) 102 { 103 struct amdgpu_device *adev = psp->adev; 104 const char *chip_name; 105 char fw_name[30]; 106 int err = 0; 107 const struct psp_firmware_header_v1_0 *hdr; 108 109 DRM_DEBUG("\n"); 110 111 switch (adev->asic_type) { 112 case CHIP_VEGA10: 113 chip_name = "vega10"; 114 break; 115 case CHIP_VEGA12: 116 chip_name = "vega12"; 117 break; 118 default: BUG(); 119 } 120 121 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 122 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 123 if (err) 124 goto out; 125 126 err = amdgpu_ucode_validate(adev->psp.sos_fw); 127 if (err) 128 goto out; 129 130 hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 131 adev->psp.sos_fw_version = le32_to_cpu(hdr->header.ucode_version); 132 adev->psp.sos_feature_version = le32_to_cpu(hdr->ucode_feature_version); 133 adev->psp.sos_bin_size = le32_to_cpu(hdr->sos_size_bytes); 134 adev->psp.sys_bin_size = le32_to_cpu(hdr->header.ucode_size_bytes) - 135 le32_to_cpu(hdr->sos_size_bytes); 136 adev->psp.sys_start_addr = (uint8_t *)hdr + 137 le32_to_cpu(hdr->header.ucode_array_offset_bytes); 138 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr + 139 le32_to_cpu(hdr->sos_offset_bytes); 140 141 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 142 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 143 if (err) 144 goto out; 145 146 err = amdgpu_ucode_validate(adev->psp.asd_fw); 147 if (err) 148 goto out; 149 150 hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 151 adev->psp.asd_fw_version = le32_to_cpu(hdr->header.ucode_version); 152 adev->psp.asd_feature_version = le32_to_cpu(hdr->ucode_feature_version); 153 adev->psp.asd_ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes); 154 adev->psp.asd_start_addr = (uint8_t *)hdr + 155 le32_to_cpu(hdr->header.ucode_array_offset_bytes); 156 157 return 0; 158 out: 159 if (err) { 160 dev_err(adev->dev, 161 "psp v3.1: Failed to load firmware \"%s\"\n", 162 fw_name); 163 release_firmware(adev->psp.sos_fw); 164 adev->psp.sos_fw = NULL; 165 release_firmware(adev->psp.asd_fw); 166 adev->psp.asd_fw = NULL; 167 } 168 169 return err; 170 } 171 172 static int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp) 173 { 174 int ret; 175 uint32_t psp_gfxdrv_command_reg = 0; 176 struct amdgpu_device *adev = psp->adev; 177 uint32_t sol_reg; 178 179 /* Check sOS sign of life register to confirm sys driver and sOS 180 * are already been loaded. 181 */ 182 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 183 if (sol_reg) 184 return 0; 185 186 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 187 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 188 0x80000000, 0x80000000, false); 189 if (ret) 190 return ret; 191 192 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 193 194 /* Copy PSP System Driver binary to memory */ 195 memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size); 196 197 /* Provide the sys driver to bootrom */ 198 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 199 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 200 psp_gfxdrv_command_reg = 1 << 16; 201 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 202 psp_gfxdrv_command_reg); 203 204 /* there might be handshake issue with hardware which needs delay */ 205 mdelay(20); 206 207 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 208 0x80000000, 0x80000000, false); 209 210 return ret; 211 } 212 213 static int psp_v3_1_bootloader_load_sos(struct psp_context *psp) 214 { 215 int ret; 216 unsigned int psp_gfxdrv_command_reg = 0; 217 struct amdgpu_device *adev = psp->adev; 218 uint32_t sol_reg; 219 220 /* Check sOS sign of life register to confirm sys driver and sOS 221 * are already been loaded. 222 */ 223 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 224 if (sol_reg) 225 return 0; 226 227 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 228 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 229 0x80000000, 0x80000000, false); 230 if (ret) 231 return ret; 232 233 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 234 235 /* Copy Secure OS binary to PSP memory */ 236 memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size); 237 238 /* Provide the PSP secure OS to bootrom */ 239 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 240 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 241 psp_gfxdrv_command_reg = 2 << 16; 242 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 243 psp_gfxdrv_command_reg); 244 245 /* there might be handshake issue with hardware which needs delay */ 246 mdelay(20); 247 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), 248 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 249 0, true); 250 251 return ret; 252 } 253 254 static int psp_v3_1_prep_cmd_buf(struct amdgpu_firmware_info *ucode, 255 struct psp_gfx_cmd_resp *cmd) 256 { 257 int ret; 258 uint64_t fw_mem_mc_addr = ucode->mc_addr; 259 260 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 261 262 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 263 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 264 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 265 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 266 267 ret = psp_v3_1_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 268 if (ret) 269 DRM_ERROR("Unknown firmware type\n"); 270 271 return ret; 272 } 273 274 static int psp_v3_1_ring_init(struct psp_context *psp, 275 enum psp_ring_type ring_type) 276 { 277 int ret = 0; 278 struct psp_ring *ring; 279 struct amdgpu_device *adev = psp->adev; 280 281 ring = &psp->km_ring; 282 283 ring->ring_type = ring_type; 284 285 /* allocate 4k Page of Local Frame Buffer memory for ring */ 286 ring->ring_size = 0x1000; 287 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 288 AMDGPU_GEM_DOMAIN_VRAM, 289 &adev->firmware.rbuf, 290 &ring->ring_mem_mc_addr, 291 (void **)&ring->ring_mem); 292 if (ret) { 293 ring->ring_size = 0; 294 return ret; 295 } 296 297 return 0; 298 } 299 300 static int psp_v3_1_ring_create(struct psp_context *psp, 301 enum psp_ring_type ring_type) 302 { 303 int ret = 0; 304 unsigned int psp_ring_reg = 0; 305 struct psp_ring *ring = &psp->km_ring; 306 struct amdgpu_device *adev = psp->adev; 307 308 /* Write low address of the ring to C2PMSG_69 */ 309 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 310 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); 311 /* Write high address of the ring to C2PMSG_70 */ 312 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 313 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); 314 /* Write size of ring to C2PMSG_71 */ 315 psp_ring_reg = ring->ring_size; 316 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); 317 /* Write the ring initialization command to C2PMSG_64 */ 318 psp_ring_reg = ring_type; 319 psp_ring_reg = psp_ring_reg << 16; 320 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 321 322 /* there might be handshake issue with hardware which needs delay */ 323 mdelay(20); 324 325 /* Wait for response flag (bit 31) in C2PMSG_64 */ 326 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 327 0x80000000, 0x8000FFFF, false); 328 329 return ret; 330 } 331 332 static int psp_v3_1_ring_stop(struct psp_context *psp, 333 enum psp_ring_type ring_type) 334 { 335 int ret = 0; 336 struct psp_ring *ring; 337 unsigned int psp_ring_reg = 0; 338 struct amdgpu_device *adev = psp->adev; 339 340 ring = &psp->km_ring; 341 342 /* Write the ring destroy command to C2PMSG_64 */ 343 psp_ring_reg = 3 << 16; 344 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 345 346 /* there might be handshake issue with hardware which needs delay */ 347 mdelay(20); 348 349 /* Wait for response flag (bit 31) in C2PMSG_64 */ 350 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 351 0x80000000, 0x80000000, false); 352 353 return ret; 354 } 355 356 static int psp_v3_1_ring_destroy(struct psp_context *psp, 357 enum psp_ring_type ring_type) 358 { 359 int ret = 0; 360 struct psp_ring *ring = &psp->km_ring; 361 struct amdgpu_device *adev = psp->adev; 362 363 ret = psp_v3_1_ring_stop(psp, ring_type); 364 if (ret) 365 DRM_ERROR("Fail to stop psp ring\n"); 366 367 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 368 &ring->ring_mem_mc_addr, 369 (void **)&ring->ring_mem); 370 371 return ret; 372 } 373 374 static int psp_v3_1_cmd_submit(struct psp_context *psp, 375 struct amdgpu_firmware_info *ucode, 376 uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, 377 int index) 378 { 379 unsigned int psp_write_ptr_reg = 0; 380 struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem; 381 struct psp_ring *ring = &psp->km_ring; 382 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 383 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 384 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 385 struct amdgpu_device *adev = psp->adev; 386 uint32_t ring_size_dw = ring->ring_size / 4; 387 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 388 389 /* KM (GPCOM) prepare write pointer */ 390 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); 391 392 /* Update KM RB frame pointer to new frame */ 393 /* write_frame ptr increments by size of rb_frame in bytes */ 394 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 395 if ((psp_write_ptr_reg % ring_size_dw) == 0) 396 write_frame = ring_buffer_start; 397 else 398 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 399 /* Check invalid write_frame ptr address */ 400 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 401 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 402 ring_buffer_start, ring_buffer_end, write_frame); 403 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 404 return -EINVAL; 405 } 406 407 /* Initialize KM RB frame */ 408 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 409 410 /* Update KM RB frame */ 411 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 412 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 413 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 414 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 415 write_frame->fence_value = index; 416 417 /* Update the write Pointer in DWORDs */ 418 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 419 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg); 420 421 return 0; 422 } 423 424 static int 425 psp_v3_1_sram_map(struct amdgpu_device *adev, 426 unsigned int *sram_offset, unsigned int *sram_addr_reg_offset, 427 unsigned int *sram_data_reg_offset, 428 enum AMDGPU_UCODE_ID ucode_id) 429 { 430 int ret = 0; 431 432 switch(ucode_id) { 433 /* TODO: needs to confirm */ 434 #if 0 435 case AMDGPU_UCODE_ID_SMC: 436 *sram_offset = 0; 437 *sram_addr_reg_offset = 0; 438 *sram_data_reg_offset = 0; 439 break; 440 #endif 441 442 case AMDGPU_UCODE_ID_CP_CE: 443 *sram_offset = 0x0; 444 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR); 445 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA); 446 break; 447 448 case AMDGPU_UCODE_ID_CP_PFP: 449 *sram_offset = 0x0; 450 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR); 451 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA); 452 break; 453 454 case AMDGPU_UCODE_ID_CP_ME: 455 *sram_offset = 0x0; 456 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR); 457 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA); 458 break; 459 460 case AMDGPU_UCODE_ID_CP_MEC1: 461 *sram_offset = 0x10000; 462 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR); 463 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); 464 break; 465 466 case AMDGPU_UCODE_ID_CP_MEC2: 467 *sram_offset = 0x10000; 468 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR); 469 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA); 470 break; 471 472 case AMDGPU_UCODE_ID_RLC_G: 473 *sram_offset = 0x2000; 474 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR); 475 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA); 476 break; 477 478 case AMDGPU_UCODE_ID_SDMA0: 479 *sram_offset = 0x0; 480 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR); 481 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA); 482 break; 483 484 /* TODO: needs to confirm */ 485 #if 0 486 case AMDGPU_UCODE_ID_SDMA1: 487 *sram_offset = ; 488 *sram_addr_reg_offset = ; 489 break; 490 491 case AMDGPU_UCODE_ID_UVD: 492 *sram_offset = ; 493 *sram_addr_reg_offset = ; 494 break; 495 496 case AMDGPU_UCODE_ID_VCE: 497 *sram_offset = ; 498 *sram_addr_reg_offset = ; 499 break; 500 #endif 501 502 case AMDGPU_UCODE_ID_MAXIMUM: 503 default: 504 ret = -EINVAL; 505 break; 506 } 507 508 return ret; 509 } 510 511 static bool psp_v3_1_compare_sram_data(struct psp_context *psp, 512 struct amdgpu_firmware_info *ucode, 513 enum AMDGPU_UCODE_ID ucode_type) 514 { 515 int err = 0; 516 unsigned int fw_sram_reg_val = 0; 517 unsigned int fw_sram_addr_reg_offset = 0; 518 unsigned int fw_sram_data_reg_offset = 0; 519 unsigned int ucode_size; 520 uint32_t *ucode_mem = NULL; 521 struct amdgpu_device *adev = psp->adev; 522 523 err = psp_v3_1_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset, 524 &fw_sram_data_reg_offset, ucode_type); 525 if (err) 526 return false; 527 528 WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val); 529 530 ucode_size = ucode->ucode_size; 531 ucode_mem = (uint32_t *)ucode->kaddr; 532 while (ucode_size) { 533 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset); 534 535 if (*ucode_mem != fw_sram_reg_val) 536 return false; 537 538 ucode_mem++; 539 /* 4 bytes */ 540 ucode_size -= 4; 541 } 542 543 return true; 544 } 545 546 static bool psp_v3_1_smu_reload_quirk(struct psp_context *psp) 547 { 548 struct amdgpu_device *adev = psp->adev; 549 uint32_t reg; 550 551 reg = smnMP1_FIRMWARE_FLAGS | 0x03b00000; 552 WREG32_SOC15(NBIO, 0, mmPCIE_INDEX2, reg); 553 reg = RREG32_SOC15(NBIO, 0, mmPCIE_DATA2); 554 return (reg & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) ? true : false; 555 } 556 557 static int psp_v3_1_mode1_reset(struct psp_context *psp) 558 { 559 int ret; 560 uint32_t offset; 561 struct amdgpu_device *adev = psp->adev; 562 563 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); 564 565 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false); 566 567 if (ret) { 568 DRM_INFO("psp is not working correctly before mode1 reset!\n"); 569 return -EINVAL; 570 } 571 572 /*send the mode 1 reset command*/ 573 WREG32(offset, 0x70000); 574 575 mdelay(1000); 576 577 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); 578 579 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false); 580 581 if (ret) { 582 DRM_INFO("psp mode 1 reset failed!\n"); 583 return -EINVAL; 584 } 585 586 DRM_INFO("psp mode1 reset succeed \n"); 587 588 return 0; 589 } 590 591 static const struct psp_funcs psp_v3_1_funcs = { 592 .init_microcode = psp_v3_1_init_microcode, 593 .bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv, 594 .bootloader_load_sos = psp_v3_1_bootloader_load_sos, 595 .prep_cmd_buf = psp_v3_1_prep_cmd_buf, 596 .ring_init = psp_v3_1_ring_init, 597 .ring_create = psp_v3_1_ring_create, 598 .ring_stop = psp_v3_1_ring_stop, 599 .ring_destroy = psp_v3_1_ring_destroy, 600 .cmd_submit = psp_v3_1_cmd_submit, 601 .compare_sram_data = psp_v3_1_compare_sram_data, 602 .smu_reload_quirk = psp_v3_1_smu_reload_quirk, 603 .mode1_reset = psp_v3_1_mode1_reset, 604 }; 605 606 void psp_v3_1_set_psp_funcs(struct psp_context *psp) 607 { 608 psp->funcs = &psp_v3_1_funcs; 609 } 610