1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drmP.h> 28 #include "amdgpu.h" 29 #include "amdgpu_psp.h" 30 #include "amdgpu_ucode.h" 31 #include "soc15_common.h" 32 #include "psp_v3_1.h" 33 34 #include "mp/mp_9_0_offset.h" 35 #include "mp/mp_9_0_sh_mask.h" 36 #include "gc/gc_9_0_offset.h" 37 #include "sdma0/sdma0_4_0_offset.h" 38 #include "nbio/nbio_6_1_offset.h" 39 40 #include "oss/osssys_4_0_offset.h" 41 #include "oss/osssys_4_0_sh_mask.h" 42 43 MODULE_FIRMWARE("amdgpu/vega10_sos.bin"); 44 MODULE_FIRMWARE("amdgpu/vega10_asd.bin"); 45 MODULE_FIRMWARE("amdgpu/vega12_sos.bin"); 46 MODULE_FIRMWARE("amdgpu/vega12_asd.bin"); 47 48 49 #define smnMP1_FIRMWARE_FLAGS 0x3010028 50 51 static uint32_t sos_old_versions[] = {1517616, 1510592, 1448594, 1446554}; 52 53 static int psp_v3_1_init_microcode(struct psp_context *psp) 54 { 55 struct amdgpu_device *adev = psp->adev; 56 const char *chip_name; 57 char fw_name[30]; 58 int err = 0; 59 const struct psp_firmware_header_v1_0 *hdr; 60 61 DRM_DEBUG("\n"); 62 63 switch (adev->asic_type) { 64 case CHIP_VEGA10: 65 chip_name = "vega10"; 66 break; 67 case CHIP_VEGA12: 68 chip_name = "vega12"; 69 break; 70 default: BUG(); 71 } 72 73 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 74 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 75 if (err) 76 goto out; 77 78 err = amdgpu_ucode_validate(adev->psp.sos_fw); 79 if (err) 80 goto out; 81 82 hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 83 adev->psp.sos_fw_version = le32_to_cpu(hdr->header.ucode_version); 84 adev->psp.sos_feature_version = le32_to_cpu(hdr->ucode_feature_version); 85 adev->psp.sos_bin_size = le32_to_cpu(hdr->sos_size_bytes); 86 adev->psp.sys_bin_size = le32_to_cpu(hdr->header.ucode_size_bytes) - 87 le32_to_cpu(hdr->sos_size_bytes); 88 adev->psp.sys_start_addr = (uint8_t *)hdr + 89 le32_to_cpu(hdr->header.ucode_array_offset_bytes); 90 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr + 91 le32_to_cpu(hdr->sos_offset_bytes); 92 93 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 94 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 95 if (err) 96 goto out; 97 98 err = amdgpu_ucode_validate(adev->psp.asd_fw); 99 if (err) 100 goto out; 101 102 hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 103 adev->psp.asd_fw_version = le32_to_cpu(hdr->header.ucode_version); 104 adev->psp.asd_feature_version = le32_to_cpu(hdr->ucode_feature_version); 105 adev->psp.asd_ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes); 106 adev->psp.asd_start_addr = (uint8_t *)hdr + 107 le32_to_cpu(hdr->header.ucode_array_offset_bytes); 108 109 return 0; 110 out: 111 if (err) { 112 dev_err(adev->dev, 113 "psp v3.1: Failed to load firmware \"%s\"\n", 114 fw_name); 115 release_firmware(adev->psp.sos_fw); 116 adev->psp.sos_fw = NULL; 117 release_firmware(adev->psp.asd_fw); 118 adev->psp.asd_fw = NULL; 119 } 120 121 return err; 122 } 123 124 static int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp) 125 { 126 int ret; 127 uint32_t psp_gfxdrv_command_reg = 0; 128 struct amdgpu_device *adev = psp->adev; 129 uint32_t sol_reg; 130 131 /* Check sOS sign of life register to confirm sys driver and sOS 132 * are already been loaded. 133 */ 134 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 135 if (sol_reg) 136 return 0; 137 138 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 139 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 140 0x80000000, 0x80000000, false); 141 if (ret) 142 return ret; 143 144 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 145 146 /* Copy PSP System Driver binary to memory */ 147 memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size); 148 149 /* Provide the sys driver to bootloader */ 150 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 151 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 152 psp_gfxdrv_command_reg = 1 << 16; 153 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 154 psp_gfxdrv_command_reg); 155 156 /* there might be handshake issue with hardware which needs delay */ 157 mdelay(20); 158 159 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 160 0x80000000, 0x80000000, false); 161 162 return ret; 163 } 164 165 static bool psp_v3_1_match_version(struct amdgpu_device *adev, uint32_t ver) 166 { 167 int i; 168 169 if (ver == adev->psp.sos_fw_version) 170 return true; 171 172 /* 173 * Double check if the latest four legacy versions. 174 * If yes, it is still the right version. 175 */ 176 for (i = 0; i < sizeof(sos_old_versions) / sizeof(uint32_t); i++) { 177 if (sos_old_versions[i] == adev->psp.sos_fw_version) 178 return true; 179 } 180 181 return false; 182 } 183 184 static int psp_v3_1_bootloader_load_sos(struct psp_context *psp) 185 { 186 int ret; 187 unsigned int psp_gfxdrv_command_reg = 0; 188 struct amdgpu_device *adev = psp->adev; 189 uint32_t sol_reg, ver; 190 191 /* Check sOS sign of life register to confirm sys driver and sOS 192 * are already been loaded. 193 */ 194 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 195 if (sol_reg) { 196 psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58); 197 printk("sos fw version = 0x%x.\n", psp->sos_fw_version); 198 return 0; 199 } 200 201 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 202 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 203 0x80000000, 0x80000000, false); 204 if (ret) 205 return ret; 206 207 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 208 209 /* Copy Secure OS binary to PSP memory */ 210 memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size); 211 212 /* Provide the PSP secure OS to bootloader */ 213 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 214 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 215 psp_gfxdrv_command_reg = 2 << 16; 216 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 217 psp_gfxdrv_command_reg); 218 219 /* there might be handshake issue with hardware which needs delay */ 220 mdelay(20); 221 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), 222 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 223 0, true); 224 225 ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58); 226 if (!psp_v3_1_match_version(adev, ver)) 227 DRM_WARN("SOS version doesn't match\n"); 228 229 return ret; 230 } 231 232 static int psp_v3_1_ring_init(struct psp_context *psp, 233 enum psp_ring_type ring_type) 234 { 235 int ret = 0; 236 struct psp_ring *ring; 237 struct amdgpu_device *adev = psp->adev; 238 239 ring = &psp->km_ring; 240 241 ring->ring_type = ring_type; 242 243 /* allocate 4k Page of Local Frame Buffer memory for ring */ 244 ring->ring_size = 0x1000; 245 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 246 AMDGPU_GEM_DOMAIN_VRAM, 247 &adev->firmware.rbuf, 248 &ring->ring_mem_mc_addr, 249 (void **)&ring->ring_mem); 250 if (ret) { 251 ring->ring_size = 0; 252 return ret; 253 } 254 255 return 0; 256 } 257 258 static void psp_v3_1_reroute_ih(struct psp_context *psp) 259 { 260 struct amdgpu_device *adev = psp->adev; 261 uint32_t tmp; 262 263 /* Change IH ring for VMC */ 264 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b); 265 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1); 266 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 267 268 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3); 269 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); 270 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); 271 272 mdelay(20); 273 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 274 0x80000000, 0x8000FFFF, false); 275 276 /* Change IH ring for UMC */ 277 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b); 278 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 279 280 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4); 281 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); 282 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); 283 284 mdelay(20); 285 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 286 0x80000000, 0x8000FFFF, false); 287 } 288 289 static int psp_v3_1_ring_create(struct psp_context *psp, 290 enum psp_ring_type ring_type) 291 { 292 int ret = 0; 293 unsigned int psp_ring_reg = 0; 294 struct psp_ring *ring = &psp->km_ring; 295 struct amdgpu_device *adev = psp->adev; 296 297 psp_v3_1_reroute_ih(psp); 298 299 /* Write low address of the ring to C2PMSG_69 */ 300 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 301 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); 302 /* Write high address of the ring to C2PMSG_70 */ 303 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 304 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); 305 /* Write size of ring to C2PMSG_71 */ 306 psp_ring_reg = ring->ring_size; 307 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); 308 /* Write the ring initialization command to C2PMSG_64 */ 309 psp_ring_reg = ring_type; 310 psp_ring_reg = psp_ring_reg << 16; 311 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 312 313 /* there might be handshake issue with hardware which needs delay */ 314 mdelay(20); 315 316 /* Wait for response flag (bit 31) in C2PMSG_64 */ 317 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 318 0x80000000, 0x8000FFFF, false); 319 320 return ret; 321 } 322 323 static int psp_v3_1_ring_stop(struct psp_context *psp, 324 enum psp_ring_type ring_type) 325 { 326 int ret = 0; 327 unsigned int psp_ring_reg = 0; 328 struct amdgpu_device *adev = psp->adev; 329 330 /* Write the ring destroy command to C2PMSG_64 */ 331 psp_ring_reg = 3 << 16; 332 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 333 334 /* there might be handshake issue with hardware which needs delay */ 335 mdelay(20); 336 337 /* Wait for response flag (bit 31) in C2PMSG_64 */ 338 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 339 0x80000000, 0x80000000, false); 340 341 return ret; 342 } 343 344 static int psp_v3_1_ring_destroy(struct psp_context *psp, 345 enum psp_ring_type ring_type) 346 { 347 int ret = 0; 348 struct psp_ring *ring = &psp->km_ring; 349 struct amdgpu_device *adev = psp->adev; 350 351 ret = psp_v3_1_ring_stop(psp, ring_type); 352 if (ret) 353 DRM_ERROR("Fail to stop psp ring\n"); 354 355 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 356 &ring->ring_mem_mc_addr, 357 (void **)&ring->ring_mem); 358 359 return ret; 360 } 361 362 static int psp_v3_1_cmd_submit(struct psp_context *psp, 363 struct amdgpu_firmware_info *ucode, 364 uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, 365 int index) 366 { 367 unsigned int psp_write_ptr_reg = 0; 368 struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem; 369 struct psp_ring *ring = &psp->km_ring; 370 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 371 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 372 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 373 struct amdgpu_device *adev = psp->adev; 374 uint32_t ring_size_dw = ring->ring_size / 4; 375 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 376 377 /* KM (GPCOM) prepare write pointer */ 378 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); 379 380 /* Update KM RB frame pointer to new frame */ 381 /* write_frame ptr increments by size of rb_frame in bytes */ 382 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 383 if ((psp_write_ptr_reg % ring_size_dw) == 0) 384 write_frame = ring_buffer_start; 385 else 386 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 387 /* Check invalid write_frame ptr address */ 388 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 389 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 390 ring_buffer_start, ring_buffer_end, write_frame); 391 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 392 return -EINVAL; 393 } 394 395 /* Initialize KM RB frame */ 396 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 397 398 /* Update KM RB frame */ 399 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 400 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 401 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 402 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 403 write_frame->fence_value = index; 404 405 /* Update the write Pointer in DWORDs */ 406 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 407 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg); 408 409 return 0; 410 } 411 412 static int 413 psp_v3_1_sram_map(struct amdgpu_device *adev, 414 unsigned int *sram_offset, unsigned int *sram_addr_reg_offset, 415 unsigned int *sram_data_reg_offset, 416 enum AMDGPU_UCODE_ID ucode_id) 417 { 418 int ret = 0; 419 420 switch(ucode_id) { 421 /* TODO: needs to confirm */ 422 #if 0 423 case AMDGPU_UCODE_ID_SMC: 424 *sram_offset = 0; 425 *sram_addr_reg_offset = 0; 426 *sram_data_reg_offset = 0; 427 break; 428 #endif 429 430 case AMDGPU_UCODE_ID_CP_CE: 431 *sram_offset = 0x0; 432 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR); 433 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA); 434 break; 435 436 case AMDGPU_UCODE_ID_CP_PFP: 437 *sram_offset = 0x0; 438 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR); 439 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA); 440 break; 441 442 case AMDGPU_UCODE_ID_CP_ME: 443 *sram_offset = 0x0; 444 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR); 445 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA); 446 break; 447 448 case AMDGPU_UCODE_ID_CP_MEC1: 449 *sram_offset = 0x10000; 450 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR); 451 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); 452 break; 453 454 case AMDGPU_UCODE_ID_CP_MEC2: 455 *sram_offset = 0x10000; 456 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR); 457 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA); 458 break; 459 460 case AMDGPU_UCODE_ID_RLC_G: 461 *sram_offset = 0x2000; 462 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR); 463 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA); 464 break; 465 466 case AMDGPU_UCODE_ID_SDMA0: 467 *sram_offset = 0x0; 468 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR); 469 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA); 470 break; 471 472 /* TODO: needs to confirm */ 473 #if 0 474 case AMDGPU_UCODE_ID_SDMA1: 475 *sram_offset = ; 476 *sram_addr_reg_offset = ; 477 break; 478 479 case AMDGPU_UCODE_ID_UVD: 480 *sram_offset = ; 481 *sram_addr_reg_offset = ; 482 break; 483 484 case AMDGPU_UCODE_ID_VCE: 485 *sram_offset = ; 486 *sram_addr_reg_offset = ; 487 break; 488 #endif 489 490 case AMDGPU_UCODE_ID_MAXIMUM: 491 default: 492 ret = -EINVAL; 493 break; 494 } 495 496 return ret; 497 } 498 499 static bool psp_v3_1_compare_sram_data(struct psp_context *psp, 500 struct amdgpu_firmware_info *ucode, 501 enum AMDGPU_UCODE_ID ucode_type) 502 { 503 int err = 0; 504 unsigned int fw_sram_reg_val = 0; 505 unsigned int fw_sram_addr_reg_offset = 0; 506 unsigned int fw_sram_data_reg_offset = 0; 507 unsigned int ucode_size; 508 uint32_t *ucode_mem = NULL; 509 struct amdgpu_device *adev = psp->adev; 510 511 err = psp_v3_1_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset, 512 &fw_sram_data_reg_offset, ucode_type); 513 if (err) 514 return false; 515 516 WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val); 517 518 ucode_size = ucode->ucode_size; 519 ucode_mem = (uint32_t *)ucode->kaddr; 520 while (ucode_size) { 521 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset); 522 523 if (*ucode_mem != fw_sram_reg_val) 524 return false; 525 526 ucode_mem++; 527 /* 4 bytes */ 528 ucode_size -= 4; 529 } 530 531 return true; 532 } 533 534 static bool psp_v3_1_smu_reload_quirk(struct psp_context *psp) 535 { 536 struct amdgpu_device *adev = psp->adev; 537 uint32_t reg; 538 539 reg = RREG32_PCIE(smnMP1_FIRMWARE_FLAGS | 0x03b00000); 540 return (reg & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) ? true : false; 541 } 542 543 static int psp_v3_1_mode1_reset(struct psp_context *psp) 544 { 545 int ret; 546 uint32_t offset; 547 struct amdgpu_device *adev = psp->adev; 548 549 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); 550 551 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false); 552 553 if (ret) { 554 DRM_INFO("psp is not working correctly before mode1 reset!\n"); 555 return -EINVAL; 556 } 557 558 /*send the mode 1 reset command*/ 559 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST); 560 561 msleep(500); 562 563 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); 564 565 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false); 566 567 if (ret) { 568 DRM_INFO("psp mode 1 reset failed!\n"); 569 return -EINVAL; 570 } 571 572 DRM_INFO("psp mode1 reset succeed \n"); 573 574 return 0; 575 } 576 577 static const struct psp_funcs psp_v3_1_funcs = { 578 .init_microcode = psp_v3_1_init_microcode, 579 .bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv, 580 .bootloader_load_sos = psp_v3_1_bootloader_load_sos, 581 .ring_init = psp_v3_1_ring_init, 582 .ring_create = psp_v3_1_ring_create, 583 .ring_stop = psp_v3_1_ring_stop, 584 .ring_destroy = psp_v3_1_ring_destroy, 585 .cmd_submit = psp_v3_1_cmd_submit, 586 .compare_sram_data = psp_v3_1_compare_sram_data, 587 .smu_reload_quirk = psp_v3_1_smu_reload_quirk, 588 .mode1_reset = psp_v3_1_mode1_reset, 589 }; 590 591 void psp_v3_1_set_psp_funcs(struct psp_context *psp) 592 { 593 psp->funcs = &psp_v3_1_funcs; 594 } 595