1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drmP.h> 28 #include "amdgpu.h" 29 #include "amdgpu_psp.h" 30 #include "amdgpu_ucode.h" 31 #include "soc15_common.h" 32 #include "psp_v3_1.h" 33 34 #include "mp/mp_9_0_offset.h" 35 #include "mp/mp_9_0_sh_mask.h" 36 #include "gc/gc_9_0_offset.h" 37 #include "sdma0/sdma0_4_0_offset.h" 38 #include "nbio/nbio_6_1_offset.h" 39 40 MODULE_FIRMWARE("amdgpu/vega10_sos.bin"); 41 MODULE_FIRMWARE("amdgpu/vega10_asd.bin"); 42 MODULE_FIRMWARE("amdgpu/vega12_sos.bin"); 43 MODULE_FIRMWARE("amdgpu/vega12_asd.bin"); 44 MODULE_FIRMWARE("amdgpu/vega20_sos.bin"); 45 MODULE_FIRMWARE("amdgpu/vega20_asd.bin"); 46 47 48 #define smnMP1_FIRMWARE_FLAGS 0x3010028 49 50 static uint32_t sos_old_versions[] = {1517616, 1510592, 1448594, 1446554}; 51 52 static int 53 psp_v3_1_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type) 54 { 55 switch(ucode->ucode_id) { 56 case AMDGPU_UCODE_ID_SDMA0: 57 *type = GFX_FW_TYPE_SDMA0; 58 break; 59 case AMDGPU_UCODE_ID_SDMA1: 60 *type = GFX_FW_TYPE_SDMA1; 61 break; 62 case AMDGPU_UCODE_ID_CP_CE: 63 *type = GFX_FW_TYPE_CP_CE; 64 break; 65 case AMDGPU_UCODE_ID_CP_PFP: 66 *type = GFX_FW_TYPE_CP_PFP; 67 break; 68 case AMDGPU_UCODE_ID_CP_ME: 69 *type = GFX_FW_TYPE_CP_ME; 70 break; 71 case AMDGPU_UCODE_ID_CP_MEC1: 72 *type = GFX_FW_TYPE_CP_MEC; 73 break; 74 case AMDGPU_UCODE_ID_CP_MEC1_JT: 75 *type = GFX_FW_TYPE_CP_MEC_ME1; 76 break; 77 case AMDGPU_UCODE_ID_CP_MEC2: 78 *type = GFX_FW_TYPE_CP_MEC; 79 break; 80 case AMDGPU_UCODE_ID_CP_MEC2_JT: 81 *type = GFX_FW_TYPE_CP_MEC_ME2; 82 break; 83 case AMDGPU_UCODE_ID_RLC_G: 84 *type = GFX_FW_TYPE_RLC_G; 85 break; 86 case AMDGPU_UCODE_ID_SMC: 87 *type = GFX_FW_TYPE_SMU; 88 break; 89 case AMDGPU_UCODE_ID_UVD: 90 *type = GFX_FW_TYPE_UVD; 91 break; 92 case AMDGPU_UCODE_ID_VCE: 93 *type = GFX_FW_TYPE_VCE; 94 break; 95 case AMDGPU_UCODE_ID_MAXIMUM: 96 default: 97 return -EINVAL; 98 } 99 100 return 0; 101 } 102 103 static int psp_v3_1_init_microcode(struct psp_context *psp) 104 { 105 struct amdgpu_device *adev = psp->adev; 106 const char *chip_name; 107 char fw_name[30]; 108 int err = 0; 109 const struct psp_firmware_header_v1_0 *hdr; 110 111 DRM_DEBUG("\n"); 112 113 switch (adev->asic_type) { 114 case CHIP_VEGA10: 115 chip_name = "vega10"; 116 break; 117 case CHIP_VEGA12: 118 chip_name = "vega12"; 119 break; 120 default: BUG(); 121 } 122 123 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 124 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 125 if (err) 126 goto out; 127 128 err = amdgpu_ucode_validate(adev->psp.sos_fw); 129 if (err) 130 goto out; 131 132 hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 133 adev->psp.sos_fw_version = le32_to_cpu(hdr->header.ucode_version); 134 adev->psp.sos_feature_version = le32_to_cpu(hdr->ucode_feature_version); 135 adev->psp.sos_bin_size = le32_to_cpu(hdr->sos_size_bytes); 136 adev->psp.sys_bin_size = le32_to_cpu(hdr->header.ucode_size_bytes) - 137 le32_to_cpu(hdr->sos_size_bytes); 138 adev->psp.sys_start_addr = (uint8_t *)hdr + 139 le32_to_cpu(hdr->header.ucode_array_offset_bytes); 140 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr + 141 le32_to_cpu(hdr->sos_offset_bytes); 142 143 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 144 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 145 if (err) 146 goto out; 147 148 err = amdgpu_ucode_validate(adev->psp.asd_fw); 149 if (err) 150 goto out; 151 152 hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 153 adev->psp.asd_fw_version = le32_to_cpu(hdr->header.ucode_version); 154 adev->psp.asd_feature_version = le32_to_cpu(hdr->ucode_feature_version); 155 adev->psp.asd_ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes); 156 adev->psp.asd_start_addr = (uint8_t *)hdr + 157 le32_to_cpu(hdr->header.ucode_array_offset_bytes); 158 159 return 0; 160 out: 161 if (err) { 162 dev_err(adev->dev, 163 "psp v3.1: Failed to load firmware \"%s\"\n", 164 fw_name); 165 release_firmware(adev->psp.sos_fw); 166 adev->psp.sos_fw = NULL; 167 release_firmware(adev->psp.asd_fw); 168 adev->psp.asd_fw = NULL; 169 } 170 171 return err; 172 } 173 174 static int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp) 175 { 176 int ret; 177 uint32_t psp_gfxdrv_command_reg = 0; 178 struct amdgpu_device *adev = psp->adev; 179 uint32_t sol_reg; 180 181 /* Check sOS sign of life register to confirm sys driver and sOS 182 * are already been loaded. 183 */ 184 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 185 if (sol_reg) 186 return 0; 187 188 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 189 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 190 0x80000000, 0x80000000, false); 191 if (ret) 192 return ret; 193 194 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 195 196 /* Copy PSP System Driver binary to memory */ 197 memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size); 198 199 /* Provide the sys driver to bootrom */ 200 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 201 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 202 psp_gfxdrv_command_reg = 1 << 16; 203 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 204 psp_gfxdrv_command_reg); 205 206 /* there might be handshake issue with hardware which needs delay */ 207 mdelay(20); 208 209 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 210 0x80000000, 0x80000000, false); 211 212 return ret; 213 } 214 215 static bool psp_v3_1_match_version(struct amdgpu_device *adev, uint32_t ver) 216 { 217 int i; 218 219 if (ver == adev->psp.sos_fw_version) 220 return true; 221 222 /* 223 * Double check if the latest four legacy versions. 224 * If yes, it is still the right version. 225 */ 226 for (i = 0; i < sizeof(sos_old_versions) / sizeof(uint32_t); i++) { 227 if (sos_old_versions[i] == adev->psp.sos_fw_version) 228 return true; 229 } 230 231 return false; 232 } 233 234 static int psp_v3_1_bootloader_load_sos(struct psp_context *psp) 235 { 236 int ret; 237 unsigned int psp_gfxdrv_command_reg = 0; 238 struct amdgpu_device *adev = psp->adev; 239 uint32_t sol_reg, ver; 240 241 /* Check sOS sign of life register to confirm sys driver and sOS 242 * are already been loaded. 243 */ 244 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 245 if (sol_reg) 246 return 0; 247 248 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 249 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 250 0x80000000, 0x80000000, false); 251 if (ret) 252 return ret; 253 254 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 255 256 /* Copy Secure OS binary to PSP memory */ 257 memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size); 258 259 /* Provide the PSP secure OS to bootrom */ 260 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 261 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 262 psp_gfxdrv_command_reg = 2 << 16; 263 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 264 psp_gfxdrv_command_reg); 265 266 /* there might be handshake issue with hardware which needs delay */ 267 mdelay(20); 268 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), 269 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 270 0, true); 271 272 ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58); 273 if (!psp_v3_1_match_version(adev, ver)) 274 DRM_WARN("SOS version doesn't match\n"); 275 276 return ret; 277 } 278 279 static int psp_v3_1_prep_cmd_buf(struct amdgpu_firmware_info *ucode, 280 struct psp_gfx_cmd_resp *cmd) 281 { 282 int ret; 283 uint64_t fw_mem_mc_addr = ucode->mc_addr; 284 285 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 286 287 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 288 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 289 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 290 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 291 292 ret = psp_v3_1_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 293 if (ret) 294 DRM_ERROR("Unknown firmware type\n"); 295 296 return ret; 297 } 298 299 static int psp_v3_1_ring_init(struct psp_context *psp, 300 enum psp_ring_type ring_type) 301 { 302 int ret = 0; 303 struct psp_ring *ring; 304 struct amdgpu_device *adev = psp->adev; 305 306 ring = &psp->km_ring; 307 308 ring->ring_type = ring_type; 309 310 /* allocate 4k Page of Local Frame Buffer memory for ring */ 311 ring->ring_size = 0x1000; 312 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 313 AMDGPU_GEM_DOMAIN_VRAM, 314 &adev->firmware.rbuf, 315 &ring->ring_mem_mc_addr, 316 (void **)&ring->ring_mem); 317 if (ret) { 318 ring->ring_size = 0; 319 return ret; 320 } 321 322 return 0; 323 } 324 325 static int psp_v3_1_ring_create(struct psp_context *psp, 326 enum psp_ring_type ring_type) 327 { 328 int ret = 0; 329 unsigned int psp_ring_reg = 0; 330 struct psp_ring *ring = &psp->km_ring; 331 struct amdgpu_device *adev = psp->adev; 332 333 /* Write low address of the ring to C2PMSG_69 */ 334 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 335 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); 336 /* Write high address of the ring to C2PMSG_70 */ 337 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 338 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); 339 /* Write size of ring to C2PMSG_71 */ 340 psp_ring_reg = ring->ring_size; 341 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); 342 /* Write the ring initialization command to C2PMSG_64 */ 343 psp_ring_reg = ring_type; 344 psp_ring_reg = psp_ring_reg << 16; 345 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 346 347 /* there might be handshake issue with hardware which needs delay */ 348 mdelay(20); 349 350 /* Wait for response flag (bit 31) in C2PMSG_64 */ 351 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 352 0x80000000, 0x8000FFFF, false); 353 354 return ret; 355 } 356 357 static int psp_v3_1_ring_stop(struct psp_context *psp, 358 enum psp_ring_type ring_type) 359 { 360 int ret = 0; 361 struct psp_ring *ring; 362 unsigned int psp_ring_reg = 0; 363 struct amdgpu_device *adev = psp->adev; 364 365 ring = &psp->km_ring; 366 367 /* Write the ring destroy command to C2PMSG_64 */ 368 psp_ring_reg = 3 << 16; 369 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 370 371 /* there might be handshake issue with hardware which needs delay */ 372 mdelay(20); 373 374 /* Wait for response flag (bit 31) in C2PMSG_64 */ 375 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 376 0x80000000, 0x80000000, false); 377 378 return ret; 379 } 380 381 static int psp_v3_1_ring_destroy(struct psp_context *psp, 382 enum psp_ring_type ring_type) 383 { 384 int ret = 0; 385 struct psp_ring *ring = &psp->km_ring; 386 struct amdgpu_device *adev = psp->adev; 387 388 ret = psp_v3_1_ring_stop(psp, ring_type); 389 if (ret) 390 DRM_ERROR("Fail to stop psp ring\n"); 391 392 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 393 &ring->ring_mem_mc_addr, 394 (void **)&ring->ring_mem); 395 396 return ret; 397 } 398 399 static int psp_v3_1_cmd_submit(struct psp_context *psp, 400 struct amdgpu_firmware_info *ucode, 401 uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, 402 int index) 403 { 404 unsigned int psp_write_ptr_reg = 0; 405 struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem; 406 struct psp_ring *ring = &psp->km_ring; 407 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 408 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 409 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 410 struct amdgpu_device *adev = psp->adev; 411 uint32_t ring_size_dw = ring->ring_size / 4; 412 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 413 414 /* KM (GPCOM) prepare write pointer */ 415 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); 416 417 /* Update KM RB frame pointer to new frame */ 418 /* write_frame ptr increments by size of rb_frame in bytes */ 419 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 420 if ((psp_write_ptr_reg % ring_size_dw) == 0) 421 write_frame = ring_buffer_start; 422 else 423 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 424 /* Check invalid write_frame ptr address */ 425 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 426 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 427 ring_buffer_start, ring_buffer_end, write_frame); 428 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 429 return -EINVAL; 430 } 431 432 /* Initialize KM RB frame */ 433 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 434 435 /* Update KM RB frame */ 436 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 437 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 438 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 439 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 440 write_frame->fence_value = index; 441 442 /* Update the write Pointer in DWORDs */ 443 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 444 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg); 445 446 return 0; 447 } 448 449 static int 450 psp_v3_1_sram_map(struct amdgpu_device *adev, 451 unsigned int *sram_offset, unsigned int *sram_addr_reg_offset, 452 unsigned int *sram_data_reg_offset, 453 enum AMDGPU_UCODE_ID ucode_id) 454 { 455 int ret = 0; 456 457 switch(ucode_id) { 458 /* TODO: needs to confirm */ 459 #if 0 460 case AMDGPU_UCODE_ID_SMC: 461 *sram_offset = 0; 462 *sram_addr_reg_offset = 0; 463 *sram_data_reg_offset = 0; 464 break; 465 #endif 466 467 case AMDGPU_UCODE_ID_CP_CE: 468 *sram_offset = 0x0; 469 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR); 470 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA); 471 break; 472 473 case AMDGPU_UCODE_ID_CP_PFP: 474 *sram_offset = 0x0; 475 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR); 476 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA); 477 break; 478 479 case AMDGPU_UCODE_ID_CP_ME: 480 *sram_offset = 0x0; 481 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR); 482 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA); 483 break; 484 485 case AMDGPU_UCODE_ID_CP_MEC1: 486 *sram_offset = 0x10000; 487 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR); 488 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); 489 break; 490 491 case AMDGPU_UCODE_ID_CP_MEC2: 492 *sram_offset = 0x10000; 493 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR); 494 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA); 495 break; 496 497 case AMDGPU_UCODE_ID_RLC_G: 498 *sram_offset = 0x2000; 499 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR); 500 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA); 501 break; 502 503 case AMDGPU_UCODE_ID_SDMA0: 504 *sram_offset = 0x0; 505 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR); 506 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA); 507 break; 508 509 /* TODO: needs to confirm */ 510 #if 0 511 case AMDGPU_UCODE_ID_SDMA1: 512 *sram_offset = ; 513 *sram_addr_reg_offset = ; 514 break; 515 516 case AMDGPU_UCODE_ID_UVD: 517 *sram_offset = ; 518 *sram_addr_reg_offset = ; 519 break; 520 521 case AMDGPU_UCODE_ID_VCE: 522 *sram_offset = ; 523 *sram_addr_reg_offset = ; 524 break; 525 #endif 526 527 case AMDGPU_UCODE_ID_MAXIMUM: 528 default: 529 ret = -EINVAL; 530 break; 531 } 532 533 return ret; 534 } 535 536 static bool psp_v3_1_compare_sram_data(struct psp_context *psp, 537 struct amdgpu_firmware_info *ucode, 538 enum AMDGPU_UCODE_ID ucode_type) 539 { 540 int err = 0; 541 unsigned int fw_sram_reg_val = 0; 542 unsigned int fw_sram_addr_reg_offset = 0; 543 unsigned int fw_sram_data_reg_offset = 0; 544 unsigned int ucode_size; 545 uint32_t *ucode_mem = NULL; 546 struct amdgpu_device *adev = psp->adev; 547 548 err = psp_v3_1_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset, 549 &fw_sram_data_reg_offset, ucode_type); 550 if (err) 551 return false; 552 553 WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val); 554 555 ucode_size = ucode->ucode_size; 556 ucode_mem = (uint32_t *)ucode->kaddr; 557 while (ucode_size) { 558 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset); 559 560 if (*ucode_mem != fw_sram_reg_val) 561 return false; 562 563 ucode_mem++; 564 /* 4 bytes */ 565 ucode_size -= 4; 566 } 567 568 return true; 569 } 570 571 static bool psp_v3_1_smu_reload_quirk(struct psp_context *psp) 572 { 573 struct amdgpu_device *adev = psp->adev; 574 uint32_t reg; 575 576 reg = smnMP1_FIRMWARE_FLAGS | 0x03b00000; 577 WREG32_SOC15(NBIO, 0, mmPCIE_INDEX2, reg); 578 reg = RREG32_SOC15(NBIO, 0, mmPCIE_DATA2); 579 return (reg & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) ? true : false; 580 } 581 582 static int psp_v3_1_mode1_reset(struct psp_context *psp) 583 { 584 int ret; 585 uint32_t offset; 586 struct amdgpu_device *adev = psp->adev; 587 588 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); 589 590 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false); 591 592 if (ret) { 593 DRM_INFO("psp is not working correctly before mode1 reset!\n"); 594 return -EINVAL; 595 } 596 597 /*send the mode 1 reset command*/ 598 WREG32(offset, 0x70000); 599 600 mdelay(1000); 601 602 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); 603 604 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false); 605 606 if (ret) { 607 DRM_INFO("psp mode 1 reset failed!\n"); 608 return -EINVAL; 609 } 610 611 DRM_INFO("psp mode1 reset succeed \n"); 612 613 return 0; 614 } 615 616 static const struct psp_funcs psp_v3_1_funcs = { 617 .init_microcode = psp_v3_1_init_microcode, 618 .bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv, 619 .bootloader_load_sos = psp_v3_1_bootloader_load_sos, 620 .prep_cmd_buf = psp_v3_1_prep_cmd_buf, 621 .ring_init = psp_v3_1_ring_init, 622 .ring_create = psp_v3_1_ring_create, 623 .ring_stop = psp_v3_1_ring_stop, 624 .ring_destroy = psp_v3_1_ring_destroy, 625 .cmd_submit = psp_v3_1_cmd_submit, 626 .compare_sram_data = psp_v3_1_compare_sram_data, 627 .smu_reload_quirk = psp_v3_1_smu_reload_quirk, 628 .mode1_reset = psp_v3_1_mode1_reset, 629 }; 630 631 void psp_v3_1_set_psp_funcs(struct psp_context *psp) 632 { 633 psp->funcs = &psp_v3_1_funcs; 634 } 635