1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drmP.h> 28 #include "amdgpu.h" 29 #include "amdgpu_psp.h" 30 #include "amdgpu_ucode.h" 31 #include "soc15_common.h" 32 #include "psp_v3_1.h" 33 34 #include "mp/mp_9_0_offset.h" 35 #include "mp/mp_9_0_sh_mask.h" 36 #include "gc/gc_9_0_offset.h" 37 #include "sdma0/sdma0_4_0_offset.h" 38 #include "nbio/nbio_6_1_offset.h" 39 40 MODULE_FIRMWARE("amdgpu/vega10_sos.bin"); 41 MODULE_FIRMWARE("amdgpu/vega10_asd.bin"); 42 43 #define smnMP1_FIRMWARE_FLAGS 0x3010028 44 45 static int 46 psp_v3_1_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type) 47 { 48 switch(ucode->ucode_id) { 49 case AMDGPU_UCODE_ID_SDMA0: 50 *type = GFX_FW_TYPE_SDMA0; 51 break; 52 case AMDGPU_UCODE_ID_SDMA1: 53 *type = GFX_FW_TYPE_SDMA1; 54 break; 55 case AMDGPU_UCODE_ID_CP_CE: 56 *type = GFX_FW_TYPE_CP_CE; 57 break; 58 case AMDGPU_UCODE_ID_CP_PFP: 59 *type = GFX_FW_TYPE_CP_PFP; 60 break; 61 case AMDGPU_UCODE_ID_CP_ME: 62 *type = GFX_FW_TYPE_CP_ME; 63 break; 64 case AMDGPU_UCODE_ID_CP_MEC1: 65 *type = GFX_FW_TYPE_CP_MEC; 66 break; 67 case AMDGPU_UCODE_ID_CP_MEC1_JT: 68 *type = GFX_FW_TYPE_CP_MEC_ME1; 69 break; 70 case AMDGPU_UCODE_ID_CP_MEC2: 71 *type = GFX_FW_TYPE_CP_MEC; 72 break; 73 case AMDGPU_UCODE_ID_CP_MEC2_JT: 74 *type = GFX_FW_TYPE_CP_MEC_ME2; 75 break; 76 case AMDGPU_UCODE_ID_RLC_G: 77 *type = GFX_FW_TYPE_RLC_G; 78 break; 79 case AMDGPU_UCODE_ID_SMC: 80 *type = GFX_FW_TYPE_SMU; 81 break; 82 case AMDGPU_UCODE_ID_UVD: 83 *type = GFX_FW_TYPE_UVD; 84 break; 85 case AMDGPU_UCODE_ID_VCE: 86 *type = GFX_FW_TYPE_VCE; 87 break; 88 case AMDGPU_UCODE_ID_MAXIMUM: 89 default: 90 return -EINVAL; 91 } 92 93 return 0; 94 } 95 96 static int psp_v3_1_init_microcode(struct psp_context *psp) 97 { 98 struct amdgpu_device *adev = psp->adev; 99 const char *chip_name; 100 char fw_name[30]; 101 int err = 0; 102 const struct psp_firmware_header_v1_0 *hdr; 103 104 DRM_DEBUG("\n"); 105 106 switch (adev->asic_type) { 107 case CHIP_VEGA10: 108 chip_name = "vega10"; 109 break; 110 default: BUG(); 111 } 112 113 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 114 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 115 if (err) 116 goto out; 117 118 err = amdgpu_ucode_validate(adev->psp.sos_fw); 119 if (err) 120 goto out; 121 122 hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 123 adev->psp.sos_fw_version = le32_to_cpu(hdr->header.ucode_version); 124 adev->psp.sos_feature_version = le32_to_cpu(hdr->ucode_feature_version); 125 adev->psp.sos_bin_size = le32_to_cpu(hdr->sos_size_bytes); 126 adev->psp.sys_bin_size = le32_to_cpu(hdr->header.ucode_size_bytes) - 127 le32_to_cpu(hdr->sos_size_bytes); 128 adev->psp.sys_start_addr = (uint8_t *)hdr + 129 le32_to_cpu(hdr->header.ucode_array_offset_bytes); 130 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr + 131 le32_to_cpu(hdr->sos_offset_bytes); 132 133 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 134 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 135 if (err) 136 goto out; 137 138 err = amdgpu_ucode_validate(adev->psp.asd_fw); 139 if (err) 140 goto out; 141 142 hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 143 adev->psp.asd_fw_version = le32_to_cpu(hdr->header.ucode_version); 144 adev->psp.asd_feature_version = le32_to_cpu(hdr->ucode_feature_version); 145 adev->psp.asd_ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes); 146 adev->psp.asd_start_addr = (uint8_t *)hdr + 147 le32_to_cpu(hdr->header.ucode_array_offset_bytes); 148 149 return 0; 150 out: 151 if (err) { 152 dev_err(adev->dev, 153 "psp v3.1: Failed to load firmware \"%s\"\n", 154 fw_name); 155 release_firmware(adev->psp.sos_fw); 156 adev->psp.sos_fw = NULL; 157 release_firmware(adev->psp.asd_fw); 158 adev->psp.asd_fw = NULL; 159 } 160 161 return err; 162 } 163 164 static int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp) 165 { 166 int ret; 167 uint32_t psp_gfxdrv_command_reg = 0; 168 struct amdgpu_device *adev = psp->adev; 169 uint32_t sol_reg; 170 171 /* Check sOS sign of life register to confirm sys driver and sOS 172 * are already been loaded. 173 */ 174 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 175 if (sol_reg) 176 return 0; 177 178 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 179 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 180 0x80000000, 0x80000000, false); 181 if (ret) 182 return ret; 183 184 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 185 186 /* Copy PSP System Driver binary to memory */ 187 memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size); 188 189 /* Provide the sys driver to bootrom */ 190 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 191 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 192 psp_gfxdrv_command_reg = 1 << 16; 193 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 194 psp_gfxdrv_command_reg); 195 196 /* there might be handshake issue with hardware which needs delay */ 197 mdelay(20); 198 199 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 200 0x80000000, 0x80000000, false); 201 202 return ret; 203 } 204 205 static int psp_v3_1_bootloader_load_sos(struct psp_context *psp) 206 { 207 int ret; 208 unsigned int psp_gfxdrv_command_reg = 0; 209 struct amdgpu_device *adev = psp->adev; 210 uint32_t sol_reg; 211 212 /* Check sOS sign of life register to confirm sys driver and sOS 213 * are already been loaded. 214 */ 215 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 216 if (sol_reg) 217 return 0; 218 219 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 220 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 221 0x80000000, 0x80000000, false); 222 if (ret) 223 return ret; 224 225 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 226 227 /* Copy Secure OS binary to PSP memory */ 228 memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size); 229 230 /* Provide the PSP secure OS to bootrom */ 231 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 232 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 233 psp_gfxdrv_command_reg = 2 << 16; 234 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 235 psp_gfxdrv_command_reg); 236 237 /* there might be handshake issue with hardware which needs delay */ 238 mdelay(20); 239 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), 240 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 241 0, true); 242 243 return ret; 244 } 245 246 static int psp_v3_1_prep_cmd_buf(struct amdgpu_firmware_info *ucode, 247 struct psp_gfx_cmd_resp *cmd) 248 { 249 int ret; 250 uint64_t fw_mem_mc_addr = ucode->mc_addr; 251 252 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 253 254 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 255 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 256 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 257 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 258 259 ret = psp_v3_1_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 260 if (ret) 261 DRM_ERROR("Unknown firmware type\n"); 262 263 return ret; 264 } 265 266 static int psp_v3_1_ring_init(struct psp_context *psp, 267 enum psp_ring_type ring_type) 268 { 269 int ret = 0; 270 struct psp_ring *ring; 271 struct amdgpu_device *adev = psp->adev; 272 273 ring = &psp->km_ring; 274 275 ring->ring_type = ring_type; 276 277 /* allocate 4k Page of Local Frame Buffer memory for ring */ 278 ring->ring_size = 0x1000; 279 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 280 AMDGPU_GEM_DOMAIN_VRAM, 281 &adev->firmware.rbuf, 282 &ring->ring_mem_mc_addr, 283 (void **)&ring->ring_mem); 284 if (ret) { 285 ring->ring_size = 0; 286 return ret; 287 } 288 289 return 0; 290 } 291 292 static int psp_v3_1_ring_create(struct psp_context *psp, 293 enum psp_ring_type ring_type) 294 { 295 int ret = 0; 296 unsigned int psp_ring_reg = 0; 297 struct psp_ring *ring = &psp->km_ring; 298 struct amdgpu_device *adev = psp->adev; 299 300 /* Write low address of the ring to C2PMSG_69 */ 301 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 302 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); 303 /* Write high address of the ring to C2PMSG_70 */ 304 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 305 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); 306 /* Write size of ring to C2PMSG_71 */ 307 psp_ring_reg = ring->ring_size; 308 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); 309 /* Write the ring initialization command to C2PMSG_64 */ 310 psp_ring_reg = ring_type; 311 psp_ring_reg = psp_ring_reg << 16; 312 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 313 314 /* there might be handshake issue with hardware which needs delay */ 315 mdelay(20); 316 317 /* Wait for response flag (bit 31) in C2PMSG_64 */ 318 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 319 0x80000000, 0x8000FFFF, false); 320 321 return ret; 322 } 323 324 static int psp_v3_1_ring_stop(struct psp_context *psp, 325 enum psp_ring_type ring_type) 326 { 327 int ret = 0; 328 struct psp_ring *ring; 329 unsigned int psp_ring_reg = 0; 330 struct amdgpu_device *adev = psp->adev; 331 332 ring = &psp->km_ring; 333 334 /* Write the ring destroy command to C2PMSG_64 */ 335 psp_ring_reg = 3 << 16; 336 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 337 338 /* there might be handshake issue with hardware which needs delay */ 339 mdelay(20); 340 341 /* Wait for response flag (bit 31) in C2PMSG_64 */ 342 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 343 0x80000000, 0x80000000, false); 344 345 return ret; 346 } 347 348 static int psp_v3_1_ring_destroy(struct psp_context *psp, 349 enum psp_ring_type ring_type) 350 { 351 int ret = 0; 352 struct psp_ring *ring = &psp->km_ring; 353 struct amdgpu_device *adev = psp->adev; 354 355 ret = psp_v3_1_ring_stop(psp, ring_type); 356 if (ret) 357 DRM_ERROR("Fail to stop psp ring\n"); 358 359 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 360 &ring->ring_mem_mc_addr, 361 (void **)&ring->ring_mem); 362 363 return ret; 364 } 365 366 static int psp_v3_1_cmd_submit(struct psp_context *psp, 367 struct amdgpu_firmware_info *ucode, 368 uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, 369 int index) 370 { 371 unsigned int psp_write_ptr_reg = 0; 372 struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem; 373 struct psp_ring *ring = &psp->km_ring; 374 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 375 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 376 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 377 struct amdgpu_device *adev = psp->adev; 378 uint32_t ring_size_dw = ring->ring_size / 4; 379 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 380 381 /* KM (GPCOM) prepare write pointer */ 382 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); 383 384 /* Update KM RB frame pointer to new frame */ 385 /* write_frame ptr increments by size of rb_frame in bytes */ 386 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 387 if ((psp_write_ptr_reg % ring_size_dw) == 0) 388 write_frame = ring_buffer_start; 389 else 390 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 391 /* Check invalid write_frame ptr address */ 392 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 393 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 394 ring_buffer_start, ring_buffer_end, write_frame); 395 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 396 return -EINVAL; 397 } 398 399 /* Initialize KM RB frame */ 400 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 401 402 /* Update KM RB frame */ 403 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 404 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 405 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 406 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 407 write_frame->fence_value = index; 408 409 /* Update the write Pointer in DWORDs */ 410 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 411 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg); 412 413 return 0; 414 } 415 416 static int 417 psp_v3_1_sram_map(struct amdgpu_device *adev, 418 unsigned int *sram_offset, unsigned int *sram_addr_reg_offset, 419 unsigned int *sram_data_reg_offset, 420 enum AMDGPU_UCODE_ID ucode_id) 421 { 422 int ret = 0; 423 424 switch(ucode_id) { 425 /* TODO: needs to confirm */ 426 #if 0 427 case AMDGPU_UCODE_ID_SMC: 428 *sram_offset = 0; 429 *sram_addr_reg_offset = 0; 430 *sram_data_reg_offset = 0; 431 break; 432 #endif 433 434 case AMDGPU_UCODE_ID_CP_CE: 435 *sram_offset = 0x0; 436 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR); 437 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA); 438 break; 439 440 case AMDGPU_UCODE_ID_CP_PFP: 441 *sram_offset = 0x0; 442 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR); 443 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA); 444 break; 445 446 case AMDGPU_UCODE_ID_CP_ME: 447 *sram_offset = 0x0; 448 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR); 449 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA); 450 break; 451 452 case AMDGPU_UCODE_ID_CP_MEC1: 453 *sram_offset = 0x10000; 454 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR); 455 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); 456 break; 457 458 case AMDGPU_UCODE_ID_CP_MEC2: 459 *sram_offset = 0x10000; 460 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR); 461 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA); 462 break; 463 464 case AMDGPU_UCODE_ID_RLC_G: 465 *sram_offset = 0x2000; 466 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR); 467 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA); 468 break; 469 470 case AMDGPU_UCODE_ID_SDMA0: 471 *sram_offset = 0x0; 472 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR); 473 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA); 474 break; 475 476 /* TODO: needs to confirm */ 477 #if 0 478 case AMDGPU_UCODE_ID_SDMA1: 479 *sram_offset = ; 480 *sram_addr_reg_offset = ; 481 break; 482 483 case AMDGPU_UCODE_ID_UVD: 484 *sram_offset = ; 485 *sram_addr_reg_offset = ; 486 break; 487 488 case AMDGPU_UCODE_ID_VCE: 489 *sram_offset = ; 490 *sram_addr_reg_offset = ; 491 break; 492 #endif 493 494 case AMDGPU_UCODE_ID_MAXIMUM: 495 default: 496 ret = -EINVAL; 497 break; 498 } 499 500 return ret; 501 } 502 503 static bool psp_v3_1_compare_sram_data(struct psp_context *psp, 504 struct amdgpu_firmware_info *ucode, 505 enum AMDGPU_UCODE_ID ucode_type) 506 { 507 int err = 0; 508 unsigned int fw_sram_reg_val = 0; 509 unsigned int fw_sram_addr_reg_offset = 0; 510 unsigned int fw_sram_data_reg_offset = 0; 511 unsigned int ucode_size; 512 uint32_t *ucode_mem = NULL; 513 struct amdgpu_device *adev = psp->adev; 514 515 err = psp_v3_1_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset, 516 &fw_sram_data_reg_offset, ucode_type); 517 if (err) 518 return false; 519 520 WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val); 521 522 ucode_size = ucode->ucode_size; 523 ucode_mem = (uint32_t *)ucode->kaddr; 524 while (ucode_size) { 525 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset); 526 527 if (*ucode_mem != fw_sram_reg_val) 528 return false; 529 530 ucode_mem++; 531 /* 4 bytes */ 532 ucode_size -= 4; 533 } 534 535 return true; 536 } 537 538 static bool psp_v3_1_smu_reload_quirk(struct psp_context *psp) 539 { 540 struct amdgpu_device *adev = psp->adev; 541 uint32_t reg; 542 543 reg = smnMP1_FIRMWARE_FLAGS | 0x03b00000; 544 WREG32_SOC15(NBIO, 0, mmPCIE_INDEX2, reg); 545 reg = RREG32_SOC15(NBIO, 0, mmPCIE_DATA2); 546 return (reg & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) ? true : false; 547 } 548 549 static int psp_v3_1_mode1_reset(struct psp_context *psp) 550 { 551 int ret; 552 uint32_t offset; 553 struct amdgpu_device *adev = psp->adev; 554 555 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); 556 557 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false); 558 559 if (ret) { 560 DRM_INFO("psp is not working correctly before mode1 reset!\n"); 561 return -EINVAL; 562 } 563 564 /*send the mode 1 reset command*/ 565 WREG32(offset, 0x70000); 566 567 mdelay(1000); 568 569 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); 570 571 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false); 572 573 if (ret) { 574 DRM_INFO("psp mode 1 reset failed!\n"); 575 return -EINVAL; 576 } 577 578 DRM_INFO("psp mode1 reset succeed \n"); 579 580 return 0; 581 } 582 583 static const struct psp_funcs psp_v3_1_funcs = { 584 .init_microcode = psp_v3_1_init_microcode, 585 .bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv, 586 .bootloader_load_sos = psp_v3_1_bootloader_load_sos, 587 .prep_cmd_buf = psp_v3_1_prep_cmd_buf, 588 .ring_init = psp_v3_1_ring_init, 589 .ring_create = psp_v3_1_ring_create, 590 .ring_stop = psp_v3_1_ring_stop, 591 .ring_destroy = psp_v3_1_ring_destroy, 592 .cmd_submit = psp_v3_1_cmd_submit, 593 .compare_sram_data = psp_v3_1_compare_sram_data, 594 .smu_reload_quirk = psp_v3_1_smu_reload_quirk, 595 .mode1_reset = psp_v3_1_mode1_reset, 596 }; 597 598 void psp_v3_1_set_psp_funcs(struct psp_context *psp) 599 { 600 psp->funcs = &psp_v3_1_funcs; 601 } 602