1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_psp.h" 32 #include "amdgpu_ucode.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 36 #include "mp/mp_9_0_offset.h" 37 #include "mp/mp_9_0_sh_mask.h" 38 #include "gc/gc_9_0_offset.h" 39 #include "sdma0/sdma0_4_0_offset.h" 40 #include "nbio/nbio_6_1_offset.h" 41 42 #include "oss/osssys_4_0_offset.h" 43 #include "oss/osssys_4_0_sh_mask.h" 44 45 MODULE_FIRMWARE("amdgpu/vega10_sos.bin"); 46 MODULE_FIRMWARE("amdgpu/vega10_asd.bin"); 47 MODULE_FIRMWARE("amdgpu/vega10_cap.bin"); 48 MODULE_FIRMWARE("amdgpu/vega12_sos.bin"); 49 MODULE_FIRMWARE("amdgpu/vega12_asd.bin"); 50 51 52 #define smnMP1_FIRMWARE_FLAGS 0x3010028 53 54 static int psp_v3_1_ring_stop(struct psp_context *psp, 55 enum psp_ring_type ring_type); 56 57 static int psp_v3_1_init_microcode(struct psp_context *psp) 58 { 59 struct amdgpu_device *adev = psp->adev; 60 const char *chip_name; 61 int err = 0; 62 63 DRM_DEBUG("\n"); 64 65 switch (adev->asic_type) { 66 case CHIP_VEGA10: 67 chip_name = "vega10"; 68 break; 69 case CHIP_VEGA12: 70 chip_name = "vega12"; 71 break; 72 default: BUG(); 73 } 74 75 err = psp_init_sos_microcode(psp, chip_name); 76 if (err) 77 return err; 78 79 err = psp_init_asd_microcode(psp, chip_name); 80 if (err) 81 return err; 82 83 return 0; 84 } 85 86 static int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp) 87 { 88 int ret; 89 uint32_t psp_gfxdrv_command_reg = 0; 90 struct amdgpu_device *adev = psp->adev; 91 uint32_t sol_reg; 92 93 /* Check sOS sign of life register to confirm sys driver and sOS 94 * are already been loaded. 95 */ 96 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 97 if (sol_reg) 98 return 0; 99 100 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 101 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 102 0x80000000, 0x80000000, false); 103 if (ret) 104 return ret; 105 106 /* Copy PSP System Driver binary to memory */ 107 psp_copy_fw(psp, psp->sys.start_addr, psp->sys.size_bytes); 108 109 /* Provide the sys driver to bootloader */ 110 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 111 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 112 psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV; 113 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 114 psp_gfxdrv_command_reg); 115 116 /* there might be handshake issue with hardware which needs delay */ 117 mdelay(20); 118 119 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 120 0x80000000, 0x80000000, false); 121 122 return ret; 123 } 124 125 static int psp_v3_1_bootloader_load_sos(struct psp_context *psp) 126 { 127 int ret; 128 unsigned int psp_gfxdrv_command_reg = 0; 129 struct amdgpu_device *adev = psp->adev; 130 uint32_t sol_reg; 131 132 /* Check sOS sign of life register to confirm sys driver and sOS 133 * are already been loaded. 134 */ 135 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 136 if (sol_reg) 137 return 0; 138 139 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 140 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 141 0x80000000, 0x80000000, false); 142 if (ret) 143 return ret; 144 145 /* Copy Secure OS binary to PSP memory */ 146 psp_copy_fw(psp, psp->sos.start_addr, psp->sos.size_bytes); 147 148 /* Provide the PSP secure OS to bootloader */ 149 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 150 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 151 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; 152 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 153 psp_gfxdrv_command_reg); 154 155 /* there might be handshake issue with hardware which needs delay */ 156 mdelay(20); 157 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), 158 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 159 0, true); 160 return ret; 161 } 162 163 static void psp_v3_1_reroute_ih(struct psp_context *psp) 164 { 165 struct amdgpu_device *adev = psp->adev; 166 uint32_t tmp; 167 168 /* Change IH ring for VMC */ 169 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b); 170 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1); 171 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 172 173 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3); 174 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); 175 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); 176 177 mdelay(20); 178 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 179 0x80000000, 0x8000FFFF, false); 180 181 /* Change IH ring for UMC */ 182 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b); 183 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 184 185 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4); 186 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); 187 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); 188 189 mdelay(20); 190 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 191 0x80000000, 0x8000FFFF, false); 192 } 193 194 static int psp_v3_1_ring_create(struct psp_context *psp, 195 enum psp_ring_type ring_type) 196 { 197 int ret = 0; 198 unsigned int psp_ring_reg = 0; 199 struct psp_ring *ring = &psp->km_ring; 200 struct amdgpu_device *adev = psp->adev; 201 202 psp_v3_1_reroute_ih(psp); 203 204 if (amdgpu_sriov_vf(adev)) { 205 ring->ring_wptr = 0; 206 ret = psp_v3_1_ring_stop(psp, ring_type); 207 if (ret) { 208 DRM_ERROR("psp_v3_1_ring_stop_sriov failed!\n"); 209 return ret; 210 } 211 212 /* Write low address of the ring to C2PMSG_102 */ 213 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 214 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg); 215 /* Write high address of the ring to C2PMSG_103 */ 216 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 217 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg); 218 /* No size initialization for sriov */ 219 /* Write the ring initialization command to C2PMSG_101 */ 220 psp_ring_reg = ring_type; 221 psp_ring_reg = psp_ring_reg << 16; 222 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, psp_ring_reg); 223 224 /* there might be hardware handshake issue which needs delay */ 225 mdelay(20); 226 227 /* Wait for response flag (bit 31) in C2PMSG_101 */ 228 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, 229 mmMP0_SMN_C2PMSG_101), 0x80000000, 230 0x8000FFFF, false); 231 } else { 232 233 /* Write low address of the ring to C2PMSG_69 */ 234 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 235 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); 236 /* Write high address of the ring to C2PMSG_70 */ 237 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 238 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); 239 /* Write size of ring to C2PMSG_71 */ 240 psp_ring_reg = ring->ring_size; 241 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); 242 /* Write the ring initialization command to C2PMSG_64 */ 243 psp_ring_reg = ring_type; 244 psp_ring_reg = psp_ring_reg << 16; 245 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 246 247 /* there might be hardware handshake issue which needs delay */ 248 mdelay(20); 249 250 /* Wait for response flag (bit 31) in C2PMSG_64 */ 251 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, 252 mmMP0_SMN_C2PMSG_64), 0x80000000, 253 0x8000FFFF, false); 254 255 } 256 return ret; 257 } 258 259 static int psp_v3_1_ring_stop(struct psp_context *psp, 260 enum psp_ring_type ring_type) 261 { 262 int ret = 0; 263 struct amdgpu_device *adev = psp->adev; 264 265 /* Write the ring destroy command*/ 266 if (amdgpu_sriov_vf(adev)) 267 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 268 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 269 else 270 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, 271 GFX_CTRL_CMD_ID_DESTROY_RINGS); 272 273 /* there might be handshake issue with hardware which needs delay */ 274 mdelay(20); 275 276 /* Wait for response flag (bit 31) */ 277 if (amdgpu_sriov_vf(adev)) 278 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 279 0x80000000, 0x80000000, false); 280 else 281 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 282 0x80000000, 0x80000000, false); 283 284 return ret; 285 } 286 287 static int psp_v3_1_ring_destroy(struct psp_context *psp, 288 enum psp_ring_type ring_type) 289 { 290 int ret = 0; 291 struct psp_ring *ring = &psp->km_ring; 292 struct amdgpu_device *adev = psp->adev; 293 294 ret = psp_v3_1_ring_stop(psp, ring_type); 295 if (ret) 296 DRM_ERROR("Fail to stop psp ring\n"); 297 298 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 299 &ring->ring_mem_mc_addr, 300 (void **)&ring->ring_mem); 301 302 return ret; 303 } 304 305 static bool psp_v3_1_smu_reload_quirk(struct psp_context *psp) 306 { 307 struct amdgpu_device *adev = psp->adev; 308 uint32_t reg; 309 310 reg = RREG32_PCIE(smnMP1_FIRMWARE_FLAGS | 0x03b00000); 311 return (reg & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) ? true : false; 312 } 313 314 static int psp_v3_1_mode1_reset(struct psp_context *psp) 315 { 316 int ret; 317 uint32_t offset; 318 struct amdgpu_device *adev = psp->adev; 319 320 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); 321 322 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false); 323 324 if (ret) { 325 DRM_INFO("psp is not working correctly before mode1 reset!\n"); 326 return -EINVAL; 327 } 328 329 /*send the mode 1 reset command*/ 330 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST); 331 332 msleep(500); 333 334 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); 335 336 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false); 337 338 if (ret) { 339 DRM_INFO("psp mode 1 reset failed!\n"); 340 return -EINVAL; 341 } 342 343 DRM_INFO("psp mode1 reset succeed \n"); 344 345 return 0; 346 } 347 348 static uint32_t psp_v3_1_ring_get_wptr(struct psp_context *psp) 349 { 350 uint32_t data; 351 struct amdgpu_device *adev = psp->adev; 352 353 if (amdgpu_sriov_vf(adev)) 354 data = psp->km_ring.ring_wptr; 355 else 356 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); 357 return data; 358 } 359 360 static void psp_v3_1_ring_set_wptr(struct psp_context *psp, uint32_t value) 361 { 362 struct amdgpu_device *adev = psp->adev; 363 364 if (amdgpu_sriov_vf(adev)) { 365 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value); 366 /* send interrupt to PSP for SRIOV ring write pointer update */ 367 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 368 GFX_CTRL_CMD_ID_CONSUME_CMD); 369 psp->km_ring.ring_wptr = value; 370 } else 371 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value); 372 } 373 374 static const struct psp_funcs psp_v3_1_funcs = { 375 .init_microcode = psp_v3_1_init_microcode, 376 .bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv, 377 .bootloader_load_sos = psp_v3_1_bootloader_load_sos, 378 .ring_create = psp_v3_1_ring_create, 379 .ring_stop = psp_v3_1_ring_stop, 380 .ring_destroy = psp_v3_1_ring_destroy, 381 .smu_reload_quirk = psp_v3_1_smu_reload_quirk, 382 .mode1_reset = psp_v3_1_mode1_reset, 383 .ring_get_wptr = psp_v3_1_ring_get_wptr, 384 .ring_set_wptr = psp_v3_1_ring_set_wptr, 385 }; 386 387 void psp_v3_1_set_psp_funcs(struct psp_context *psp) 388 { 389 psp->funcs = &psp_v3_1_funcs; 390 } 391