1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "amdgpu_psp.h" 25 #include "amdgpu_ucode.h" 26 #include "soc15_common.h" 27 #include "psp_v13_0.h" 28 29 #include "mp/mp_13_0_2_offset.h" 30 #include "mp/mp_13_0_2_sh_mask.h" 31 32 MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin"); 33 MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin"); 34 35 static int psp_v13_0_init_microcode(struct psp_context *psp) 36 { 37 struct amdgpu_device *adev = psp->adev; 38 const char *chip_name; 39 int err = 0; 40 41 switch (adev->asic_type) { 42 case CHIP_ALDEBARAN: 43 chip_name = "aldebaran"; 44 break; 45 default: 46 BUG(); 47 } 48 49 err = psp_init_sos_microcode(psp, chip_name); 50 if (err) 51 return err; 52 53 err = psp_init_ta_microcode(&adev->psp, chip_name); 54 55 return err; 56 } 57 58 static bool psp_v13_0_is_sos_alive(struct psp_context *psp) 59 { 60 struct amdgpu_device *adev = psp->adev; 61 uint32_t sol_reg; 62 63 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 64 65 return sol_reg != 0x0; 66 } 67 68 static int psp_v13_0_wait_for_bootloader(struct psp_context *psp) 69 { 70 struct amdgpu_device *adev = psp->adev; 71 72 int ret; 73 int retry_loop; 74 75 for (retry_loop = 0; retry_loop < 10; retry_loop++) { 76 /* Wait for bootloader to signify that is 77 ready having bit 31 of C2PMSG_35 set to 1 */ 78 ret = psp_wait_for(psp, 79 SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 80 0x80000000, 81 0x80000000, 82 false); 83 84 if (ret == 0) 85 return 0; 86 } 87 88 return ret; 89 } 90 91 static int psp_v13_0_bootloader_load_kdb(struct psp_context *psp) 92 { 93 int ret; 94 uint32_t psp_gfxdrv_command_reg = 0; 95 struct amdgpu_device *adev = psp->adev; 96 97 /* Check tOS sign of life register to confirm sys driver and sOS 98 * are already been loaded. 99 */ 100 if (psp_v13_0_is_sos_alive(psp)) 101 return 0; 102 103 ret = psp_v13_0_wait_for_bootloader(psp); 104 if (ret) 105 return ret; 106 107 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 108 109 /* Copy PSP KDB binary to memory */ 110 memcpy(psp->fw_pri_buf, psp->kdb_start_addr, psp->kdb_bin_size); 111 112 /* Provide the PSP KDB to bootloader */ 113 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 114 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 115 psp_gfxdrv_command_reg = PSP_BL__LOAD_KEY_DATABASE; 116 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 117 psp_gfxdrv_command_reg); 118 119 ret = psp_v13_0_wait_for_bootloader(psp); 120 121 return ret; 122 } 123 124 static int psp_v13_0_bootloader_load_sysdrv(struct psp_context *psp) 125 { 126 int ret; 127 uint32_t psp_gfxdrv_command_reg = 0; 128 struct amdgpu_device *adev = psp->adev; 129 130 /* Check sOS sign of life register to confirm sys driver and sOS 131 * are already been loaded. 132 */ 133 if (psp_v13_0_is_sos_alive(psp)) 134 return 0; 135 136 ret = psp_v13_0_wait_for_bootloader(psp); 137 if (ret) 138 return ret; 139 140 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 141 142 /* Copy PSP System Driver binary to memory */ 143 memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size); 144 145 /* Provide the sys driver to bootloader */ 146 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 147 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 148 psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV; 149 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 150 psp_gfxdrv_command_reg); 151 152 /* there might be handshake issue with hardware which needs delay */ 153 mdelay(20); 154 155 ret = psp_v13_0_wait_for_bootloader(psp); 156 157 return ret; 158 } 159 160 static int psp_v13_0_bootloader_load_sos(struct psp_context *psp) 161 { 162 int ret; 163 unsigned int psp_gfxdrv_command_reg = 0; 164 struct amdgpu_device *adev = psp->adev; 165 166 /* Check sOS sign of life register to confirm sys driver and sOS 167 * are already been loaded. 168 */ 169 if (psp_v13_0_is_sos_alive(psp)) 170 return 0; 171 172 ret = psp_v13_0_wait_for_bootloader(psp); 173 if (ret) 174 return ret; 175 176 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 177 178 /* Copy Secure OS binary to PSP memory */ 179 memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size); 180 181 /* Provide the PSP secure OS to bootloader */ 182 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 183 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 184 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; 185 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 186 psp_gfxdrv_command_reg); 187 188 /* there might be handshake issue with hardware which needs delay */ 189 mdelay(20); 190 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81), 191 RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81), 192 0, true); 193 194 return ret; 195 } 196 197 static int psp_v13_0_ring_init(struct psp_context *psp, 198 enum psp_ring_type ring_type) 199 { 200 int ret = 0; 201 struct psp_ring *ring; 202 struct amdgpu_device *adev = psp->adev; 203 204 ring = &psp->km_ring; 205 206 ring->ring_type = ring_type; 207 208 /* allocate 4k Page of Local Frame Buffer memory for ring */ 209 ring->ring_size = 0x1000; 210 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 211 AMDGPU_GEM_DOMAIN_VRAM, 212 &adev->firmware.rbuf, 213 &ring->ring_mem_mc_addr, 214 (void **)&ring->ring_mem); 215 if (ret) { 216 ring->ring_size = 0; 217 return ret; 218 } 219 220 return 0; 221 } 222 223 static int psp_v13_0_ring_stop(struct psp_context *psp, 224 enum psp_ring_type ring_type) 225 { 226 int ret = 0; 227 struct amdgpu_device *adev = psp->adev; 228 229 if (amdgpu_sriov_vf(adev)) { 230 /* Write the ring destroy command*/ 231 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 232 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 233 /* there might be handshake issue with hardware which needs delay */ 234 mdelay(20); 235 /* Wait for response flag (bit 31) */ 236 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 237 0x80000000, 0x80000000, false); 238 } else { 239 /* Write the ring destroy command*/ 240 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, 241 GFX_CTRL_CMD_ID_DESTROY_RINGS); 242 /* there might be handshake issue with hardware which needs delay */ 243 mdelay(20); 244 /* Wait for response flag (bit 31) */ 245 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 246 0x80000000, 0x80000000, false); 247 } 248 249 return ret; 250 } 251 252 static int psp_v13_0_ring_create(struct psp_context *psp, 253 enum psp_ring_type ring_type) 254 { 255 int ret = 0; 256 unsigned int psp_ring_reg = 0; 257 struct psp_ring *ring = &psp->km_ring; 258 struct amdgpu_device *adev = psp->adev; 259 260 if (amdgpu_sriov_vf(adev)) { 261 ret = psp_v13_0_ring_stop(psp, ring_type); 262 if (ret) { 263 DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n"); 264 return ret; 265 } 266 267 /* Write low address of the ring to C2PMSG_102 */ 268 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 269 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg); 270 /* Write high address of the ring to C2PMSG_103 */ 271 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 272 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg); 273 274 /* Write the ring initialization command to C2PMSG_101 */ 275 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 276 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 277 278 /* there might be handshake issue with hardware which needs delay */ 279 mdelay(20); 280 281 /* Wait for response flag (bit 31) in C2PMSG_101 */ 282 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 283 0x80000000, 0x8000FFFF, false); 284 285 } else { 286 /* Wait for sOS ready for ring creation */ 287 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 288 0x80000000, 0x80000000, false); 289 if (ret) { 290 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n"); 291 return ret; 292 } 293 294 /* Write low address of the ring to C2PMSG_69 */ 295 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 296 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg); 297 /* Write high address of the ring to C2PMSG_70 */ 298 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 299 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg); 300 /* Write size of ring to C2PMSG_71 */ 301 psp_ring_reg = ring->ring_size; 302 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg); 303 /* Write the ring initialization command to C2PMSG_64 */ 304 psp_ring_reg = ring_type; 305 psp_ring_reg = psp_ring_reg << 16; 306 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg); 307 308 /* there might be handshake issue with hardware which needs delay */ 309 mdelay(20); 310 311 /* Wait for response flag (bit 31) in C2PMSG_64 */ 312 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 313 0x80000000, 0x8000FFFF, false); 314 } 315 316 return ret; 317 } 318 319 static int psp_v13_0_ring_destroy(struct psp_context *psp, 320 enum psp_ring_type ring_type) 321 { 322 int ret = 0; 323 struct psp_ring *ring = &psp->km_ring; 324 struct amdgpu_device *adev = psp->adev; 325 326 ret = psp_v13_0_ring_stop(psp, ring_type); 327 if (ret) 328 DRM_ERROR("Fail to stop psp ring\n"); 329 330 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 331 &ring->ring_mem_mc_addr, 332 (void **)&ring->ring_mem); 333 334 return ret; 335 } 336 337 static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp) 338 { 339 uint32_t data; 340 struct amdgpu_device *adev = psp->adev; 341 342 if (amdgpu_sriov_vf(adev)) 343 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102); 344 else 345 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67); 346 347 return data; 348 } 349 350 static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value) 351 { 352 struct amdgpu_device *adev = psp->adev; 353 354 if (amdgpu_sriov_vf(adev)) { 355 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value); 356 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 357 GFX_CTRL_CMD_ID_CONSUME_CMD); 358 } else 359 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value); 360 } 361 362 static const struct psp_funcs psp_v13_0_funcs = { 363 .init_microcode = psp_v13_0_init_microcode, 364 .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb, 365 .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv, 366 .bootloader_load_sos = psp_v13_0_bootloader_load_sos, 367 .ring_init = psp_v13_0_ring_init, 368 .ring_create = psp_v13_0_ring_create, 369 .ring_stop = psp_v13_0_ring_stop, 370 .ring_destroy = psp_v13_0_ring_destroy, 371 .ring_get_wptr = psp_v13_0_ring_get_wptr, 372 .ring_set_wptr = psp_v13_0_ring_set_wptr, 373 }; 374 375 void psp_v13_0_set_psp_funcs(struct psp_context *psp) 376 { 377 psp->funcs = &psp_v13_0_funcs; 378 } 379