1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <drm/drm_drv.h> 24 #include <linux/vmalloc.h> 25 #include "amdgpu.h" 26 #include "amdgpu_psp.h" 27 #include "amdgpu_ucode.h" 28 #include "soc15_common.h" 29 #include "psp_v13_0.h" 30 31 #include "mp/mp_13_0_2_offset.h" 32 #include "mp/mp_13_0_2_sh_mask.h" 33 34 MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin"); 35 MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin"); 36 MODULE_FIRMWARE("amdgpu/aldebaran_cap.bin"); 37 MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin"); 38 MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin"); 39 MODULE_FIRMWARE("amdgpu/psp_13_0_5_toc.bin"); 40 MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin"); 41 MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin"); 42 MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin"); 43 MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin"); 44 MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta.bin"); 45 MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin"); 46 MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin"); 47 48 /* For large FW files the time to complete can be very long */ 49 #define USBC_PD_POLLING_LIMIT_S 240 50 51 /* Read USB-PD from LFB */ 52 #define GFX_CMD_USB_PD_USE_LFB 0x480 53 54 /* VBIOS gfl defines */ 55 #define MBOX_READY_MASK 0x80000000 56 #define MBOX_STATUS_MASK 0x0000FFFF 57 #define MBOX_COMMAND_MASK 0x00FF0000 58 #define MBOX_READY_FLAG 0x80000000 59 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO 0x2 60 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3 61 #define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4 62 63 /* memory training timeout define */ 64 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000 65 66 static int psp_v13_0_init_microcode(struct psp_context *psp) 67 { 68 struct amdgpu_device *adev = psp->adev; 69 const char *chip_name; 70 char ucode_prefix[30]; 71 int err = 0; 72 73 switch (adev->ip_versions[MP0_HWIP][0]) { 74 case IP_VERSION(13, 0, 2): 75 chip_name = "aldebaran"; 76 break; 77 case IP_VERSION(13, 0, 1): 78 case IP_VERSION(13, 0, 3): 79 chip_name = "yellow_carp"; 80 break; 81 default: 82 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 83 chip_name = ucode_prefix; 84 break; 85 } 86 87 switch (adev->ip_versions[MP0_HWIP][0]) { 88 case IP_VERSION(13, 0, 2): 89 err = psp_init_sos_microcode(psp, chip_name); 90 if (err) 91 return err; 92 /* It's not necessary to load ras ta on Guest side */ 93 if (!amdgpu_sriov_vf(adev)) { 94 err = psp_init_ta_microcode(&adev->psp, chip_name); 95 if (err) 96 return err; 97 } 98 break; 99 case IP_VERSION(13, 0, 1): 100 case IP_VERSION(13, 0, 3): 101 case IP_VERSION(13, 0, 5): 102 case IP_VERSION(13, 0, 8): 103 err = psp_init_toc_microcode(psp, chip_name); 104 if (err) 105 return err; 106 err = psp_init_ta_microcode(psp, chip_name); 107 if (err) 108 return err; 109 break; 110 case IP_VERSION(13, 0, 0): 111 case IP_VERSION(13, 0, 7): 112 err = psp_init_sos_microcode(psp, chip_name); 113 if (err) 114 return err; 115 /* It's not necessary to load ras ta on Guest side */ 116 err = psp_init_ta_microcode(psp, chip_name); 117 if (err) 118 return err; 119 break; 120 default: 121 BUG(); 122 } 123 124 return 0; 125 } 126 127 static bool psp_v13_0_is_sos_alive(struct psp_context *psp) 128 { 129 struct amdgpu_device *adev = psp->adev; 130 uint32_t sol_reg; 131 132 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 133 134 return sol_reg != 0x0; 135 } 136 137 static int psp_v13_0_wait_for_bootloader(struct psp_context *psp) 138 { 139 struct amdgpu_device *adev = psp->adev; 140 141 int ret; 142 int retry_loop; 143 144 for (retry_loop = 0; retry_loop < 10; retry_loop++) { 145 /* Wait for bootloader to signify that is 146 ready having bit 31 of C2PMSG_35 set to 1 */ 147 ret = psp_wait_for(psp, 148 SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 149 0x80000000, 150 0x80000000, 151 false); 152 153 if (ret == 0) 154 return 0; 155 } 156 157 return ret; 158 } 159 160 static int psp_v13_0_bootloader_load_component(struct psp_context *psp, 161 struct psp_bin_desc *bin_desc, 162 enum psp_bootloader_cmd bl_cmd) 163 { 164 int ret; 165 uint32_t psp_gfxdrv_command_reg = 0; 166 struct amdgpu_device *adev = psp->adev; 167 168 /* Check tOS sign of life register to confirm sys driver and sOS 169 * are already been loaded. 170 */ 171 if (psp_v13_0_is_sos_alive(psp)) 172 return 0; 173 174 ret = psp_v13_0_wait_for_bootloader(psp); 175 if (ret) 176 return ret; 177 178 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 179 180 /* Copy PSP KDB binary to memory */ 181 memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes); 182 183 /* Provide the PSP KDB to bootloader */ 184 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 185 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 186 psp_gfxdrv_command_reg = bl_cmd; 187 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 188 psp_gfxdrv_command_reg); 189 190 ret = psp_v13_0_wait_for_bootloader(psp); 191 192 return ret; 193 } 194 195 static int psp_v13_0_bootloader_load_kdb(struct psp_context *psp) 196 { 197 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE); 198 } 199 200 static int psp_v13_0_bootloader_load_spl(struct psp_context *psp) 201 { 202 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE); 203 } 204 205 static int psp_v13_0_bootloader_load_sysdrv(struct psp_context *psp) 206 { 207 return psp_v13_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV); 208 } 209 210 static int psp_v13_0_bootloader_load_soc_drv(struct psp_context *psp) 211 { 212 return psp_v13_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV); 213 } 214 215 static int psp_v13_0_bootloader_load_intf_drv(struct psp_context *psp) 216 { 217 return psp_v13_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV); 218 } 219 220 static int psp_v13_0_bootloader_load_dbg_drv(struct psp_context *psp) 221 { 222 return psp_v13_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV); 223 } 224 225 static int psp_v13_0_bootloader_load_sos(struct psp_context *psp) 226 { 227 int ret; 228 unsigned int psp_gfxdrv_command_reg = 0; 229 struct amdgpu_device *adev = psp->adev; 230 231 /* Check sOS sign of life register to confirm sys driver and sOS 232 * are already been loaded. 233 */ 234 if (psp_v13_0_is_sos_alive(psp)) 235 return 0; 236 237 ret = psp_v13_0_wait_for_bootloader(psp); 238 if (ret) 239 return ret; 240 241 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 242 243 /* Copy Secure OS binary to PSP memory */ 244 memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes); 245 246 /* Provide the PSP secure OS to bootloader */ 247 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 248 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 249 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; 250 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 251 psp_gfxdrv_command_reg); 252 253 /* there might be handshake issue with hardware which needs delay */ 254 mdelay(20); 255 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81), 256 RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81), 257 0, true); 258 259 return ret; 260 } 261 262 static int psp_v13_0_ring_init(struct psp_context *psp, 263 enum psp_ring_type ring_type) 264 { 265 int ret = 0; 266 struct psp_ring *ring; 267 struct amdgpu_device *adev = psp->adev; 268 269 ring = &psp->km_ring; 270 271 ring->ring_type = ring_type; 272 273 /* allocate 4k Page of Local Frame Buffer memory for ring */ 274 ring->ring_size = 0x1000; 275 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 276 AMDGPU_GEM_DOMAIN_VRAM, 277 &adev->firmware.rbuf, 278 &ring->ring_mem_mc_addr, 279 (void **)&ring->ring_mem); 280 if (ret) { 281 ring->ring_size = 0; 282 return ret; 283 } 284 285 return 0; 286 } 287 288 static int psp_v13_0_ring_stop(struct psp_context *psp, 289 enum psp_ring_type ring_type) 290 { 291 int ret = 0; 292 struct amdgpu_device *adev = psp->adev; 293 294 if (amdgpu_sriov_vf(adev)) { 295 /* Write the ring destroy command*/ 296 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 297 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 298 /* there might be handshake issue with hardware which needs delay */ 299 mdelay(20); 300 /* Wait for response flag (bit 31) */ 301 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 302 0x80000000, 0x80000000, false); 303 } else { 304 /* Write the ring destroy command*/ 305 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, 306 GFX_CTRL_CMD_ID_DESTROY_RINGS); 307 /* there might be handshake issue with hardware which needs delay */ 308 mdelay(20); 309 /* Wait for response flag (bit 31) */ 310 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 311 0x80000000, 0x80000000, false); 312 } 313 314 return ret; 315 } 316 317 static int psp_v13_0_ring_create(struct psp_context *psp, 318 enum psp_ring_type ring_type) 319 { 320 int ret = 0; 321 unsigned int psp_ring_reg = 0; 322 struct psp_ring *ring = &psp->km_ring; 323 struct amdgpu_device *adev = psp->adev; 324 325 if (amdgpu_sriov_vf(adev)) { 326 ret = psp_v13_0_ring_stop(psp, ring_type); 327 if (ret) { 328 DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n"); 329 return ret; 330 } 331 332 /* Write low address of the ring to C2PMSG_102 */ 333 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 334 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg); 335 /* Write high address of the ring to C2PMSG_103 */ 336 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 337 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg); 338 339 /* Write the ring initialization command to C2PMSG_101 */ 340 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 341 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 342 343 /* there might be handshake issue with hardware which needs delay */ 344 mdelay(20); 345 346 /* Wait for response flag (bit 31) in C2PMSG_101 */ 347 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 348 0x80000000, 0x8000FFFF, false); 349 350 } else { 351 /* Wait for sOS ready for ring creation */ 352 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 353 0x80000000, 0x80000000, false); 354 if (ret) { 355 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n"); 356 return ret; 357 } 358 359 /* Write low address of the ring to C2PMSG_69 */ 360 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 361 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg); 362 /* Write high address of the ring to C2PMSG_70 */ 363 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 364 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg); 365 /* Write size of ring to C2PMSG_71 */ 366 psp_ring_reg = ring->ring_size; 367 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg); 368 /* Write the ring initialization command to C2PMSG_64 */ 369 psp_ring_reg = ring_type; 370 psp_ring_reg = psp_ring_reg << 16; 371 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg); 372 373 /* there might be handshake issue with hardware which needs delay */ 374 mdelay(20); 375 376 /* Wait for response flag (bit 31) in C2PMSG_64 */ 377 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 378 0x80000000, 0x8000FFFF, false); 379 } 380 381 return ret; 382 } 383 384 static int psp_v13_0_ring_destroy(struct psp_context *psp, 385 enum psp_ring_type ring_type) 386 { 387 int ret = 0; 388 struct psp_ring *ring = &psp->km_ring; 389 struct amdgpu_device *adev = psp->adev; 390 391 ret = psp_v13_0_ring_stop(psp, ring_type); 392 if (ret) 393 DRM_ERROR("Fail to stop psp ring\n"); 394 395 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 396 &ring->ring_mem_mc_addr, 397 (void **)&ring->ring_mem); 398 399 return ret; 400 } 401 402 static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp) 403 { 404 uint32_t data; 405 struct amdgpu_device *adev = psp->adev; 406 407 if (amdgpu_sriov_vf(adev)) 408 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102); 409 else 410 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67); 411 412 return data; 413 } 414 415 static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value) 416 { 417 struct amdgpu_device *adev = psp->adev; 418 419 if (amdgpu_sriov_vf(adev)) { 420 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value); 421 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 422 GFX_CTRL_CMD_ID_CONSUME_CMD); 423 } else 424 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value); 425 } 426 427 static int psp_v13_0_memory_training_send_msg(struct psp_context *psp, int msg) 428 { 429 int ret; 430 int i; 431 uint32_t data_32; 432 int max_wait; 433 struct amdgpu_device *adev = psp->adev; 434 435 data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20); 436 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, data_32); 437 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, msg); 438 439 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout; 440 for (i = 0; i < max_wait; i++) { 441 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 442 0x80000000, 0x80000000, false); 443 if (ret == 0) 444 break; 445 } 446 if (i < max_wait) 447 ret = 0; 448 else 449 ret = -ETIME; 450 451 dev_dbg(adev->dev, "training %s %s, cost %d @ %d ms\n", 452 (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long", 453 (ret == 0) ? "succeed" : "failed", 454 i, adev->usec_timeout/1000); 455 return ret; 456 } 457 458 459 static int psp_v13_0_memory_training(struct psp_context *psp, uint32_t ops) 460 { 461 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 462 uint32_t *pcache = (uint32_t *)ctx->sys_cache; 463 struct amdgpu_device *adev = psp->adev; 464 uint32_t p2c_header[4]; 465 uint32_t sz; 466 void *buf; 467 int ret, idx; 468 469 if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) { 470 dev_dbg(adev->dev, "Memory training is not supported.\n"); 471 return 0; 472 } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) { 473 dev_err(adev->dev, "Memory training initialization failure.\n"); 474 return -EINVAL; 475 } 476 477 if (psp_v13_0_is_sos_alive(psp)) { 478 dev_dbg(adev->dev, "SOS is alive, skip memory training.\n"); 479 return 0; 480 } 481 482 amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false); 483 dev_dbg(adev->dev, "sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n", 484 pcache[0], pcache[1], pcache[2], pcache[3], 485 p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]); 486 487 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 488 dev_dbg(adev->dev, "Short training depends on restore.\n"); 489 ops |= PSP_MEM_TRAIN_RESTORE; 490 } 491 492 if ((ops & PSP_MEM_TRAIN_RESTORE) && 493 pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 494 dev_dbg(adev->dev, "sys_cache[0] is invalid, restore depends on save.\n"); 495 ops |= PSP_MEM_TRAIN_SAVE; 496 } 497 498 if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 499 !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 500 pcache[3] == p2c_header[3])) { 501 dev_dbg(adev->dev, "sys_cache is invalid or out-of-date, need save training data to sys_cache.\n"); 502 ops |= PSP_MEM_TRAIN_SAVE; 503 } 504 505 if ((ops & PSP_MEM_TRAIN_SAVE) && 506 p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 507 dev_dbg(adev->dev, "p2c_header[0] is invalid, save depends on long training.\n"); 508 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG; 509 } 510 511 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 512 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG; 513 ops |= PSP_MEM_TRAIN_SAVE; 514 } 515 516 dev_dbg(adev->dev, "Memory training ops:%x.\n", ops); 517 518 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 519 /* 520 * Long training will encroach a certain amount on the bottom of VRAM; 521 * save the content from the bottom of VRAM to system memory 522 * before training, and restore it after training to avoid 523 * VRAM corruption. 524 */ 525 sz = GDDR6_MEM_TRAINING_ENCROACHED_SIZE; 526 527 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) { 528 dev_err(adev->dev, "visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n", 529 adev->gmc.visible_vram_size, 530 adev->mman.aper_base_kaddr); 531 return -EINVAL; 532 } 533 534 buf = vmalloc(sz); 535 if (!buf) { 536 dev_err(adev->dev, "failed to allocate system memory.\n"); 537 return -ENOMEM; 538 } 539 540 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 541 memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz); 542 ret = psp_v13_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN); 543 if (ret) { 544 DRM_ERROR("Send long training msg failed.\n"); 545 vfree(buf); 546 drm_dev_exit(idx); 547 return ret; 548 } 549 550 memcpy_toio(adev->mman.aper_base_kaddr, buf, sz); 551 adev->hdp.funcs->flush_hdp(adev, NULL); 552 vfree(buf); 553 drm_dev_exit(idx); 554 } else { 555 vfree(buf); 556 return -ENODEV; 557 } 558 } 559 560 if (ops & PSP_MEM_TRAIN_SAVE) { 561 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false); 562 } 563 564 if (ops & PSP_MEM_TRAIN_RESTORE) { 565 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true); 566 } 567 568 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 569 ret = psp_v13_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ? 570 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN); 571 if (ret) { 572 dev_err(adev->dev, "send training msg failed.\n"); 573 return ret; 574 } 575 } 576 ctx->training_cnt++; 577 return 0; 578 } 579 580 static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr) 581 { 582 struct amdgpu_device *adev = psp->adev; 583 uint32_t reg_status; 584 int ret, i = 0; 585 586 /* 587 * LFB address which is aligned to 1MB address and has to be 588 * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P 589 * register 590 */ 591 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20)); 592 593 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 594 0x80000000, 0x80000000, false); 595 if (ret) 596 return ret; 597 598 /* Fireup interrupt so PSP can pick up the address */ 599 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16)); 600 601 /* FW load takes very long time */ 602 do { 603 msleep(1000); 604 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35); 605 606 if (reg_status & 0x80000000) 607 goto done; 608 609 } while (++i < USBC_PD_POLLING_LIMIT_S); 610 611 return -ETIME; 612 done: 613 614 if ((reg_status & 0xFFFF) != 0) { 615 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n", 616 reg_status & 0xFFFF); 617 return -EIO; 618 } 619 620 return 0; 621 } 622 623 static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver) 624 { 625 struct amdgpu_device *adev = psp->adev; 626 int ret; 627 628 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER); 629 630 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 631 0x80000000, 0x80000000, false); 632 if (!ret) 633 *fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36); 634 635 return ret; 636 } 637 638 static int psp_v13_0_exec_spi_cmd(struct psp_context *psp, int cmd) 639 { 640 uint32_t reg_status = 0, reg_val = 0; 641 struct amdgpu_device *adev = psp->adev; 642 int ret; 643 644 /* clear MBX ready (MBOX_READY_MASK bit is 0) and set update command */ 645 reg_val |= (cmd << 16); 646 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115, reg_val); 647 648 /* Ring the doorbell */ 649 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_73, 1); 650 651 if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE) 652 return 0; 653 654 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 655 MBOX_READY_FLAG, MBOX_READY_MASK, false); 656 if (ret) { 657 dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret); 658 return ret; 659 } 660 661 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115); 662 if ((reg_status & 0xFFFF) != 0) { 663 dev_err(adev->dev, "SPI cmd %x failed, fail status = %04x\n", 664 cmd, reg_status & 0xFFFF); 665 return -EIO; 666 } 667 668 return 0; 669 } 670 671 static int psp_v13_0_update_spirom(struct psp_context *psp, 672 uint64_t fw_pri_mc_addr) 673 { 674 struct amdgpu_device *adev = psp->adev; 675 int ret; 676 677 /* Confirm PSP is ready to start */ 678 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 679 MBOX_READY_FLAG, MBOX_READY_MASK, false); 680 if (ret) { 681 dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret); 682 return ret; 683 } 684 685 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr)); 686 687 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO); 688 if (ret) 689 return ret; 690 691 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr)); 692 693 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI); 694 if (ret) 695 return ret; 696 697 psp->vbflash_done = true; 698 699 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE); 700 if (ret) 701 return ret; 702 703 return 0; 704 } 705 706 static int psp_v13_0_vbflash_status(struct psp_context *psp) 707 { 708 struct amdgpu_device *adev = psp->adev; 709 710 return RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115); 711 } 712 713 static const struct psp_funcs psp_v13_0_funcs = { 714 .init_microcode = psp_v13_0_init_microcode, 715 .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb, 716 .bootloader_load_spl = psp_v13_0_bootloader_load_spl, 717 .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv, 718 .bootloader_load_soc_drv = psp_v13_0_bootloader_load_soc_drv, 719 .bootloader_load_intf_drv = psp_v13_0_bootloader_load_intf_drv, 720 .bootloader_load_dbg_drv = psp_v13_0_bootloader_load_dbg_drv, 721 .bootloader_load_sos = psp_v13_0_bootloader_load_sos, 722 .ring_init = psp_v13_0_ring_init, 723 .ring_create = psp_v13_0_ring_create, 724 .ring_stop = psp_v13_0_ring_stop, 725 .ring_destroy = psp_v13_0_ring_destroy, 726 .ring_get_wptr = psp_v13_0_ring_get_wptr, 727 .ring_set_wptr = psp_v13_0_ring_set_wptr, 728 .mem_training = psp_v13_0_memory_training, 729 .load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw, 730 .read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw, 731 .update_spirom = psp_v13_0_update_spirom, 732 .vbflash_stat = psp_v13_0_vbflash_status 733 }; 734 735 void psp_v13_0_set_psp_funcs(struct psp_context *psp) 736 { 737 psp->funcs = &psp_v13_0_funcs; 738 } 739