1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "amdgpu_psp.h" 25 #include "amdgpu_ucode.h" 26 #include "soc15_common.h" 27 #include "psp_v13_0.h" 28 29 #include "mp/mp_13_0_2_offset.h" 30 #include "mp/mp_13_0_2_sh_mask.h" 31 32 MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin"); 33 MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin"); 34 MODULE_FIRMWARE("amdgpu/aldebaran_cap.bin"); 35 MODULE_FIRMWARE("amdgpu/yellow_carp_asd.bin"); 36 MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin"); 37 MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin"); 38 MODULE_FIRMWARE("amdgpu/psp_13_0_5_asd.bin"); 39 MODULE_FIRMWARE("amdgpu/psp_13_0_5_toc.bin"); 40 MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin"); 41 MODULE_FIRMWARE("amdgpu/psp_13_0_8_asd.bin"); 42 MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin"); 43 MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin"); 44 MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin"); 45 MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin"); 46 47 /* For large FW files the time to complete can be very long */ 48 #define USBC_PD_POLLING_LIMIT_S 240 49 50 /* Read USB-PD from LFB */ 51 #define GFX_CMD_USB_PD_USE_LFB 0x480 52 53 /* VBIOS gfl defines */ 54 #define MBOX_READY_MASK 0x80000000 55 #define MBOX_STATUS_MASK 0x0000FFFF 56 #define MBOX_COMMAND_MASK 0x00FF0000 57 #define MBOX_READY_FLAG 0x80000000 58 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO 0x2 59 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3 60 #define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4 61 62 static int psp_v13_0_init_microcode(struct psp_context *psp) 63 { 64 struct amdgpu_device *adev = psp->adev; 65 const char *chip_name; 66 char ucode_prefix[30]; 67 int err = 0; 68 69 switch (adev->ip_versions[MP0_HWIP][0]) { 70 case IP_VERSION(13, 0, 2): 71 chip_name = "aldebaran"; 72 break; 73 case IP_VERSION(13, 0, 1): 74 case IP_VERSION(13, 0, 3): 75 chip_name = "yellow_carp"; 76 break; 77 default: 78 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 79 chip_name = ucode_prefix; 80 break; 81 } 82 83 switch (adev->ip_versions[MP0_HWIP][0]) { 84 case IP_VERSION(13, 0, 2): 85 err = psp_init_sos_microcode(psp, chip_name); 86 if (err) 87 return err; 88 err = psp_init_ta_microcode(&adev->psp, chip_name); 89 if (err) 90 return err; 91 break; 92 case IP_VERSION(13, 0, 1): 93 case IP_VERSION(13, 0, 3): 94 case IP_VERSION(13, 0, 5): 95 case IP_VERSION(13, 0, 8): 96 err = psp_init_asd_microcode(psp, chip_name); 97 if (err) 98 return err; 99 err = psp_init_toc_microcode(psp, chip_name); 100 if (err) 101 return err; 102 err = psp_init_ta_microcode(psp, chip_name); 103 if (err) 104 return err; 105 break; 106 case IP_VERSION(13, 0, 0): 107 case IP_VERSION(13, 0, 7): 108 err = psp_init_sos_microcode(psp, chip_name); 109 if (err) 110 return err; 111 break; 112 default: 113 BUG(); 114 } 115 116 return 0; 117 } 118 119 static bool psp_v13_0_is_sos_alive(struct psp_context *psp) 120 { 121 struct amdgpu_device *adev = psp->adev; 122 uint32_t sol_reg; 123 124 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 125 126 return sol_reg != 0x0; 127 } 128 129 static int psp_v13_0_wait_for_bootloader(struct psp_context *psp) 130 { 131 struct amdgpu_device *adev = psp->adev; 132 133 int ret; 134 int retry_loop; 135 136 for (retry_loop = 0; retry_loop < 10; retry_loop++) { 137 /* Wait for bootloader to signify that is 138 ready having bit 31 of C2PMSG_35 set to 1 */ 139 ret = psp_wait_for(psp, 140 SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 141 0x80000000, 142 0x80000000, 143 false); 144 145 if (ret == 0) 146 return 0; 147 } 148 149 return ret; 150 } 151 152 static int psp_v13_0_bootloader_load_component(struct psp_context *psp, 153 struct psp_bin_desc *bin_desc, 154 enum psp_bootloader_cmd bl_cmd) 155 { 156 int ret; 157 uint32_t psp_gfxdrv_command_reg = 0; 158 struct amdgpu_device *adev = psp->adev; 159 160 /* Check tOS sign of life register to confirm sys driver and sOS 161 * are already been loaded. 162 */ 163 if (psp_v13_0_is_sos_alive(psp)) 164 return 0; 165 166 ret = psp_v13_0_wait_for_bootloader(psp); 167 if (ret) 168 return ret; 169 170 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 171 172 /* Copy PSP KDB binary to memory */ 173 memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes); 174 175 /* Provide the PSP KDB to bootloader */ 176 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 177 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 178 psp_gfxdrv_command_reg = bl_cmd; 179 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 180 psp_gfxdrv_command_reg); 181 182 ret = psp_v13_0_wait_for_bootloader(psp); 183 184 return ret; 185 } 186 187 static int psp_v13_0_bootloader_load_kdb(struct psp_context *psp) 188 { 189 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE); 190 } 191 192 static int psp_v13_0_bootloader_load_spl(struct psp_context *psp) 193 { 194 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE); 195 } 196 197 static int psp_v13_0_bootloader_load_sysdrv(struct psp_context *psp) 198 { 199 return psp_v13_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV); 200 } 201 202 static int psp_v13_0_bootloader_load_soc_drv(struct psp_context *psp) 203 { 204 return psp_v13_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV); 205 } 206 207 static int psp_v13_0_bootloader_load_intf_drv(struct psp_context *psp) 208 { 209 return psp_v13_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV); 210 } 211 212 static int psp_v13_0_bootloader_load_dbg_drv(struct psp_context *psp) 213 { 214 return psp_v13_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV); 215 } 216 217 static int psp_v13_0_bootloader_load_sos(struct psp_context *psp) 218 { 219 int ret; 220 unsigned int psp_gfxdrv_command_reg = 0; 221 struct amdgpu_device *adev = psp->adev; 222 223 /* Check sOS sign of life register to confirm sys driver and sOS 224 * are already been loaded. 225 */ 226 if (psp_v13_0_is_sos_alive(psp)) 227 return 0; 228 229 ret = psp_v13_0_wait_for_bootloader(psp); 230 if (ret) 231 return ret; 232 233 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 234 235 /* Copy Secure OS binary to PSP memory */ 236 memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes); 237 238 /* Provide the PSP secure OS to bootloader */ 239 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 240 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 241 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; 242 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 243 psp_gfxdrv_command_reg); 244 245 /* there might be handshake issue with hardware which needs delay */ 246 mdelay(20); 247 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81), 248 RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81), 249 0, true); 250 251 return ret; 252 } 253 254 static int psp_v13_0_ring_init(struct psp_context *psp, 255 enum psp_ring_type ring_type) 256 { 257 int ret = 0; 258 struct psp_ring *ring; 259 struct amdgpu_device *adev = psp->adev; 260 261 ring = &psp->km_ring; 262 263 ring->ring_type = ring_type; 264 265 /* allocate 4k Page of Local Frame Buffer memory for ring */ 266 ring->ring_size = 0x1000; 267 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 268 AMDGPU_GEM_DOMAIN_VRAM, 269 &adev->firmware.rbuf, 270 &ring->ring_mem_mc_addr, 271 (void **)&ring->ring_mem); 272 if (ret) { 273 ring->ring_size = 0; 274 return ret; 275 } 276 277 return 0; 278 } 279 280 static int psp_v13_0_ring_stop(struct psp_context *psp, 281 enum psp_ring_type ring_type) 282 { 283 int ret = 0; 284 struct amdgpu_device *adev = psp->adev; 285 286 if (amdgpu_sriov_vf(adev)) { 287 /* Write the ring destroy command*/ 288 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 289 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 290 /* there might be handshake issue with hardware which needs delay */ 291 mdelay(20); 292 /* Wait for response flag (bit 31) */ 293 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 294 0x80000000, 0x80000000, false); 295 } else { 296 /* Write the ring destroy command*/ 297 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, 298 GFX_CTRL_CMD_ID_DESTROY_RINGS); 299 /* there might be handshake issue with hardware which needs delay */ 300 mdelay(20); 301 /* Wait for response flag (bit 31) */ 302 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 303 0x80000000, 0x80000000, false); 304 } 305 306 return ret; 307 } 308 309 static int psp_v13_0_ring_create(struct psp_context *psp, 310 enum psp_ring_type ring_type) 311 { 312 int ret = 0; 313 unsigned int psp_ring_reg = 0; 314 struct psp_ring *ring = &psp->km_ring; 315 struct amdgpu_device *adev = psp->adev; 316 317 if (amdgpu_sriov_vf(adev)) { 318 ret = psp_v13_0_ring_stop(psp, ring_type); 319 if (ret) { 320 DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n"); 321 return ret; 322 } 323 324 /* Write low address of the ring to C2PMSG_102 */ 325 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 326 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg); 327 /* Write high address of the ring to C2PMSG_103 */ 328 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 329 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg); 330 331 /* Write the ring initialization command to C2PMSG_101 */ 332 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 333 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 334 335 /* there might be handshake issue with hardware which needs delay */ 336 mdelay(20); 337 338 /* Wait for response flag (bit 31) in C2PMSG_101 */ 339 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 340 0x80000000, 0x8000FFFF, false); 341 342 } else { 343 /* Wait for sOS ready for ring creation */ 344 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 345 0x80000000, 0x80000000, false); 346 if (ret) { 347 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n"); 348 return ret; 349 } 350 351 /* Write low address of the ring to C2PMSG_69 */ 352 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 353 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg); 354 /* Write high address of the ring to C2PMSG_70 */ 355 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 356 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg); 357 /* Write size of ring to C2PMSG_71 */ 358 psp_ring_reg = ring->ring_size; 359 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg); 360 /* Write the ring initialization command to C2PMSG_64 */ 361 psp_ring_reg = ring_type; 362 psp_ring_reg = psp_ring_reg << 16; 363 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg); 364 365 /* there might be handshake issue with hardware which needs delay */ 366 mdelay(20); 367 368 /* Wait for response flag (bit 31) in C2PMSG_64 */ 369 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 370 0x80000000, 0x8000FFFF, false); 371 } 372 373 return ret; 374 } 375 376 static int psp_v13_0_ring_destroy(struct psp_context *psp, 377 enum psp_ring_type ring_type) 378 { 379 int ret = 0; 380 struct psp_ring *ring = &psp->km_ring; 381 struct amdgpu_device *adev = psp->adev; 382 383 ret = psp_v13_0_ring_stop(psp, ring_type); 384 if (ret) 385 DRM_ERROR("Fail to stop psp ring\n"); 386 387 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 388 &ring->ring_mem_mc_addr, 389 (void **)&ring->ring_mem); 390 391 return ret; 392 } 393 394 static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp) 395 { 396 uint32_t data; 397 struct amdgpu_device *adev = psp->adev; 398 399 if (amdgpu_sriov_vf(adev)) 400 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102); 401 else 402 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67); 403 404 return data; 405 } 406 407 static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value) 408 { 409 struct amdgpu_device *adev = psp->adev; 410 411 if (amdgpu_sriov_vf(adev)) { 412 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value); 413 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 414 GFX_CTRL_CMD_ID_CONSUME_CMD); 415 } else 416 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value); 417 } 418 419 static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr) 420 { 421 struct amdgpu_device *adev = psp->adev; 422 uint32_t reg_status; 423 int ret, i = 0; 424 425 /* 426 * LFB address which is aligned to 1MB address and has to be 427 * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P 428 * register 429 */ 430 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20)); 431 432 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 433 0x80000000, 0x80000000, false); 434 if (ret) 435 return ret; 436 437 /* Fireup interrupt so PSP can pick up the address */ 438 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16)); 439 440 /* FW load takes very long time */ 441 do { 442 msleep(1000); 443 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35); 444 445 if (reg_status & 0x80000000) 446 goto done; 447 448 } while (++i < USBC_PD_POLLING_LIMIT_S); 449 450 return -ETIME; 451 done: 452 453 if ((reg_status & 0xFFFF) != 0) { 454 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n", 455 reg_status & 0xFFFF); 456 return -EIO; 457 } 458 459 return 0; 460 } 461 462 static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver) 463 { 464 struct amdgpu_device *adev = psp->adev; 465 int ret; 466 467 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER); 468 469 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 470 0x80000000, 0x80000000, false); 471 if (!ret) 472 *fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36); 473 474 return ret; 475 } 476 477 static int psp_v13_0_exec_spi_cmd(struct psp_context *psp, int cmd) 478 { 479 uint32_t reg_status = 0, reg_val = 0; 480 struct amdgpu_device *adev = psp->adev; 481 int ret; 482 483 /* clear MBX ready (MBOX_READY_MASK bit is 0) and set update command */ 484 reg_val |= (cmd << 16); 485 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115, reg_val); 486 487 /* Ring the doorbell */ 488 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_73, 1); 489 490 if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE) 491 return 0; 492 493 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 494 MBOX_READY_FLAG, MBOX_READY_MASK, false); 495 if (ret) { 496 dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret); 497 return ret; 498 } 499 500 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115); 501 if ((reg_status & 0xFFFF) != 0) { 502 dev_err(adev->dev, "SPI cmd %x failed, fail status = %04x\n", 503 cmd, reg_status & 0xFFFF); 504 return -EIO; 505 } 506 507 return 0; 508 } 509 510 static int psp_v13_0_update_spirom(struct psp_context *psp, 511 uint64_t fw_pri_mc_addr) 512 { 513 struct amdgpu_device *adev = psp->adev; 514 int ret; 515 516 /* Confirm PSP is ready to start */ 517 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 518 MBOX_READY_FLAG, MBOX_READY_MASK, false); 519 if (ret) { 520 dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret); 521 return ret; 522 } 523 524 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr)); 525 526 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO); 527 if (ret) 528 return ret; 529 530 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr)); 531 532 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI); 533 if (ret) 534 return ret; 535 536 psp->vbflash_done = true; 537 538 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE); 539 if (ret) 540 return ret; 541 542 return 0; 543 } 544 545 static int psp_v13_0_vbflash_status(struct psp_context *psp) 546 { 547 struct amdgpu_device *adev = psp->adev; 548 549 return RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115); 550 } 551 552 static const struct psp_funcs psp_v13_0_funcs = { 553 .init_microcode = psp_v13_0_init_microcode, 554 .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb, 555 .bootloader_load_spl = psp_v13_0_bootloader_load_spl, 556 .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv, 557 .bootloader_load_soc_drv = psp_v13_0_bootloader_load_soc_drv, 558 .bootloader_load_intf_drv = psp_v13_0_bootloader_load_intf_drv, 559 .bootloader_load_dbg_drv = psp_v13_0_bootloader_load_dbg_drv, 560 .bootloader_load_sos = psp_v13_0_bootloader_load_sos, 561 .ring_init = psp_v13_0_ring_init, 562 .ring_create = psp_v13_0_ring_create, 563 .ring_stop = psp_v13_0_ring_stop, 564 .ring_destroy = psp_v13_0_ring_destroy, 565 .ring_get_wptr = psp_v13_0_ring_get_wptr, 566 .ring_set_wptr = psp_v13_0_ring_set_wptr, 567 .load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw, 568 .read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw, 569 .update_spirom = psp_v13_0_update_spirom, 570 .vbflash_stat = psp_v13_0_vbflash_status 571 }; 572 573 void psp_v13_0_set_psp_funcs(struct psp_context *psp) 574 { 575 psp->funcs = &psp_v13_0_funcs; 576 } 577