1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "amdgpu_psp.h" 25 #include "amdgpu_ucode.h" 26 #include "soc15_common.h" 27 #include "psp_v13_0.h" 28 29 #include "mp/mp_13_0_2_offset.h" 30 #include "mp/mp_13_0_2_sh_mask.h" 31 32 MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin"); 33 MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin"); 34 MODULE_FIRMWARE("amdgpu/aldebaran_cap.bin"); 35 MODULE_FIRMWARE("amdgpu/yellow_carp_asd.bin"); 36 MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin"); 37 MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin"); 38 MODULE_FIRMWARE("amdgpu/psp_13_0_5_asd.bin"); 39 MODULE_FIRMWARE("amdgpu/psp_13_0_5_toc.bin"); 40 MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin"); 41 MODULE_FIRMWARE("amdgpu/psp_13_0_8_asd.bin"); 42 MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin"); 43 MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin"); 44 MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin"); 45 46 /* For large FW files the time to complete can be very long */ 47 #define USBC_PD_POLLING_LIMIT_S 240 48 49 /* Read USB-PD from LFB */ 50 #define GFX_CMD_USB_PD_USE_LFB 0x480 51 52 static int psp_v13_0_init_microcode(struct psp_context *psp) 53 { 54 struct amdgpu_device *adev = psp->adev; 55 const char *chip_name; 56 char ucode_prefix[30]; 57 int err = 0; 58 59 switch (adev->ip_versions[MP0_HWIP][0]) { 60 case IP_VERSION(13, 0, 2): 61 chip_name = "aldebaran"; 62 break; 63 case IP_VERSION(13, 0, 1): 64 case IP_VERSION(13, 0, 3): 65 chip_name = "yellow_carp"; 66 break; 67 default: 68 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 69 chip_name = ucode_prefix; 70 break; 71 } 72 73 switch (adev->ip_versions[MP0_HWIP][0]) { 74 case IP_VERSION(13, 0, 2): 75 err = psp_init_sos_microcode(psp, chip_name); 76 if (err) 77 return err; 78 err = psp_init_ta_microcode(&adev->psp, chip_name); 79 if (err) 80 return err; 81 break; 82 case IP_VERSION(13, 0, 1): 83 case IP_VERSION(13, 0, 3): 84 case IP_VERSION(13, 0, 5): 85 case IP_VERSION(13, 0, 8): 86 err = psp_init_asd_microcode(psp, chip_name); 87 if (err) 88 return err; 89 err = psp_init_toc_microcode(psp, chip_name); 90 if (err) 91 return err; 92 err = psp_init_ta_microcode(psp, chip_name); 93 if (err) 94 return err; 95 break; 96 case IP_VERSION(13, 0, 0): 97 err = psp_init_sos_microcode(psp, chip_name); 98 if (err) 99 return err; 100 break; 101 default: 102 BUG(); 103 } 104 105 return 0; 106 } 107 108 static bool psp_v13_0_is_sos_alive(struct psp_context *psp) 109 { 110 struct amdgpu_device *adev = psp->adev; 111 uint32_t sol_reg; 112 113 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 114 115 return sol_reg != 0x0; 116 } 117 118 static int psp_v13_0_wait_for_bootloader(struct psp_context *psp) 119 { 120 struct amdgpu_device *adev = psp->adev; 121 122 int ret; 123 int retry_loop; 124 125 for (retry_loop = 0; retry_loop < 10; retry_loop++) { 126 /* Wait for bootloader to signify that is 127 ready having bit 31 of C2PMSG_35 set to 1 */ 128 ret = psp_wait_for(psp, 129 SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 130 0x80000000, 131 0x80000000, 132 false); 133 134 if (ret == 0) 135 return 0; 136 } 137 138 return ret; 139 } 140 141 static int psp_v13_0_bootloader_load_component(struct psp_context *psp, 142 struct psp_bin_desc *bin_desc, 143 enum psp_bootloader_cmd bl_cmd) 144 { 145 int ret; 146 uint32_t psp_gfxdrv_command_reg = 0; 147 struct amdgpu_device *adev = psp->adev; 148 149 /* Check tOS sign of life register to confirm sys driver and sOS 150 * are already been loaded. 151 */ 152 if (psp_v13_0_is_sos_alive(psp)) 153 return 0; 154 155 ret = psp_v13_0_wait_for_bootloader(psp); 156 if (ret) 157 return ret; 158 159 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 160 161 /* Copy PSP KDB binary to memory */ 162 memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes); 163 164 /* Provide the PSP KDB to bootloader */ 165 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 166 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 167 psp_gfxdrv_command_reg = bl_cmd; 168 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 169 psp_gfxdrv_command_reg); 170 171 ret = psp_v13_0_wait_for_bootloader(psp); 172 173 return ret; 174 } 175 176 static int psp_v13_0_bootloader_load_kdb(struct psp_context *psp) 177 { 178 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE); 179 } 180 181 static int psp_v13_0_bootloader_load_spl(struct psp_context *psp) 182 { 183 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE); 184 } 185 186 static int psp_v13_0_bootloader_load_sysdrv(struct psp_context *psp) 187 { 188 return psp_v13_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV); 189 } 190 191 static int psp_v13_0_bootloader_load_soc_drv(struct psp_context *psp) 192 { 193 return psp_v13_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV); 194 } 195 196 static int psp_v13_0_bootloader_load_intf_drv(struct psp_context *psp) 197 { 198 return psp_v13_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV); 199 } 200 201 static int psp_v13_0_bootloader_load_dbg_drv(struct psp_context *psp) 202 { 203 return psp_v13_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV); 204 } 205 206 static int psp_v13_0_bootloader_load_sos(struct psp_context *psp) 207 { 208 int ret; 209 unsigned int psp_gfxdrv_command_reg = 0; 210 struct amdgpu_device *adev = psp->adev; 211 212 /* Check sOS sign of life register to confirm sys driver and sOS 213 * are already been loaded. 214 */ 215 if (psp_v13_0_is_sos_alive(psp)) 216 return 0; 217 218 ret = psp_v13_0_wait_for_bootloader(psp); 219 if (ret) 220 return ret; 221 222 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 223 224 /* Copy Secure OS binary to PSP memory */ 225 memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes); 226 227 /* Provide the PSP secure OS to bootloader */ 228 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 229 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 230 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; 231 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 232 psp_gfxdrv_command_reg); 233 234 /* there might be handshake issue with hardware which needs delay */ 235 mdelay(20); 236 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81), 237 RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81), 238 0, true); 239 240 return ret; 241 } 242 243 static int psp_v13_0_ring_init(struct psp_context *psp, 244 enum psp_ring_type ring_type) 245 { 246 int ret = 0; 247 struct psp_ring *ring; 248 struct amdgpu_device *adev = psp->adev; 249 250 ring = &psp->km_ring; 251 252 ring->ring_type = ring_type; 253 254 /* allocate 4k Page of Local Frame Buffer memory for ring */ 255 ring->ring_size = 0x1000; 256 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 257 AMDGPU_GEM_DOMAIN_VRAM, 258 &adev->firmware.rbuf, 259 &ring->ring_mem_mc_addr, 260 (void **)&ring->ring_mem); 261 if (ret) { 262 ring->ring_size = 0; 263 return ret; 264 } 265 266 return 0; 267 } 268 269 static int psp_v13_0_ring_stop(struct psp_context *psp, 270 enum psp_ring_type ring_type) 271 { 272 int ret = 0; 273 struct amdgpu_device *adev = psp->adev; 274 275 if (amdgpu_sriov_vf(adev)) { 276 /* Write the ring destroy command*/ 277 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 278 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 279 /* there might be handshake issue with hardware which needs delay */ 280 mdelay(20); 281 /* Wait for response flag (bit 31) */ 282 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 283 0x80000000, 0x80000000, false); 284 } else { 285 /* Write the ring destroy command*/ 286 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, 287 GFX_CTRL_CMD_ID_DESTROY_RINGS); 288 /* there might be handshake issue with hardware which needs delay */ 289 mdelay(20); 290 /* Wait for response flag (bit 31) */ 291 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 292 0x80000000, 0x80000000, false); 293 } 294 295 return ret; 296 } 297 298 static int psp_v13_0_ring_create(struct psp_context *psp, 299 enum psp_ring_type ring_type) 300 { 301 int ret = 0; 302 unsigned int psp_ring_reg = 0; 303 struct psp_ring *ring = &psp->km_ring; 304 struct amdgpu_device *adev = psp->adev; 305 306 if (amdgpu_sriov_vf(adev)) { 307 ret = psp_v13_0_ring_stop(psp, ring_type); 308 if (ret) { 309 DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n"); 310 return ret; 311 } 312 313 /* Write low address of the ring to C2PMSG_102 */ 314 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 315 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg); 316 /* Write high address of the ring to C2PMSG_103 */ 317 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 318 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg); 319 320 /* Write the ring initialization command to C2PMSG_101 */ 321 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 322 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 323 324 /* there might be handshake issue with hardware which needs delay */ 325 mdelay(20); 326 327 /* Wait for response flag (bit 31) in C2PMSG_101 */ 328 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 329 0x80000000, 0x8000FFFF, false); 330 331 } else { 332 /* Wait for sOS ready for ring creation */ 333 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 334 0x80000000, 0x80000000, false); 335 if (ret) { 336 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n"); 337 return ret; 338 } 339 340 /* Write low address of the ring to C2PMSG_69 */ 341 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 342 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg); 343 /* Write high address of the ring to C2PMSG_70 */ 344 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 345 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg); 346 /* Write size of ring to C2PMSG_71 */ 347 psp_ring_reg = ring->ring_size; 348 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg); 349 /* Write the ring initialization command to C2PMSG_64 */ 350 psp_ring_reg = ring_type; 351 psp_ring_reg = psp_ring_reg << 16; 352 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg); 353 354 /* there might be handshake issue with hardware which needs delay */ 355 mdelay(20); 356 357 /* Wait for response flag (bit 31) in C2PMSG_64 */ 358 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 359 0x80000000, 0x8000FFFF, false); 360 } 361 362 return ret; 363 } 364 365 static int psp_v13_0_ring_destroy(struct psp_context *psp, 366 enum psp_ring_type ring_type) 367 { 368 int ret = 0; 369 struct psp_ring *ring = &psp->km_ring; 370 struct amdgpu_device *adev = psp->adev; 371 372 ret = psp_v13_0_ring_stop(psp, ring_type); 373 if (ret) 374 DRM_ERROR("Fail to stop psp ring\n"); 375 376 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 377 &ring->ring_mem_mc_addr, 378 (void **)&ring->ring_mem); 379 380 return ret; 381 } 382 383 static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp) 384 { 385 uint32_t data; 386 struct amdgpu_device *adev = psp->adev; 387 388 if (amdgpu_sriov_vf(adev)) 389 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102); 390 else 391 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67); 392 393 return data; 394 } 395 396 static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value) 397 { 398 struct amdgpu_device *adev = psp->adev; 399 400 if (amdgpu_sriov_vf(adev)) { 401 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value); 402 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 403 GFX_CTRL_CMD_ID_CONSUME_CMD); 404 } else 405 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value); 406 } 407 408 static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr) 409 { 410 struct amdgpu_device *adev = psp->adev; 411 uint32_t reg_status; 412 int ret, i = 0; 413 414 /* 415 * LFB address which is aligned to 1MB address and has to be 416 * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P 417 * register 418 */ 419 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20)); 420 421 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 422 0x80000000, 0x80000000, false); 423 if (ret) 424 return ret; 425 426 /* Fireup interrupt so PSP can pick up the address */ 427 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16)); 428 429 /* FW load takes very long time */ 430 do { 431 msleep(1000); 432 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35); 433 434 if (reg_status & 0x80000000) 435 goto done; 436 437 } while (++i < USBC_PD_POLLING_LIMIT_S); 438 439 return -ETIME; 440 done: 441 442 if ((reg_status & 0xFFFF) != 0) { 443 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n", 444 reg_status & 0xFFFF); 445 return -EIO; 446 } 447 448 return 0; 449 } 450 451 static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver) 452 { 453 struct amdgpu_device *adev = psp->adev; 454 int ret; 455 456 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER); 457 458 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 459 0x80000000, 0x80000000, false); 460 if (!ret) 461 *fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36); 462 463 return ret; 464 } 465 466 static const struct psp_funcs psp_v13_0_funcs = { 467 .init_microcode = psp_v13_0_init_microcode, 468 .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb, 469 .bootloader_load_spl = psp_v13_0_bootloader_load_spl, 470 .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv, 471 .bootloader_load_soc_drv = psp_v13_0_bootloader_load_soc_drv, 472 .bootloader_load_intf_drv = psp_v13_0_bootloader_load_intf_drv, 473 .bootloader_load_dbg_drv = psp_v13_0_bootloader_load_dbg_drv, 474 .bootloader_load_sos = psp_v13_0_bootloader_load_sos, 475 .ring_init = psp_v13_0_ring_init, 476 .ring_create = psp_v13_0_ring_create, 477 .ring_stop = psp_v13_0_ring_stop, 478 .ring_destroy = psp_v13_0_ring_destroy, 479 .ring_get_wptr = psp_v13_0_ring_get_wptr, 480 .ring_set_wptr = psp_v13_0_ring_set_wptr, 481 .load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw, 482 .read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw 483 }; 484 485 void psp_v13_0_set_psp_funcs(struct psp_context *psp) 486 { 487 psp->funcs = &psp_v13_0_funcs; 488 } 489