1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "amdgpu_psp.h" 25 #include "amdgpu_ucode.h" 26 #include "soc15_common.h" 27 #include "psp_v13_0.h" 28 29 #include "mp/mp_13_0_2_offset.h" 30 #include "mp/mp_13_0_2_sh_mask.h" 31 32 MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin"); 33 MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin"); 34 MODULE_FIRMWARE("amdgpu/yellow_carp_asd.bin"); 35 MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin"); 36 MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin"); 37 38 /* For large FW files the time to complete can be very long */ 39 #define USBC_PD_POLLING_LIMIT_S 240 40 41 /* Read USB-PD from LFB */ 42 #define GFX_CMD_USB_PD_USE_LFB 0x480 43 44 static int psp_v13_0_init_microcode(struct psp_context *psp) 45 { 46 struct amdgpu_device *adev = psp->adev; 47 const char *chip_name; 48 int err = 0; 49 50 switch (adev->asic_type) { 51 case CHIP_ALDEBARAN: 52 chip_name = "aldebaran"; 53 break; 54 case CHIP_YELLOW_CARP: 55 chip_name = "yellow_carp"; 56 break; 57 default: 58 BUG(); 59 } 60 switch (adev->asic_type) { 61 case CHIP_ALDEBARAN: 62 err = psp_init_sos_microcode(psp, chip_name); 63 if (err) 64 return err; 65 err = psp_init_ta_microcode(&adev->psp, chip_name); 66 if (err) 67 return err; 68 break; 69 case CHIP_YELLOW_CARP: 70 err = psp_init_asd_microcode(psp, chip_name); 71 if (err) 72 return err; 73 err = psp_init_toc_microcode(psp, chip_name); 74 if (err) 75 return err; 76 err = psp_init_ta_microcode(psp, chip_name); 77 if (err) 78 return err; 79 break; 80 default: 81 BUG(); 82 } 83 84 return 0; 85 } 86 87 static bool psp_v13_0_is_sos_alive(struct psp_context *psp) 88 { 89 struct amdgpu_device *adev = psp->adev; 90 uint32_t sol_reg; 91 92 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 93 94 return sol_reg != 0x0; 95 } 96 97 static int psp_v13_0_wait_for_bootloader(struct psp_context *psp) 98 { 99 struct amdgpu_device *adev = psp->adev; 100 101 int ret; 102 int retry_loop; 103 104 for (retry_loop = 0; retry_loop < 10; retry_loop++) { 105 /* Wait for bootloader to signify that is 106 ready having bit 31 of C2PMSG_35 set to 1 */ 107 ret = psp_wait_for(psp, 108 SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 109 0x80000000, 110 0x80000000, 111 false); 112 113 if (ret == 0) 114 return 0; 115 } 116 117 return ret; 118 } 119 120 static int psp_v13_0_bootloader_load_kdb(struct psp_context *psp) 121 { 122 int ret; 123 uint32_t psp_gfxdrv_command_reg = 0; 124 struct amdgpu_device *adev = psp->adev; 125 126 /* Check tOS sign of life register to confirm sys driver and sOS 127 * are already been loaded. 128 */ 129 if (psp_v13_0_is_sos_alive(psp)) 130 return 0; 131 132 ret = psp_v13_0_wait_for_bootloader(psp); 133 if (ret) 134 return ret; 135 136 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 137 138 /* Copy PSP KDB binary to memory */ 139 memcpy(psp->fw_pri_buf, psp->kdb_start_addr, psp->kdb_bin_size); 140 141 /* Provide the PSP KDB to bootloader */ 142 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 143 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 144 psp_gfxdrv_command_reg = PSP_BL__LOAD_KEY_DATABASE; 145 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 146 psp_gfxdrv_command_reg); 147 148 ret = psp_v13_0_wait_for_bootloader(psp); 149 150 return ret; 151 } 152 153 static int psp_v13_0_bootloader_load_sysdrv(struct psp_context *psp) 154 { 155 int ret; 156 uint32_t psp_gfxdrv_command_reg = 0; 157 struct amdgpu_device *adev = psp->adev; 158 159 /* Check sOS sign of life register to confirm sys driver and sOS 160 * are already been loaded. 161 */ 162 if (psp_v13_0_is_sos_alive(psp)) 163 return 0; 164 165 ret = psp_v13_0_wait_for_bootloader(psp); 166 if (ret) 167 return ret; 168 169 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 170 171 /* Copy PSP System Driver binary to memory */ 172 memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size); 173 174 /* Provide the sys driver to bootloader */ 175 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 176 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 177 psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV; 178 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 179 psp_gfxdrv_command_reg); 180 181 /* there might be handshake issue with hardware which needs delay */ 182 mdelay(20); 183 184 ret = psp_v13_0_wait_for_bootloader(psp); 185 186 return ret; 187 } 188 189 static int psp_v13_0_bootloader_load_sos(struct psp_context *psp) 190 { 191 int ret; 192 unsigned int psp_gfxdrv_command_reg = 0; 193 struct amdgpu_device *adev = psp->adev; 194 195 /* Check sOS sign of life register to confirm sys driver and sOS 196 * are already been loaded. 197 */ 198 if (psp_v13_0_is_sos_alive(psp)) 199 return 0; 200 201 ret = psp_v13_0_wait_for_bootloader(psp); 202 if (ret) 203 return ret; 204 205 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 206 207 /* Copy Secure OS binary to PSP memory */ 208 memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size); 209 210 /* Provide the PSP secure OS to bootloader */ 211 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 212 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 213 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; 214 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 215 psp_gfxdrv_command_reg); 216 217 /* there might be handshake issue with hardware which needs delay */ 218 mdelay(20); 219 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81), 220 RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81), 221 0, true); 222 223 return ret; 224 } 225 226 static int psp_v13_0_ring_init(struct psp_context *psp, 227 enum psp_ring_type ring_type) 228 { 229 int ret = 0; 230 struct psp_ring *ring; 231 struct amdgpu_device *adev = psp->adev; 232 233 ring = &psp->km_ring; 234 235 ring->ring_type = ring_type; 236 237 /* allocate 4k Page of Local Frame Buffer memory for ring */ 238 ring->ring_size = 0x1000; 239 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 240 AMDGPU_GEM_DOMAIN_VRAM, 241 &adev->firmware.rbuf, 242 &ring->ring_mem_mc_addr, 243 (void **)&ring->ring_mem); 244 if (ret) { 245 ring->ring_size = 0; 246 return ret; 247 } 248 249 return 0; 250 } 251 252 static int psp_v13_0_ring_stop(struct psp_context *psp, 253 enum psp_ring_type ring_type) 254 { 255 int ret = 0; 256 struct amdgpu_device *adev = psp->adev; 257 258 if (amdgpu_sriov_vf(adev)) { 259 /* Write the ring destroy command*/ 260 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 261 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 262 /* there might be handshake issue with hardware which needs delay */ 263 mdelay(20); 264 /* Wait for response flag (bit 31) */ 265 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 266 0x80000000, 0x80000000, false); 267 } else { 268 /* Write the ring destroy command*/ 269 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, 270 GFX_CTRL_CMD_ID_DESTROY_RINGS); 271 /* there might be handshake issue with hardware which needs delay */ 272 mdelay(20); 273 /* Wait for response flag (bit 31) */ 274 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 275 0x80000000, 0x80000000, false); 276 } 277 278 return ret; 279 } 280 281 static int psp_v13_0_ring_create(struct psp_context *psp, 282 enum psp_ring_type ring_type) 283 { 284 int ret = 0; 285 unsigned int psp_ring_reg = 0; 286 struct psp_ring *ring = &psp->km_ring; 287 struct amdgpu_device *adev = psp->adev; 288 289 if (amdgpu_sriov_vf(adev)) { 290 ret = psp_v13_0_ring_stop(psp, ring_type); 291 if (ret) { 292 DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n"); 293 return ret; 294 } 295 296 /* Write low address of the ring to C2PMSG_102 */ 297 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 298 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg); 299 /* Write high address of the ring to C2PMSG_103 */ 300 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 301 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg); 302 303 /* Write the ring initialization command to C2PMSG_101 */ 304 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 305 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 306 307 /* there might be handshake issue with hardware which needs delay */ 308 mdelay(20); 309 310 /* Wait for response flag (bit 31) in C2PMSG_101 */ 311 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 312 0x80000000, 0x8000FFFF, false); 313 314 } else { 315 /* Wait for sOS ready for ring creation */ 316 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 317 0x80000000, 0x80000000, false); 318 if (ret) { 319 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n"); 320 return ret; 321 } 322 323 /* Write low address of the ring to C2PMSG_69 */ 324 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 325 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg); 326 /* Write high address of the ring to C2PMSG_70 */ 327 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 328 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg); 329 /* Write size of ring to C2PMSG_71 */ 330 psp_ring_reg = ring->ring_size; 331 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg); 332 /* Write the ring initialization command to C2PMSG_64 */ 333 psp_ring_reg = ring_type; 334 psp_ring_reg = psp_ring_reg << 16; 335 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg); 336 337 /* there might be handshake issue with hardware which needs delay */ 338 mdelay(20); 339 340 /* Wait for response flag (bit 31) in C2PMSG_64 */ 341 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 342 0x80000000, 0x8000FFFF, false); 343 } 344 345 return ret; 346 } 347 348 static int psp_v13_0_ring_destroy(struct psp_context *psp, 349 enum psp_ring_type ring_type) 350 { 351 int ret = 0; 352 struct psp_ring *ring = &psp->km_ring; 353 struct amdgpu_device *adev = psp->adev; 354 355 ret = psp_v13_0_ring_stop(psp, ring_type); 356 if (ret) 357 DRM_ERROR("Fail to stop psp ring\n"); 358 359 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 360 &ring->ring_mem_mc_addr, 361 (void **)&ring->ring_mem); 362 363 return ret; 364 } 365 366 static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp) 367 { 368 uint32_t data; 369 struct amdgpu_device *adev = psp->adev; 370 371 if (amdgpu_sriov_vf(adev)) 372 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102); 373 else 374 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67); 375 376 return data; 377 } 378 379 static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value) 380 { 381 struct amdgpu_device *adev = psp->adev; 382 383 if (amdgpu_sriov_vf(adev)) { 384 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value); 385 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 386 GFX_CTRL_CMD_ID_CONSUME_CMD); 387 } else 388 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value); 389 } 390 391 static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr) 392 { 393 struct amdgpu_device *adev = psp->adev; 394 uint32_t reg_status; 395 int ret, i = 0; 396 397 /* 398 * LFB address which is aligned to 1MB address and has to be 399 * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P 400 * register 401 */ 402 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20)); 403 404 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 405 0x80000000, 0x80000000, false); 406 if (ret) 407 return ret; 408 409 /* Fireup interrupt so PSP can pick up the address */ 410 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16)); 411 412 /* FW load takes very long time */ 413 do { 414 msleep(1000); 415 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35); 416 417 if (reg_status & 0x80000000) 418 goto done; 419 420 } while (++i < USBC_PD_POLLING_LIMIT_S); 421 422 return -ETIME; 423 done: 424 425 if ((reg_status & 0xFFFF) != 0) { 426 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n", 427 reg_status & 0xFFFF); 428 return -EIO; 429 } 430 431 return 0; 432 } 433 434 static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver) 435 { 436 struct amdgpu_device *adev = psp->adev; 437 int ret; 438 439 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER); 440 441 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 442 0x80000000, 0x80000000, false); 443 if (!ret) 444 *fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36); 445 446 return ret; 447 } 448 449 static const struct psp_funcs psp_v13_0_funcs = { 450 .init_microcode = psp_v13_0_init_microcode, 451 .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb, 452 .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv, 453 .bootloader_load_sos = psp_v13_0_bootloader_load_sos, 454 .ring_init = psp_v13_0_ring_init, 455 .ring_create = psp_v13_0_ring_create, 456 .ring_stop = psp_v13_0_ring_stop, 457 .ring_destroy = psp_v13_0_ring_destroy, 458 .ring_get_wptr = psp_v13_0_ring_get_wptr, 459 .ring_set_wptr = psp_v13_0_ring_set_wptr, 460 .load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw, 461 .read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw 462 }; 463 464 void psp_v13_0_set_psp_funcs(struct psp_context *psp) 465 { 466 psp->funcs = &psp_v13_0_funcs; 467 } 468