1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <drm/drm_drv.h> 24 #include <linux/vmalloc.h> 25 #include "amdgpu.h" 26 #include "amdgpu_psp.h" 27 #include "amdgpu_ucode.h" 28 #include "soc15_common.h" 29 #include "psp_v13_0.h" 30 31 #include "mp/mp_13_0_2_offset.h" 32 #include "mp/mp_13_0_2_sh_mask.h" 33 34 MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin"); 35 MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin"); 36 MODULE_FIRMWARE("amdgpu/aldebaran_cap.bin"); 37 MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin"); 38 MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin"); 39 MODULE_FIRMWARE("amdgpu/psp_13_0_5_toc.bin"); 40 MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin"); 41 MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin"); 42 MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin"); 43 MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin"); 44 MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta.bin"); 45 MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin"); 46 MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin"); 47 MODULE_FIRMWARE("amdgpu/psp_13_0_10_sos.bin"); 48 MODULE_FIRMWARE("amdgpu/psp_13_0_10_ta.bin"); 49 MODULE_FIRMWARE("amdgpu/psp_13_0_11_toc.bin"); 50 MODULE_FIRMWARE("amdgpu/psp_13_0_11_ta.bin"); 51 MODULE_FIRMWARE("amdgpu/psp_13_0_6_sos.bin"); 52 53 /* For large FW files the time to complete can be very long */ 54 #define USBC_PD_POLLING_LIMIT_S 240 55 56 /* Read USB-PD from LFB */ 57 #define GFX_CMD_USB_PD_USE_LFB 0x480 58 59 /* VBIOS gfl defines */ 60 #define MBOX_READY_MASK 0x80000000 61 #define MBOX_STATUS_MASK 0x0000FFFF 62 #define MBOX_COMMAND_MASK 0x00FF0000 63 #define MBOX_READY_FLAG 0x80000000 64 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO 0x2 65 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3 66 #define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4 67 68 /* memory training timeout define */ 69 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000 70 71 static int psp_v13_0_init_microcode(struct psp_context *psp) 72 { 73 struct amdgpu_device *adev = psp->adev; 74 char ucode_prefix[30]; 75 int err = 0; 76 77 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 78 79 switch (adev->ip_versions[MP0_HWIP][0]) { 80 case IP_VERSION(13, 0, 2): 81 err = psp_init_sos_microcode(psp, ucode_prefix); 82 if (err) 83 return err; 84 /* It's not necessary to load ras ta on Guest side */ 85 if (!amdgpu_sriov_vf(adev)) { 86 err = psp_init_ta_microcode(psp, ucode_prefix); 87 if (err) 88 return err; 89 } 90 break; 91 case IP_VERSION(13, 0, 1): 92 case IP_VERSION(13, 0, 3): 93 case IP_VERSION(13, 0, 5): 94 case IP_VERSION(13, 0, 8): 95 case IP_VERSION(13, 0, 11): 96 err = psp_init_toc_microcode(psp, ucode_prefix); 97 if (err) 98 return err; 99 err = psp_init_ta_microcode(psp, ucode_prefix); 100 if (err) 101 return err; 102 break; 103 case IP_VERSION(13, 0, 0): 104 case IP_VERSION(13, 0, 6): 105 case IP_VERSION(13, 0, 7): 106 case IP_VERSION(13, 0, 10): 107 err = psp_init_sos_microcode(psp, ucode_prefix); 108 if (err) 109 return err; 110 /* It's not necessary to load ras ta on Guest side */ 111 err = psp_init_ta_microcode(psp, ucode_prefix); 112 if (err) 113 return err; 114 break; 115 default: 116 BUG(); 117 } 118 119 return 0; 120 } 121 122 static bool psp_v13_0_is_sos_alive(struct psp_context *psp) 123 { 124 struct amdgpu_device *adev = psp->adev; 125 uint32_t sol_reg; 126 127 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 128 129 return sol_reg != 0x0; 130 } 131 132 static int psp_v13_0_wait_for_bootloader(struct psp_context *psp) 133 { 134 struct amdgpu_device *adev = psp->adev; 135 136 int ret; 137 int retry_loop; 138 139 for (retry_loop = 0; retry_loop < 10; retry_loop++) { 140 /* Wait for bootloader to signify that is 141 ready having bit 31 of C2PMSG_35 set to 1 */ 142 ret = psp_wait_for(psp, 143 SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 144 0x80000000, 145 0x80000000, 146 false); 147 148 if (ret == 0) 149 return 0; 150 } 151 152 return ret; 153 } 154 155 static int psp_v13_0_bootloader_load_component(struct psp_context *psp, 156 struct psp_bin_desc *bin_desc, 157 enum psp_bootloader_cmd bl_cmd) 158 { 159 int ret; 160 uint32_t psp_gfxdrv_command_reg = 0; 161 struct amdgpu_device *adev = psp->adev; 162 163 /* Check tOS sign of life register to confirm sys driver and sOS 164 * are already been loaded. 165 */ 166 if (psp_v13_0_is_sos_alive(psp)) 167 return 0; 168 169 ret = psp_v13_0_wait_for_bootloader(psp); 170 if (ret) 171 return ret; 172 173 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 174 175 /* Copy PSP KDB binary to memory */ 176 memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes); 177 178 /* Provide the PSP KDB to bootloader */ 179 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 180 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 181 psp_gfxdrv_command_reg = bl_cmd; 182 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 183 psp_gfxdrv_command_reg); 184 185 ret = psp_v13_0_wait_for_bootloader(psp); 186 187 return ret; 188 } 189 190 static int psp_v13_0_bootloader_load_kdb(struct psp_context *psp) 191 { 192 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE); 193 } 194 195 static int psp_v13_0_bootloader_load_spl(struct psp_context *psp) 196 { 197 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE); 198 } 199 200 static int psp_v13_0_bootloader_load_sysdrv(struct psp_context *psp) 201 { 202 return psp_v13_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV); 203 } 204 205 static int psp_v13_0_bootloader_load_soc_drv(struct psp_context *psp) 206 { 207 return psp_v13_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV); 208 } 209 210 static int psp_v13_0_bootloader_load_intf_drv(struct psp_context *psp) 211 { 212 return psp_v13_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV); 213 } 214 215 static int psp_v13_0_bootloader_load_dbg_drv(struct psp_context *psp) 216 { 217 return psp_v13_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV); 218 } 219 220 static int psp_v13_0_bootloader_load_ras_drv(struct psp_context *psp) 221 { 222 return psp_v13_0_bootloader_load_component(psp, &psp->ras_drv, PSP_BL__LOAD_RASDRV); 223 } 224 225 226 static int psp_v13_0_bootloader_load_sos(struct psp_context *psp) 227 { 228 int ret; 229 unsigned int psp_gfxdrv_command_reg = 0; 230 struct amdgpu_device *adev = psp->adev; 231 232 /* Check sOS sign of life register to confirm sys driver and sOS 233 * are already been loaded. 234 */ 235 if (psp_v13_0_is_sos_alive(psp)) 236 return 0; 237 238 ret = psp_v13_0_wait_for_bootloader(psp); 239 if (ret) 240 return ret; 241 242 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 243 244 /* Copy Secure OS binary to PSP memory */ 245 memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes); 246 247 /* Provide the PSP secure OS to bootloader */ 248 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 249 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 250 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; 251 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 252 psp_gfxdrv_command_reg); 253 254 /* there might be handshake issue with hardware which needs delay */ 255 mdelay(20); 256 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81), 257 RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81), 258 0, true); 259 260 return ret; 261 } 262 263 static int psp_v13_0_ring_stop(struct psp_context *psp, 264 enum psp_ring_type ring_type) 265 { 266 int ret = 0; 267 struct amdgpu_device *adev = psp->adev; 268 269 if (amdgpu_sriov_vf(adev)) { 270 /* Write the ring destroy command*/ 271 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 272 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 273 /* there might be handshake issue with hardware which needs delay */ 274 mdelay(20); 275 /* Wait for response flag (bit 31) */ 276 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 277 0x80000000, 0x80000000, false); 278 } else { 279 /* Write the ring destroy command*/ 280 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, 281 GFX_CTRL_CMD_ID_DESTROY_RINGS); 282 /* there might be handshake issue with hardware which needs delay */ 283 mdelay(20); 284 /* Wait for response flag (bit 31) */ 285 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 286 0x80000000, 0x80000000, false); 287 } 288 289 return ret; 290 } 291 292 static int psp_v13_0_ring_create(struct psp_context *psp, 293 enum psp_ring_type ring_type) 294 { 295 int ret = 0; 296 unsigned int psp_ring_reg = 0; 297 struct psp_ring *ring = &psp->km_ring; 298 struct amdgpu_device *adev = psp->adev; 299 300 if (amdgpu_sriov_vf(adev)) { 301 ret = psp_v13_0_ring_stop(psp, ring_type); 302 if (ret) { 303 DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n"); 304 return ret; 305 } 306 307 /* Write low address of the ring to C2PMSG_102 */ 308 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 309 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg); 310 /* Write high address of the ring to C2PMSG_103 */ 311 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 312 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg); 313 314 /* Write the ring initialization command to C2PMSG_101 */ 315 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 316 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 317 318 /* there might be handshake issue with hardware which needs delay */ 319 mdelay(20); 320 321 /* Wait for response flag (bit 31) in C2PMSG_101 */ 322 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 323 0x80000000, 0x8000FFFF, false); 324 325 } else { 326 /* Wait for sOS ready for ring creation */ 327 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 328 0x80000000, 0x80000000, false); 329 if (ret) { 330 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n"); 331 return ret; 332 } 333 334 /* Write low address of the ring to C2PMSG_69 */ 335 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 336 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg); 337 /* Write high address of the ring to C2PMSG_70 */ 338 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 339 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg); 340 /* Write size of ring to C2PMSG_71 */ 341 psp_ring_reg = ring->ring_size; 342 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg); 343 /* Write the ring initialization command to C2PMSG_64 */ 344 psp_ring_reg = ring_type; 345 psp_ring_reg = psp_ring_reg << 16; 346 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg); 347 348 /* there might be handshake issue with hardware which needs delay */ 349 mdelay(20); 350 351 /* Wait for response flag (bit 31) in C2PMSG_64 */ 352 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 353 0x80000000, 0x8000FFFF, false); 354 } 355 356 return ret; 357 } 358 359 static int psp_v13_0_ring_destroy(struct psp_context *psp, 360 enum psp_ring_type ring_type) 361 { 362 int ret = 0; 363 struct psp_ring *ring = &psp->km_ring; 364 struct amdgpu_device *adev = psp->adev; 365 366 ret = psp_v13_0_ring_stop(psp, ring_type); 367 if (ret) 368 DRM_ERROR("Fail to stop psp ring\n"); 369 370 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 371 &ring->ring_mem_mc_addr, 372 (void **)&ring->ring_mem); 373 374 return ret; 375 } 376 377 static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp) 378 { 379 uint32_t data; 380 struct amdgpu_device *adev = psp->adev; 381 382 if (amdgpu_sriov_vf(adev)) 383 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102); 384 else 385 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67); 386 387 return data; 388 } 389 390 static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value) 391 { 392 struct amdgpu_device *adev = psp->adev; 393 394 if (amdgpu_sriov_vf(adev)) { 395 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value); 396 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 397 GFX_CTRL_CMD_ID_CONSUME_CMD); 398 } else 399 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value); 400 } 401 402 static int psp_v13_0_memory_training_send_msg(struct psp_context *psp, int msg) 403 { 404 int ret; 405 int i; 406 uint32_t data_32; 407 int max_wait; 408 struct amdgpu_device *adev = psp->adev; 409 410 data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20); 411 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, data_32); 412 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, msg); 413 414 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout; 415 for (i = 0; i < max_wait; i++) { 416 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 417 0x80000000, 0x80000000, false); 418 if (ret == 0) 419 break; 420 } 421 if (i < max_wait) 422 ret = 0; 423 else 424 ret = -ETIME; 425 426 dev_dbg(adev->dev, "training %s %s, cost %d @ %d ms\n", 427 (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long", 428 (ret == 0) ? "succeed" : "failed", 429 i, adev->usec_timeout/1000); 430 return ret; 431 } 432 433 434 static int psp_v13_0_memory_training(struct psp_context *psp, uint32_t ops) 435 { 436 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 437 uint32_t *pcache = (uint32_t *)ctx->sys_cache; 438 struct amdgpu_device *adev = psp->adev; 439 uint32_t p2c_header[4]; 440 uint32_t sz; 441 void *buf; 442 int ret, idx; 443 444 if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) { 445 dev_dbg(adev->dev, "Memory training is not supported.\n"); 446 return 0; 447 } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) { 448 dev_err(adev->dev, "Memory training initialization failure.\n"); 449 return -EINVAL; 450 } 451 452 if (psp_v13_0_is_sos_alive(psp)) { 453 dev_dbg(adev->dev, "SOS is alive, skip memory training.\n"); 454 return 0; 455 } 456 457 amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false); 458 dev_dbg(adev->dev, "sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n", 459 pcache[0], pcache[1], pcache[2], pcache[3], 460 p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]); 461 462 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 463 dev_dbg(adev->dev, "Short training depends on restore.\n"); 464 ops |= PSP_MEM_TRAIN_RESTORE; 465 } 466 467 if ((ops & PSP_MEM_TRAIN_RESTORE) && 468 pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 469 dev_dbg(adev->dev, "sys_cache[0] is invalid, restore depends on save.\n"); 470 ops |= PSP_MEM_TRAIN_SAVE; 471 } 472 473 if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 474 !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 475 pcache[3] == p2c_header[3])) { 476 dev_dbg(adev->dev, "sys_cache is invalid or out-of-date, need save training data to sys_cache.\n"); 477 ops |= PSP_MEM_TRAIN_SAVE; 478 } 479 480 if ((ops & PSP_MEM_TRAIN_SAVE) && 481 p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 482 dev_dbg(adev->dev, "p2c_header[0] is invalid, save depends on long training.\n"); 483 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG; 484 } 485 486 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 487 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG; 488 ops |= PSP_MEM_TRAIN_SAVE; 489 } 490 491 dev_dbg(adev->dev, "Memory training ops:%x.\n", ops); 492 493 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 494 /* 495 * Long training will encroach a certain amount on the bottom of VRAM; 496 * save the content from the bottom of VRAM to system memory 497 * before training, and restore it after training to avoid 498 * VRAM corruption. 499 */ 500 sz = GDDR6_MEM_TRAINING_ENCROACHED_SIZE; 501 502 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) { 503 dev_err(adev->dev, "visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n", 504 adev->gmc.visible_vram_size, 505 adev->mman.aper_base_kaddr); 506 return -EINVAL; 507 } 508 509 buf = vmalloc(sz); 510 if (!buf) { 511 dev_err(adev->dev, "failed to allocate system memory.\n"); 512 return -ENOMEM; 513 } 514 515 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 516 memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz); 517 ret = psp_v13_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN); 518 if (ret) { 519 DRM_ERROR("Send long training msg failed.\n"); 520 vfree(buf); 521 drm_dev_exit(idx); 522 return ret; 523 } 524 525 memcpy_toio(adev->mman.aper_base_kaddr, buf, sz); 526 adev->hdp.funcs->flush_hdp(adev, NULL); 527 vfree(buf); 528 drm_dev_exit(idx); 529 } else { 530 vfree(buf); 531 return -ENODEV; 532 } 533 } 534 535 if (ops & PSP_MEM_TRAIN_SAVE) { 536 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false); 537 } 538 539 if (ops & PSP_MEM_TRAIN_RESTORE) { 540 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true); 541 } 542 543 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 544 ret = psp_v13_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ? 545 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN); 546 if (ret) { 547 dev_err(adev->dev, "send training msg failed.\n"); 548 return ret; 549 } 550 } 551 ctx->training_cnt++; 552 return 0; 553 } 554 555 static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr) 556 { 557 struct amdgpu_device *adev = psp->adev; 558 uint32_t reg_status; 559 int ret, i = 0; 560 561 /* 562 * LFB address which is aligned to 1MB address and has to be 563 * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P 564 * register 565 */ 566 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20)); 567 568 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 569 0x80000000, 0x80000000, false); 570 if (ret) 571 return ret; 572 573 /* Fireup interrupt so PSP can pick up the address */ 574 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16)); 575 576 /* FW load takes very long time */ 577 do { 578 msleep(1000); 579 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35); 580 581 if (reg_status & 0x80000000) 582 goto done; 583 584 } while (++i < USBC_PD_POLLING_LIMIT_S); 585 586 return -ETIME; 587 done: 588 589 if ((reg_status & 0xFFFF) != 0) { 590 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n", 591 reg_status & 0xFFFF); 592 return -EIO; 593 } 594 595 return 0; 596 } 597 598 static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver) 599 { 600 struct amdgpu_device *adev = psp->adev; 601 int ret; 602 603 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER); 604 605 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 606 0x80000000, 0x80000000, false); 607 if (!ret) 608 *fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36); 609 610 return ret; 611 } 612 613 static int psp_v13_0_exec_spi_cmd(struct psp_context *psp, int cmd) 614 { 615 uint32_t reg_status = 0, reg_val = 0; 616 struct amdgpu_device *adev = psp->adev; 617 int ret; 618 619 /* clear MBX ready (MBOX_READY_MASK bit is 0) and set update command */ 620 reg_val |= (cmd << 16); 621 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115, reg_val); 622 623 /* Ring the doorbell */ 624 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_73, 1); 625 626 if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE) 627 ret = psp_wait_for_spirom_update(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 628 MBOX_READY_FLAG, MBOX_READY_MASK, PSP_SPIROM_UPDATE_TIMEOUT); 629 else 630 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 631 MBOX_READY_FLAG, MBOX_READY_MASK, false); 632 if (ret) { 633 dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret); 634 return ret; 635 } 636 637 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115); 638 if ((reg_status & 0xFFFF) != 0) { 639 dev_err(adev->dev, "SPI cmd %x failed, fail status = %04x\n", 640 cmd, reg_status & 0xFFFF); 641 return -EIO; 642 } 643 644 return 0; 645 } 646 647 static int psp_v13_0_update_spirom(struct psp_context *psp, 648 uint64_t fw_pri_mc_addr) 649 { 650 struct amdgpu_device *adev = psp->adev; 651 int ret; 652 653 /* Confirm PSP is ready to start */ 654 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 655 MBOX_READY_FLAG, MBOX_READY_MASK, false); 656 if (ret) { 657 dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret); 658 return ret; 659 } 660 661 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr)); 662 663 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO); 664 if (ret) 665 return ret; 666 667 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr)); 668 669 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI); 670 if (ret) 671 return ret; 672 673 psp->vbflash_done = true; 674 675 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE); 676 if (ret) 677 return ret; 678 679 return 0; 680 } 681 682 static int psp_v13_0_vbflash_status(struct psp_context *psp) 683 { 684 struct amdgpu_device *adev = psp->adev; 685 686 return RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115); 687 } 688 689 static const struct psp_funcs psp_v13_0_funcs = { 690 .init_microcode = psp_v13_0_init_microcode, 691 .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb, 692 .bootloader_load_spl = psp_v13_0_bootloader_load_spl, 693 .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv, 694 .bootloader_load_soc_drv = psp_v13_0_bootloader_load_soc_drv, 695 .bootloader_load_intf_drv = psp_v13_0_bootloader_load_intf_drv, 696 .bootloader_load_dbg_drv = psp_v13_0_bootloader_load_dbg_drv, 697 .bootloader_load_ras_drv = psp_v13_0_bootloader_load_ras_drv, 698 .bootloader_load_sos = psp_v13_0_bootloader_load_sos, 699 .ring_create = psp_v13_0_ring_create, 700 .ring_stop = psp_v13_0_ring_stop, 701 .ring_destroy = psp_v13_0_ring_destroy, 702 .ring_get_wptr = psp_v13_0_ring_get_wptr, 703 .ring_set_wptr = psp_v13_0_ring_set_wptr, 704 .mem_training = psp_v13_0_memory_training, 705 .load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw, 706 .read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw, 707 .update_spirom = psp_v13_0_update_spirom, 708 .vbflash_stat = psp_v13_0_vbflash_status 709 }; 710 711 void psp_v13_0_set_psp_funcs(struct psp_context *psp) 712 { 713 psp->funcs = &psp_v13_0_funcs; 714 } 715