1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "amdgpu_psp.h" 25 #include "amdgpu_ucode.h" 26 #include "soc15_common.h" 27 #include "psp_v13_0.h" 28 29 #include "mp/mp_13_0_2_offset.h" 30 #include "mp/mp_13_0_2_sh_mask.h" 31 32 MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin"); 33 MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin"); 34 MODULE_FIRMWARE("amdgpu/yellow_carp_asd.bin"); 35 MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin"); 36 MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin"); 37 38 /* For large FW files the time to complete can be very long */ 39 #define USBC_PD_POLLING_LIMIT_S 240 40 41 /* Read USB-PD from LFB */ 42 #define GFX_CMD_USB_PD_USE_LFB 0x480 43 44 static int psp_v13_0_init_microcode(struct psp_context *psp) 45 { 46 struct amdgpu_device *adev = psp->adev; 47 const char *chip_name; 48 int err = 0; 49 50 switch (adev->ip_versions[MP0_HWIP][0]) { 51 case IP_VERSION(13, 0, 2): 52 chip_name = "aldebaran"; 53 break; 54 case IP_VERSION(13, 0, 1): 55 case IP_VERSION(13, 0, 3): 56 chip_name = "yellow_carp"; 57 break; 58 default: 59 BUG(); 60 } 61 switch (adev->ip_versions[MP0_HWIP][0]) { 62 case IP_VERSION(13, 0, 2): 63 err = psp_init_sos_microcode(psp, chip_name); 64 if (err) 65 return err; 66 err = psp_init_ta_microcode(&adev->psp, chip_name); 67 if (err) 68 return err; 69 break; 70 case IP_VERSION(13, 0, 1): 71 case IP_VERSION(13, 0, 3): 72 err = psp_init_asd_microcode(psp, chip_name); 73 if (err) 74 return err; 75 err = psp_init_toc_microcode(psp, chip_name); 76 if (err) 77 return err; 78 err = psp_init_ta_microcode(psp, chip_name); 79 if (err) 80 return err; 81 break; 82 default: 83 BUG(); 84 } 85 86 return 0; 87 } 88 89 static bool psp_v13_0_is_sos_alive(struct psp_context *psp) 90 { 91 struct amdgpu_device *adev = psp->adev; 92 uint32_t sol_reg; 93 94 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 95 96 return sol_reg != 0x0; 97 } 98 99 static int psp_v13_0_wait_for_bootloader(struct psp_context *psp) 100 { 101 struct amdgpu_device *adev = psp->adev; 102 103 int ret; 104 int retry_loop; 105 106 for (retry_loop = 0; retry_loop < 10; retry_loop++) { 107 /* Wait for bootloader to signify that is 108 ready having bit 31 of C2PMSG_35 set to 1 */ 109 ret = psp_wait_for(psp, 110 SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 111 0x80000000, 112 0x80000000, 113 false); 114 115 if (ret == 0) 116 return 0; 117 } 118 119 return ret; 120 } 121 122 static int psp_v13_0_bootloader_load_component(struct psp_context *psp, 123 struct psp_bin_desc *bin_desc, 124 enum psp_bootloader_cmd bl_cmd) 125 { 126 int ret; 127 uint32_t psp_gfxdrv_command_reg = 0; 128 struct amdgpu_device *adev = psp->adev; 129 130 /* Check tOS sign of life register to confirm sys driver and sOS 131 * are already been loaded. 132 */ 133 if (psp_v13_0_is_sos_alive(psp)) 134 return 0; 135 136 ret = psp_v13_0_wait_for_bootloader(psp); 137 if (ret) 138 return ret; 139 140 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 141 142 /* Copy PSP KDB binary to memory */ 143 memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes); 144 145 /* Provide the PSP KDB to bootloader */ 146 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 147 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 148 psp_gfxdrv_command_reg = bl_cmd; 149 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 150 psp_gfxdrv_command_reg); 151 152 ret = psp_v13_0_wait_for_bootloader(psp); 153 154 return ret; 155 } 156 157 static int psp_v13_0_bootloader_load_kdb(struct psp_context *psp) 158 { 159 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE); 160 } 161 162 static int psp_v13_0_bootloader_load_sysdrv(struct psp_context *psp) 163 { 164 return psp_v13_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV); 165 } 166 167 static int psp_v13_0_bootloader_load_soc_drv(struct psp_context *psp) 168 { 169 return psp_v13_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV); 170 } 171 172 static int psp_v13_0_bootloader_load_intf_drv(struct psp_context *psp) 173 { 174 return psp_v13_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV); 175 } 176 177 static int psp_v13_0_bootloader_load_dbg_drv(struct psp_context *psp) 178 { 179 return psp_v13_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV); 180 } 181 182 static int psp_v13_0_bootloader_load_sos(struct psp_context *psp) 183 { 184 int ret; 185 unsigned int psp_gfxdrv_command_reg = 0; 186 struct amdgpu_device *adev = psp->adev; 187 188 /* Check sOS sign of life register to confirm sys driver and sOS 189 * are already been loaded. 190 */ 191 if (psp_v13_0_is_sos_alive(psp)) 192 return 0; 193 194 ret = psp_v13_0_wait_for_bootloader(psp); 195 if (ret) 196 return ret; 197 198 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 199 200 /* Copy Secure OS binary to PSP memory */ 201 memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes); 202 203 /* Provide the PSP secure OS to bootloader */ 204 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 205 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 206 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; 207 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 208 psp_gfxdrv_command_reg); 209 210 /* there might be handshake issue with hardware which needs delay */ 211 mdelay(20); 212 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81), 213 RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81), 214 0, true); 215 216 return ret; 217 } 218 219 static int psp_v13_0_ring_init(struct psp_context *psp, 220 enum psp_ring_type ring_type) 221 { 222 int ret = 0; 223 struct psp_ring *ring; 224 struct amdgpu_device *adev = psp->adev; 225 226 ring = &psp->km_ring; 227 228 ring->ring_type = ring_type; 229 230 /* allocate 4k Page of Local Frame Buffer memory for ring */ 231 ring->ring_size = 0x1000; 232 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 233 AMDGPU_GEM_DOMAIN_VRAM, 234 &adev->firmware.rbuf, 235 &ring->ring_mem_mc_addr, 236 (void **)&ring->ring_mem); 237 if (ret) { 238 ring->ring_size = 0; 239 return ret; 240 } 241 242 return 0; 243 } 244 245 static int psp_v13_0_ring_stop(struct psp_context *psp, 246 enum psp_ring_type ring_type) 247 { 248 int ret = 0; 249 struct amdgpu_device *adev = psp->adev; 250 251 if (amdgpu_sriov_vf(adev)) { 252 /* Write the ring destroy command*/ 253 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 254 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 255 /* there might be handshake issue with hardware which needs delay */ 256 mdelay(20); 257 /* Wait for response flag (bit 31) */ 258 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 259 0x80000000, 0x80000000, false); 260 } else { 261 /* Write the ring destroy command*/ 262 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, 263 GFX_CTRL_CMD_ID_DESTROY_RINGS); 264 /* there might be handshake issue with hardware which needs delay */ 265 mdelay(20); 266 /* Wait for response flag (bit 31) */ 267 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 268 0x80000000, 0x80000000, false); 269 } 270 271 return ret; 272 } 273 274 static int psp_v13_0_ring_create(struct psp_context *psp, 275 enum psp_ring_type ring_type) 276 { 277 int ret = 0; 278 unsigned int psp_ring_reg = 0; 279 struct psp_ring *ring = &psp->km_ring; 280 struct amdgpu_device *adev = psp->adev; 281 282 if (amdgpu_sriov_vf(adev)) { 283 ret = psp_v13_0_ring_stop(psp, ring_type); 284 if (ret) { 285 DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n"); 286 return ret; 287 } 288 289 /* Write low address of the ring to C2PMSG_102 */ 290 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 291 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg); 292 /* Write high address of the ring to C2PMSG_103 */ 293 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 294 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg); 295 296 /* Write the ring initialization command to C2PMSG_101 */ 297 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 298 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 299 300 /* there might be handshake issue with hardware which needs delay */ 301 mdelay(20); 302 303 /* Wait for response flag (bit 31) in C2PMSG_101 */ 304 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 305 0x80000000, 0x8000FFFF, false); 306 307 } else { 308 /* Wait for sOS ready for ring creation */ 309 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 310 0x80000000, 0x80000000, false); 311 if (ret) { 312 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n"); 313 return ret; 314 } 315 316 /* Write low address of the ring to C2PMSG_69 */ 317 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 318 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg); 319 /* Write high address of the ring to C2PMSG_70 */ 320 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 321 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg); 322 /* Write size of ring to C2PMSG_71 */ 323 psp_ring_reg = ring->ring_size; 324 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg); 325 /* Write the ring initialization command to C2PMSG_64 */ 326 psp_ring_reg = ring_type; 327 psp_ring_reg = psp_ring_reg << 16; 328 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg); 329 330 /* there might be handshake issue with hardware which needs delay */ 331 mdelay(20); 332 333 /* Wait for response flag (bit 31) in C2PMSG_64 */ 334 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 335 0x80000000, 0x8000FFFF, false); 336 } 337 338 return ret; 339 } 340 341 static int psp_v13_0_ring_destroy(struct psp_context *psp, 342 enum psp_ring_type ring_type) 343 { 344 int ret = 0; 345 struct psp_ring *ring = &psp->km_ring; 346 struct amdgpu_device *adev = psp->adev; 347 348 ret = psp_v13_0_ring_stop(psp, ring_type); 349 if (ret) 350 DRM_ERROR("Fail to stop psp ring\n"); 351 352 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 353 &ring->ring_mem_mc_addr, 354 (void **)&ring->ring_mem); 355 356 return ret; 357 } 358 359 static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp) 360 { 361 uint32_t data; 362 struct amdgpu_device *adev = psp->adev; 363 364 if (amdgpu_sriov_vf(adev)) 365 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102); 366 else 367 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67); 368 369 return data; 370 } 371 372 static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value) 373 { 374 struct amdgpu_device *adev = psp->adev; 375 376 if (amdgpu_sriov_vf(adev)) { 377 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value); 378 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 379 GFX_CTRL_CMD_ID_CONSUME_CMD); 380 } else 381 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value); 382 } 383 384 static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr) 385 { 386 struct amdgpu_device *adev = psp->adev; 387 uint32_t reg_status; 388 int ret, i = 0; 389 390 /* 391 * LFB address which is aligned to 1MB address and has to be 392 * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P 393 * register 394 */ 395 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20)); 396 397 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 398 0x80000000, 0x80000000, false); 399 if (ret) 400 return ret; 401 402 /* Fireup interrupt so PSP can pick up the address */ 403 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16)); 404 405 /* FW load takes very long time */ 406 do { 407 msleep(1000); 408 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35); 409 410 if (reg_status & 0x80000000) 411 goto done; 412 413 } while (++i < USBC_PD_POLLING_LIMIT_S); 414 415 return -ETIME; 416 done: 417 418 if ((reg_status & 0xFFFF) != 0) { 419 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n", 420 reg_status & 0xFFFF); 421 return -EIO; 422 } 423 424 return 0; 425 } 426 427 static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver) 428 { 429 struct amdgpu_device *adev = psp->adev; 430 int ret; 431 432 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER); 433 434 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 435 0x80000000, 0x80000000, false); 436 if (!ret) 437 *fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36); 438 439 return ret; 440 } 441 442 static const struct psp_funcs psp_v13_0_funcs = { 443 .init_microcode = psp_v13_0_init_microcode, 444 .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb, 445 .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv, 446 .bootloader_load_soc_drv = psp_v13_0_bootloader_load_soc_drv, 447 .bootloader_load_intf_drv = psp_v13_0_bootloader_load_intf_drv, 448 .bootloader_load_dbg_drv = psp_v13_0_bootloader_load_dbg_drv, 449 .bootloader_load_sos = psp_v13_0_bootloader_load_sos, 450 .ring_init = psp_v13_0_ring_init, 451 .ring_create = psp_v13_0_ring_create, 452 .ring_stop = psp_v13_0_ring_stop, 453 .ring_destroy = psp_v13_0_ring_destroy, 454 .ring_get_wptr = psp_v13_0_ring_get_wptr, 455 .ring_set_wptr = psp_v13_0_ring_set_wptr, 456 .load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw, 457 .read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw 458 }; 459 460 void psp_v13_0_set_psp_funcs(struct psp_context *psp) 461 { 462 psp->funcs = &psp_v13_0_funcs; 463 } 464