1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <drm/drm_drv.h> 24 #include <linux/vmalloc.h> 25 #include "amdgpu.h" 26 #include "amdgpu_psp.h" 27 #include "amdgpu_ucode.h" 28 #include "soc15_common.h" 29 #include "psp_v13_0.h" 30 31 #include "mp/mp_13_0_2_offset.h" 32 #include "mp/mp_13_0_2_sh_mask.h" 33 34 MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin"); 35 MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin"); 36 MODULE_FIRMWARE("amdgpu/aldebaran_cap.bin"); 37 MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin"); 38 MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin"); 39 MODULE_FIRMWARE("amdgpu/psp_13_0_5_toc.bin"); 40 MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin"); 41 MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin"); 42 MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin"); 43 MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin"); 44 MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta.bin"); 45 MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin"); 46 MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin"); 47 MODULE_FIRMWARE("amdgpu/psp_13_0_10_sos.bin"); 48 49 /* For large FW files the time to complete can be very long */ 50 #define USBC_PD_POLLING_LIMIT_S 240 51 52 /* Read USB-PD from LFB */ 53 #define GFX_CMD_USB_PD_USE_LFB 0x480 54 55 /* VBIOS gfl defines */ 56 #define MBOX_READY_MASK 0x80000000 57 #define MBOX_STATUS_MASK 0x0000FFFF 58 #define MBOX_COMMAND_MASK 0x00FF0000 59 #define MBOX_READY_FLAG 0x80000000 60 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO 0x2 61 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3 62 #define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4 63 64 /* memory training timeout define */ 65 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000 66 67 static int psp_v13_0_init_microcode(struct psp_context *psp) 68 { 69 struct amdgpu_device *adev = psp->adev; 70 const char *chip_name; 71 char ucode_prefix[30]; 72 int err = 0; 73 74 switch (adev->ip_versions[MP0_HWIP][0]) { 75 case IP_VERSION(13, 0, 2): 76 chip_name = "aldebaran"; 77 break; 78 case IP_VERSION(13, 0, 1): 79 case IP_VERSION(13, 0, 3): 80 chip_name = "yellow_carp"; 81 break; 82 default: 83 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 84 chip_name = ucode_prefix; 85 break; 86 } 87 88 switch (adev->ip_versions[MP0_HWIP][0]) { 89 case IP_VERSION(13, 0, 2): 90 err = psp_init_sos_microcode(psp, chip_name); 91 if (err) 92 return err; 93 /* It's not necessary to load ras ta on Guest side */ 94 if (!amdgpu_sriov_vf(adev)) { 95 err = psp_init_ta_microcode(&adev->psp, chip_name); 96 if (err) 97 return err; 98 } 99 break; 100 case IP_VERSION(13, 0, 1): 101 case IP_VERSION(13, 0, 3): 102 case IP_VERSION(13, 0, 5): 103 case IP_VERSION(13, 0, 8): 104 err = psp_init_toc_microcode(psp, chip_name); 105 if (err) 106 return err; 107 err = psp_init_ta_microcode(psp, chip_name); 108 if (err) 109 return err; 110 break; 111 case IP_VERSION(13, 0, 0): 112 case IP_VERSION(13, 0, 7): 113 case IP_VERSION(13, 0, 10): 114 err = psp_init_sos_microcode(psp, chip_name); 115 if (err) 116 return err; 117 /* It's not necessary to load ras ta on Guest side */ 118 err = psp_init_ta_microcode(psp, chip_name); 119 if (err) 120 return err; 121 break; 122 default: 123 BUG(); 124 } 125 126 return 0; 127 } 128 129 static bool psp_v13_0_is_sos_alive(struct psp_context *psp) 130 { 131 struct amdgpu_device *adev = psp->adev; 132 uint32_t sol_reg; 133 134 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 135 136 return sol_reg != 0x0; 137 } 138 139 static int psp_v13_0_wait_for_bootloader(struct psp_context *psp) 140 { 141 struct amdgpu_device *adev = psp->adev; 142 143 int ret; 144 int retry_loop; 145 146 for (retry_loop = 0; retry_loop < 10; retry_loop++) { 147 /* Wait for bootloader to signify that is 148 ready having bit 31 of C2PMSG_35 set to 1 */ 149 ret = psp_wait_for(psp, 150 SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 151 0x80000000, 152 0x80000000, 153 false); 154 155 if (ret == 0) 156 return 0; 157 } 158 159 return ret; 160 } 161 162 static int psp_v13_0_bootloader_load_component(struct psp_context *psp, 163 struct psp_bin_desc *bin_desc, 164 enum psp_bootloader_cmd bl_cmd) 165 { 166 int ret; 167 uint32_t psp_gfxdrv_command_reg = 0; 168 struct amdgpu_device *adev = psp->adev; 169 170 /* Check tOS sign of life register to confirm sys driver and sOS 171 * are already been loaded. 172 */ 173 if (psp_v13_0_is_sos_alive(psp)) 174 return 0; 175 176 ret = psp_v13_0_wait_for_bootloader(psp); 177 if (ret) 178 return ret; 179 180 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 181 182 /* Copy PSP KDB binary to memory */ 183 memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes); 184 185 /* Provide the PSP KDB to bootloader */ 186 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 187 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 188 psp_gfxdrv_command_reg = bl_cmd; 189 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 190 psp_gfxdrv_command_reg); 191 192 ret = psp_v13_0_wait_for_bootloader(psp); 193 194 return ret; 195 } 196 197 static int psp_v13_0_bootloader_load_kdb(struct psp_context *psp) 198 { 199 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE); 200 } 201 202 static int psp_v13_0_bootloader_load_spl(struct psp_context *psp) 203 { 204 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE); 205 } 206 207 static int psp_v13_0_bootloader_load_sysdrv(struct psp_context *psp) 208 { 209 return psp_v13_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV); 210 } 211 212 static int psp_v13_0_bootloader_load_soc_drv(struct psp_context *psp) 213 { 214 return psp_v13_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV); 215 } 216 217 static int psp_v13_0_bootloader_load_intf_drv(struct psp_context *psp) 218 { 219 return psp_v13_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV); 220 } 221 222 static int psp_v13_0_bootloader_load_dbg_drv(struct psp_context *psp) 223 { 224 return psp_v13_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV); 225 } 226 227 static int psp_v13_0_bootloader_load_ras_drv(struct psp_context *psp) 228 { 229 return psp_v13_0_bootloader_load_component(psp, &psp->ras_drv, PSP_BL__LOAD_RASDRV); 230 } 231 232 233 static int psp_v13_0_bootloader_load_sos(struct psp_context *psp) 234 { 235 int ret; 236 unsigned int psp_gfxdrv_command_reg = 0; 237 struct amdgpu_device *adev = psp->adev; 238 239 /* Check sOS sign of life register to confirm sys driver and sOS 240 * are already been loaded. 241 */ 242 if (psp_v13_0_is_sos_alive(psp)) 243 return 0; 244 245 ret = psp_v13_0_wait_for_bootloader(psp); 246 if (ret) 247 return ret; 248 249 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 250 251 /* Copy Secure OS binary to PSP memory */ 252 memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes); 253 254 /* Provide the PSP secure OS to bootloader */ 255 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 256 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 257 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; 258 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 259 psp_gfxdrv_command_reg); 260 261 /* there might be handshake issue with hardware which needs delay */ 262 mdelay(20); 263 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81), 264 RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81), 265 0, true); 266 267 return ret; 268 } 269 270 static int psp_v13_0_ring_init(struct psp_context *psp, 271 enum psp_ring_type ring_type) 272 { 273 int ret = 0; 274 struct psp_ring *ring; 275 struct amdgpu_device *adev = psp->adev; 276 277 ring = &psp->km_ring; 278 279 ring->ring_type = ring_type; 280 281 /* allocate 4k Page of Local Frame Buffer memory for ring */ 282 ring->ring_size = 0x1000; 283 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 284 AMDGPU_GEM_DOMAIN_VRAM, 285 &adev->firmware.rbuf, 286 &ring->ring_mem_mc_addr, 287 (void **)&ring->ring_mem); 288 if (ret) { 289 ring->ring_size = 0; 290 return ret; 291 } 292 293 return 0; 294 } 295 296 static int psp_v13_0_ring_stop(struct psp_context *psp, 297 enum psp_ring_type ring_type) 298 { 299 int ret = 0; 300 struct amdgpu_device *adev = psp->adev; 301 302 if (amdgpu_sriov_vf(adev)) { 303 /* Write the ring destroy command*/ 304 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 305 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 306 /* there might be handshake issue with hardware which needs delay */ 307 mdelay(20); 308 /* Wait for response flag (bit 31) */ 309 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 310 0x80000000, 0x80000000, false); 311 } else { 312 /* Write the ring destroy command*/ 313 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, 314 GFX_CTRL_CMD_ID_DESTROY_RINGS); 315 /* there might be handshake issue with hardware which needs delay */ 316 mdelay(20); 317 /* Wait for response flag (bit 31) */ 318 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 319 0x80000000, 0x80000000, false); 320 } 321 322 return ret; 323 } 324 325 static int psp_v13_0_ring_create(struct psp_context *psp, 326 enum psp_ring_type ring_type) 327 { 328 int ret = 0; 329 unsigned int psp_ring_reg = 0; 330 struct psp_ring *ring = &psp->km_ring; 331 struct amdgpu_device *adev = psp->adev; 332 333 if (amdgpu_sriov_vf(adev)) { 334 ret = psp_v13_0_ring_stop(psp, ring_type); 335 if (ret) { 336 DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n"); 337 return ret; 338 } 339 340 /* Write low address of the ring to C2PMSG_102 */ 341 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 342 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg); 343 /* Write high address of the ring to C2PMSG_103 */ 344 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 345 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg); 346 347 /* Write the ring initialization command to C2PMSG_101 */ 348 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 349 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 350 351 /* there might be handshake issue with hardware which needs delay */ 352 mdelay(20); 353 354 /* Wait for response flag (bit 31) in C2PMSG_101 */ 355 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 356 0x80000000, 0x8000FFFF, false); 357 358 } else { 359 /* Wait for sOS ready for ring creation */ 360 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 361 0x80000000, 0x80000000, false); 362 if (ret) { 363 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n"); 364 return ret; 365 } 366 367 /* Write low address of the ring to C2PMSG_69 */ 368 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 369 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg); 370 /* Write high address of the ring to C2PMSG_70 */ 371 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 372 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg); 373 /* Write size of ring to C2PMSG_71 */ 374 psp_ring_reg = ring->ring_size; 375 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg); 376 /* Write the ring initialization command to C2PMSG_64 */ 377 psp_ring_reg = ring_type; 378 psp_ring_reg = psp_ring_reg << 16; 379 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg); 380 381 /* there might be handshake issue with hardware which needs delay */ 382 mdelay(20); 383 384 /* Wait for response flag (bit 31) in C2PMSG_64 */ 385 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 386 0x80000000, 0x8000FFFF, false); 387 } 388 389 return ret; 390 } 391 392 static int psp_v13_0_ring_destroy(struct psp_context *psp, 393 enum psp_ring_type ring_type) 394 { 395 int ret = 0; 396 struct psp_ring *ring = &psp->km_ring; 397 struct amdgpu_device *adev = psp->adev; 398 399 ret = psp_v13_0_ring_stop(psp, ring_type); 400 if (ret) 401 DRM_ERROR("Fail to stop psp ring\n"); 402 403 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 404 &ring->ring_mem_mc_addr, 405 (void **)&ring->ring_mem); 406 407 return ret; 408 } 409 410 static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp) 411 { 412 uint32_t data; 413 struct amdgpu_device *adev = psp->adev; 414 415 if (amdgpu_sriov_vf(adev)) 416 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102); 417 else 418 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67); 419 420 return data; 421 } 422 423 static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value) 424 { 425 struct amdgpu_device *adev = psp->adev; 426 427 if (amdgpu_sriov_vf(adev)) { 428 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value); 429 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 430 GFX_CTRL_CMD_ID_CONSUME_CMD); 431 } else 432 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value); 433 } 434 435 static int psp_v13_0_memory_training_send_msg(struct psp_context *psp, int msg) 436 { 437 int ret; 438 int i; 439 uint32_t data_32; 440 int max_wait; 441 struct amdgpu_device *adev = psp->adev; 442 443 data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20); 444 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, data_32); 445 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, msg); 446 447 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout; 448 for (i = 0; i < max_wait; i++) { 449 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 450 0x80000000, 0x80000000, false); 451 if (ret == 0) 452 break; 453 } 454 if (i < max_wait) 455 ret = 0; 456 else 457 ret = -ETIME; 458 459 dev_dbg(adev->dev, "training %s %s, cost %d @ %d ms\n", 460 (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long", 461 (ret == 0) ? "succeed" : "failed", 462 i, adev->usec_timeout/1000); 463 return ret; 464 } 465 466 467 static int psp_v13_0_memory_training(struct psp_context *psp, uint32_t ops) 468 { 469 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 470 uint32_t *pcache = (uint32_t *)ctx->sys_cache; 471 struct amdgpu_device *adev = psp->adev; 472 uint32_t p2c_header[4]; 473 uint32_t sz; 474 void *buf; 475 int ret, idx; 476 477 if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) { 478 dev_dbg(adev->dev, "Memory training is not supported.\n"); 479 return 0; 480 } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) { 481 dev_err(adev->dev, "Memory training initialization failure.\n"); 482 return -EINVAL; 483 } 484 485 if (psp_v13_0_is_sos_alive(psp)) { 486 dev_dbg(adev->dev, "SOS is alive, skip memory training.\n"); 487 return 0; 488 } 489 490 amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false); 491 dev_dbg(adev->dev, "sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n", 492 pcache[0], pcache[1], pcache[2], pcache[3], 493 p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]); 494 495 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 496 dev_dbg(adev->dev, "Short training depends on restore.\n"); 497 ops |= PSP_MEM_TRAIN_RESTORE; 498 } 499 500 if ((ops & PSP_MEM_TRAIN_RESTORE) && 501 pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 502 dev_dbg(adev->dev, "sys_cache[0] is invalid, restore depends on save.\n"); 503 ops |= PSP_MEM_TRAIN_SAVE; 504 } 505 506 if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 507 !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 508 pcache[3] == p2c_header[3])) { 509 dev_dbg(adev->dev, "sys_cache is invalid or out-of-date, need save training data to sys_cache.\n"); 510 ops |= PSP_MEM_TRAIN_SAVE; 511 } 512 513 if ((ops & PSP_MEM_TRAIN_SAVE) && 514 p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 515 dev_dbg(adev->dev, "p2c_header[0] is invalid, save depends on long training.\n"); 516 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG; 517 } 518 519 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 520 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG; 521 ops |= PSP_MEM_TRAIN_SAVE; 522 } 523 524 dev_dbg(adev->dev, "Memory training ops:%x.\n", ops); 525 526 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 527 /* 528 * Long training will encroach a certain amount on the bottom of VRAM; 529 * save the content from the bottom of VRAM to system memory 530 * before training, and restore it after training to avoid 531 * VRAM corruption. 532 */ 533 sz = GDDR6_MEM_TRAINING_ENCROACHED_SIZE; 534 535 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) { 536 dev_err(adev->dev, "visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n", 537 adev->gmc.visible_vram_size, 538 adev->mman.aper_base_kaddr); 539 return -EINVAL; 540 } 541 542 buf = vmalloc(sz); 543 if (!buf) { 544 dev_err(adev->dev, "failed to allocate system memory.\n"); 545 return -ENOMEM; 546 } 547 548 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 549 memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz); 550 ret = psp_v13_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN); 551 if (ret) { 552 DRM_ERROR("Send long training msg failed.\n"); 553 vfree(buf); 554 drm_dev_exit(idx); 555 return ret; 556 } 557 558 memcpy_toio(adev->mman.aper_base_kaddr, buf, sz); 559 adev->hdp.funcs->flush_hdp(adev, NULL); 560 vfree(buf); 561 drm_dev_exit(idx); 562 } else { 563 vfree(buf); 564 return -ENODEV; 565 } 566 } 567 568 if (ops & PSP_MEM_TRAIN_SAVE) { 569 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false); 570 } 571 572 if (ops & PSP_MEM_TRAIN_RESTORE) { 573 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true); 574 } 575 576 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 577 ret = psp_v13_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ? 578 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN); 579 if (ret) { 580 dev_err(adev->dev, "send training msg failed.\n"); 581 return ret; 582 } 583 } 584 ctx->training_cnt++; 585 return 0; 586 } 587 588 static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr) 589 { 590 struct amdgpu_device *adev = psp->adev; 591 uint32_t reg_status; 592 int ret, i = 0; 593 594 /* 595 * LFB address which is aligned to 1MB address and has to be 596 * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P 597 * register 598 */ 599 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20)); 600 601 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 602 0x80000000, 0x80000000, false); 603 if (ret) 604 return ret; 605 606 /* Fireup interrupt so PSP can pick up the address */ 607 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16)); 608 609 /* FW load takes very long time */ 610 do { 611 msleep(1000); 612 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35); 613 614 if (reg_status & 0x80000000) 615 goto done; 616 617 } while (++i < USBC_PD_POLLING_LIMIT_S); 618 619 return -ETIME; 620 done: 621 622 if ((reg_status & 0xFFFF) != 0) { 623 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n", 624 reg_status & 0xFFFF); 625 return -EIO; 626 } 627 628 return 0; 629 } 630 631 static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver) 632 { 633 struct amdgpu_device *adev = psp->adev; 634 int ret; 635 636 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER); 637 638 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 639 0x80000000, 0x80000000, false); 640 if (!ret) 641 *fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36); 642 643 return ret; 644 } 645 646 static int psp_v13_0_exec_spi_cmd(struct psp_context *psp, int cmd) 647 { 648 uint32_t reg_status = 0, reg_val = 0; 649 struct amdgpu_device *adev = psp->adev; 650 int ret; 651 652 /* clear MBX ready (MBOX_READY_MASK bit is 0) and set update command */ 653 reg_val |= (cmd << 16); 654 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115, reg_val); 655 656 /* Ring the doorbell */ 657 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_73, 1); 658 659 if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE) 660 return 0; 661 662 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 663 MBOX_READY_FLAG, MBOX_READY_MASK, false); 664 if (ret) { 665 dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret); 666 return ret; 667 } 668 669 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115); 670 if ((reg_status & 0xFFFF) != 0) { 671 dev_err(adev->dev, "SPI cmd %x failed, fail status = %04x\n", 672 cmd, reg_status & 0xFFFF); 673 return -EIO; 674 } 675 676 return 0; 677 } 678 679 static int psp_v13_0_update_spirom(struct psp_context *psp, 680 uint64_t fw_pri_mc_addr) 681 { 682 struct amdgpu_device *adev = psp->adev; 683 int ret; 684 685 /* Confirm PSP is ready to start */ 686 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 687 MBOX_READY_FLAG, MBOX_READY_MASK, false); 688 if (ret) { 689 dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret); 690 return ret; 691 } 692 693 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr)); 694 695 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO); 696 if (ret) 697 return ret; 698 699 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr)); 700 701 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI); 702 if (ret) 703 return ret; 704 705 psp->vbflash_done = true; 706 707 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE); 708 if (ret) 709 return ret; 710 711 return 0; 712 } 713 714 static int psp_v13_0_vbflash_status(struct psp_context *psp) 715 { 716 struct amdgpu_device *adev = psp->adev; 717 718 return RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115); 719 } 720 721 static const struct psp_funcs psp_v13_0_funcs = { 722 .init_microcode = psp_v13_0_init_microcode, 723 .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb, 724 .bootloader_load_spl = psp_v13_0_bootloader_load_spl, 725 .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv, 726 .bootloader_load_soc_drv = psp_v13_0_bootloader_load_soc_drv, 727 .bootloader_load_intf_drv = psp_v13_0_bootloader_load_intf_drv, 728 .bootloader_load_dbg_drv = psp_v13_0_bootloader_load_dbg_drv, 729 .bootloader_load_ras_drv = psp_v13_0_bootloader_load_ras_drv, 730 .bootloader_load_sos = psp_v13_0_bootloader_load_sos, 731 .ring_init = psp_v13_0_ring_init, 732 .ring_create = psp_v13_0_ring_create, 733 .ring_stop = psp_v13_0_ring_stop, 734 .ring_destroy = psp_v13_0_ring_destroy, 735 .ring_get_wptr = psp_v13_0_ring_get_wptr, 736 .ring_set_wptr = psp_v13_0_ring_set_wptr, 737 .mem_training = psp_v13_0_memory_training, 738 .load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw, 739 .read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw, 740 .update_spirom = psp_v13_0_update_spirom, 741 .vbflash_stat = psp_v13_0_vbflash_status 742 }; 743 744 void psp_v13_0_set_psp_funcs(struct psp_context *psp) 745 { 746 psp->funcs = &psp_v13_0_funcs; 747 } 748