1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <drm/drm_drv.h> 24 #include <linux/vmalloc.h> 25 #include "amdgpu.h" 26 #include "amdgpu_psp.h" 27 #include "amdgpu_ucode.h" 28 #include "soc15_common.h" 29 #include "psp_v13_0.h" 30 31 #include "mp/mp_13_0_2_offset.h" 32 #include "mp/mp_13_0_2_sh_mask.h" 33 34 MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin"); 35 MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin"); 36 MODULE_FIRMWARE("amdgpu/aldebaran_cap.bin"); 37 MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin"); 38 MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin"); 39 MODULE_FIRMWARE("amdgpu/psp_13_0_5_toc.bin"); 40 MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin"); 41 MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin"); 42 MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin"); 43 MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin"); 44 MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta.bin"); 45 MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin"); 46 MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin"); 47 MODULE_FIRMWARE("amdgpu/psp_13_0_10_sos.bin"); 48 MODULE_FIRMWARE("amdgpu/psp_13_0_10_ta.bin"); 49 MODULE_FIRMWARE("amdgpu/psp_13_0_11_toc.bin"); 50 MODULE_FIRMWARE("amdgpu/psp_13_0_11_ta.bin"); 51 MODULE_FIRMWARE("amdgpu/psp_13_0_6_sos.bin"); 52 MODULE_FIRMWARE("amdgpu/psp_13_0_6_ta.bin"); 53 54 /* For large FW files the time to complete can be very long */ 55 #define USBC_PD_POLLING_LIMIT_S 240 56 57 /* Read USB-PD from LFB */ 58 #define GFX_CMD_USB_PD_USE_LFB 0x480 59 60 /* VBIOS gfl defines */ 61 #define MBOX_READY_MASK 0x80000000 62 #define MBOX_STATUS_MASK 0x0000FFFF 63 #define MBOX_COMMAND_MASK 0x00FF0000 64 #define MBOX_READY_FLAG 0x80000000 65 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO 0x2 66 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3 67 #define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4 68 69 /* memory training timeout define */ 70 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000 71 72 static int psp_v13_0_init_microcode(struct psp_context *psp) 73 { 74 struct amdgpu_device *adev = psp->adev; 75 char ucode_prefix[30]; 76 int err = 0; 77 78 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 79 80 switch (adev->ip_versions[MP0_HWIP][0]) { 81 case IP_VERSION(13, 0, 2): 82 err = psp_init_sos_microcode(psp, ucode_prefix); 83 if (err) 84 return err; 85 /* It's not necessary to load ras ta on Guest side */ 86 if (!amdgpu_sriov_vf(adev)) { 87 err = psp_init_ta_microcode(psp, ucode_prefix); 88 if (err) 89 return err; 90 } 91 break; 92 case IP_VERSION(13, 0, 1): 93 case IP_VERSION(13, 0, 3): 94 case IP_VERSION(13, 0, 5): 95 case IP_VERSION(13, 0, 8): 96 case IP_VERSION(13, 0, 11): 97 err = psp_init_toc_microcode(psp, ucode_prefix); 98 if (err) 99 return err; 100 err = psp_init_ta_microcode(psp, ucode_prefix); 101 if (err) 102 return err; 103 break; 104 case IP_VERSION(13, 0, 0): 105 case IP_VERSION(13, 0, 6): 106 case IP_VERSION(13, 0, 7): 107 case IP_VERSION(13, 0, 10): 108 err = psp_init_sos_microcode(psp, ucode_prefix); 109 if (err) 110 return err; 111 /* It's not necessary to load ras ta on Guest side */ 112 err = psp_init_ta_microcode(psp, ucode_prefix); 113 if (err) 114 return err; 115 break; 116 default: 117 BUG(); 118 } 119 120 return 0; 121 } 122 123 static bool psp_v13_0_is_sos_alive(struct psp_context *psp) 124 { 125 struct amdgpu_device *adev = psp->adev; 126 uint32_t sol_reg; 127 128 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 129 130 return sol_reg != 0x0; 131 } 132 133 static int psp_v13_0_wait_for_bootloader(struct psp_context *psp) 134 { 135 struct amdgpu_device *adev = psp->adev; 136 137 int ret; 138 int retry_loop; 139 140 /* Wait for bootloader to signify that it is ready having bit 31 of 141 * C2PMSG_35 set to 1. All other bits are expected to be cleared. 142 * If there is an error in processing command, bits[7:0] will be set. 143 * This is applicable for PSP v13.0.6 and newer. 144 */ 145 for (retry_loop = 0; retry_loop < 10; retry_loop++) { 146 ret = psp_wait_for( 147 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 148 0x80000000, 0xffffffff, false); 149 150 if (ret == 0) 151 return 0; 152 } 153 154 return ret; 155 } 156 157 static int psp_v13_0_bootloader_load_component(struct psp_context *psp, 158 struct psp_bin_desc *bin_desc, 159 enum psp_bootloader_cmd bl_cmd) 160 { 161 int ret; 162 uint32_t psp_gfxdrv_command_reg = 0; 163 struct amdgpu_device *adev = psp->adev; 164 165 /* Check tOS sign of life register to confirm sys driver and sOS 166 * are already been loaded. 167 */ 168 if (psp_v13_0_is_sos_alive(psp)) 169 return 0; 170 171 ret = psp_v13_0_wait_for_bootloader(psp); 172 if (ret) 173 return ret; 174 175 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 176 177 /* Copy PSP KDB binary to memory */ 178 memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes); 179 180 /* Provide the PSP KDB to bootloader */ 181 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 182 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 183 psp_gfxdrv_command_reg = bl_cmd; 184 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 185 psp_gfxdrv_command_reg); 186 187 ret = psp_v13_0_wait_for_bootloader(psp); 188 189 return ret; 190 } 191 192 static int psp_v13_0_bootloader_load_kdb(struct psp_context *psp) 193 { 194 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE); 195 } 196 197 static int psp_v13_0_bootloader_load_spl(struct psp_context *psp) 198 { 199 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE); 200 } 201 202 static int psp_v13_0_bootloader_load_sysdrv(struct psp_context *psp) 203 { 204 return psp_v13_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV); 205 } 206 207 static int psp_v13_0_bootloader_load_soc_drv(struct psp_context *psp) 208 { 209 return psp_v13_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV); 210 } 211 212 static int psp_v13_0_bootloader_load_intf_drv(struct psp_context *psp) 213 { 214 return psp_v13_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV); 215 } 216 217 static int psp_v13_0_bootloader_load_dbg_drv(struct psp_context *psp) 218 { 219 return psp_v13_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV); 220 } 221 222 static int psp_v13_0_bootloader_load_ras_drv(struct psp_context *psp) 223 { 224 return psp_v13_0_bootloader_load_component(psp, &psp->ras_drv, PSP_BL__LOAD_RASDRV); 225 } 226 227 228 static int psp_v13_0_bootloader_load_sos(struct psp_context *psp) 229 { 230 int ret; 231 unsigned int psp_gfxdrv_command_reg = 0; 232 struct amdgpu_device *adev = psp->adev; 233 234 /* Check sOS sign of life register to confirm sys driver and sOS 235 * are already been loaded. 236 */ 237 if (psp_v13_0_is_sos_alive(psp)) 238 return 0; 239 240 ret = psp_v13_0_wait_for_bootloader(psp); 241 if (ret) 242 return ret; 243 244 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 245 246 /* Copy Secure OS binary to PSP memory */ 247 memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes); 248 249 /* Provide the PSP secure OS to bootloader */ 250 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 251 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 252 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; 253 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 254 psp_gfxdrv_command_reg); 255 256 /* there might be handshake issue with hardware which needs delay */ 257 mdelay(20); 258 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81), 259 RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81), 260 0, true); 261 262 return ret; 263 } 264 265 static int psp_v13_0_ring_stop(struct psp_context *psp, 266 enum psp_ring_type ring_type) 267 { 268 int ret = 0; 269 struct amdgpu_device *adev = psp->adev; 270 271 if (amdgpu_sriov_vf(adev)) { 272 /* Write the ring destroy command*/ 273 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 274 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 275 /* there might be handshake issue with hardware which needs delay */ 276 mdelay(20); 277 /* Wait for response flag (bit 31) */ 278 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 279 0x80000000, 0x80000000, false); 280 } else { 281 /* Write the ring destroy command*/ 282 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, 283 GFX_CTRL_CMD_ID_DESTROY_RINGS); 284 /* there might be handshake issue with hardware which needs delay */ 285 mdelay(20); 286 /* Wait for response flag (bit 31) */ 287 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 288 0x80000000, 0x80000000, false); 289 } 290 291 return ret; 292 } 293 294 static int psp_v13_0_ring_create(struct psp_context *psp, 295 enum psp_ring_type ring_type) 296 { 297 int ret = 0; 298 unsigned int psp_ring_reg = 0; 299 struct psp_ring *ring = &psp->km_ring; 300 struct amdgpu_device *adev = psp->adev; 301 302 if (amdgpu_sriov_vf(adev)) { 303 ret = psp_v13_0_ring_stop(psp, ring_type); 304 if (ret) { 305 DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n"); 306 return ret; 307 } 308 309 /* Write low address of the ring to C2PMSG_102 */ 310 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 311 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg); 312 /* Write high address of the ring to C2PMSG_103 */ 313 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 314 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg); 315 316 /* Write the ring initialization command to C2PMSG_101 */ 317 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 318 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 319 320 /* there might be handshake issue with hardware which needs delay */ 321 mdelay(20); 322 323 /* Wait for response flag (bit 31) in C2PMSG_101 */ 324 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 325 0x80000000, 0x8000FFFF, false); 326 327 } else { 328 /* Wait for sOS ready for ring creation */ 329 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 330 0x80000000, 0x80000000, false); 331 if (ret) { 332 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n"); 333 return ret; 334 } 335 336 /* Write low address of the ring to C2PMSG_69 */ 337 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 338 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg); 339 /* Write high address of the ring to C2PMSG_70 */ 340 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 341 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg); 342 /* Write size of ring to C2PMSG_71 */ 343 psp_ring_reg = ring->ring_size; 344 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg); 345 /* Write the ring initialization command to C2PMSG_64 */ 346 psp_ring_reg = ring_type; 347 psp_ring_reg = psp_ring_reg << 16; 348 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg); 349 350 /* there might be handshake issue with hardware which needs delay */ 351 mdelay(20); 352 353 /* Wait for response flag (bit 31) in C2PMSG_64 */ 354 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 355 0x80000000, 0x8000FFFF, false); 356 } 357 358 return ret; 359 } 360 361 static int psp_v13_0_ring_destroy(struct psp_context *psp, 362 enum psp_ring_type ring_type) 363 { 364 int ret = 0; 365 struct psp_ring *ring = &psp->km_ring; 366 struct amdgpu_device *adev = psp->adev; 367 368 ret = psp_v13_0_ring_stop(psp, ring_type); 369 if (ret) 370 DRM_ERROR("Fail to stop psp ring\n"); 371 372 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 373 &ring->ring_mem_mc_addr, 374 (void **)&ring->ring_mem); 375 376 return ret; 377 } 378 379 static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp) 380 { 381 uint32_t data; 382 struct amdgpu_device *adev = psp->adev; 383 384 if (amdgpu_sriov_vf(adev)) 385 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102); 386 else 387 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67); 388 389 return data; 390 } 391 392 static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value) 393 { 394 struct amdgpu_device *adev = psp->adev; 395 396 if (amdgpu_sriov_vf(adev)) { 397 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value); 398 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 399 GFX_CTRL_CMD_ID_CONSUME_CMD); 400 } else 401 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value); 402 } 403 404 static int psp_v13_0_memory_training_send_msg(struct psp_context *psp, int msg) 405 { 406 int ret; 407 int i; 408 uint32_t data_32; 409 int max_wait; 410 struct amdgpu_device *adev = psp->adev; 411 412 data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20); 413 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, data_32); 414 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, msg); 415 416 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout; 417 for (i = 0; i < max_wait; i++) { 418 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 419 0x80000000, 0x80000000, false); 420 if (ret == 0) 421 break; 422 } 423 if (i < max_wait) 424 ret = 0; 425 else 426 ret = -ETIME; 427 428 dev_dbg(adev->dev, "training %s %s, cost %d @ %d ms\n", 429 (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long", 430 (ret == 0) ? "succeed" : "failed", 431 i, adev->usec_timeout/1000); 432 return ret; 433 } 434 435 436 static int psp_v13_0_memory_training(struct psp_context *psp, uint32_t ops) 437 { 438 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 439 uint32_t *pcache = (uint32_t *)ctx->sys_cache; 440 struct amdgpu_device *adev = psp->adev; 441 uint32_t p2c_header[4]; 442 uint32_t sz; 443 void *buf; 444 int ret, idx; 445 446 if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) { 447 dev_dbg(adev->dev, "Memory training is not supported.\n"); 448 return 0; 449 } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) { 450 dev_err(adev->dev, "Memory training initialization failure.\n"); 451 return -EINVAL; 452 } 453 454 if (psp_v13_0_is_sos_alive(psp)) { 455 dev_dbg(adev->dev, "SOS is alive, skip memory training.\n"); 456 return 0; 457 } 458 459 amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false); 460 dev_dbg(adev->dev, "sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n", 461 pcache[0], pcache[1], pcache[2], pcache[3], 462 p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]); 463 464 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 465 dev_dbg(adev->dev, "Short training depends on restore.\n"); 466 ops |= PSP_MEM_TRAIN_RESTORE; 467 } 468 469 if ((ops & PSP_MEM_TRAIN_RESTORE) && 470 pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 471 dev_dbg(adev->dev, "sys_cache[0] is invalid, restore depends on save.\n"); 472 ops |= PSP_MEM_TRAIN_SAVE; 473 } 474 475 if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 476 !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 477 pcache[3] == p2c_header[3])) { 478 dev_dbg(adev->dev, "sys_cache is invalid or out-of-date, need save training data to sys_cache.\n"); 479 ops |= PSP_MEM_TRAIN_SAVE; 480 } 481 482 if ((ops & PSP_MEM_TRAIN_SAVE) && 483 p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 484 dev_dbg(adev->dev, "p2c_header[0] is invalid, save depends on long training.\n"); 485 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG; 486 } 487 488 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 489 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG; 490 ops |= PSP_MEM_TRAIN_SAVE; 491 } 492 493 dev_dbg(adev->dev, "Memory training ops:%x.\n", ops); 494 495 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 496 /* 497 * Long training will encroach a certain amount on the bottom of VRAM; 498 * save the content from the bottom of VRAM to system memory 499 * before training, and restore it after training to avoid 500 * VRAM corruption. 501 */ 502 sz = GDDR6_MEM_TRAINING_ENCROACHED_SIZE; 503 504 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) { 505 dev_err(adev->dev, "visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n", 506 adev->gmc.visible_vram_size, 507 adev->mman.aper_base_kaddr); 508 return -EINVAL; 509 } 510 511 buf = vmalloc(sz); 512 if (!buf) { 513 dev_err(adev->dev, "failed to allocate system memory.\n"); 514 return -ENOMEM; 515 } 516 517 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 518 memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz); 519 ret = psp_v13_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN); 520 if (ret) { 521 DRM_ERROR("Send long training msg failed.\n"); 522 vfree(buf); 523 drm_dev_exit(idx); 524 return ret; 525 } 526 527 memcpy_toio(adev->mman.aper_base_kaddr, buf, sz); 528 adev->hdp.funcs->flush_hdp(adev, NULL); 529 vfree(buf); 530 drm_dev_exit(idx); 531 } else { 532 vfree(buf); 533 return -ENODEV; 534 } 535 } 536 537 if (ops & PSP_MEM_TRAIN_SAVE) { 538 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false); 539 } 540 541 if (ops & PSP_MEM_TRAIN_RESTORE) { 542 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true); 543 } 544 545 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 546 ret = psp_v13_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ? 547 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN); 548 if (ret) { 549 dev_err(adev->dev, "send training msg failed.\n"); 550 return ret; 551 } 552 } 553 ctx->training_cnt++; 554 return 0; 555 } 556 557 static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr) 558 { 559 struct amdgpu_device *adev = psp->adev; 560 uint32_t reg_status; 561 int ret, i = 0; 562 563 /* 564 * LFB address which is aligned to 1MB address and has to be 565 * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P 566 * register 567 */ 568 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20)); 569 570 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 571 0x80000000, 0x80000000, false); 572 if (ret) 573 return ret; 574 575 /* Fireup interrupt so PSP can pick up the address */ 576 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16)); 577 578 /* FW load takes very long time */ 579 do { 580 msleep(1000); 581 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35); 582 583 if (reg_status & 0x80000000) 584 goto done; 585 586 } while (++i < USBC_PD_POLLING_LIMIT_S); 587 588 return -ETIME; 589 done: 590 591 if ((reg_status & 0xFFFF) != 0) { 592 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n", 593 reg_status & 0xFFFF); 594 return -EIO; 595 } 596 597 return 0; 598 } 599 600 static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver) 601 { 602 struct amdgpu_device *adev = psp->adev; 603 int ret; 604 605 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER); 606 607 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 608 0x80000000, 0x80000000, false); 609 if (!ret) 610 *fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36); 611 612 return ret; 613 } 614 615 static int psp_v13_0_exec_spi_cmd(struct psp_context *psp, int cmd) 616 { 617 uint32_t reg_status = 0, reg_val = 0; 618 struct amdgpu_device *adev = psp->adev; 619 int ret; 620 621 /* clear MBX ready (MBOX_READY_MASK bit is 0) and set update command */ 622 reg_val |= (cmd << 16); 623 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115, reg_val); 624 625 /* Ring the doorbell */ 626 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_73, 1); 627 628 if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE) 629 ret = psp_wait_for_spirom_update(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 630 MBOX_READY_FLAG, MBOX_READY_MASK, PSP_SPIROM_UPDATE_TIMEOUT); 631 else 632 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 633 MBOX_READY_FLAG, MBOX_READY_MASK, false); 634 if (ret) { 635 dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret); 636 return ret; 637 } 638 639 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115); 640 if ((reg_status & 0xFFFF) != 0) { 641 dev_err(adev->dev, "SPI cmd %x failed, fail status = %04x\n", 642 cmd, reg_status & 0xFFFF); 643 return -EIO; 644 } 645 646 return 0; 647 } 648 649 static int psp_v13_0_update_spirom(struct psp_context *psp, 650 uint64_t fw_pri_mc_addr) 651 { 652 struct amdgpu_device *adev = psp->adev; 653 int ret; 654 655 /* Confirm PSP is ready to start */ 656 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 657 MBOX_READY_FLAG, MBOX_READY_MASK, false); 658 if (ret) { 659 dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret); 660 return ret; 661 } 662 663 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr)); 664 665 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO); 666 if (ret) 667 return ret; 668 669 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr)); 670 671 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI); 672 if (ret) 673 return ret; 674 675 psp->vbflash_done = true; 676 677 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE); 678 if (ret) 679 return ret; 680 681 return 0; 682 } 683 684 static int psp_v13_0_vbflash_status(struct psp_context *psp) 685 { 686 struct amdgpu_device *adev = psp->adev; 687 688 return RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115); 689 } 690 691 static const struct psp_funcs psp_v13_0_funcs = { 692 .init_microcode = psp_v13_0_init_microcode, 693 .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb, 694 .bootloader_load_spl = psp_v13_0_bootloader_load_spl, 695 .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv, 696 .bootloader_load_soc_drv = psp_v13_0_bootloader_load_soc_drv, 697 .bootloader_load_intf_drv = psp_v13_0_bootloader_load_intf_drv, 698 .bootloader_load_dbg_drv = psp_v13_0_bootloader_load_dbg_drv, 699 .bootloader_load_ras_drv = psp_v13_0_bootloader_load_ras_drv, 700 .bootloader_load_sos = psp_v13_0_bootloader_load_sos, 701 .ring_create = psp_v13_0_ring_create, 702 .ring_stop = psp_v13_0_ring_stop, 703 .ring_destroy = psp_v13_0_ring_destroy, 704 .ring_get_wptr = psp_v13_0_ring_get_wptr, 705 .ring_set_wptr = psp_v13_0_ring_set_wptr, 706 .mem_training = psp_v13_0_memory_training, 707 .load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw, 708 .read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw, 709 .update_spirom = psp_v13_0_update_spirom, 710 .vbflash_stat = psp_v13_0_vbflash_status 711 }; 712 713 void psp_v13_0_set_psp_funcs(struct psp_context *psp) 714 { 715 psp->funcs = &psp_v13_0_funcs; 716 } 717