1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <drm/drm_drv.h> 24 #include <linux/vmalloc.h> 25 #include "amdgpu.h" 26 #include "amdgpu_psp.h" 27 #include "amdgpu_ucode.h" 28 #include "soc15_common.h" 29 #include "psp_v13_0.h" 30 31 #include "mp/mp_13_0_2_offset.h" 32 #include "mp/mp_13_0_2_sh_mask.h" 33 34 MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin"); 35 MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin"); 36 MODULE_FIRMWARE("amdgpu/aldebaran_cap.bin"); 37 MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin"); 38 MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin"); 39 MODULE_FIRMWARE("amdgpu/psp_13_0_5_toc.bin"); 40 MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin"); 41 MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin"); 42 MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin"); 43 MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin"); 44 MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta.bin"); 45 MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin"); 46 MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin"); 47 MODULE_FIRMWARE("amdgpu/psp_13_0_10_sos.bin"); 48 MODULE_FIRMWARE("amdgpu/psp_13_0_10_ta.bin"); 49 MODULE_FIRMWARE("amdgpu/psp_13_0_11_toc.bin"); 50 MODULE_FIRMWARE("amdgpu/psp_13_0_11_ta.bin"); 51 MODULE_FIRMWARE("amdgpu/psp_13_0_6_sos.bin"); 52 MODULE_FIRMWARE("amdgpu/psp_13_0_6_ta.bin"); 53 MODULE_FIRMWARE("amdgpu/psp_14_0_0_toc.bin"); 54 MODULE_FIRMWARE("amdgpu/psp_14_0_0_ta.bin"); 55 56 /* For large FW files the time to complete can be very long */ 57 #define USBC_PD_POLLING_LIMIT_S 240 58 59 /* Read USB-PD from LFB */ 60 #define GFX_CMD_USB_PD_USE_LFB 0x480 61 62 /* VBIOS gfl defines */ 63 #define MBOX_READY_MASK 0x80000000 64 #define MBOX_STATUS_MASK 0x0000FFFF 65 #define MBOX_COMMAND_MASK 0x00FF0000 66 #define MBOX_READY_FLAG 0x80000000 67 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO 0x2 68 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3 69 #define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4 70 71 /* memory training timeout define */ 72 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000 73 74 static int psp_v13_0_init_microcode(struct psp_context *psp) 75 { 76 struct amdgpu_device *adev = psp->adev; 77 char ucode_prefix[30]; 78 int err = 0; 79 80 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 81 82 switch (adev->ip_versions[MP0_HWIP][0]) { 83 case IP_VERSION(13, 0, 2): 84 err = psp_init_sos_microcode(psp, ucode_prefix); 85 if (err) 86 return err; 87 /* It's not necessary to load ras ta on Guest side */ 88 if (!amdgpu_sriov_vf(adev)) { 89 err = psp_init_ta_microcode(psp, ucode_prefix); 90 if (err) 91 return err; 92 } 93 break; 94 case IP_VERSION(13, 0, 1): 95 case IP_VERSION(13, 0, 3): 96 case IP_VERSION(13, 0, 5): 97 case IP_VERSION(13, 0, 8): 98 case IP_VERSION(13, 0, 11): 99 case IP_VERSION(14, 0, 0): 100 err = psp_init_toc_microcode(psp, ucode_prefix); 101 if (err) 102 return err; 103 err = psp_init_ta_microcode(psp, ucode_prefix); 104 if (err) 105 return err; 106 break; 107 case IP_VERSION(13, 0, 0): 108 case IP_VERSION(13, 0, 6): 109 case IP_VERSION(13, 0, 7): 110 case IP_VERSION(13, 0, 10): 111 err = psp_init_sos_microcode(psp, ucode_prefix); 112 if (err) 113 return err; 114 /* It's not necessary to load ras ta on Guest side */ 115 err = psp_init_ta_microcode(psp, ucode_prefix); 116 if (err) 117 return err; 118 break; 119 default: 120 BUG(); 121 } 122 123 return 0; 124 } 125 126 static bool psp_v13_0_is_sos_alive(struct psp_context *psp) 127 { 128 struct amdgpu_device *adev = psp->adev; 129 uint32_t sol_reg; 130 131 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 132 133 return sol_reg != 0x0; 134 } 135 136 static int psp_v13_0_wait_for_vmbx_ready(struct psp_context *psp) 137 { 138 struct amdgpu_device *adev = psp->adev; 139 int retry_loop, ret; 140 141 for (retry_loop = 0; retry_loop < 70; retry_loop++) { 142 /* Wait for bootloader to signify that is 143 ready having bit 31 of C2PMSG_33 set to 1 */ 144 ret = psp_wait_for( 145 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_33), 146 0x80000000, 0xffffffff, false); 147 148 if (ret == 0) 149 break; 150 } 151 152 if (ret) 153 dev_warn(adev->dev, "Bootloader wait timed out"); 154 155 return ret; 156 } 157 158 static int psp_v13_0_wait_for_bootloader(struct psp_context *psp) 159 { 160 struct amdgpu_device *adev = psp->adev; 161 int retry_loop, ret; 162 163 /* Wait for bootloader to signify that it is ready having bit 31 of 164 * C2PMSG_35 set to 1. All other bits are expected to be cleared. 165 * If there is an error in processing command, bits[7:0] will be set. 166 * This is applicable for PSP v13.0.6 and newer. 167 */ 168 for (retry_loop = 0; retry_loop < 10; retry_loop++) { 169 ret = psp_wait_for( 170 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 171 0x80000000, 0xffffffff, false); 172 173 if (ret == 0) 174 return 0; 175 } 176 177 return ret; 178 } 179 180 static int psp_v13_0_wait_for_bootloader_steady_state(struct psp_context *psp) 181 { 182 struct amdgpu_device *adev = psp->adev; 183 184 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 6)) { 185 psp_v13_0_wait_for_vmbx_ready(psp); 186 187 return psp_v13_0_wait_for_bootloader(psp); 188 } 189 190 return 0; 191 } 192 193 static int psp_v13_0_bootloader_load_component(struct psp_context *psp, 194 struct psp_bin_desc *bin_desc, 195 enum psp_bootloader_cmd bl_cmd) 196 { 197 int ret; 198 uint32_t psp_gfxdrv_command_reg = 0; 199 struct amdgpu_device *adev = psp->adev; 200 201 /* Check tOS sign of life register to confirm sys driver and sOS 202 * are already been loaded. 203 */ 204 if (psp_v13_0_is_sos_alive(psp)) 205 return 0; 206 207 ret = psp_v13_0_wait_for_bootloader(psp); 208 if (ret) 209 return ret; 210 211 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 212 213 /* Copy PSP KDB binary to memory */ 214 memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes); 215 216 /* Provide the PSP KDB to bootloader */ 217 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 218 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 219 psp_gfxdrv_command_reg = bl_cmd; 220 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 221 psp_gfxdrv_command_reg); 222 223 ret = psp_v13_0_wait_for_bootloader(psp); 224 225 return ret; 226 } 227 228 static int psp_v13_0_bootloader_load_kdb(struct psp_context *psp) 229 { 230 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE); 231 } 232 233 static int psp_v13_0_bootloader_load_spl(struct psp_context *psp) 234 { 235 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE); 236 } 237 238 static int psp_v13_0_bootloader_load_sysdrv(struct psp_context *psp) 239 { 240 return psp_v13_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV); 241 } 242 243 static int psp_v13_0_bootloader_load_soc_drv(struct psp_context *psp) 244 { 245 return psp_v13_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV); 246 } 247 248 static int psp_v13_0_bootloader_load_intf_drv(struct psp_context *psp) 249 { 250 return psp_v13_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV); 251 } 252 253 static int psp_v13_0_bootloader_load_dbg_drv(struct psp_context *psp) 254 { 255 return psp_v13_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV); 256 } 257 258 static int psp_v13_0_bootloader_load_ras_drv(struct psp_context *psp) 259 { 260 return psp_v13_0_bootloader_load_component(psp, &psp->ras_drv, PSP_BL__LOAD_RASDRV); 261 } 262 263 264 static int psp_v13_0_bootloader_load_sos(struct psp_context *psp) 265 { 266 int ret; 267 unsigned int psp_gfxdrv_command_reg = 0; 268 struct amdgpu_device *adev = psp->adev; 269 270 /* Check sOS sign of life register to confirm sys driver and sOS 271 * are already been loaded. 272 */ 273 if (psp_v13_0_is_sos_alive(psp)) 274 return 0; 275 276 ret = psp_v13_0_wait_for_bootloader(psp); 277 if (ret) 278 return ret; 279 280 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 281 282 /* Copy Secure OS binary to PSP memory */ 283 memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes); 284 285 /* Provide the PSP secure OS to bootloader */ 286 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 287 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 288 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; 289 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 290 psp_gfxdrv_command_reg); 291 292 /* there might be handshake issue with hardware which needs delay */ 293 mdelay(20); 294 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81), 295 RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81), 296 0, true); 297 298 return ret; 299 } 300 301 static int psp_v13_0_ring_stop(struct psp_context *psp, 302 enum psp_ring_type ring_type) 303 { 304 int ret = 0; 305 struct amdgpu_device *adev = psp->adev; 306 307 if (amdgpu_sriov_vf(adev)) { 308 /* Write the ring destroy command*/ 309 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 310 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 311 /* there might be handshake issue with hardware which needs delay */ 312 mdelay(20); 313 /* Wait for response flag (bit 31) */ 314 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 315 0x80000000, 0x80000000, false); 316 } else { 317 /* Write the ring destroy command*/ 318 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, 319 GFX_CTRL_CMD_ID_DESTROY_RINGS); 320 /* there might be handshake issue with hardware which needs delay */ 321 mdelay(20); 322 /* Wait for response flag (bit 31) */ 323 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 324 0x80000000, 0x80000000, false); 325 } 326 327 return ret; 328 } 329 330 static int psp_v13_0_ring_create(struct psp_context *psp, 331 enum psp_ring_type ring_type) 332 { 333 int ret = 0; 334 unsigned int psp_ring_reg = 0; 335 struct psp_ring *ring = &psp->km_ring; 336 struct amdgpu_device *adev = psp->adev; 337 338 if (amdgpu_sriov_vf(adev)) { 339 ret = psp_v13_0_ring_stop(psp, ring_type); 340 if (ret) { 341 DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n"); 342 return ret; 343 } 344 345 /* Write low address of the ring to C2PMSG_102 */ 346 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 347 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg); 348 /* Write high address of the ring to C2PMSG_103 */ 349 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 350 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg); 351 352 /* Write the ring initialization command to C2PMSG_101 */ 353 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 354 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 355 356 /* there might be handshake issue with hardware which needs delay */ 357 mdelay(20); 358 359 /* Wait for response flag (bit 31) in C2PMSG_101 */ 360 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 361 0x80000000, 0x8000FFFF, false); 362 363 } else { 364 /* Wait for sOS ready for ring creation */ 365 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 366 0x80000000, 0x80000000, false); 367 if (ret) { 368 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n"); 369 return ret; 370 } 371 372 /* Write low address of the ring to C2PMSG_69 */ 373 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 374 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg); 375 /* Write high address of the ring to C2PMSG_70 */ 376 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 377 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg); 378 /* Write size of ring to C2PMSG_71 */ 379 psp_ring_reg = ring->ring_size; 380 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg); 381 /* Write the ring initialization command to C2PMSG_64 */ 382 psp_ring_reg = ring_type; 383 psp_ring_reg = psp_ring_reg << 16; 384 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg); 385 386 /* there might be handshake issue with hardware which needs delay */ 387 mdelay(20); 388 389 /* Wait for response flag (bit 31) in C2PMSG_64 */ 390 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 391 0x80000000, 0x8000FFFF, false); 392 } 393 394 return ret; 395 } 396 397 static int psp_v13_0_ring_destroy(struct psp_context *psp, 398 enum psp_ring_type ring_type) 399 { 400 int ret = 0; 401 struct psp_ring *ring = &psp->km_ring; 402 struct amdgpu_device *adev = psp->adev; 403 404 ret = psp_v13_0_ring_stop(psp, ring_type); 405 if (ret) 406 DRM_ERROR("Fail to stop psp ring\n"); 407 408 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 409 &ring->ring_mem_mc_addr, 410 (void **)&ring->ring_mem); 411 412 return ret; 413 } 414 415 static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp) 416 { 417 uint32_t data; 418 struct amdgpu_device *adev = psp->adev; 419 420 if (amdgpu_sriov_vf(adev)) 421 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102); 422 else 423 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67); 424 425 return data; 426 } 427 428 static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value) 429 { 430 struct amdgpu_device *adev = psp->adev; 431 432 if (amdgpu_sriov_vf(adev)) { 433 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value); 434 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 435 GFX_CTRL_CMD_ID_CONSUME_CMD); 436 } else 437 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value); 438 } 439 440 static int psp_v13_0_memory_training_send_msg(struct psp_context *psp, int msg) 441 { 442 int ret; 443 int i; 444 uint32_t data_32; 445 int max_wait; 446 struct amdgpu_device *adev = psp->adev; 447 448 data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20); 449 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, data_32); 450 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, msg); 451 452 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout; 453 for (i = 0; i < max_wait; i++) { 454 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 455 0x80000000, 0x80000000, false); 456 if (ret == 0) 457 break; 458 } 459 if (i < max_wait) 460 ret = 0; 461 else 462 ret = -ETIME; 463 464 dev_dbg(adev->dev, "training %s %s, cost %d @ %d ms\n", 465 (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long", 466 (ret == 0) ? "succeed" : "failed", 467 i, adev->usec_timeout/1000); 468 return ret; 469 } 470 471 472 static int psp_v13_0_memory_training(struct psp_context *psp, uint32_t ops) 473 { 474 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 475 uint32_t *pcache = (uint32_t *)ctx->sys_cache; 476 struct amdgpu_device *adev = psp->adev; 477 uint32_t p2c_header[4]; 478 uint32_t sz; 479 void *buf; 480 int ret, idx; 481 482 if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) { 483 dev_dbg(adev->dev, "Memory training is not supported.\n"); 484 return 0; 485 } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) { 486 dev_err(adev->dev, "Memory training initialization failure.\n"); 487 return -EINVAL; 488 } 489 490 if (psp_v13_0_is_sos_alive(psp)) { 491 dev_dbg(adev->dev, "SOS is alive, skip memory training.\n"); 492 return 0; 493 } 494 495 amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false); 496 dev_dbg(adev->dev, "sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n", 497 pcache[0], pcache[1], pcache[2], pcache[3], 498 p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]); 499 500 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 501 dev_dbg(adev->dev, "Short training depends on restore.\n"); 502 ops |= PSP_MEM_TRAIN_RESTORE; 503 } 504 505 if ((ops & PSP_MEM_TRAIN_RESTORE) && 506 pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 507 dev_dbg(adev->dev, "sys_cache[0] is invalid, restore depends on save.\n"); 508 ops |= PSP_MEM_TRAIN_SAVE; 509 } 510 511 if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 512 !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 513 pcache[3] == p2c_header[3])) { 514 dev_dbg(adev->dev, "sys_cache is invalid or out-of-date, need save training data to sys_cache.\n"); 515 ops |= PSP_MEM_TRAIN_SAVE; 516 } 517 518 if ((ops & PSP_MEM_TRAIN_SAVE) && 519 p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 520 dev_dbg(adev->dev, "p2c_header[0] is invalid, save depends on long training.\n"); 521 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG; 522 } 523 524 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 525 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG; 526 ops |= PSP_MEM_TRAIN_SAVE; 527 } 528 529 dev_dbg(adev->dev, "Memory training ops:%x.\n", ops); 530 531 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 532 /* 533 * Long training will encroach a certain amount on the bottom of VRAM; 534 * save the content from the bottom of VRAM to system memory 535 * before training, and restore it after training to avoid 536 * VRAM corruption. 537 */ 538 sz = GDDR6_MEM_TRAINING_ENCROACHED_SIZE; 539 540 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) { 541 dev_err(adev->dev, "visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n", 542 adev->gmc.visible_vram_size, 543 adev->mman.aper_base_kaddr); 544 return -EINVAL; 545 } 546 547 buf = vmalloc(sz); 548 if (!buf) { 549 dev_err(adev->dev, "failed to allocate system memory.\n"); 550 return -ENOMEM; 551 } 552 553 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 554 memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz); 555 ret = psp_v13_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN); 556 if (ret) { 557 DRM_ERROR("Send long training msg failed.\n"); 558 vfree(buf); 559 drm_dev_exit(idx); 560 return ret; 561 } 562 563 memcpy_toio(adev->mman.aper_base_kaddr, buf, sz); 564 adev->hdp.funcs->flush_hdp(adev, NULL); 565 vfree(buf); 566 drm_dev_exit(idx); 567 } else { 568 vfree(buf); 569 return -ENODEV; 570 } 571 } 572 573 if (ops & PSP_MEM_TRAIN_SAVE) { 574 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false); 575 } 576 577 if (ops & PSP_MEM_TRAIN_RESTORE) { 578 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true); 579 } 580 581 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 582 ret = psp_v13_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ? 583 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN); 584 if (ret) { 585 dev_err(adev->dev, "send training msg failed.\n"); 586 return ret; 587 } 588 } 589 ctx->training_cnt++; 590 return 0; 591 } 592 593 static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr) 594 { 595 struct amdgpu_device *adev = psp->adev; 596 uint32_t reg_status; 597 int ret, i = 0; 598 599 /* 600 * LFB address which is aligned to 1MB address and has to be 601 * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P 602 * register 603 */ 604 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20)); 605 606 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 607 0x80000000, 0x80000000, false); 608 if (ret) 609 return ret; 610 611 /* Fireup interrupt so PSP can pick up the address */ 612 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16)); 613 614 /* FW load takes very long time */ 615 do { 616 msleep(1000); 617 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35); 618 619 if (reg_status & 0x80000000) 620 goto done; 621 622 } while (++i < USBC_PD_POLLING_LIMIT_S); 623 624 return -ETIME; 625 done: 626 627 if ((reg_status & 0xFFFF) != 0) { 628 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n", 629 reg_status & 0xFFFF); 630 return -EIO; 631 } 632 633 return 0; 634 } 635 636 static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver) 637 { 638 struct amdgpu_device *adev = psp->adev; 639 int ret; 640 641 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER); 642 643 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 644 0x80000000, 0x80000000, false); 645 if (!ret) 646 *fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36); 647 648 return ret; 649 } 650 651 static int psp_v13_0_exec_spi_cmd(struct psp_context *psp, int cmd) 652 { 653 uint32_t reg_status = 0, reg_val = 0; 654 struct amdgpu_device *adev = psp->adev; 655 int ret; 656 657 /* clear MBX ready (MBOX_READY_MASK bit is 0) and set update command */ 658 reg_val |= (cmd << 16); 659 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115, reg_val); 660 661 /* Ring the doorbell */ 662 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_73, 1); 663 664 if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE) 665 ret = psp_wait_for_spirom_update(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 666 MBOX_READY_FLAG, MBOX_READY_MASK, PSP_SPIROM_UPDATE_TIMEOUT); 667 else 668 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 669 MBOX_READY_FLAG, MBOX_READY_MASK, false); 670 if (ret) { 671 dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret); 672 return ret; 673 } 674 675 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115); 676 if ((reg_status & 0xFFFF) != 0) { 677 dev_err(adev->dev, "SPI cmd %x failed, fail status = %04x\n", 678 cmd, reg_status & 0xFFFF); 679 return -EIO; 680 } 681 682 return 0; 683 } 684 685 static int psp_v13_0_update_spirom(struct psp_context *psp, 686 uint64_t fw_pri_mc_addr) 687 { 688 struct amdgpu_device *adev = psp->adev; 689 int ret; 690 691 /* Confirm PSP is ready to start */ 692 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 693 MBOX_READY_FLAG, MBOX_READY_MASK, false); 694 if (ret) { 695 dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret); 696 return ret; 697 } 698 699 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr)); 700 701 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO); 702 if (ret) 703 return ret; 704 705 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr)); 706 707 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI); 708 if (ret) 709 return ret; 710 711 psp->vbflash_done = true; 712 713 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE); 714 if (ret) 715 return ret; 716 717 return 0; 718 } 719 720 static int psp_v13_0_vbflash_status(struct psp_context *psp) 721 { 722 struct amdgpu_device *adev = psp->adev; 723 724 return RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115); 725 } 726 727 static int psp_v13_0_fatal_error_recovery_quirk(struct psp_context *psp) 728 { 729 struct amdgpu_device *adev = psp->adev; 730 731 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 10)) { 732 uint32_t reg_data; 733 /* MP1 fatal error: trigger PSP dram read to unhalt PSP 734 * during MP1 triggered sync flood. 735 */ 736 reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67); 737 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, reg_data + 0x10); 738 739 /* delay 1000ms for the mode1 reset for fatal error 740 * to be recovered back. 741 */ 742 msleep(1000); 743 } 744 745 return 0; 746 } 747 748 static const struct psp_funcs psp_v13_0_funcs = { 749 .init_microcode = psp_v13_0_init_microcode, 750 .wait_for_bootloader = psp_v13_0_wait_for_bootloader_steady_state, 751 .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb, 752 .bootloader_load_spl = psp_v13_0_bootloader_load_spl, 753 .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv, 754 .bootloader_load_soc_drv = psp_v13_0_bootloader_load_soc_drv, 755 .bootloader_load_intf_drv = psp_v13_0_bootloader_load_intf_drv, 756 .bootloader_load_dbg_drv = psp_v13_0_bootloader_load_dbg_drv, 757 .bootloader_load_ras_drv = psp_v13_0_bootloader_load_ras_drv, 758 .bootloader_load_sos = psp_v13_0_bootloader_load_sos, 759 .ring_create = psp_v13_0_ring_create, 760 .ring_stop = psp_v13_0_ring_stop, 761 .ring_destroy = psp_v13_0_ring_destroy, 762 .ring_get_wptr = psp_v13_0_ring_get_wptr, 763 .ring_set_wptr = psp_v13_0_ring_set_wptr, 764 .mem_training = psp_v13_0_memory_training, 765 .load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw, 766 .read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw, 767 .update_spirom = psp_v13_0_update_spirom, 768 .vbflash_stat = psp_v13_0_vbflash_status, 769 .fatal_error_recovery_quirk = psp_v13_0_fatal_error_recovery_quirk, 770 }; 771 772 void psp_v13_0_set_psp_funcs(struct psp_context *psp) 773 { 774 psp->funcs = &psp_v13_0_funcs; 775 } 776