1 /*
2  * Copyright 2020 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 #include <drm/drm_drv.h>
24 #include <linux/vmalloc.h>
25 #include "amdgpu.h"
26 #include "amdgpu_psp.h"
27 #include "amdgpu_ucode.h"
28 #include "soc15_common.h"
29 #include "psp_v13_0.h"
30 
31 #include "mp/mp_13_0_2_offset.h"
32 #include "mp/mp_13_0_2_sh_mask.h"
33 
34 MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin");
35 MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin");
36 MODULE_FIRMWARE("amdgpu/aldebaran_cap.bin");
37 MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin");
38 MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin");
39 MODULE_FIRMWARE("amdgpu/psp_13_0_5_toc.bin");
40 MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin");
41 MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin");
42 MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin");
43 MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin");
44 MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta.bin");
45 MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin");
46 MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin");
47 MODULE_FIRMWARE("amdgpu/psp_13_0_10_sos.bin");
48 MODULE_FIRMWARE("amdgpu/psp_13_0_10_ta.bin");
49 MODULE_FIRMWARE("amdgpu/psp_13_0_11_toc.bin");
50 MODULE_FIRMWARE("amdgpu/psp_13_0_11_ta.bin");
51 MODULE_FIRMWARE("amdgpu/psp_13_0_6_sos.bin");
52 MODULE_FIRMWARE("amdgpu/psp_13_0_6_ta.bin");
53 MODULE_FIRMWARE("amdgpu/psp_14_0_0_toc.bin");
54 MODULE_FIRMWARE("amdgpu/psp_14_0_0_ta.bin");
55 
56 /* For large FW files the time to complete can be very long */
57 #define USBC_PD_POLLING_LIMIT_S 240
58 
59 /* Read USB-PD from LFB */
60 #define GFX_CMD_USB_PD_USE_LFB 0x480
61 
62 /* Retry times for vmbx ready wait */
63 #define PSP_VMBX_POLLING_LIMIT 3000
64 
65 /* VBIOS gfl defines */
66 #define MBOX_READY_MASK 0x80000000
67 #define MBOX_STATUS_MASK 0x0000FFFF
68 #define MBOX_COMMAND_MASK 0x00FF0000
69 #define MBOX_READY_FLAG 0x80000000
70 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO 0x2
71 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3
72 #define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4
73 
74 /* memory training timeout define */
75 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US	3000000
76 
77 static int psp_v13_0_init_microcode(struct psp_context *psp)
78 {
79 	struct amdgpu_device *adev = psp->adev;
80 	char ucode_prefix[30];
81 	int err = 0;
82 
83 	amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
84 
85 	switch (adev->ip_versions[MP0_HWIP][0]) {
86 	case IP_VERSION(13, 0, 2):
87 		err = psp_init_sos_microcode(psp, ucode_prefix);
88 		if (err)
89 			return err;
90 		/* It's not necessary to load ras ta on Guest side */
91 		if (!amdgpu_sriov_vf(adev)) {
92 			err = psp_init_ta_microcode(psp, ucode_prefix);
93 			if (err)
94 				return err;
95 		}
96 		break;
97 	case IP_VERSION(13, 0, 1):
98 	case IP_VERSION(13, 0, 3):
99 	case IP_VERSION(13, 0, 5):
100 	case IP_VERSION(13, 0, 8):
101 	case IP_VERSION(13, 0, 11):
102 	case IP_VERSION(14, 0, 0):
103 		err = psp_init_toc_microcode(psp, ucode_prefix);
104 		if (err)
105 			return err;
106 		err = psp_init_ta_microcode(psp, ucode_prefix);
107 		if (err)
108 			return err;
109 		break;
110 	case IP_VERSION(13, 0, 0):
111 	case IP_VERSION(13, 0, 6):
112 	case IP_VERSION(13, 0, 7):
113 	case IP_VERSION(13, 0, 10):
114 		err = psp_init_sos_microcode(psp, ucode_prefix);
115 		if (err)
116 			return err;
117 		/* It's not necessary to load ras ta on Guest side */
118 		err = psp_init_ta_microcode(psp, ucode_prefix);
119 		if (err)
120 			return err;
121 		break;
122 	default:
123 		BUG();
124 	}
125 
126 	return 0;
127 }
128 
129 static bool psp_v13_0_is_sos_alive(struct psp_context *psp)
130 {
131 	struct amdgpu_device *adev = psp->adev;
132 	uint32_t sol_reg;
133 
134 	sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
135 
136 	return sol_reg != 0x0;
137 }
138 
139 static int psp_v13_0_wait_for_vmbx_ready(struct psp_context *psp)
140 {
141 	struct amdgpu_device *adev = psp->adev;
142 	int retry_loop, ret;
143 
144 	for (retry_loop = 0; retry_loop < PSP_VMBX_POLLING_LIMIT; retry_loop++) {
145 		/* Wait for bootloader to signify that is
146 		   ready having bit 31 of C2PMSG_33 set to 1 */
147 		ret = psp_wait_for(
148 			psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_33),
149 			0x80000000, 0xffffffff, false);
150 
151 		if (ret == 0)
152 			break;
153 	}
154 
155 	if (ret)
156 		dev_warn(adev->dev, "Bootloader wait timed out");
157 
158 	return ret;
159 }
160 
161 static int psp_v13_0_wait_for_bootloader(struct psp_context *psp)
162 {
163 	struct amdgpu_device *adev = psp->adev;
164 	int retry_loop, retry_cnt, ret;
165 
166 	retry_cnt =
167 		(adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 6)) ?
168 			PSP_VMBX_POLLING_LIMIT :
169 			10;
170 	/* Wait for bootloader to signify that it is ready having bit 31 of
171 	 * C2PMSG_35 set to 1. All other bits are expected to be cleared.
172 	 * If there is an error in processing command, bits[7:0] will be set.
173 	 * This is applicable for PSP v13.0.6 and newer.
174 	 */
175 	for (retry_loop = 0; retry_loop < retry_cnt; retry_loop++) {
176 		ret = psp_wait_for(
177 			psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
178 			0x80000000, 0xffffffff, false);
179 
180 		if (ret == 0)
181 			return 0;
182 	}
183 
184 	return ret;
185 }
186 
187 static int psp_v13_0_wait_for_bootloader_steady_state(struct psp_context *psp)
188 {
189 	struct amdgpu_device *adev = psp->adev;
190 
191 	if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 6)) {
192 		psp_v13_0_wait_for_vmbx_ready(psp);
193 
194 		return psp_v13_0_wait_for_bootloader(psp);
195 	}
196 
197 	return 0;
198 }
199 
200 static int psp_v13_0_bootloader_load_component(struct psp_context  	*psp,
201 					       struct psp_bin_desc 	*bin_desc,
202 					       enum psp_bootloader_cmd  bl_cmd)
203 {
204 	int ret;
205 	uint32_t psp_gfxdrv_command_reg = 0;
206 	struct amdgpu_device *adev = psp->adev;
207 
208 	/* Check tOS sign of life register to confirm sys driver and sOS
209 	 * are already been loaded.
210 	 */
211 	if (psp_v13_0_is_sos_alive(psp))
212 		return 0;
213 
214 	ret = psp_v13_0_wait_for_bootloader(psp);
215 	if (ret)
216 		return ret;
217 
218 	memset(psp->fw_pri_buf, 0, PSP_1_MEG);
219 
220 	/* Copy PSP KDB binary to memory */
221 	memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes);
222 
223 	/* Provide the PSP KDB to bootloader */
224 	WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
225 	       (uint32_t)(psp->fw_pri_mc_addr >> 20));
226 	psp_gfxdrv_command_reg = bl_cmd;
227 	WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
228 	       psp_gfxdrv_command_reg);
229 
230 	ret = psp_v13_0_wait_for_bootloader(psp);
231 
232 	return ret;
233 }
234 
235 static int psp_v13_0_bootloader_load_kdb(struct psp_context *psp)
236 {
237 	return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE);
238 }
239 
240 static int psp_v13_0_bootloader_load_spl(struct psp_context *psp)
241 {
242 	return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE);
243 }
244 
245 static int psp_v13_0_bootloader_load_sysdrv(struct psp_context *psp)
246 {
247 	return psp_v13_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV);
248 }
249 
250 static int psp_v13_0_bootloader_load_soc_drv(struct psp_context *psp)
251 {
252 	return psp_v13_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV);
253 }
254 
255 static int psp_v13_0_bootloader_load_intf_drv(struct psp_context *psp)
256 {
257 	return psp_v13_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV);
258 }
259 
260 static int psp_v13_0_bootloader_load_dbg_drv(struct psp_context *psp)
261 {
262 	return psp_v13_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV);
263 }
264 
265 static int psp_v13_0_bootloader_load_ras_drv(struct psp_context *psp)
266 {
267 	return psp_v13_0_bootloader_load_component(psp, &psp->ras_drv, PSP_BL__LOAD_RASDRV);
268 }
269 
270 
271 static int psp_v13_0_bootloader_load_sos(struct psp_context *psp)
272 {
273 	int ret;
274 	unsigned int psp_gfxdrv_command_reg = 0;
275 	struct amdgpu_device *adev = psp->adev;
276 
277 	/* Check sOS sign of life register to confirm sys driver and sOS
278 	 * are already been loaded.
279 	 */
280 	if (psp_v13_0_is_sos_alive(psp))
281 		return 0;
282 
283 	ret = psp_v13_0_wait_for_bootloader(psp);
284 	if (ret)
285 		return ret;
286 
287 	memset(psp->fw_pri_buf, 0, PSP_1_MEG);
288 
289 	/* Copy Secure OS binary to PSP memory */
290 	memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes);
291 
292 	/* Provide the PSP secure OS to bootloader */
293 	WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
294 	       (uint32_t)(psp->fw_pri_mc_addr >> 20));
295 	psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
296 	WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
297 	       psp_gfxdrv_command_reg);
298 
299 	/* there might be handshake issue with hardware which needs delay */
300 	mdelay(20);
301 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81),
302 			   RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81),
303 			   0, true);
304 
305 	return ret;
306 }
307 
308 static int psp_v13_0_ring_stop(struct psp_context *psp,
309 			       enum psp_ring_type ring_type)
310 {
311 	int ret = 0;
312 	struct amdgpu_device *adev = psp->adev;
313 
314 	if (amdgpu_sriov_vf(adev)) {
315 		/* Write the ring destroy command*/
316 		WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
317 			     GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
318 		/* there might be handshake issue with hardware which needs delay */
319 		mdelay(20);
320 		/* Wait for response flag (bit 31) */
321 		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
322 				   0x80000000, 0x80000000, false);
323 	} else {
324 		/* Write the ring destroy command*/
325 		WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64,
326 			     GFX_CTRL_CMD_ID_DESTROY_RINGS);
327 		/* there might be handshake issue with hardware which needs delay */
328 		mdelay(20);
329 		/* Wait for response flag (bit 31) */
330 		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
331 				   0x80000000, 0x80000000, false);
332 	}
333 
334 	return ret;
335 }
336 
337 static int psp_v13_0_ring_create(struct psp_context *psp,
338 				 enum psp_ring_type ring_type)
339 {
340 	int ret = 0;
341 	unsigned int psp_ring_reg = 0;
342 	struct psp_ring *ring = &psp->km_ring;
343 	struct amdgpu_device *adev = psp->adev;
344 
345 	if (amdgpu_sriov_vf(adev)) {
346 		ret = psp_v13_0_ring_stop(psp, ring_type);
347 		if (ret) {
348 			DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n");
349 			return ret;
350 		}
351 
352 		/* Write low address of the ring to C2PMSG_102 */
353 		psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
354 		WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg);
355 		/* Write high address of the ring to C2PMSG_103 */
356 		psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
357 		WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg);
358 
359 		/* Write the ring initialization command to C2PMSG_101 */
360 		WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
361 			     GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
362 
363 		/* there might be handshake issue with hardware which needs delay */
364 		mdelay(20);
365 
366 		/* Wait for response flag (bit 31) in C2PMSG_101 */
367 		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
368 				   0x80000000, 0x8000FFFF, false);
369 
370 	} else {
371 		/* Wait for sOS ready for ring creation */
372 		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
373 				   0x80000000, 0x80000000, false);
374 		if (ret) {
375 			DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
376 			return ret;
377 		}
378 
379 		/* Write low address of the ring to C2PMSG_69 */
380 		psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
381 		WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg);
382 		/* Write high address of the ring to C2PMSG_70 */
383 		psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
384 		WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg);
385 		/* Write size of ring to C2PMSG_71 */
386 		psp_ring_reg = ring->ring_size;
387 		WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg);
388 		/* Write the ring initialization command to C2PMSG_64 */
389 		psp_ring_reg = ring_type;
390 		psp_ring_reg = psp_ring_reg << 16;
391 		WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg);
392 
393 		/* there might be handshake issue with hardware which needs delay */
394 		mdelay(20);
395 
396 		/* Wait for response flag (bit 31) in C2PMSG_64 */
397 		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
398 				   0x80000000, 0x8000FFFF, false);
399 	}
400 
401 	return ret;
402 }
403 
404 static int psp_v13_0_ring_destroy(struct psp_context *psp,
405 				  enum psp_ring_type ring_type)
406 {
407 	int ret = 0;
408 	struct psp_ring *ring = &psp->km_ring;
409 	struct amdgpu_device *adev = psp->adev;
410 
411 	ret = psp_v13_0_ring_stop(psp, ring_type);
412 	if (ret)
413 		DRM_ERROR("Fail to stop psp ring\n");
414 
415 	amdgpu_bo_free_kernel(&adev->firmware.rbuf,
416 			      &ring->ring_mem_mc_addr,
417 			      (void **)&ring->ring_mem);
418 
419 	return ret;
420 }
421 
422 static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp)
423 {
424 	uint32_t data;
425 	struct amdgpu_device *adev = psp->adev;
426 
427 	if (amdgpu_sriov_vf(adev))
428 		data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102);
429 	else
430 		data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
431 
432 	return data;
433 }
434 
435 static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
436 {
437 	struct amdgpu_device *adev = psp->adev;
438 
439 	if (amdgpu_sriov_vf(adev)) {
440 		WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value);
441 		WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
442 			     GFX_CTRL_CMD_ID_CONSUME_CMD);
443 	} else
444 		WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value);
445 }
446 
447 static int psp_v13_0_memory_training_send_msg(struct psp_context *psp, int msg)
448 {
449 	int ret;
450 	int i;
451 	uint32_t data_32;
452 	int max_wait;
453 	struct amdgpu_device *adev = psp->adev;
454 
455 	data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20);
456 	WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, data_32);
457 	WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, msg);
458 
459 	max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout;
460 	for (i = 0; i < max_wait; i++) {
461 		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
462 				   0x80000000, 0x80000000, false);
463 		if (ret == 0)
464 			break;
465 	}
466 	if (i < max_wait)
467 		ret = 0;
468 	else
469 		ret = -ETIME;
470 
471 	dev_dbg(adev->dev, "training %s %s, cost %d @ %d ms\n",
472 		  (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long",
473 		  (ret == 0) ? "succeed" : "failed",
474 		  i, adev->usec_timeout/1000);
475 	return ret;
476 }
477 
478 
479 static int psp_v13_0_memory_training(struct psp_context *psp, uint32_t ops)
480 {
481 	struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
482 	uint32_t *pcache = (uint32_t *)ctx->sys_cache;
483 	struct amdgpu_device *adev = psp->adev;
484 	uint32_t p2c_header[4];
485 	uint32_t sz;
486 	void *buf;
487 	int ret, idx;
488 
489 	if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) {
490 		dev_dbg(adev->dev, "Memory training is not supported.\n");
491 		return 0;
492 	} else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) {
493 		dev_err(adev->dev, "Memory training initialization failure.\n");
494 		return -EINVAL;
495 	}
496 
497 	if (psp_v13_0_is_sos_alive(psp)) {
498 		dev_dbg(adev->dev, "SOS is alive, skip memory training.\n");
499 		return 0;
500 	}
501 
502 	amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false);
503 	dev_dbg(adev->dev, "sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n",
504 		  pcache[0], pcache[1], pcache[2], pcache[3],
505 		  p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]);
506 
507 	if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
508 		dev_dbg(adev->dev, "Short training depends on restore.\n");
509 		ops |= PSP_MEM_TRAIN_RESTORE;
510 	}
511 
512 	if ((ops & PSP_MEM_TRAIN_RESTORE) &&
513 	    pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
514 		dev_dbg(adev->dev, "sys_cache[0] is invalid, restore depends on save.\n");
515 		ops |= PSP_MEM_TRAIN_SAVE;
516 	}
517 
518 	if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
519 	    !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
520 	      pcache[3] == p2c_header[3])) {
521 		dev_dbg(adev->dev, "sys_cache is invalid or out-of-date, need save training data to sys_cache.\n");
522 		ops |= PSP_MEM_TRAIN_SAVE;
523 	}
524 
525 	if ((ops & PSP_MEM_TRAIN_SAVE) &&
526 	    p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
527 		dev_dbg(adev->dev, "p2c_header[0] is invalid, save depends on long training.\n");
528 		ops |= PSP_MEM_TRAIN_SEND_LONG_MSG;
529 	}
530 
531 	if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
532 		ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG;
533 		ops |= PSP_MEM_TRAIN_SAVE;
534 	}
535 
536 	dev_dbg(adev->dev, "Memory training ops:%x.\n", ops);
537 
538 	if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
539 		/*
540 		 * Long training will encroach a certain amount on the bottom of VRAM;
541 		 * save the content from the bottom of VRAM to system memory
542 		 * before training, and restore it after training to avoid
543 		 * VRAM corruption.
544 		 */
545 		sz = GDDR6_MEM_TRAINING_ENCROACHED_SIZE;
546 
547 		if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) {
548 			dev_err(adev->dev, "visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n",
549 				  adev->gmc.visible_vram_size,
550 				  adev->mman.aper_base_kaddr);
551 			return -EINVAL;
552 		}
553 
554 		buf = vmalloc(sz);
555 		if (!buf) {
556 			dev_err(adev->dev, "failed to allocate system memory.\n");
557 			return -ENOMEM;
558 		}
559 
560 		if (drm_dev_enter(adev_to_drm(adev), &idx)) {
561 			memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz);
562 			ret = psp_v13_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN);
563 			if (ret) {
564 				DRM_ERROR("Send long training msg failed.\n");
565 				vfree(buf);
566 				drm_dev_exit(idx);
567 				return ret;
568 			}
569 
570 			memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
571 			adev->hdp.funcs->flush_hdp(adev, NULL);
572 			vfree(buf);
573 			drm_dev_exit(idx);
574 		} else {
575 			vfree(buf);
576 			return -ENODEV;
577 		}
578 	}
579 
580 	if (ops & PSP_MEM_TRAIN_SAVE) {
581 		amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false);
582 	}
583 
584 	if (ops & PSP_MEM_TRAIN_RESTORE) {
585 		amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true);
586 	}
587 
588 	if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
589 		ret = psp_v13_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ?
590 							 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN);
591 		if (ret) {
592 			dev_err(adev->dev, "send training msg failed.\n");
593 			return ret;
594 		}
595 	}
596 	ctx->training_cnt++;
597 	return 0;
598 }
599 
600 static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr)
601 {
602 	struct amdgpu_device *adev = psp->adev;
603 	uint32_t reg_status;
604 	int ret, i = 0;
605 
606 	/*
607 	 * LFB address which is aligned to 1MB address and has to be
608 	 * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P
609 	 * register
610 	 */
611 	WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20));
612 
613 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
614 			     0x80000000, 0x80000000, false);
615 	if (ret)
616 		return ret;
617 
618 	/* Fireup interrupt so PSP can pick up the address */
619 	WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16));
620 
621 	/* FW load takes very long time */
622 	do {
623 		msleep(1000);
624 		reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35);
625 
626 		if (reg_status & 0x80000000)
627 			goto done;
628 
629 	} while (++i < USBC_PD_POLLING_LIMIT_S);
630 
631 	return -ETIME;
632 done:
633 
634 	if ((reg_status & 0xFFFF) != 0) {
635 		DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n",
636 				reg_status & 0xFFFF);
637 		return -EIO;
638 	}
639 
640 	return 0;
641 }
642 
643 static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)
644 {
645 	struct amdgpu_device *adev = psp->adev;
646 	int ret;
647 
648 	WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER);
649 
650 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
651 				     0x80000000, 0x80000000, false);
652 	if (!ret)
653 		*fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36);
654 
655 	return ret;
656 }
657 
658 static int psp_v13_0_exec_spi_cmd(struct psp_context *psp, int cmd)
659 {
660 	uint32_t reg_status = 0, reg_val = 0;
661 	struct amdgpu_device *adev = psp->adev;
662 	int ret;
663 
664 	/* clear MBX ready (MBOX_READY_MASK bit is 0) and set update command */
665 	reg_val |= (cmd << 16);
666 	WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115,  reg_val);
667 
668 	/* Ring the doorbell */
669 	WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_73, 1);
670 
671 	if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE)
672 		ret = psp_wait_for_spirom_update(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
673 						 MBOX_READY_FLAG, MBOX_READY_MASK, PSP_SPIROM_UPDATE_TIMEOUT);
674 	else
675 		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
676 				   MBOX_READY_FLAG, MBOX_READY_MASK, false);
677 	if (ret) {
678 		dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret);
679 		return ret;
680 	}
681 
682 	reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);
683 	if ((reg_status & 0xFFFF) != 0) {
684 		dev_err(adev->dev, "SPI cmd %x failed, fail status = %04x\n",
685 				cmd, reg_status & 0xFFFF);
686 		return -EIO;
687 	}
688 
689 	return 0;
690 }
691 
692 static int psp_v13_0_update_spirom(struct psp_context *psp,
693 				   uint64_t fw_pri_mc_addr)
694 {
695 	struct amdgpu_device *adev = psp->adev;
696 	int ret;
697 
698 	/* Confirm PSP is ready to start */
699 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
700 			   MBOX_READY_FLAG, MBOX_READY_MASK, false);
701 	if (ret) {
702 		dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret);
703 		return ret;
704 	}
705 
706 	WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr));
707 
708 	ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO);
709 	if (ret)
710 		return ret;
711 
712 	WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr));
713 
714 	ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI);
715 	if (ret)
716 		return ret;
717 
718 	psp->vbflash_done = true;
719 
720 	ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE);
721 	if (ret)
722 		return ret;
723 
724 	return 0;
725 }
726 
727 static int psp_v13_0_vbflash_status(struct psp_context *psp)
728 {
729 	struct amdgpu_device *adev = psp->adev;
730 
731 	return RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);
732 }
733 
734 static int psp_v13_0_fatal_error_recovery_quirk(struct psp_context *psp)
735 {
736 	struct amdgpu_device *adev = psp->adev;
737 
738 	if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 10)) {
739 		uint32_t  reg_data;
740 		/* MP1 fatal error: trigger PSP dram read to unhalt PSP
741 		 * during MP1 triggered sync flood.
742 		 */
743 		reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
744 		WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, reg_data + 0x10);
745 
746 		/* delay 1000ms for the mode1 reset for fatal error
747 		 * to be recovered back.
748 		 */
749 		msleep(1000);
750 	}
751 
752 	return 0;
753 }
754 
755 static const struct psp_funcs psp_v13_0_funcs = {
756 	.init_microcode = psp_v13_0_init_microcode,
757 	.wait_for_bootloader = psp_v13_0_wait_for_bootloader_steady_state,
758 	.bootloader_load_kdb = psp_v13_0_bootloader_load_kdb,
759 	.bootloader_load_spl = psp_v13_0_bootloader_load_spl,
760 	.bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv,
761 	.bootloader_load_soc_drv = psp_v13_0_bootloader_load_soc_drv,
762 	.bootloader_load_intf_drv = psp_v13_0_bootloader_load_intf_drv,
763 	.bootloader_load_dbg_drv = psp_v13_0_bootloader_load_dbg_drv,
764 	.bootloader_load_ras_drv = psp_v13_0_bootloader_load_ras_drv,
765 	.bootloader_load_sos = psp_v13_0_bootloader_load_sos,
766 	.ring_create = psp_v13_0_ring_create,
767 	.ring_stop = psp_v13_0_ring_stop,
768 	.ring_destroy = psp_v13_0_ring_destroy,
769 	.ring_get_wptr = psp_v13_0_ring_get_wptr,
770 	.ring_set_wptr = psp_v13_0_ring_set_wptr,
771 	.mem_training = psp_v13_0_memory_training,
772 	.load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw,
773 	.read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw,
774 	.update_spirom = psp_v13_0_update_spirom,
775 	.vbflash_stat = psp_v13_0_vbflash_status,
776 	.fatal_error_recovery_quirk = psp_v13_0_fatal_error_recovery_quirk,
777 };
778 
779 void psp_v13_0_set_psp_funcs(struct psp_context *psp)
780 {
781 	psp->funcs = &psp_v13_0_funcs;
782 }
783