1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <drm/drm_drv.h> 24 #include <linux/vmalloc.h> 25 #include "amdgpu.h" 26 #include "amdgpu_psp.h" 27 #include "amdgpu_ucode.h" 28 #include "soc15_common.h" 29 #include "psp_v13_0.h" 30 31 #include "mp/mp_13_0_2_offset.h" 32 #include "mp/mp_13_0_2_sh_mask.h" 33 34 MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin"); 35 MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin"); 36 MODULE_FIRMWARE("amdgpu/aldebaran_cap.bin"); 37 MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin"); 38 MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin"); 39 MODULE_FIRMWARE("amdgpu/psp_13_0_5_toc.bin"); 40 MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin"); 41 MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin"); 42 MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin"); 43 MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin"); 44 MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta.bin"); 45 MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin"); 46 MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin"); 47 MODULE_FIRMWARE("amdgpu/psp_13_0_10_sos.bin"); 48 MODULE_FIRMWARE("amdgpu/psp_13_0_10_ta.bin"); 49 MODULE_FIRMWARE("amdgpu/psp_13_0_11_toc.bin"); 50 MODULE_FIRMWARE("amdgpu/psp_13_0_11_ta.bin"); 51 MODULE_FIRMWARE("amdgpu/psp_13_0_6_sos.bin"); 52 MODULE_FIRMWARE("amdgpu/psp_13_0_6_ta.bin"); 53 54 /* For large FW files the time to complete can be very long */ 55 #define USBC_PD_POLLING_LIMIT_S 240 56 57 /* Read USB-PD from LFB */ 58 #define GFX_CMD_USB_PD_USE_LFB 0x480 59 60 /* VBIOS gfl defines */ 61 #define MBOX_READY_MASK 0x80000000 62 #define MBOX_STATUS_MASK 0x0000FFFF 63 #define MBOX_COMMAND_MASK 0x00FF0000 64 #define MBOX_READY_FLAG 0x80000000 65 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO 0x2 66 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3 67 #define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4 68 69 /* memory training timeout define */ 70 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000 71 72 static int psp_v13_0_init_microcode(struct psp_context *psp) 73 { 74 struct amdgpu_device *adev = psp->adev; 75 char ucode_prefix[30]; 76 int err = 0; 77 78 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 79 80 switch (adev->ip_versions[MP0_HWIP][0]) { 81 case IP_VERSION(13, 0, 2): 82 err = psp_init_sos_microcode(psp, ucode_prefix); 83 if (err) 84 return err; 85 /* It's not necessary to load ras ta on Guest side */ 86 if (!amdgpu_sriov_vf(adev)) { 87 err = psp_init_ta_microcode(psp, ucode_prefix); 88 if (err) 89 return err; 90 } 91 break; 92 case IP_VERSION(13, 0, 1): 93 case IP_VERSION(13, 0, 3): 94 case IP_VERSION(13, 0, 5): 95 case IP_VERSION(13, 0, 8): 96 case IP_VERSION(13, 0, 11): 97 err = psp_init_toc_microcode(psp, ucode_prefix); 98 if (err) 99 return err; 100 err = psp_init_ta_microcode(psp, ucode_prefix); 101 if (err) 102 return err; 103 break; 104 case IP_VERSION(13, 0, 0): 105 case IP_VERSION(13, 0, 6): 106 case IP_VERSION(13, 0, 7): 107 case IP_VERSION(13, 0, 10): 108 err = psp_init_sos_microcode(psp, ucode_prefix); 109 if (err) 110 return err; 111 /* It's not necessary to load ras ta on Guest side */ 112 err = psp_init_ta_microcode(psp, ucode_prefix); 113 if (err) 114 return err; 115 break; 116 default: 117 BUG(); 118 } 119 120 return 0; 121 } 122 123 static bool psp_v13_0_is_sos_alive(struct psp_context *psp) 124 { 125 struct amdgpu_device *adev = psp->adev; 126 uint32_t sol_reg; 127 128 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 129 130 return sol_reg != 0x0; 131 } 132 133 static int psp_v13_0_wait_for_bootloader(struct psp_context *psp) 134 { 135 struct amdgpu_device *adev = psp->adev; 136 137 int ret; 138 int retry_loop; 139 140 for (retry_loop = 0; retry_loop < 10; retry_loop++) { 141 /* Wait for bootloader to signify that is 142 ready having bit 31 of C2PMSG_35 set to 1 */ 143 ret = psp_wait_for(psp, 144 SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 145 0x80000000, 146 0x80000000, 147 false); 148 149 if (ret == 0) 150 return 0; 151 } 152 153 return ret; 154 } 155 156 static int psp_v13_0_bootloader_load_component(struct psp_context *psp, 157 struct psp_bin_desc *bin_desc, 158 enum psp_bootloader_cmd bl_cmd) 159 { 160 int ret; 161 uint32_t psp_gfxdrv_command_reg = 0; 162 struct amdgpu_device *adev = psp->adev; 163 164 /* Check tOS sign of life register to confirm sys driver and sOS 165 * are already been loaded. 166 */ 167 if (psp_v13_0_is_sos_alive(psp)) 168 return 0; 169 170 ret = psp_v13_0_wait_for_bootloader(psp); 171 if (ret) 172 return ret; 173 174 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 175 176 /* Copy PSP KDB binary to memory */ 177 memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes); 178 179 /* Provide the PSP KDB to bootloader */ 180 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 181 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 182 psp_gfxdrv_command_reg = bl_cmd; 183 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 184 psp_gfxdrv_command_reg); 185 186 ret = psp_v13_0_wait_for_bootloader(psp); 187 188 return ret; 189 } 190 191 static int psp_v13_0_bootloader_load_kdb(struct psp_context *psp) 192 { 193 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE); 194 } 195 196 static int psp_v13_0_bootloader_load_spl(struct psp_context *psp) 197 { 198 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE); 199 } 200 201 static int psp_v13_0_bootloader_load_sysdrv(struct psp_context *psp) 202 { 203 return psp_v13_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV); 204 } 205 206 static int psp_v13_0_bootloader_load_soc_drv(struct psp_context *psp) 207 { 208 return psp_v13_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV); 209 } 210 211 static int psp_v13_0_bootloader_load_intf_drv(struct psp_context *psp) 212 { 213 return psp_v13_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV); 214 } 215 216 static int psp_v13_0_bootloader_load_dbg_drv(struct psp_context *psp) 217 { 218 return psp_v13_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV); 219 } 220 221 static int psp_v13_0_bootloader_load_ras_drv(struct psp_context *psp) 222 { 223 return psp_v13_0_bootloader_load_component(psp, &psp->ras_drv, PSP_BL__LOAD_RASDRV); 224 } 225 226 227 static int psp_v13_0_bootloader_load_sos(struct psp_context *psp) 228 { 229 int ret; 230 unsigned int psp_gfxdrv_command_reg = 0; 231 struct amdgpu_device *adev = psp->adev; 232 233 /* Check sOS sign of life register to confirm sys driver and sOS 234 * are already been loaded. 235 */ 236 if (psp_v13_0_is_sos_alive(psp)) 237 return 0; 238 239 ret = psp_v13_0_wait_for_bootloader(psp); 240 if (ret) 241 return ret; 242 243 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 244 245 /* Copy Secure OS binary to PSP memory */ 246 memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes); 247 248 /* Provide the PSP secure OS to bootloader */ 249 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 250 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 251 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; 252 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 253 psp_gfxdrv_command_reg); 254 255 /* there might be handshake issue with hardware which needs delay */ 256 mdelay(20); 257 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81), 258 RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81), 259 0, true); 260 261 return ret; 262 } 263 264 static int psp_v13_0_ring_stop(struct psp_context *psp, 265 enum psp_ring_type ring_type) 266 { 267 int ret = 0; 268 struct amdgpu_device *adev = psp->adev; 269 270 if (amdgpu_sriov_vf(adev)) { 271 /* Write the ring destroy command*/ 272 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 273 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 274 /* there might be handshake issue with hardware which needs delay */ 275 mdelay(20); 276 /* Wait for response flag (bit 31) */ 277 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 278 0x80000000, 0x80000000, false); 279 } else { 280 /* Write the ring destroy command*/ 281 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, 282 GFX_CTRL_CMD_ID_DESTROY_RINGS); 283 /* there might be handshake issue with hardware which needs delay */ 284 mdelay(20); 285 /* Wait for response flag (bit 31) */ 286 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 287 0x80000000, 0x80000000, false); 288 } 289 290 return ret; 291 } 292 293 static int psp_v13_0_ring_create(struct psp_context *psp, 294 enum psp_ring_type ring_type) 295 { 296 int ret = 0; 297 unsigned int psp_ring_reg = 0; 298 struct psp_ring *ring = &psp->km_ring; 299 struct amdgpu_device *adev = psp->adev; 300 301 if (amdgpu_sriov_vf(adev)) { 302 ret = psp_v13_0_ring_stop(psp, ring_type); 303 if (ret) { 304 DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n"); 305 return ret; 306 } 307 308 /* Write low address of the ring to C2PMSG_102 */ 309 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 310 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg); 311 /* Write high address of the ring to C2PMSG_103 */ 312 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 313 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg); 314 315 /* Write the ring initialization command to C2PMSG_101 */ 316 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 317 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 318 319 /* there might be handshake issue with hardware which needs delay */ 320 mdelay(20); 321 322 /* Wait for response flag (bit 31) in C2PMSG_101 */ 323 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 324 0x80000000, 0x8000FFFF, false); 325 326 } else { 327 /* Wait for sOS ready for ring creation */ 328 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 329 0x80000000, 0x80000000, false); 330 if (ret) { 331 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n"); 332 return ret; 333 } 334 335 /* Write low address of the ring to C2PMSG_69 */ 336 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 337 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg); 338 /* Write high address of the ring to C2PMSG_70 */ 339 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 340 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg); 341 /* Write size of ring to C2PMSG_71 */ 342 psp_ring_reg = ring->ring_size; 343 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg); 344 /* Write the ring initialization command to C2PMSG_64 */ 345 psp_ring_reg = ring_type; 346 psp_ring_reg = psp_ring_reg << 16; 347 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg); 348 349 /* there might be handshake issue with hardware which needs delay */ 350 mdelay(20); 351 352 /* Wait for response flag (bit 31) in C2PMSG_64 */ 353 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 354 0x80000000, 0x8000FFFF, false); 355 } 356 357 return ret; 358 } 359 360 static int psp_v13_0_ring_destroy(struct psp_context *psp, 361 enum psp_ring_type ring_type) 362 { 363 int ret = 0; 364 struct psp_ring *ring = &psp->km_ring; 365 struct amdgpu_device *adev = psp->adev; 366 367 ret = psp_v13_0_ring_stop(psp, ring_type); 368 if (ret) 369 DRM_ERROR("Fail to stop psp ring\n"); 370 371 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 372 &ring->ring_mem_mc_addr, 373 (void **)&ring->ring_mem); 374 375 return ret; 376 } 377 378 static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp) 379 { 380 uint32_t data; 381 struct amdgpu_device *adev = psp->adev; 382 383 if (amdgpu_sriov_vf(adev)) 384 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102); 385 else 386 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67); 387 388 return data; 389 } 390 391 static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value) 392 { 393 struct amdgpu_device *adev = psp->adev; 394 395 if (amdgpu_sriov_vf(adev)) { 396 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value); 397 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 398 GFX_CTRL_CMD_ID_CONSUME_CMD); 399 } else 400 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value); 401 } 402 403 static int psp_v13_0_memory_training_send_msg(struct psp_context *psp, int msg) 404 { 405 int ret; 406 int i; 407 uint32_t data_32; 408 int max_wait; 409 struct amdgpu_device *adev = psp->adev; 410 411 data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20); 412 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, data_32); 413 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, msg); 414 415 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout; 416 for (i = 0; i < max_wait; i++) { 417 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 418 0x80000000, 0x80000000, false); 419 if (ret == 0) 420 break; 421 } 422 if (i < max_wait) 423 ret = 0; 424 else 425 ret = -ETIME; 426 427 dev_dbg(adev->dev, "training %s %s, cost %d @ %d ms\n", 428 (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long", 429 (ret == 0) ? "succeed" : "failed", 430 i, adev->usec_timeout/1000); 431 return ret; 432 } 433 434 435 static int psp_v13_0_memory_training(struct psp_context *psp, uint32_t ops) 436 { 437 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 438 uint32_t *pcache = (uint32_t *)ctx->sys_cache; 439 struct amdgpu_device *adev = psp->adev; 440 uint32_t p2c_header[4]; 441 uint32_t sz; 442 void *buf; 443 int ret, idx; 444 445 if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) { 446 dev_dbg(adev->dev, "Memory training is not supported.\n"); 447 return 0; 448 } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) { 449 dev_err(adev->dev, "Memory training initialization failure.\n"); 450 return -EINVAL; 451 } 452 453 if (psp_v13_0_is_sos_alive(psp)) { 454 dev_dbg(adev->dev, "SOS is alive, skip memory training.\n"); 455 return 0; 456 } 457 458 amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false); 459 dev_dbg(adev->dev, "sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n", 460 pcache[0], pcache[1], pcache[2], pcache[3], 461 p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]); 462 463 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 464 dev_dbg(adev->dev, "Short training depends on restore.\n"); 465 ops |= PSP_MEM_TRAIN_RESTORE; 466 } 467 468 if ((ops & PSP_MEM_TRAIN_RESTORE) && 469 pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 470 dev_dbg(adev->dev, "sys_cache[0] is invalid, restore depends on save.\n"); 471 ops |= PSP_MEM_TRAIN_SAVE; 472 } 473 474 if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 475 !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 476 pcache[3] == p2c_header[3])) { 477 dev_dbg(adev->dev, "sys_cache is invalid or out-of-date, need save training data to sys_cache.\n"); 478 ops |= PSP_MEM_TRAIN_SAVE; 479 } 480 481 if ((ops & PSP_MEM_TRAIN_SAVE) && 482 p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 483 dev_dbg(adev->dev, "p2c_header[0] is invalid, save depends on long training.\n"); 484 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG; 485 } 486 487 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 488 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG; 489 ops |= PSP_MEM_TRAIN_SAVE; 490 } 491 492 dev_dbg(adev->dev, "Memory training ops:%x.\n", ops); 493 494 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 495 /* 496 * Long training will encroach a certain amount on the bottom of VRAM; 497 * save the content from the bottom of VRAM to system memory 498 * before training, and restore it after training to avoid 499 * VRAM corruption. 500 */ 501 sz = GDDR6_MEM_TRAINING_ENCROACHED_SIZE; 502 503 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) { 504 dev_err(adev->dev, "visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n", 505 adev->gmc.visible_vram_size, 506 adev->mman.aper_base_kaddr); 507 return -EINVAL; 508 } 509 510 buf = vmalloc(sz); 511 if (!buf) { 512 dev_err(adev->dev, "failed to allocate system memory.\n"); 513 return -ENOMEM; 514 } 515 516 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 517 memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz); 518 ret = psp_v13_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN); 519 if (ret) { 520 DRM_ERROR("Send long training msg failed.\n"); 521 vfree(buf); 522 drm_dev_exit(idx); 523 return ret; 524 } 525 526 memcpy_toio(adev->mman.aper_base_kaddr, buf, sz); 527 adev->hdp.funcs->flush_hdp(adev, NULL); 528 vfree(buf); 529 drm_dev_exit(idx); 530 } else { 531 vfree(buf); 532 return -ENODEV; 533 } 534 } 535 536 if (ops & PSP_MEM_TRAIN_SAVE) { 537 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false); 538 } 539 540 if (ops & PSP_MEM_TRAIN_RESTORE) { 541 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true); 542 } 543 544 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 545 ret = psp_v13_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ? 546 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN); 547 if (ret) { 548 dev_err(adev->dev, "send training msg failed.\n"); 549 return ret; 550 } 551 } 552 ctx->training_cnt++; 553 return 0; 554 } 555 556 static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr) 557 { 558 struct amdgpu_device *adev = psp->adev; 559 uint32_t reg_status; 560 int ret, i = 0; 561 562 /* 563 * LFB address which is aligned to 1MB address and has to be 564 * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P 565 * register 566 */ 567 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20)); 568 569 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 570 0x80000000, 0x80000000, false); 571 if (ret) 572 return ret; 573 574 /* Fireup interrupt so PSP can pick up the address */ 575 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16)); 576 577 /* FW load takes very long time */ 578 do { 579 msleep(1000); 580 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35); 581 582 if (reg_status & 0x80000000) 583 goto done; 584 585 } while (++i < USBC_PD_POLLING_LIMIT_S); 586 587 return -ETIME; 588 done: 589 590 if ((reg_status & 0xFFFF) != 0) { 591 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n", 592 reg_status & 0xFFFF); 593 return -EIO; 594 } 595 596 return 0; 597 } 598 599 static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver) 600 { 601 struct amdgpu_device *adev = psp->adev; 602 int ret; 603 604 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER); 605 606 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 607 0x80000000, 0x80000000, false); 608 if (!ret) 609 *fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36); 610 611 return ret; 612 } 613 614 static int psp_v13_0_exec_spi_cmd(struct psp_context *psp, int cmd) 615 { 616 uint32_t reg_status = 0, reg_val = 0; 617 struct amdgpu_device *adev = psp->adev; 618 int ret; 619 620 /* clear MBX ready (MBOX_READY_MASK bit is 0) and set update command */ 621 reg_val |= (cmd << 16); 622 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115, reg_val); 623 624 /* Ring the doorbell */ 625 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_73, 1); 626 627 if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE) 628 ret = psp_wait_for_spirom_update(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 629 MBOX_READY_FLAG, MBOX_READY_MASK, PSP_SPIROM_UPDATE_TIMEOUT); 630 else 631 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 632 MBOX_READY_FLAG, MBOX_READY_MASK, false); 633 if (ret) { 634 dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret); 635 return ret; 636 } 637 638 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115); 639 if ((reg_status & 0xFFFF) != 0) { 640 dev_err(adev->dev, "SPI cmd %x failed, fail status = %04x\n", 641 cmd, reg_status & 0xFFFF); 642 return -EIO; 643 } 644 645 return 0; 646 } 647 648 static int psp_v13_0_update_spirom(struct psp_context *psp, 649 uint64_t fw_pri_mc_addr) 650 { 651 struct amdgpu_device *adev = psp->adev; 652 int ret; 653 654 /* Confirm PSP is ready to start */ 655 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 656 MBOX_READY_FLAG, MBOX_READY_MASK, false); 657 if (ret) { 658 dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret); 659 return ret; 660 } 661 662 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr)); 663 664 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO); 665 if (ret) 666 return ret; 667 668 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr)); 669 670 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI); 671 if (ret) 672 return ret; 673 674 psp->vbflash_done = true; 675 676 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE); 677 if (ret) 678 return ret; 679 680 return 0; 681 } 682 683 static int psp_v13_0_vbflash_status(struct psp_context *psp) 684 { 685 struct amdgpu_device *adev = psp->adev; 686 687 return RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115); 688 } 689 690 static const struct psp_funcs psp_v13_0_funcs = { 691 .init_microcode = psp_v13_0_init_microcode, 692 .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb, 693 .bootloader_load_spl = psp_v13_0_bootloader_load_spl, 694 .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv, 695 .bootloader_load_soc_drv = psp_v13_0_bootloader_load_soc_drv, 696 .bootloader_load_intf_drv = psp_v13_0_bootloader_load_intf_drv, 697 .bootloader_load_dbg_drv = psp_v13_0_bootloader_load_dbg_drv, 698 .bootloader_load_ras_drv = psp_v13_0_bootloader_load_ras_drv, 699 .bootloader_load_sos = psp_v13_0_bootloader_load_sos, 700 .ring_create = psp_v13_0_ring_create, 701 .ring_stop = psp_v13_0_ring_stop, 702 .ring_destroy = psp_v13_0_ring_destroy, 703 .ring_get_wptr = psp_v13_0_ring_get_wptr, 704 .ring_set_wptr = psp_v13_0_ring_set_wptr, 705 .mem_training = psp_v13_0_memory_training, 706 .load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw, 707 .read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw, 708 .update_spirom = psp_v13_0_update_spirom, 709 .vbflash_stat = psp_v13_0_vbflash_status 710 }; 711 712 void psp_v13_0_set_psp_funcs(struct psp_context *psp) 713 { 714 psp->funcs = &psp_v13_0_funcs; 715 } 716