1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/firmware.h> 24 #include <linux/module.h> 25 #include "amdgpu.h" 26 #include "amdgpu_psp.h" 27 #include "amdgpu_ucode.h" 28 #include "soc15_common.h" 29 #include "psp_v12_0.h" 30 31 #include "mp/mp_12_0_0_offset.h" 32 #include "mp/mp_12_0_0_sh_mask.h" 33 #include "gc/gc_9_0_offset.h" 34 #include "sdma0/sdma0_4_0_offset.h" 35 #include "nbio/nbio_7_4_offset.h" 36 37 #include "oss/osssys_4_0_offset.h" 38 #include "oss/osssys_4_0_sh_mask.h" 39 40 MODULE_FIRMWARE("amdgpu/renoir_asd.bin"); 41 MODULE_FIRMWARE("amdgpu/renoir_ta.bin"); 42 MODULE_FIRMWARE("amdgpu/green_sardine_asd.bin"); 43 MODULE_FIRMWARE("amdgpu/green_sardine_ta.bin"); 44 45 /* address block */ 46 #define smnMP1_FIRMWARE_FLAGS 0x3010024 47 48 static int psp_v12_0_init_microcode(struct psp_context *psp) 49 { 50 struct amdgpu_device *adev = psp->adev; 51 const char *chip_name; 52 char fw_name[30]; 53 int err = 0; 54 const struct ta_firmware_header_v1_0 *ta_hdr; 55 DRM_DEBUG("\n"); 56 57 switch (adev->asic_type) { 58 case CHIP_RENOIR: 59 if (adev->apu_flags & AMD_APU_IS_RENOIR) 60 chip_name = "renoir"; 61 else 62 chip_name = "green_sardine"; 63 break; 64 default: 65 BUG(); 66 } 67 68 err = psp_init_asd_microcode(psp, chip_name); 69 if (err) 70 goto out; 71 72 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 73 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 74 if (err) { 75 release_firmware(adev->psp.ta_fw); 76 adev->psp.ta_fw = NULL; 77 dev_info(adev->dev, 78 "psp v12.0: Failed to load firmware \"%s\"\n", 79 fw_name); 80 } else { 81 err = amdgpu_ucode_validate(adev->psp.ta_fw); 82 if (err) 83 goto out2; 84 85 ta_hdr = (const struct ta_firmware_header_v1_0 *) 86 adev->psp.ta_fw->data; 87 adev->psp.ta_hdcp_ucode_version = 88 le32_to_cpu(ta_hdr->ta_hdcp_ucode_version); 89 adev->psp.ta_hdcp_ucode_size = 90 le32_to_cpu(ta_hdr->ta_hdcp_size_bytes); 91 adev->psp.ta_hdcp_start_addr = 92 (uint8_t *)ta_hdr + 93 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 94 95 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 96 97 adev->psp.ta_dtm_ucode_version = 98 le32_to_cpu(ta_hdr->ta_dtm_ucode_version); 99 adev->psp.ta_dtm_ucode_size = 100 le32_to_cpu(ta_hdr->ta_dtm_size_bytes); 101 adev->psp.ta_dtm_start_addr = 102 (uint8_t *)adev->psp.ta_hdcp_start_addr + 103 le32_to_cpu(ta_hdr->ta_dtm_offset_bytes); 104 } 105 106 return 0; 107 108 out2: 109 release_firmware(adev->psp.ta_fw); 110 adev->psp.ta_fw = NULL; 111 out: 112 if (err) { 113 dev_err(adev->dev, 114 "psp v12.0: Failed to load firmware \"%s\"\n", 115 fw_name); 116 } 117 118 return err; 119 } 120 121 static int psp_v12_0_bootloader_load_sysdrv(struct psp_context *psp) 122 { 123 int ret; 124 uint32_t psp_gfxdrv_command_reg = 0; 125 struct amdgpu_device *adev = psp->adev; 126 uint32_t sol_reg; 127 128 /* Check sOS sign of life register to confirm sys driver and sOS 129 * are already been loaded. 130 */ 131 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 132 if (sol_reg) 133 return 0; 134 135 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 136 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 137 0x80000000, 0x80000000, false); 138 if (ret) 139 return ret; 140 141 /* Copy PSP System Driver binary to memory */ 142 psp_copy_fw(psp, psp->sys_start_addr, psp->sys_bin_size); 143 144 /* Provide the sys driver to bootloader */ 145 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 146 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 147 psp_gfxdrv_command_reg = 1 << 16; 148 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 149 psp_gfxdrv_command_reg); 150 151 /* there might be handshake issue with hardware which needs delay */ 152 mdelay(20); 153 154 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 155 0x80000000, 0x80000000, false); 156 157 return ret; 158 } 159 160 static int psp_v12_0_bootloader_load_sos(struct psp_context *psp) 161 { 162 int ret; 163 unsigned int psp_gfxdrv_command_reg = 0; 164 struct amdgpu_device *adev = psp->adev; 165 uint32_t sol_reg; 166 167 /* Check sOS sign of life register to confirm sys driver and sOS 168 * are already been loaded. 169 */ 170 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 171 if (sol_reg) 172 return 0; 173 174 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 175 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 176 0x80000000, 0x80000000, false); 177 if (ret) 178 return ret; 179 180 /* Copy Secure OS binary to PSP memory */ 181 psp_copy_fw(psp, psp->sos_start_addr, psp->sos_bin_size); 182 183 /* Provide the PSP secure OS to bootloader */ 184 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 185 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 186 psp_gfxdrv_command_reg = 2 << 16; 187 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 188 psp_gfxdrv_command_reg); 189 190 /* there might be handshake issue with hardware which needs delay */ 191 mdelay(20); 192 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), 193 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 194 0, true); 195 196 return ret; 197 } 198 199 static void psp_v12_0_reroute_ih(struct psp_context *psp) 200 { 201 struct amdgpu_device *adev = psp->adev; 202 uint32_t tmp; 203 204 /* Change IH ring for VMC */ 205 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b); 206 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1); 207 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 208 209 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3); 210 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); 211 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); 212 213 mdelay(20); 214 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 215 0x80000000, 0x8000FFFF, false); 216 217 /* Change IH ring for UMC */ 218 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b); 219 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 220 221 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4); 222 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); 223 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); 224 225 mdelay(20); 226 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 227 0x80000000, 0x8000FFFF, false); 228 } 229 230 static int psp_v12_0_ring_init(struct psp_context *psp, 231 enum psp_ring_type ring_type) 232 { 233 int ret = 0; 234 struct psp_ring *ring; 235 struct amdgpu_device *adev = psp->adev; 236 237 psp_v12_0_reroute_ih(psp); 238 239 ring = &psp->km_ring; 240 241 ring->ring_type = ring_type; 242 243 /* allocate 4k Page of Local Frame Buffer memory for ring */ 244 ring->ring_size = 0x1000; 245 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 246 AMDGPU_GEM_DOMAIN_VRAM, 247 &adev->firmware.rbuf, 248 &ring->ring_mem_mc_addr, 249 (void **)&ring->ring_mem); 250 if (ret) { 251 ring->ring_size = 0; 252 return ret; 253 } 254 255 return 0; 256 } 257 258 static int psp_v12_0_ring_create(struct psp_context *psp, 259 enum psp_ring_type ring_type) 260 { 261 int ret = 0; 262 unsigned int psp_ring_reg = 0; 263 struct psp_ring *ring = &psp->km_ring; 264 struct amdgpu_device *adev = psp->adev; 265 266 if (amdgpu_sriov_vf(psp->adev)) { 267 /* Write low address of the ring to C2PMSG_102 */ 268 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 269 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg); 270 /* Write high address of the ring to C2PMSG_103 */ 271 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 272 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg); 273 274 /* Write the ring initialization command to C2PMSG_101 */ 275 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 276 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 277 278 /* there might be handshake issue with hardware which needs delay */ 279 mdelay(20); 280 281 /* Wait for response flag (bit 31) in C2PMSG_101 */ 282 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 283 0x80000000, 0x8000FFFF, false); 284 285 } else { 286 /* Write low address of the ring to C2PMSG_69 */ 287 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 288 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); 289 /* Write high address of the ring to C2PMSG_70 */ 290 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 291 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); 292 /* Write size of ring to C2PMSG_71 */ 293 psp_ring_reg = ring->ring_size; 294 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); 295 /* Write the ring initialization command to C2PMSG_64 */ 296 psp_ring_reg = ring_type; 297 psp_ring_reg = psp_ring_reg << 16; 298 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 299 300 /* there might be handshake issue with hardware which needs delay */ 301 mdelay(20); 302 303 /* Wait for response flag (bit 31) in C2PMSG_64 */ 304 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 305 0x80000000, 0x8000FFFF, false); 306 } 307 308 return ret; 309 } 310 311 static int psp_v12_0_ring_stop(struct psp_context *psp, 312 enum psp_ring_type ring_type) 313 { 314 int ret = 0; 315 struct amdgpu_device *adev = psp->adev; 316 317 /* Write the ring destroy command*/ 318 if (amdgpu_sriov_vf(adev)) 319 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 320 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 321 else 322 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, 323 GFX_CTRL_CMD_ID_DESTROY_RINGS); 324 325 /* there might be handshake issue with hardware which needs delay */ 326 mdelay(20); 327 328 /* Wait for response flag (bit 31) */ 329 if (amdgpu_sriov_vf(adev)) 330 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 331 0x80000000, 0x80000000, false); 332 else 333 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 334 0x80000000, 0x80000000, false); 335 336 return ret; 337 } 338 339 static int psp_v12_0_ring_destroy(struct psp_context *psp, 340 enum psp_ring_type ring_type) 341 { 342 int ret = 0; 343 struct psp_ring *ring = &psp->km_ring; 344 struct amdgpu_device *adev = psp->adev; 345 346 ret = psp_v12_0_ring_stop(psp, ring_type); 347 if (ret) 348 DRM_ERROR("Fail to stop psp ring\n"); 349 350 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 351 &ring->ring_mem_mc_addr, 352 (void **)&ring->ring_mem); 353 354 return ret; 355 } 356 357 static int psp_v12_0_mode1_reset(struct psp_context *psp) 358 { 359 int ret; 360 uint32_t offset; 361 struct amdgpu_device *adev = psp->adev; 362 363 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); 364 365 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false); 366 367 if (ret) { 368 DRM_INFO("psp is not working correctly before mode1 reset!\n"); 369 return -EINVAL; 370 } 371 372 /*send the mode 1 reset command*/ 373 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST); 374 375 msleep(500); 376 377 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); 378 379 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false); 380 381 if (ret) { 382 DRM_INFO("psp mode 1 reset failed!\n"); 383 return -EINVAL; 384 } 385 386 DRM_INFO("psp mode1 reset succeed \n"); 387 388 return 0; 389 } 390 391 static uint32_t psp_v12_0_ring_get_wptr(struct psp_context *psp) 392 { 393 uint32_t data; 394 struct amdgpu_device *adev = psp->adev; 395 396 if (amdgpu_sriov_vf(adev)) 397 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102); 398 else 399 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); 400 401 return data; 402 } 403 404 static void psp_v12_0_ring_set_wptr(struct psp_context *psp, uint32_t value) 405 { 406 struct amdgpu_device *adev = psp->adev; 407 408 if (amdgpu_sriov_vf(adev)) { 409 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value); 410 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD); 411 } else 412 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value); 413 } 414 415 static const struct psp_funcs psp_v12_0_funcs = { 416 .init_microcode = psp_v12_0_init_microcode, 417 .bootloader_load_sysdrv = psp_v12_0_bootloader_load_sysdrv, 418 .bootloader_load_sos = psp_v12_0_bootloader_load_sos, 419 .ring_init = psp_v12_0_ring_init, 420 .ring_create = psp_v12_0_ring_create, 421 .ring_stop = psp_v12_0_ring_stop, 422 .ring_destroy = psp_v12_0_ring_destroy, 423 .mode1_reset = psp_v12_0_mode1_reset, 424 .ring_get_wptr = psp_v12_0_ring_get_wptr, 425 .ring_set_wptr = psp_v12_0_ring_set_wptr, 426 }; 427 428 void psp_v12_0_set_psp_funcs(struct psp_context *psp) 429 { 430 psp->funcs = &psp_v12_0_funcs; 431 } 432